./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.11.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4e30283-6fdf-4eb6-a660-5941ff648c3f/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4e30283-6fdf-4eb6-a660-5941ff648c3f/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4e30283-6fdf-4eb6-a660-5941ff648c3f/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4e30283-6fdf-4eb6-a660-5941ff648c3f/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.11.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4e30283-6fdf-4eb6-a660-5941ff648c3f/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4e30283-6fdf-4eb6-a660-5941ff648c3f/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 79f20a4b12634e812af836a5fe92e9d987e7766e2c28337c49504608346f2347 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 15:05:41,800 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 15:05:41,802 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 15:05:41,821 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 15:05:41,821 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 15:05:41,822 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 15:05:41,823 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 15:05:41,824 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 15:05:41,826 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 15:05:41,827 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 15:05:41,828 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 15:05:41,829 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 15:05:41,829 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 15:05:41,830 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 15:05:41,831 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 15:05:41,832 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 15:05:41,833 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 15:05:41,834 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 15:05:41,835 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 15:05:41,837 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 15:05:41,838 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 15:05:41,839 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 15:05:41,840 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 15:05:41,841 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 15:05:41,844 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 15:05:41,844 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 15:05:41,845 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 15:05:41,845 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 15:05:41,846 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 15:05:41,846 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 15:05:41,847 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 15:05:41,847 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 15:05:41,848 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 15:05:41,849 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 15:05:41,850 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 15:05:41,850 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 15:05:41,850 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 15:05:41,850 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 15:05:41,851 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 15:05:41,851 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 15:05:41,852 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 15:05:41,853 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4e30283-6fdf-4eb6-a660-5941ff648c3f/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 15:05:41,884 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 15:05:41,884 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 15:05:41,884 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 15:05:41,891 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 15:05:41,892 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 15:05:41,892 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 15:05:41,892 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 15:05:41,892 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 15:05:41,892 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 15:05:41,892 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 15:05:41,893 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 15:05:41,893 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 15:05:41,893 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 15:05:41,893 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 15:05:41,893 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 15:05:41,893 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 15:05:41,894 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 15:05:41,894 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 15:05:41,894 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 15:05:41,894 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 15:05:41,894 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 15:05:41,894 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 15:05:41,895 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 15:05:41,895 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 15:05:41,895 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 15:05:41,895 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 15:05:41,895 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 15:05:41,895 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 15:05:41,896 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 15:05:41,896 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 15:05:41,896 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 15:05:41,897 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 15:05:41,897 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4e30283-6fdf-4eb6-a660-5941ff648c3f/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4e30283-6fdf-4eb6-a660-5941ff648c3f/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 79f20a4b12634e812af836a5fe92e9d987e7766e2c28337c49504608346f2347 [2022-12-13 15:05:42,083 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 15:05:42,102 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 15:05:42,105 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 15:05:42,106 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 15:05:42,106 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 15:05:42,107 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4e30283-6fdf-4eb6-a660-5941ff648c3f/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/token_ring.11.cil-1.c [2022-12-13 15:05:44,638 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 15:05:44,818 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 15:05:44,818 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4e30283-6fdf-4eb6-a660-5941ff648c3f/sv-benchmarks/c/systemc/token_ring.11.cil-1.c [2022-12-13 15:05:44,830 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4e30283-6fdf-4eb6-a660-5941ff648c3f/bin/uautomizer-uyxdKDjOR8/data/761c5d6ac/75d524698af241c9a9522930132176fe/FLAG69999b389 [2022-12-13 15:05:45,209 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4e30283-6fdf-4eb6-a660-5941ff648c3f/bin/uautomizer-uyxdKDjOR8/data/761c5d6ac/75d524698af241c9a9522930132176fe [2022-12-13 15:05:45,214 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 15:05:45,216 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 15:05:45,218 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 15:05:45,218 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 15:05:45,223 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 15:05:45,223 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 03:05:45" (1/1) ... [2022-12-13 15:05:45,224 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2d152908 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:05:45, skipping insertion in model container [2022-12-13 15:05:45,224 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 03:05:45" (1/1) ... [2022-12-13 15:05:45,231 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 15:05:45,270 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 15:05:45,379 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4e30283-6fdf-4eb6-a660-5941ff648c3f/sv-benchmarks/c/systemc/token_ring.11.cil-1.c[671,684] [2022-12-13 15:05:45,482 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 15:05:45,494 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 15:05:45,502 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4e30283-6fdf-4eb6-a660-5941ff648c3f/sv-benchmarks/c/systemc/token_ring.11.cil-1.c[671,684] [2022-12-13 15:05:45,561 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 15:05:45,579 INFO L208 MainTranslator]: Completed translation [2022-12-13 15:05:45,580 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:05:45 WrapperNode [2022-12-13 15:05:45,580 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 15:05:45,581 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 15:05:45,581 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 15:05:45,581 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 15:05:45,587 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:05:45" (1/1) ... [2022-12-13 15:05:45,598 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:05:45" (1/1) ... [2022-12-13 15:05:45,685 INFO L138 Inliner]: procedures = 50, calls = 65, calls flagged for inlining = 60, calls inlined = 239, statements flattened = 3657 [2022-12-13 15:05:45,685 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 15:05:45,686 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 15:05:45,686 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 15:05:45,686 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 15:05:45,693 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:05:45" (1/1) ... [2022-12-13 15:05:45,693 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:05:45" (1/1) ... [2022-12-13 15:05:45,702 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:05:45" (1/1) ... [2022-12-13 15:05:45,702 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:05:45" (1/1) ... [2022-12-13 15:05:45,735 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:05:45" (1/1) ... [2022-12-13 15:05:45,767 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:05:45" (1/1) ... [2022-12-13 15:05:45,773 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:05:45" (1/1) ... [2022-12-13 15:05:45,781 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:05:45" (1/1) ... [2022-12-13 15:05:45,792 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 15:05:45,793 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 15:05:45,793 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 15:05:45,793 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 15:05:45,794 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:05:45" (1/1) ... [2022-12-13 15:05:45,799 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 15:05:45,807 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4e30283-6fdf-4eb6-a660-5941ff648c3f/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 15:05:45,817 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4e30283-6fdf-4eb6-a660-5941ff648c3f/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 15:05:45,819 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f4e30283-6fdf-4eb6-a660-5941ff648c3f/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 15:05:45,851 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 15:05:45,852 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 15:05:45,852 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 15:05:45,852 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 15:05:45,944 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 15:05:45,946 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 15:05:47,242 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 15:05:47,255 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 15:05:47,255 INFO L300 CfgBuilder]: Removed 14 assume(true) statements. [2022-12-13 15:05:47,258 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 03:05:47 BoogieIcfgContainer [2022-12-13 15:05:47,258 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 15:05:47,258 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 15:05:47,258 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 15:05:47,261 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 15:05:47,262 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 15:05:47,262 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 03:05:45" (1/3) ... [2022-12-13 15:05:47,263 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@29f1270e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 03:05:47, skipping insertion in model container [2022-12-13 15:05:47,263 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 15:05:47,263 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:05:45" (2/3) ... [2022-12-13 15:05:47,263 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@29f1270e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 03:05:47, skipping insertion in model container [2022-12-13 15:05:47,263 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 15:05:47,263 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 03:05:47" (3/3) ... [2022-12-13 15:05:47,264 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.11.cil-1.c [2022-12-13 15:05:47,330 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 15:05:47,331 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 15:05:47,331 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 15:05:47,331 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 15:05:47,331 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 15:05:47,331 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 15:05:47,331 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 15:05:47,331 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 15:05:47,340 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1579 states, 1578 states have (on average 1.503168567807351) internal successors, (2372), 1578 states have internal predecessors, (2372), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:47,382 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1424 [2022-12-13 15:05:47,382 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:05:47,382 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:05:47,392 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:47,392 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:47,392 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 15:05:47,394 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1579 states, 1578 states have (on average 1.503168567807351) internal successors, (2372), 1578 states have internal predecessors, (2372), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:47,404 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1424 [2022-12-13 15:05:47,404 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:05:47,404 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:05:47,407 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:47,407 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:47,414 INFO L748 eck$LassoCheckResult]: Stem: 111#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 1501#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 536#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1498#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 657#L792true assume !(1 == ~m_i~0);~m_st~0 := 2; 993#L792-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 45#L797-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1415#L802-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1301#L807-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 634#L812-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1127#L817-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 919#L822-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1062#L827-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 1361#L832-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 1209#L837-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1216#L842-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 994#L847-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 794#L1121true assume !(0 == ~M_E~0); 583#L1121-2true assume !(0 == ~T1_E~0); 179#L1126-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 272#L1131-1true assume !(0 == ~T3_E~0); 333#L1136-1true assume !(0 == ~T4_E~0); 481#L1141-1true assume !(0 == ~T5_E~0); 1254#L1146-1true assume !(0 == ~T6_E~0); 729#L1151-1true assume !(0 == ~T7_E~0); 369#L1156-1true assume !(0 == ~T8_E~0); 38#L1161-1true assume !(0 == ~T9_E~0); 857#L1166-1true assume 0 == ~T10_E~0;~T10_E~0 := 1; 142#L1171-1true assume !(0 == ~T11_E~0); 744#L1176-1true assume !(0 == ~E_M~0); 880#L1181-1true assume !(0 == ~E_1~0); 1333#L1186-1true assume !(0 == ~E_2~0); 936#L1191-1true assume !(0 == ~E_3~0); 158#L1196-1true assume !(0 == ~E_4~0); 1344#L1201-1true assume !(0 == ~E_5~0); 1422#L1206-1true assume 0 == ~E_6~0;~E_6~0 := 1; 995#L1211-1true assume !(0 == ~E_7~0); 1148#L1216-1true assume !(0 == ~E_8~0); 233#L1221-1true assume !(0 == ~E_9~0); 1079#L1226-1true assume !(0 == ~E_10~0); 86#L1231-1true assume !(0 == ~E_11~0); 1227#L1236-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 745#L556true assume 1 == ~m_pc~0; 758#L557true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25#L567true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 458#is_master_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1128#L1391true assume !(0 != activate_threads_~tmp~1#1); 910#L1391-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1076#L575true assume !(1 == ~t1_pc~0); 5#L575-2true is_transmit1_triggered_~__retres1~1#1 := 0; 71#L586true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 796#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 240#L1399true assume !(0 != activate_threads_~tmp___0~0#1); 217#L1399-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 717#L594true assume 1 == ~t2_pc~0; 181#L595true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1526#L605true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 180#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33#L1407true assume !(0 != activate_threads_~tmp___1~0#1); 66#L1407-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1200#L613true assume !(1 == ~t3_pc~0); 1545#L613-2true is_transmit3_triggered_~__retres1~3#1 := 0; 307#L624true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 774#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 480#L1415true assume !(0 != activate_threads_~tmp___2~0#1); 1072#L1415-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 293#L632true assume 1 == ~t4_pc~0; 643#L633true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 795#L643true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1497#L1423true assume !(0 != activate_threads_~tmp___3~0#1); 749#L1423-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 530#L651true assume 1 == ~t5_pc~0; 959#L652true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 124#L662true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1269#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 456#L1431true assume !(0 != activate_threads_~tmp___4~0#1); 131#L1431-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1106#L670true assume !(1 == ~t6_pc~0); 966#L670-2true is_transmit6_triggered_~__retres1~6#1 := 0; 324#L681true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 175#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1303#L1439true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 508#L1439-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1326#L689true assume 1 == ~t7_pc~0; 1519#L690true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 593#L700true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1520#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 992#L1447true assume !(0 != activate_threads_~tmp___6~0#1); 440#L1447-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1181#L708true assume !(1 == ~t8_pc~0); 178#L708-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1124#L719true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1230#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1103#L1455true assume !(0 != activate_threads_~tmp___7~0#1); 209#L1455-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 279#L727true assume 1 == ~t9_pc~0; 1218#L728true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1413#L738true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 203#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1435#L1463true assume !(0 != activate_threads_~tmp___8~0#1); 1305#L1463-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 238#L746true assume !(1 == ~t10_pc~0); 706#L746-2true is_transmit10_triggered_~__retres1~10#1 := 0; 818#L757true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1044#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1118#L1471true assume !(0 != activate_threads_~tmp___9~0#1); 914#L1471-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 338#L765true assume 1 == ~t11_pc~0; 1369#L766true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1391#L776true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1146#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 964#L1479true assume !(0 != activate_threads_~tmp___10~0#1); 1158#L1479-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1099#L1249true assume !(1 == ~M_E~0); 647#L1249-2true assume !(1 == ~T1_E~0); 393#L1254-1true assume !(1 == ~T2_E~0); 31#L1259-1true assume !(1 == ~T3_E~0); 22#L1264-1true assume !(1 == ~T4_E~0); 1575#L1269-1true assume !(1 == ~T5_E~0); 1506#L1274-1true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1238#L1279-1true assume !(1 == ~T7_E~0); 119#L1284-1true assume !(1 == ~T8_E~0); 1370#L1289-1true assume !(1 == ~T9_E~0); 423#L1294-1true assume !(1 == ~T10_E~0); 430#L1299-1true assume !(1 == ~T11_E~0); 1431#L1304-1true assume !(1 == ~E_M~0); 1462#L1309-1true assume !(1 == ~E_1~0); 1438#L1314-1true assume 1 == ~E_2~0;~E_2~0 := 2; 96#L1319-1true assume !(1 == ~E_3~0); 840#L1324-1true assume !(1 == ~E_4~0); 155#L1329-1true assume !(1 == ~E_5~0); 1040#L1334-1true assume !(1 == ~E_6~0); 1397#L1339-1true assume !(1 == ~E_7~0); 1161#L1344-1true assume !(1 == ~E_8~0); 1525#L1349-1true assume !(1 == ~E_9~0); 519#L1354-1true assume 1 == ~E_10~0;~E_10~0 := 2; 844#L1359-1true assume !(1 == ~E_11~0); 1375#L1364-1true assume { :end_inline_reset_delta_events } true; 201#L1690-2true [2022-12-13 15:05:47,415 INFO L750 eck$LassoCheckResult]: Loop: 201#L1690-2true assume !false; 867#L1691true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 856#L1096true assume !true; 419#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 258#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 322#L1121-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1518#L1121-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1314#L1126-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 454#L1131-3true assume !(0 == ~T3_E~0); 1530#L1136-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1511#L1141-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 751#L1146-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 177#L1151-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1154#L1156-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1383#L1161-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 584#L1166-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1248#L1171-3true assume !(0 == ~T11_E~0); 616#L1176-3true assume 0 == ~E_M~0;~E_M~0 := 1; 199#L1181-3true assume 0 == ~E_1~0;~E_1~0 := 1; 1217#L1186-3true assume 0 == ~E_2~0;~E_2~0 := 1; 684#L1191-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1205#L1196-3true assume 0 == ~E_4~0;~E_4~0 := 1; 891#L1201-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1425#L1206-3true assume 0 == ~E_6~0;~E_6~0 := 1; 596#L1211-3true assume !(0 == ~E_7~0); 152#L1216-3true assume 0 == ~E_8~0;~E_8~0 := 1; 400#L1221-3true assume 0 == ~E_9~0;~E_9~0 := 1; 865#L1226-3true assume 0 == ~E_10~0;~E_10~0 := 1; 184#L1231-3true assume 0 == ~E_11~0;~E_11~0 := 1; 313#L1236-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1453#L556-39true assume 1 == ~m_pc~0; 693#L557-13true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 662#L567-13true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 554#is_master_triggered_returnLabel#14true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 342#L1391-39true assume !(0 != activate_threads_~tmp~1#1); 1295#L1391-41true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 626#L575-39true assume !(1 == ~t1_pc~0); 1424#L575-41true is_transmit1_triggered_~__retres1~1#1 := 0; 894#L586-13true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1384#is_transmit1_triggered_returnLabel#14true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1480#L1399-39true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 608#L1399-41true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 799#L594-39true assume 1 == ~t2_pc~0; 920#L595-13true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 610#L605-13true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 379#is_transmit2_triggered_returnLabel#14true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1107#L1407-39true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 273#L1407-41true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1068#L613-39true assume !(1 == ~t3_pc~0); 1449#L613-41true is_transmit3_triggered_~__retres1~3#1 := 0; 12#L624-13true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1555#is_transmit3_triggered_returnLabel#14true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 807#L1415-39true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 64#L1415-41true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1493#L632-39true assume 1 == ~t4_pc~0; 1015#L633-13true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 377#L643-13true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 488#is_transmit4_triggered_returnLabel#14true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1075#L1423-39true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1011#L1423-41true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 189#L651-39true assume 1 == ~t5_pc~0; 1561#L652-13true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 989#L662-13true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 504#is_transmit5_triggered_returnLabel#14true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1265#L1431-39true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1503#L1431-41true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1372#L670-39true assume 1 == ~t6_pc~0; 1478#L671-13true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 34#L681-13true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1460#is_transmit6_triggered_returnLabel#14true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 479#L1439-39true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 398#L1439-41true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 553#L689-39true assume 1 == ~t7_pc~0; 977#L690-13true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 492#L700-13true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 789#is_transmit7_triggered_returnLabel#14true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1468#L1447-39true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 125#L1447-41true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 733#L708-39true assume 1 == ~t8_pc~0; 99#L709-13true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 432#L719-13true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 882#is_transmit8_triggered_returnLabel#14true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1169#L1455-39true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 759#L1455-41true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 360#L727-39true assume 1 == ~t9_pc~0; 1504#L728-13true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 224#L738-13true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47#is_transmit9_triggered_returnLabel#14true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1139#L1463-39true assume !(0 != activate_threads_~tmp___8~0#1); 802#L1463-41true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 949#L746-39true assume !(1 == ~t10_pc~0); 1064#L746-41true is_transmit10_triggered_~__retres1~10#1 := 0; 1278#L757-13true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1137#is_transmit10_triggered_returnLabel#14true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 540#L1471-39true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 955#L1471-41true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1456#L765-39true assume !(1 == ~t11_pc~0); 283#L765-41true is_transmit11_triggered_~__retres1~11#1 := 0; 1187#L776-13true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 520#is_transmit11_triggered_returnLabel#14true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 200#L1479-39true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 712#L1479-41true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 578#L1249-3true assume 1 == ~M_E~0;~M_E~0 := 2; 108#L1249-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1348#L1254-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1152#L1259-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 678#L1264-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 88#L1269-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1416#L1274-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1235#L1279-3true assume !(1 == ~T7_E~0); 347#L1284-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1280#L1289-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 341#L1294-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1457#L1299-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 516#L1304-3true assume 1 == ~E_M~0;~E_M~0 := 2; 859#L1309-3true assume 1 == ~E_1~0;~E_1~0 := 2; 292#L1314-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1534#L1319-3true assume !(1 == ~E_3~0); 903#L1324-3true assume 1 == ~E_4~0;~E_4~0 := 2; 137#L1329-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1412#L1334-3true assume 1 == ~E_6~0;~E_6~0 := 2; 464#L1339-3true assume 1 == ~E_7~0;~E_7~0 := 2; 670#L1344-3true assume 1 == ~E_8~0;~E_8~0 := 2; 631#L1349-3true assume 1 == ~E_9~0;~E_9~0 := 2; 276#L1354-3true assume 1 == ~E_10~0;~E_10~0 := 2; 642#L1359-3true assume !(1 == ~E_11~0); 1430#L1364-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 72#L860-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 603#L922-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 153#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 837#L1709true assume !(0 == start_simulation_~tmp~3#1); 1291#L1709-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 927#L860-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1528#L922-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 17#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 106#L1664true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 617#L1671true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1071#stop_simulation_returnLabel#1true start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1056#L1722true assume !(0 != start_simulation_~tmp___0~1#1); 201#L1690-2true [2022-12-13 15:05:47,420 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:47,420 INFO L85 PathProgramCache]: Analyzing trace with hash 430082112, now seen corresponding path program 1 times [2022-12-13 15:05:47,427 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:47,427 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1983284528] [2022-12-13 15:05:47,427 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:47,427 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:47,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:47,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:47,626 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:47,627 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1983284528] [2022-12-13 15:05:47,627 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1983284528] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:47,627 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:47,628 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:47,629 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [277234204] [2022-12-13 15:05:47,629 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:47,633 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:05:47,634 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:47,634 INFO L85 PathProgramCache]: Analyzing trace with hash -1486348707, now seen corresponding path program 1 times [2022-12-13 15:05:47,634 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:47,634 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1961840179] [2022-12-13 15:05:47,635 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:47,635 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:47,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:47,676 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:47,677 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:47,677 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1961840179] [2022-12-13 15:05:47,677 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1961840179] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:47,677 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:47,677 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 15:05:47,677 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2130454473] [2022-12-13 15:05:47,677 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:47,678 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:05:47,679 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:05:47,702 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-12-13 15:05:47,702 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-12-13 15:05:47,708 INFO L87 Difference]: Start difference. First operand has 1579 states, 1578 states have (on average 1.503168567807351) internal successors, (2372), 1578 states have internal predecessors, (2372), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 69.5) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:47,752 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:05:47,752 INFO L93 Difference]: Finished difference Result 1577 states and 2340 transitions. [2022-12-13 15:05:47,753 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1577 states and 2340 transitions. [2022-12-13 15:05:47,761 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-12-13 15:05:47,769 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1577 states to 1571 states and 2334 transitions. [2022-12-13 15:05:47,770 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2022-12-13 15:05:47,772 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2022-12-13 15:05:47,772 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2334 transitions. [2022-12-13 15:05:47,776 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:05:47,777 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2334 transitions. [2022-12-13 15:05:47,792 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2334 transitions. [2022-12-13 15:05:47,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2022-12-13 15:05:47,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4856779121578612) internal successors, (2334), 1570 states have internal predecessors, (2334), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:47,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2334 transitions. [2022-12-13 15:05:47,835 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2334 transitions. [2022-12-13 15:05:47,836 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-12-13 15:05:47,839 INFO L428 stractBuchiCegarLoop]: Abstraction has 1571 states and 2334 transitions. [2022-12-13 15:05:47,839 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 15:05:47,839 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2334 transitions. [2022-12-13 15:05:47,852 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-12-13 15:05:47,852 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:05:47,852 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:05:47,854 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:47,854 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:47,854 INFO L748 eck$LassoCheckResult]: Stem: 3395#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 3396#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 4120#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4121#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4259#L792 assume !(1 == ~m_i~0);~m_st~0 := 2; 4260#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3256#L797-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3257#L802-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4693#L807-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4230#L812-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4231#L817-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4495#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4496#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4594#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4666#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4667#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4544#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4394#L1121 assume !(0 == ~M_E~0); 4171#L1121-2 assume !(0 == ~T1_E~0); 3536#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3537#L1131-1 assume !(0 == ~T3_E~0); 3704#L1136-1 assume !(0 == ~T4_E~0); 3809#L1141-1 assume !(0 == ~T5_E~0); 4031#L1146-1 assume !(0 == ~T6_E~0); 4326#L1151-1 assume !(0 == ~T7_E~0); 3873#L1156-1 assume !(0 == ~T8_E~0); 3242#L1161-1 assume !(0 == ~T9_E~0); 3243#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3466#L1171-1 assume !(0 == ~T11_E~0); 3467#L1176-1 assume !(0 == ~E_M~0); 4339#L1181-1 assume !(0 == ~E_1~0); 4458#L1186-1 assume !(0 == ~E_2~0); 4508#L1191-1 assume !(0 == ~E_3~0); 3497#L1196-1 assume !(0 == ~E_4~0); 3498#L1201-1 assume !(0 == ~E_5~0); 4707#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 4545#L1211-1 assume !(0 == ~E_7~0); 4546#L1216-1 assume !(0 == ~E_8~0); 3637#L1221-1 assume !(0 == ~E_9~0); 3638#L1226-1 assume !(0 == ~E_10~0); 3342#L1231-1 assume !(0 == ~E_11~0); 3343#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4340#L556 assume 1 == ~m_pc~0; 4341#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3216#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3217#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4005#L1391 assume !(0 != activate_threads_~tmp~1#1); 4485#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4486#L575 assume !(1 == ~t1_pc~0); 3171#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3172#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3309#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3651#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 3606#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3607#L594 assume 1 == ~t2_pc~0; 3539#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3540#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3538#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3231#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 3232#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3298#L613 assume !(1 == ~t3_pc~0); 3413#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3412#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3762#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4029#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 4030#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3734#L632 assume 1 == ~t4_pc~0; 3735#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4246#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3248#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3249#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 4345#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4108#L651 assume 1 == ~t5_pc~0; 4109#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3425#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3426#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4002#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 3440#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3441#L670 assume !(1 == ~t6_pc~0); 4528#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3792#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3529#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3530#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4073#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4074#L689 assume 1 == ~t7_pc~0; 4702#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4189#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4190#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4543#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 3975#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3976#L708 assume !(1 == ~t8_pc~0); 3534#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3535#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4631#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4619#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 3592#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3593#L727 assume 1 == ~t9_pc~0; 3714#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3300#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3581#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3582#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 4694#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3647#L746 assume !(1 == ~t10_pc~0); 3648#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4300#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4411#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4580#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 4489#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3818#L765 assume 1 == ~t11_pc~0; 3819#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4021#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4638#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4526#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 4527#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4615#L1249 assume !(1 == ~M_E~0); 4250#L1249-2 assume !(1 == ~T1_E~0); 3908#L1254-1 assume !(1 == ~T2_E~0); 3227#L1259-1 assume !(1 == ~T3_E~0); 3209#L1264-1 assume !(1 == ~T4_E~0); 3210#L1269-1 assume !(1 == ~T5_E~0); 4732#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4674#L1279-1 assume !(1 == ~T7_E~0); 3414#L1284-1 assume !(1 == ~T8_E~0); 3415#L1289-1 assume !(1 == ~T9_E~0); 3955#L1294-1 assume !(1 == ~T10_E~0); 3956#L1299-1 assume !(1 == ~T11_E~0); 3965#L1304-1 assume !(1 == ~E_M~0); 4724#L1309-1 assume !(1 == ~E_1~0); 4726#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3363#L1319-1 assume !(1 == ~E_3~0); 3364#L1324-1 assume !(1 == ~E_4~0); 3490#L1329-1 assume !(1 == ~E_5~0); 3491#L1334-1 assume !(1 == ~E_6~0); 4575#L1339-1 assume !(1 == ~E_7~0); 4645#L1344-1 assume !(1 == ~E_8~0); 4646#L1349-1 assume !(1 == ~E_9~0); 4091#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 4092#L1359-1 assume !(1 == ~E_11~0); 4435#L1364-1 assume { :end_inline_reset_delta_events } true; 3578#L1690-2 [2022-12-13 15:05:47,855 INFO L750 eck$LassoCheckResult]: Loop: 3578#L1690-2 assume !false; 3579#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3465#L1096 assume !false; 4442#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3318#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3319#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4343#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3816#L937 assume !(0 != eval_~tmp~0#1); 3817#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3682#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3683#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3789#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4696#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3998#L1131-3 assume !(0 == ~T3_E~0); 3999#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4733#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4346#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3532#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3533#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4641#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4172#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4173#L1171-3 assume !(0 == ~T11_E~0); 4212#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3574#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3575#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4285#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4286#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4467#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4468#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4193#L1211-3 assume !(0 == ~E_7~0); 3486#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3487#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3920#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3547#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3548#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3771#L556-39 assume 1 == ~m_pc~0; 4293#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4264#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4139#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3828#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 3829#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4222#L575-39 assume !(1 == ~t1_pc~0); 4224#L575-41 is_transmit1_triggered_~__retres1~1#1 := 0; 4472#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4473#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4715#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4204#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4205#L594-39 assume !(1 == ~t2_pc~0); 4396#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 4207#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3888#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3889#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3705#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3706#L613-39 assume 1 == ~t3_pc~0; 4598#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3187#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3188#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4403#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3294#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3295#L632-39 assume 1 == ~t4_pc~0; 4561#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3885#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3886#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4046#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4559#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3556#L651-39 assume 1 == ~t5_pc~0; 3557#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3326#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4067#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4068#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4688#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4710#L670-39 assume !(1 == ~t6_pc~0); 4295#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 3233#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3234#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4028#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3916#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3917#L689-39 assume !(1 == ~t7_pc~0); 4035#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 4036#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4052#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4387#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3427#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3428#L708-39 assume 1 == ~t8_pc~0; 3368#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3369#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3966#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4460#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4356#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3857#L727-39 assume !(1 == ~t9_pc~0); 3858#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 3621#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3260#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3261#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 4399#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4400#L746-39 assume 1 == ~t10_pc~0; 4374#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4375#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4637#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4126#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4127#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4517#L765-39 assume 1 == ~t11_pc~0; 3237#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3239#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4093#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3576#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3577#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4165#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3389#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3390#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4640#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4277#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3346#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3347#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4673#L1279-3 assume !(1 == ~T7_E~0); 3833#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3834#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3826#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3827#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4085#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4086#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3732#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3733#L1319-3 assume !(1 == ~E_3~0); 4482#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3453#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3454#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4012#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4013#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4229#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3711#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3712#L1359-3 assume !(1 == ~E_11~0); 4245#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3310#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3311#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3488#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 3489#L1709 assume !(0 == start_simulation_~tmp~3#1); 3740#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4502#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3420#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3197#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 3198#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3387#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4213#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 4590#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 3578#L1690-2 [2022-12-13 15:05:47,855 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:47,856 INFO L85 PathProgramCache]: Analyzing trace with hash 430082112, now seen corresponding path program 2 times [2022-12-13 15:05:47,856 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:47,856 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1667499306] [2022-12-13 15:05:47,856 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:47,856 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:47,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:47,916 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:47,916 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:47,916 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1667499306] [2022-12-13 15:05:47,916 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1667499306] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:47,916 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:47,917 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:47,917 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1072480027] [2022-12-13 15:05:47,917 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:47,918 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:05:47,918 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:47,918 INFO L85 PathProgramCache]: Analyzing trace with hash 368720065, now seen corresponding path program 1 times [2022-12-13 15:05:47,919 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:47,919 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1981567012] [2022-12-13 15:05:47,919 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:47,919 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:47,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:48,001 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:48,001 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:48,002 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1981567012] [2022-12-13 15:05:48,002 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1981567012] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:48,002 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:48,002 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:48,002 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [841664875] [2022-12-13 15:05:48,003 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:48,003 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:05:48,003 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:05:48,004 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:05:48,004 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:05:48,004 INFO L87 Difference]: Start difference. First operand 1571 states and 2334 transitions. cyclomatic complexity: 764 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:48,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:05:48,036 INFO L93 Difference]: Finished difference Result 1571 states and 2333 transitions. [2022-12-13 15:05:48,036 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2333 transitions. [2022-12-13 15:05:48,042 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-12-13 15:05:48,046 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2333 transitions. [2022-12-13 15:05:48,047 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2022-12-13 15:05:48,048 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2022-12-13 15:05:48,048 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2333 transitions. [2022-12-13 15:05:48,049 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:05:48,049 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2333 transitions. [2022-12-13 15:05:48,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2333 transitions. [2022-12-13 15:05:48,065 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2022-12-13 15:05:48,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4850413749204328) internal successors, (2333), 1570 states have internal predecessors, (2333), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:48,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2333 transitions. [2022-12-13 15:05:48,070 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2333 transitions. [2022-12-13 15:05:48,070 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:05:48,071 INFO L428 stractBuchiCegarLoop]: Abstraction has 1571 states and 2333 transitions. [2022-12-13 15:05:48,071 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 15:05:48,071 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2333 transitions. [2022-12-13 15:05:48,076 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-12-13 15:05:48,076 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:05:48,076 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:05:48,077 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:48,078 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:48,078 INFO L748 eck$LassoCheckResult]: Stem: 6544#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 6545#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 7269#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7270#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7408#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 7409#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6405#L797-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 6406#L802-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 7842#L807-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7379#L812-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7380#L817-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7644#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7645#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7743#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7815#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7816#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 7693#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7543#L1121 assume !(0 == ~M_E~0); 7320#L1121-2 assume !(0 == ~T1_E~0); 6685#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6686#L1131-1 assume !(0 == ~T3_E~0); 6853#L1136-1 assume !(0 == ~T4_E~0); 6958#L1141-1 assume !(0 == ~T5_E~0); 7180#L1146-1 assume !(0 == ~T6_E~0); 7475#L1151-1 assume !(0 == ~T7_E~0); 7022#L1156-1 assume !(0 == ~T8_E~0); 6391#L1161-1 assume !(0 == ~T9_E~0); 6392#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6615#L1171-1 assume !(0 == ~T11_E~0); 6616#L1176-1 assume !(0 == ~E_M~0); 7488#L1181-1 assume !(0 == ~E_1~0); 7607#L1186-1 assume !(0 == ~E_2~0); 7657#L1191-1 assume !(0 == ~E_3~0); 6646#L1196-1 assume !(0 == ~E_4~0); 6647#L1201-1 assume !(0 == ~E_5~0); 7856#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 7694#L1211-1 assume !(0 == ~E_7~0); 7695#L1216-1 assume !(0 == ~E_8~0); 6786#L1221-1 assume !(0 == ~E_9~0); 6787#L1226-1 assume !(0 == ~E_10~0); 6491#L1231-1 assume !(0 == ~E_11~0); 6492#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7489#L556 assume 1 == ~m_pc~0; 7490#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6365#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6366#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7154#L1391 assume !(0 != activate_threads_~tmp~1#1); 7634#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7635#L575 assume !(1 == ~t1_pc~0); 6320#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6321#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6458#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6800#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 6755#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6756#L594 assume 1 == ~t2_pc~0; 6688#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6689#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6687#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6380#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 6381#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6447#L613 assume !(1 == ~t3_pc~0); 6562#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6561#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6911#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7178#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 7179#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6883#L632 assume 1 == ~t4_pc~0; 6884#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7395#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6397#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6398#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 7494#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7257#L651 assume 1 == ~t5_pc~0; 7258#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6574#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6575#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7151#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 6589#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6590#L670 assume !(1 == ~t6_pc~0); 7677#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6941#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6678#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6679#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7222#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7223#L689 assume 1 == ~t7_pc~0; 7851#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7338#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7339#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7692#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 7124#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7125#L708 assume !(1 == ~t8_pc~0); 6683#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 6684#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7780#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7768#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 6741#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6742#L727 assume 1 == ~t9_pc~0; 6863#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6449#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6730#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6731#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 7843#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6796#L746 assume !(1 == ~t10_pc~0); 6797#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 7449#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7560#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7729#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 7638#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6967#L765 assume 1 == ~t11_pc~0; 6968#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7170#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7787#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 7675#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 7676#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7764#L1249 assume !(1 == ~M_E~0); 7399#L1249-2 assume !(1 == ~T1_E~0); 7057#L1254-1 assume !(1 == ~T2_E~0); 6376#L1259-1 assume !(1 == ~T3_E~0); 6358#L1264-1 assume !(1 == ~T4_E~0); 6359#L1269-1 assume !(1 == ~T5_E~0); 7881#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7823#L1279-1 assume !(1 == ~T7_E~0); 6563#L1284-1 assume !(1 == ~T8_E~0); 6564#L1289-1 assume !(1 == ~T9_E~0); 7104#L1294-1 assume !(1 == ~T10_E~0); 7105#L1299-1 assume !(1 == ~T11_E~0); 7114#L1304-1 assume !(1 == ~E_M~0); 7873#L1309-1 assume !(1 == ~E_1~0); 7875#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6512#L1319-1 assume !(1 == ~E_3~0); 6513#L1324-1 assume !(1 == ~E_4~0); 6639#L1329-1 assume !(1 == ~E_5~0); 6640#L1334-1 assume !(1 == ~E_6~0); 7724#L1339-1 assume !(1 == ~E_7~0); 7794#L1344-1 assume !(1 == ~E_8~0); 7795#L1349-1 assume !(1 == ~E_9~0); 7240#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 7241#L1359-1 assume !(1 == ~E_11~0); 7584#L1364-1 assume { :end_inline_reset_delta_events } true; 6727#L1690-2 [2022-12-13 15:05:48,078 INFO L750 eck$LassoCheckResult]: Loop: 6727#L1690-2 assume !false; 6728#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6614#L1096 assume !false; 7591#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 6467#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6468#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 7492#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 6965#L937 assume !(0 != eval_~tmp~0#1); 6966#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6831#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6832#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6938#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7845#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7147#L1131-3 assume !(0 == ~T3_E~0); 7148#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7882#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7495#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6681#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6682#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7790#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7321#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 7322#L1171-3 assume !(0 == ~T11_E~0); 7361#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6723#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6724#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7434#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7435#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7616#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7617#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7342#L1211-3 assume !(0 == ~E_7~0); 6635#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6636#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 7069#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6696#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 6697#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6920#L556-39 assume 1 == ~m_pc~0; 7442#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7413#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7288#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6977#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 6978#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7371#L575-39 assume 1 == ~t1_pc~0; 7372#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7621#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7622#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7864#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7353#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7354#L594-39 assume !(1 == ~t2_pc~0); 7545#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 7356#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7037#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7038#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6854#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6855#L613-39 assume 1 == ~t3_pc~0; 7747#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6336#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6337#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7552#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6443#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6444#L632-39 assume !(1 == ~t4_pc~0); 7585#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 7034#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7035#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7195#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7708#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6705#L651-39 assume 1 == ~t5_pc~0; 6706#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6475#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7216#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7217#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7837#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7859#L670-39 assume !(1 == ~t6_pc~0); 7444#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 6382#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6383#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7177#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7065#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7066#L689-39 assume !(1 == ~t7_pc~0); 7184#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 7185#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7201#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7536#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6576#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6577#L708-39 assume 1 == ~t8_pc~0; 6517#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6518#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7115#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7609#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7505#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7006#L727-39 assume 1 == ~t9_pc~0; 7008#L728-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6770#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6409#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6410#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 7548#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7549#L746-39 assume 1 == ~t10_pc~0; 7523#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7524#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7786#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7275#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 7276#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7666#L765-39 assume 1 == ~t11_pc~0; 6386#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 6388#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7242#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 6725#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 6726#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7314#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6538#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6539#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7789#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7426#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6495#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6496#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7822#L1279-3 assume !(1 == ~T7_E~0); 6982#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6983#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6975#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6976#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 7234#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7235#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6881#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6882#L1319-3 assume !(1 == ~E_3~0); 7631#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6602#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6603#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7161#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7162#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7378#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6860#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 6861#L1359-3 assume !(1 == ~E_11~0); 7394#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 6459#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6460#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6637#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 6638#L1709 assume !(0 == start_simulation_~tmp~3#1); 6889#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7651#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6569#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6346#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 6347#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6536#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7362#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 7739#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 6727#L1690-2 [2022-12-13 15:05:48,079 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:48,079 INFO L85 PathProgramCache]: Analyzing trace with hash -968871490, now seen corresponding path program 1 times [2022-12-13 15:05:48,079 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:48,079 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [188583165] [2022-12-13 15:05:48,079 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:48,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:48,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:48,118 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:48,118 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:48,118 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [188583165] [2022-12-13 15:05:48,118 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [188583165] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:48,118 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:48,119 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:48,119 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [199922202] [2022-12-13 15:05:48,119 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:48,119 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:05:48,120 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:48,120 INFO L85 PathProgramCache]: Analyzing trace with hash -2055718272, now seen corresponding path program 1 times [2022-12-13 15:05:48,120 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:48,120 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [623612389] [2022-12-13 15:05:48,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:48,121 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:48,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:48,209 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:48,209 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:48,210 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [623612389] [2022-12-13 15:05:48,210 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [623612389] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:48,210 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:48,210 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:48,210 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [820685532] [2022-12-13 15:05:48,210 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:48,211 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:05:48,211 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:05:48,211 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:05:48,212 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:05:48,212 INFO L87 Difference]: Start difference. First operand 1571 states and 2333 transitions. cyclomatic complexity: 763 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:48,239 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:05:48,239 INFO L93 Difference]: Finished difference Result 1571 states and 2332 transitions. [2022-12-13 15:05:48,239 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2332 transitions. [2022-12-13 15:05:48,245 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-12-13 15:05:48,249 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2332 transitions. [2022-12-13 15:05:48,249 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2022-12-13 15:05:48,250 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2022-12-13 15:05:48,250 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2332 transitions. [2022-12-13 15:05:48,252 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:05:48,252 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2332 transitions. [2022-12-13 15:05:48,254 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2332 transitions. [2022-12-13 15:05:48,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2022-12-13 15:05:48,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4844048376830044) internal successors, (2332), 1570 states have internal predecessors, (2332), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:48,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2332 transitions. [2022-12-13 15:05:48,270 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2332 transitions. [2022-12-13 15:05:48,271 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:05:48,271 INFO L428 stractBuchiCegarLoop]: Abstraction has 1571 states and 2332 transitions. [2022-12-13 15:05:48,271 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 15:05:48,271 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2332 transitions. [2022-12-13 15:05:48,276 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-12-13 15:05:48,276 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:05:48,276 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:05:48,277 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:48,277 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:48,278 INFO L748 eck$LassoCheckResult]: Stem: 9693#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 9694#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 10421#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10422#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10557#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 10558#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9558#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9559#L802-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 10991#L807-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10528#L812-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10529#L817-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10793#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10794#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10892#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 10964#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10965#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 10842#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10692#L1121 assume !(0 == ~M_E~0); 10469#L1121-2 assume !(0 == ~T1_E~0); 9834#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9835#L1131-1 assume !(0 == ~T3_E~0); 10002#L1136-1 assume !(0 == ~T4_E~0); 10107#L1141-1 assume !(0 == ~T5_E~0); 10334#L1146-1 assume !(0 == ~T6_E~0); 10624#L1151-1 assume !(0 == ~T7_E~0); 10171#L1156-1 assume !(0 == ~T8_E~0); 9540#L1161-1 assume !(0 == ~T9_E~0); 9541#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9764#L1171-1 assume !(0 == ~T11_E~0); 9765#L1176-1 assume !(0 == ~E_M~0); 10637#L1181-1 assume !(0 == ~E_1~0); 10756#L1186-1 assume !(0 == ~E_2~0); 10806#L1191-1 assume !(0 == ~E_3~0); 9795#L1196-1 assume !(0 == ~E_4~0); 9796#L1201-1 assume !(0 == ~E_5~0); 11005#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 10843#L1211-1 assume !(0 == ~E_7~0); 10844#L1216-1 assume !(0 == ~E_8~0); 9938#L1221-1 assume !(0 == ~E_9~0); 9939#L1226-1 assume !(0 == ~E_10~0); 9640#L1231-1 assume !(0 == ~E_11~0); 9641#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10639#L556 assume 1 == ~m_pc~0; 10640#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9514#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9515#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10303#L1391 assume !(0 != activate_threads_~tmp~1#1); 10784#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10785#L575 assume !(1 == ~t1_pc~0); 9469#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9470#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9607#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9951#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 9904#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9905#L594 assume 1 == ~t2_pc~0; 9837#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9838#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9836#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9531#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 9532#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9596#L613 assume !(1 == ~t3_pc~0); 9711#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9710#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10060#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10327#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 10328#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10032#L632 assume 1 == ~t4_pc~0; 10033#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10544#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9550#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9551#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 10643#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10406#L651 assume 1 == ~t5_pc~0; 10407#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9723#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9724#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10300#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 9738#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9739#L670 assume !(1 == ~t6_pc~0); 10827#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10095#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9828#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9829#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10373#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10374#L689 assume 1 == ~t7_pc~0; 11000#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10487#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10488#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10841#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 10273#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10274#L708 assume !(1 == ~t8_pc~0); 9832#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 9833#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10930#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10917#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 9890#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9891#L727 assume 1 == ~t9_pc~0; 10012#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9598#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9879#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9880#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 10993#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9946#L746 assume !(1 == ~t10_pc~0); 9947#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 10598#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10709#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10878#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 10787#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10119#L765 assume 1 == ~t11_pc~0; 10120#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10319#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10936#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 10824#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 10825#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10913#L1249 assume !(1 == ~M_E~0); 10549#L1249-2 assume !(1 == ~T1_E~0); 10206#L1254-1 assume !(1 == ~T2_E~0); 9525#L1259-1 assume !(1 == ~T3_E~0); 9507#L1264-1 assume !(1 == ~T4_E~0); 9508#L1269-1 assume !(1 == ~T5_E~0); 11030#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10972#L1279-1 assume !(1 == ~T7_E~0); 9712#L1284-1 assume !(1 == ~T8_E~0); 9713#L1289-1 assume !(1 == ~T9_E~0); 10253#L1294-1 assume !(1 == ~T10_E~0); 10254#L1299-1 assume !(1 == ~T11_E~0); 10263#L1304-1 assume !(1 == ~E_M~0); 11022#L1309-1 assume !(1 == ~E_1~0); 11024#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 9661#L1319-1 assume !(1 == ~E_3~0); 9662#L1324-1 assume !(1 == ~E_4~0); 9788#L1329-1 assume !(1 == ~E_5~0); 9789#L1334-1 assume !(1 == ~E_6~0); 10873#L1339-1 assume !(1 == ~E_7~0); 10943#L1344-1 assume !(1 == ~E_8~0); 10944#L1349-1 assume !(1 == ~E_9~0); 10390#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 10391#L1359-1 assume !(1 == ~E_11~0); 10733#L1364-1 assume { :end_inline_reset_delta_events } true; 9877#L1690-2 [2022-12-13 15:05:48,278 INFO L750 eck$LassoCheckResult]: Loop: 9877#L1690-2 assume !false; 9878#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9763#L1096 assume !false; 10740#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 9616#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9617#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 10642#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 10114#L937 assume !(0 != eval_~tmp~0#1); 10115#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9980#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9981#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10089#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10994#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10296#L1131-3 assume !(0 == ~T3_E~0); 10297#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11031#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10644#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9830#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9831#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10939#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10470#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 10471#L1171-3 assume !(0 == ~T11_E~0); 10510#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9872#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9873#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10583#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10584#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10765#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10766#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10491#L1211-3 assume !(0 == ~E_7~0); 9784#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9785#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 10218#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9845#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 9846#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10069#L556-39 assume !(1 == ~m_pc~0); 10592#L556-41 is_master_triggered_~__retres1~0#1 := 0; 10562#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10437#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10126#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 10127#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10520#L575-39 assume 1 == ~t1_pc~0; 10521#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10770#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10771#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11013#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10502#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10503#L594-39 assume !(1 == ~t2_pc~0); 10694#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 10505#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10186#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10187#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10003#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10004#L613-39 assume 1 == ~t3_pc~0; 10896#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9485#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9486#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10701#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9592#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9593#L632-39 assume 1 == ~t4_pc~0; 10859#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10183#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10184#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10344#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10857#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9854#L651-39 assume !(1 == ~t5_pc~0); 9623#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 9624#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10365#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10366#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10986#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11008#L670-39 assume !(1 == ~t6_pc~0); 10593#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 9529#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9530#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10326#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10214#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10215#L689-39 assume 1 == ~t7_pc~0; 10436#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10333#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10350#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10685#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9725#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9726#L708-39 assume 1 == ~t8_pc~0; 9666#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9667#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10264#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10758#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10654#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10155#L727-39 assume !(1 == ~t9_pc~0); 10156#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 9919#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9556#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9557#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 10697#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10698#L746-39 assume 1 == ~t10_pc~0; 10672#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 10673#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10935#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10424#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 10425#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10815#L765-39 assume !(1 == ~t11_pc~0); 9536#L765-41 is_transmit11_triggered_~__retres1~11#1 := 0; 9537#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10389#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9874#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 9875#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10463#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9687#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9688#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10938#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10575#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9644#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9645#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10971#L1279-3 assume !(1 == ~T7_E~0); 10131#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10132#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10124#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 10125#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 10383#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10384#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10027#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10028#L1319-3 assume !(1 == ~E_3~0); 10780#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9748#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9749#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10310#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10311#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10527#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10009#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 10010#L1359-3 assume !(1 == ~E_11~0); 10543#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 9608#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9609#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9786#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 9787#L1709 assume !(0 == start_simulation_~tmp~3#1); 10038#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10800#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9718#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9495#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 9496#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9685#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10511#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 10888#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 9877#L1690-2 [2022-12-13 15:05:48,279 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:48,279 INFO L85 PathProgramCache]: Analyzing trace with hash -1332337988, now seen corresponding path program 1 times [2022-12-13 15:05:48,279 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:48,279 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1083646191] [2022-12-13 15:05:48,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:48,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:48,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:48,318 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:48,319 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:48,319 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1083646191] [2022-12-13 15:05:48,319 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1083646191] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:48,319 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:48,319 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:48,320 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1487609455] [2022-12-13 15:05:48,320 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:48,320 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:05:48,321 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:48,321 INFO L85 PathProgramCache]: Analyzing trace with hash 207708290, now seen corresponding path program 1 times [2022-12-13 15:05:48,321 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:48,321 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1701031808] [2022-12-13 15:05:48,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:48,322 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:48,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:48,376 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:48,376 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:48,376 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1701031808] [2022-12-13 15:05:48,376 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1701031808] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:48,377 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:48,377 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:48,377 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [561614845] [2022-12-13 15:05:48,377 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:48,377 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:05:48,378 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:05:48,378 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:05:48,378 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:05:48,378 INFO L87 Difference]: Start difference. First operand 1571 states and 2332 transitions. cyclomatic complexity: 762 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:48,416 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:05:48,416 INFO L93 Difference]: Finished difference Result 1571 states and 2331 transitions. [2022-12-13 15:05:48,416 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2331 transitions. [2022-12-13 15:05:48,425 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-12-13 15:05:48,434 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2331 transitions. [2022-12-13 15:05:48,435 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2022-12-13 15:05:48,436 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2022-12-13 15:05:48,436 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2331 transitions. [2022-12-13 15:05:48,451 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:05:48,451 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2331 transitions. [2022-12-13 15:05:48,453 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2331 transitions. [2022-12-13 15:05:48,467 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2022-12-13 15:05:48,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4837683004455762) internal successors, (2331), 1570 states have internal predecessors, (2331), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:48,473 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2331 transitions. [2022-12-13 15:05:48,473 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2331 transitions. [2022-12-13 15:05:48,473 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:05:48,474 INFO L428 stractBuchiCegarLoop]: Abstraction has 1571 states and 2331 transitions. [2022-12-13 15:05:48,474 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 15:05:48,474 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2331 transitions. [2022-12-13 15:05:48,480 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-12-13 15:05:48,480 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:05:48,480 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:05:48,482 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:48,482 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:48,483 INFO L748 eck$LassoCheckResult]: Stem: 12842#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 12843#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 13567#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13568#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13706#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 13707#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12705#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12706#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14140#L807-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13677#L812-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13678#L817-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13942#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 13943#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14041#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14113#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 14114#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 13991#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13841#L1121 assume !(0 == ~M_E~0); 13618#L1121-2 assume !(0 == ~T1_E~0); 12983#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12984#L1131-1 assume !(0 == ~T3_E~0); 13151#L1136-1 assume !(0 == ~T4_E~0); 13256#L1141-1 assume !(0 == ~T5_E~0); 13478#L1146-1 assume !(0 == ~T6_E~0); 13773#L1151-1 assume !(0 == ~T7_E~0); 13320#L1156-1 assume !(0 == ~T8_E~0); 12689#L1161-1 assume !(0 == ~T9_E~0); 12690#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12913#L1171-1 assume !(0 == ~T11_E~0); 12914#L1176-1 assume !(0 == ~E_M~0); 13786#L1181-1 assume !(0 == ~E_1~0); 13905#L1186-1 assume !(0 == ~E_2~0); 13955#L1191-1 assume !(0 == ~E_3~0); 12944#L1196-1 assume !(0 == ~E_4~0); 12945#L1201-1 assume !(0 == ~E_5~0); 14154#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 13992#L1211-1 assume !(0 == ~E_7~0); 13993#L1216-1 assume !(0 == ~E_8~0); 13084#L1221-1 assume !(0 == ~E_9~0); 13085#L1226-1 assume !(0 == ~E_10~0); 12789#L1231-1 assume !(0 == ~E_11~0); 12790#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13787#L556 assume 1 == ~m_pc~0; 13788#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12663#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12664#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13452#L1391 assume !(0 != activate_threads_~tmp~1#1); 13932#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13933#L575 assume !(1 == ~t1_pc~0); 12618#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12619#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12756#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13098#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 13053#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13054#L594 assume 1 == ~t2_pc~0; 12986#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12987#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12985#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12678#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 12679#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12745#L613 assume !(1 == ~t3_pc~0); 12860#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12859#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13209#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13476#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 13477#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13181#L632 assume 1 == ~t4_pc~0; 13182#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13693#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12695#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12696#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 13792#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13555#L651 assume 1 == ~t5_pc~0; 13556#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12872#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12873#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13449#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 12887#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12888#L670 assume !(1 == ~t6_pc~0); 13975#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 13239#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12976#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12977#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13520#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13521#L689 assume 1 == ~t7_pc~0; 14149#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13636#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13637#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13990#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 13422#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13423#L708 assume !(1 == ~t8_pc~0); 12981#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12982#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14078#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14066#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 13039#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13040#L727 assume 1 == ~t9_pc~0; 13161#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12747#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13028#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13029#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 14141#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13094#L746 assume !(1 == ~t10_pc~0); 13095#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 13747#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13858#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14027#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 13936#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13265#L765 assume 1 == ~t11_pc~0; 13266#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 13468#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14085#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13973#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 13974#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14062#L1249 assume !(1 == ~M_E~0); 13697#L1249-2 assume !(1 == ~T1_E~0); 13355#L1254-1 assume !(1 == ~T2_E~0); 12674#L1259-1 assume !(1 == ~T3_E~0); 12656#L1264-1 assume !(1 == ~T4_E~0); 12657#L1269-1 assume !(1 == ~T5_E~0); 14179#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14121#L1279-1 assume !(1 == ~T7_E~0); 12861#L1284-1 assume !(1 == ~T8_E~0); 12862#L1289-1 assume !(1 == ~T9_E~0); 13402#L1294-1 assume !(1 == ~T10_E~0); 13403#L1299-1 assume !(1 == ~T11_E~0); 13412#L1304-1 assume !(1 == ~E_M~0); 14171#L1309-1 assume !(1 == ~E_1~0); 14173#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 12810#L1319-1 assume !(1 == ~E_3~0); 12811#L1324-1 assume !(1 == ~E_4~0); 12937#L1329-1 assume !(1 == ~E_5~0); 12938#L1334-1 assume !(1 == ~E_6~0); 14022#L1339-1 assume !(1 == ~E_7~0); 14092#L1344-1 assume !(1 == ~E_8~0); 14093#L1349-1 assume !(1 == ~E_9~0); 13539#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 13540#L1359-1 assume !(1 == ~E_11~0); 13882#L1364-1 assume { :end_inline_reset_delta_events } true; 13025#L1690-2 [2022-12-13 15:05:48,483 INFO L750 eck$LassoCheckResult]: Loop: 13025#L1690-2 assume !false; 13026#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12912#L1096 assume !false; 13889#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 12765#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12766#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 13790#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 13263#L937 assume !(0 != eval_~tmp~0#1); 13264#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13129#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13130#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13238#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14143#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13445#L1131-3 assume !(0 == ~T3_E~0); 13446#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14180#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13793#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12979#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12980#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14088#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13619#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13620#L1171-3 assume !(0 == ~T11_E~0); 13660#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13021#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13022#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13732#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13733#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13914#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13915#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13640#L1211-3 assume !(0 == ~E_7~0); 12933#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12934#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 13367#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12994#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 12995#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13218#L556-39 assume 1 == ~m_pc~0; 13740#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13711#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13586#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13275#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 13276#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13669#L575-39 assume 1 == ~t1_pc~0; 13670#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13919#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13920#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14162#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13651#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13652#L594-39 assume !(1 == ~t2_pc~0); 13843#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 13654#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13335#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13336#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13152#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13153#L613-39 assume 1 == ~t3_pc~0; 14045#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12634#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12635#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13852#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12741#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12742#L632-39 assume 1 == ~t4_pc~0; 14008#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13332#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13333#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13493#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14006#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13003#L651-39 assume !(1 == ~t5_pc~0); 12772#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 12773#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13514#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13515#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14135#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14157#L670-39 assume !(1 == ~t6_pc~0); 13742#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 12680#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12681#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13475#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13363#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13364#L689-39 assume 1 == ~t7_pc~0; 13585#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13483#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13499#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13834#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12874#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12875#L708-39 assume !(1 == ~t8_pc~0); 12817#L708-41 is_transmit8_triggered_~__retres1~8#1 := 0; 12816#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13413#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13907#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13803#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13303#L727-39 assume !(1 == ~t9_pc~0); 13304#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 13068#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12703#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12704#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 13845#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13846#L746-39 assume 1 == ~t10_pc~0; 13821#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13822#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14084#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13572#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13573#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13964#L765-39 assume 1 == ~t11_pc~0; 12684#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 12686#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13538#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13023#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 13024#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13612#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12835#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12836#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14087#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13724#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12793#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12794#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14120#L1279-3 assume !(1 == ~T7_E~0); 13280#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13281#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13271#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13272#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13532#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13533#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13175#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13176#L1319-3 assume !(1 == ~E_3~0); 13929#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12894#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12895#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13459#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13460#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13676#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13158#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 13159#L1359-3 assume !(1 == ~E_11~0); 13692#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 12757#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12758#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12935#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 12936#L1709 assume !(0 == start_simulation_~tmp~3#1); 13187#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13949#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12867#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12644#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 12645#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12834#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13659#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 14037#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 13025#L1690-2 [2022-12-13 15:05:48,484 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:48,484 INFO L85 PathProgramCache]: Analyzing trace with hash -1621157378, now seen corresponding path program 1 times [2022-12-13 15:05:48,484 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:48,484 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [382772040] [2022-12-13 15:05:48,485 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:48,485 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:48,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:48,526 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:48,526 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:48,526 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [382772040] [2022-12-13 15:05:48,527 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [382772040] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:48,527 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:48,527 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:48,527 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1999484921] [2022-12-13 15:05:48,527 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:48,528 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:05:48,528 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:48,528 INFO L85 PathProgramCache]: Analyzing trace with hash 302317697, now seen corresponding path program 1 times [2022-12-13 15:05:48,528 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:48,529 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [159231590] [2022-12-13 15:05:48,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:48,529 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:48,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:48,580 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:48,580 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:48,580 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [159231590] [2022-12-13 15:05:48,581 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [159231590] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:48,581 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:48,581 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:48,581 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1589334272] [2022-12-13 15:05:48,581 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:48,581 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:05:48,582 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:05:48,582 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:05:48,582 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:05:48,582 INFO L87 Difference]: Start difference. First operand 1571 states and 2331 transitions. cyclomatic complexity: 761 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:48,609 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:05:48,609 INFO L93 Difference]: Finished difference Result 1571 states and 2330 transitions. [2022-12-13 15:05:48,609 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2330 transitions. [2022-12-13 15:05:48,615 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-12-13 15:05:48,619 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2330 transitions. [2022-12-13 15:05:48,619 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2022-12-13 15:05:48,620 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2022-12-13 15:05:48,620 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2330 transitions. [2022-12-13 15:05:48,621 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:05:48,621 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2330 transitions. [2022-12-13 15:05:48,623 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2330 transitions. [2022-12-13 15:05:48,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2022-12-13 15:05:48,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4831317632081478) internal successors, (2330), 1570 states have internal predecessors, (2330), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:48,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2330 transitions. [2022-12-13 15:05:48,639 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2330 transitions. [2022-12-13 15:05:48,640 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:05:48,640 INFO L428 stractBuchiCegarLoop]: Abstraction has 1571 states and 2330 transitions. [2022-12-13 15:05:48,640 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 15:05:48,640 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2330 transitions. [2022-12-13 15:05:48,648 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-12-13 15:05:48,648 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:05:48,648 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:05:48,649 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:48,649 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:48,650 INFO L748 eck$LassoCheckResult]: Stem: 15991#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 15992#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 16716#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16717#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16855#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 16856#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15852#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15853#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17289#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16826#L812-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 16827#L817-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17091#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17092#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17190#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17262#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17263#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17140#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16990#L1121 assume !(0 == ~M_E~0); 16767#L1121-2 assume !(0 == ~T1_E~0); 16132#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16133#L1131-1 assume !(0 == ~T3_E~0); 16300#L1136-1 assume !(0 == ~T4_E~0); 16405#L1141-1 assume !(0 == ~T5_E~0); 16627#L1146-1 assume !(0 == ~T6_E~0); 16922#L1151-1 assume !(0 == ~T7_E~0); 16469#L1156-1 assume !(0 == ~T8_E~0); 15838#L1161-1 assume !(0 == ~T9_E~0); 15839#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16062#L1171-1 assume !(0 == ~T11_E~0); 16063#L1176-1 assume !(0 == ~E_M~0); 16935#L1181-1 assume !(0 == ~E_1~0); 17054#L1186-1 assume !(0 == ~E_2~0); 17104#L1191-1 assume !(0 == ~E_3~0); 16093#L1196-1 assume !(0 == ~E_4~0); 16094#L1201-1 assume !(0 == ~E_5~0); 17303#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 17141#L1211-1 assume !(0 == ~E_7~0); 17142#L1216-1 assume !(0 == ~E_8~0); 16233#L1221-1 assume !(0 == ~E_9~0); 16234#L1226-1 assume !(0 == ~E_10~0); 15938#L1231-1 assume !(0 == ~E_11~0); 15939#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16936#L556 assume 1 == ~m_pc~0; 16937#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15812#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15813#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16601#L1391 assume !(0 != activate_threads_~tmp~1#1); 17081#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17082#L575 assume !(1 == ~t1_pc~0); 15767#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15768#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15905#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16247#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 16202#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16203#L594 assume 1 == ~t2_pc~0; 16135#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16136#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16134#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15827#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 15828#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15894#L613 assume !(1 == ~t3_pc~0); 16009#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16008#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16358#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16625#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 16626#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16330#L632 assume 1 == ~t4_pc~0; 16331#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16842#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15844#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15845#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 16941#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16704#L651 assume 1 == ~t5_pc~0; 16705#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16021#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16022#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16598#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 16036#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16037#L670 assume !(1 == ~t6_pc~0); 17124#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16388#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16125#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16126#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16669#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16670#L689 assume 1 == ~t7_pc~0; 17298#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16785#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16786#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17139#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 16571#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16572#L708 assume !(1 == ~t8_pc~0); 16130#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16131#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17227#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17215#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 16188#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16189#L727 assume 1 == ~t9_pc~0; 16310#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15896#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16177#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16178#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 17290#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16243#L746 assume !(1 == ~t10_pc~0); 16244#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 16896#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17007#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17176#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 17085#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16414#L765 assume 1 == ~t11_pc~0; 16415#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 16617#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17234#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17122#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 17123#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17211#L1249 assume !(1 == ~M_E~0); 16846#L1249-2 assume !(1 == ~T1_E~0); 16504#L1254-1 assume !(1 == ~T2_E~0); 15823#L1259-1 assume !(1 == ~T3_E~0); 15805#L1264-1 assume !(1 == ~T4_E~0); 15806#L1269-1 assume !(1 == ~T5_E~0); 17328#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17270#L1279-1 assume !(1 == ~T7_E~0); 16010#L1284-1 assume !(1 == ~T8_E~0); 16011#L1289-1 assume !(1 == ~T9_E~0); 16551#L1294-1 assume !(1 == ~T10_E~0); 16552#L1299-1 assume !(1 == ~T11_E~0); 16561#L1304-1 assume !(1 == ~E_M~0); 17320#L1309-1 assume !(1 == ~E_1~0); 17322#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 15959#L1319-1 assume !(1 == ~E_3~0); 15960#L1324-1 assume !(1 == ~E_4~0); 16086#L1329-1 assume !(1 == ~E_5~0); 16087#L1334-1 assume !(1 == ~E_6~0); 17171#L1339-1 assume !(1 == ~E_7~0); 17241#L1344-1 assume !(1 == ~E_8~0); 17242#L1349-1 assume !(1 == ~E_9~0); 16687#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 16688#L1359-1 assume !(1 == ~E_11~0); 17031#L1364-1 assume { :end_inline_reset_delta_events } true; 16174#L1690-2 [2022-12-13 15:05:48,650 INFO L750 eck$LassoCheckResult]: Loop: 16174#L1690-2 assume !false; 16175#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16061#L1096 assume !false; 17038#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 15914#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15915#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16939#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16412#L937 assume !(0 != eval_~tmp~0#1); 16413#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16278#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16279#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16385#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17292#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16594#L1131-3 assume !(0 == ~T3_E~0); 16595#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17329#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16942#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16128#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16129#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17237#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16768#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16769#L1171-3 assume !(0 == ~T11_E~0); 16808#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16170#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16171#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16881#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16882#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17063#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17064#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16789#L1211-3 assume !(0 == ~E_7~0); 16082#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16083#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 16516#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16143#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16144#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16367#L556-39 assume 1 == ~m_pc~0; 16889#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16860#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16735#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16424#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 16425#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16818#L575-39 assume 1 == ~t1_pc~0; 16819#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17068#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17069#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17311#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16800#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16801#L594-39 assume !(1 == ~t2_pc~0); 16992#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 16803#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16484#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16485#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16301#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16302#L613-39 assume 1 == ~t3_pc~0; 17194#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15783#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15784#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16999#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15890#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15891#L632-39 assume 1 == ~t4_pc~0; 17157#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16481#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16482#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16642#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17155#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16152#L651-39 assume !(1 == ~t5_pc~0); 15921#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 15922#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16663#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16664#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17284#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17306#L670-39 assume !(1 == ~t6_pc~0); 16891#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 15829#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15830#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16624#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16512#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16513#L689-39 assume !(1 == ~t7_pc~0); 16631#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 16632#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16648#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16983#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16023#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16024#L708-39 assume 1 == ~t8_pc~0; 15964#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15965#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16562#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17056#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16952#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16453#L727-39 assume !(1 == ~t9_pc~0); 16454#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 16217#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15856#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15857#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 16995#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16996#L746-39 assume 1 == ~t10_pc~0; 16970#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16971#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17233#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16722#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16723#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17113#L765-39 assume 1 == ~t11_pc~0; 15833#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15835#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16689#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16172#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 16173#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16761#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15985#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15986#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17236#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16873#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15942#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15943#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17269#L1279-3 assume !(1 == ~T7_E~0); 16429#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16430#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16422#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16423#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 16681#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16682#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16328#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16329#L1319-3 assume !(1 == ~E_3~0); 17078#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16049#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16050#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16608#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16609#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16825#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 16307#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16308#L1359-3 assume !(1 == ~E_11~0); 16841#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 15906#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15907#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16084#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 16085#L1709 assume !(0 == start_simulation_~tmp~3#1); 16336#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 17098#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 16016#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 15793#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 15794#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15983#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16809#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 17186#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 16174#L1690-2 [2022-12-13 15:05:48,651 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:48,651 INFO L85 PathProgramCache]: Analyzing trace with hash -1076284804, now seen corresponding path program 1 times [2022-12-13 15:05:48,651 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:48,651 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [16993600] [2022-12-13 15:05:48,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:48,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:48,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:48,683 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:48,683 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:48,683 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [16993600] [2022-12-13 15:05:48,683 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [16993600] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:48,683 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:48,684 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:48,684 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1181632511] [2022-12-13 15:05:48,684 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:48,684 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:05:48,685 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:48,685 INFO L85 PathProgramCache]: Analyzing trace with hash 1411279809, now seen corresponding path program 1 times [2022-12-13 15:05:48,685 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:48,685 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1085750249] [2022-12-13 15:05:48,685 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:48,685 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:48,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:48,735 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:48,735 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:48,735 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1085750249] [2022-12-13 15:05:48,735 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1085750249] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:48,736 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:48,736 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:48,736 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1093080838] [2022-12-13 15:05:48,736 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:48,736 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:05:48,736 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:05:48,737 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:05:48,737 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:05:48,737 INFO L87 Difference]: Start difference. First operand 1571 states and 2330 transitions. cyclomatic complexity: 760 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:48,763 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:05:48,763 INFO L93 Difference]: Finished difference Result 1571 states and 2329 transitions. [2022-12-13 15:05:48,763 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2329 transitions. [2022-12-13 15:05:48,767 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-12-13 15:05:48,771 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2329 transitions. [2022-12-13 15:05:48,771 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2022-12-13 15:05:48,772 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2022-12-13 15:05:48,772 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2329 transitions. [2022-12-13 15:05:48,773 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:05:48,774 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2329 transitions. [2022-12-13 15:05:48,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2329 transitions. [2022-12-13 15:05:48,787 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2022-12-13 15:05:48,789 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4824952259707194) internal successors, (2329), 1570 states have internal predecessors, (2329), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:48,791 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2329 transitions. [2022-12-13 15:05:48,791 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2329 transitions. [2022-12-13 15:05:48,791 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:05:48,792 INFO L428 stractBuchiCegarLoop]: Abstraction has 1571 states and 2329 transitions. [2022-12-13 15:05:48,792 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 15:05:48,792 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2329 transitions. [2022-12-13 15:05:48,795 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-12-13 15:05:48,795 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:05:48,795 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:05:48,797 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:48,797 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:48,797 INFO L748 eck$LassoCheckResult]: Stem: 19140#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 19141#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 19865#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19866#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20004#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 20005#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19001#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19002#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20438#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19975#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19976#L817-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 20240#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20241#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 20339#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20411#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20412#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 20289#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20139#L1121 assume !(0 == ~M_E~0); 19916#L1121-2 assume !(0 == ~T1_E~0); 19281#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19282#L1131-1 assume !(0 == ~T3_E~0); 19449#L1136-1 assume !(0 == ~T4_E~0); 19554#L1141-1 assume !(0 == ~T5_E~0); 19776#L1146-1 assume !(0 == ~T6_E~0); 20071#L1151-1 assume !(0 == ~T7_E~0); 19618#L1156-1 assume !(0 == ~T8_E~0); 18987#L1161-1 assume !(0 == ~T9_E~0); 18988#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19211#L1171-1 assume !(0 == ~T11_E~0); 19212#L1176-1 assume !(0 == ~E_M~0); 20084#L1181-1 assume !(0 == ~E_1~0); 20203#L1186-1 assume !(0 == ~E_2~0); 20253#L1191-1 assume !(0 == ~E_3~0); 19242#L1196-1 assume !(0 == ~E_4~0); 19243#L1201-1 assume !(0 == ~E_5~0); 20452#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 20290#L1211-1 assume !(0 == ~E_7~0); 20291#L1216-1 assume !(0 == ~E_8~0); 19382#L1221-1 assume !(0 == ~E_9~0); 19383#L1226-1 assume !(0 == ~E_10~0); 19087#L1231-1 assume !(0 == ~E_11~0); 19088#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20085#L556 assume 1 == ~m_pc~0; 20086#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18961#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18962#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19750#L1391 assume !(0 != activate_threads_~tmp~1#1); 20230#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20231#L575 assume !(1 == ~t1_pc~0); 18916#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 18917#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19054#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19396#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 19351#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19352#L594 assume 1 == ~t2_pc~0; 19284#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19285#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19283#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18976#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 18977#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19043#L613 assume !(1 == ~t3_pc~0); 19158#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19157#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19507#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19774#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 19775#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19479#L632 assume 1 == ~t4_pc~0; 19480#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19991#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18993#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18994#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 20090#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19853#L651 assume 1 == ~t5_pc~0; 19854#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19170#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19171#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19747#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 19185#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19186#L670 assume !(1 == ~t6_pc~0); 20273#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19537#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19274#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19275#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19818#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19819#L689 assume 1 == ~t7_pc~0; 20447#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19934#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19935#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20288#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 19720#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19721#L708 assume !(1 == ~t8_pc~0); 19279#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19280#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20376#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20364#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 19337#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19338#L727 assume 1 == ~t9_pc~0; 19459#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19045#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19326#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19327#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 20439#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19392#L746 assume !(1 == ~t10_pc~0); 19393#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 20045#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20156#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20325#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 20234#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19563#L765 assume 1 == ~t11_pc~0; 19564#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19766#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20383#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20271#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 20272#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20360#L1249 assume !(1 == ~M_E~0); 19995#L1249-2 assume !(1 == ~T1_E~0); 19653#L1254-1 assume !(1 == ~T2_E~0); 18972#L1259-1 assume !(1 == ~T3_E~0); 18954#L1264-1 assume !(1 == ~T4_E~0); 18955#L1269-1 assume !(1 == ~T5_E~0); 20477#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20419#L1279-1 assume !(1 == ~T7_E~0); 19159#L1284-1 assume !(1 == ~T8_E~0); 19160#L1289-1 assume !(1 == ~T9_E~0); 19700#L1294-1 assume !(1 == ~T10_E~0); 19701#L1299-1 assume !(1 == ~T11_E~0); 19710#L1304-1 assume !(1 == ~E_M~0); 20469#L1309-1 assume !(1 == ~E_1~0); 20471#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 19108#L1319-1 assume !(1 == ~E_3~0); 19109#L1324-1 assume !(1 == ~E_4~0); 19235#L1329-1 assume !(1 == ~E_5~0); 19236#L1334-1 assume !(1 == ~E_6~0); 20320#L1339-1 assume !(1 == ~E_7~0); 20390#L1344-1 assume !(1 == ~E_8~0); 20391#L1349-1 assume !(1 == ~E_9~0); 19836#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 19837#L1359-1 assume !(1 == ~E_11~0); 20180#L1364-1 assume { :end_inline_reset_delta_events } true; 19323#L1690-2 [2022-12-13 15:05:48,797 INFO L750 eck$LassoCheckResult]: Loop: 19323#L1690-2 assume !false; 19324#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19210#L1096 assume !false; 20187#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19063#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19064#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 20088#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19561#L937 assume !(0 != eval_~tmp~0#1); 19562#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19427#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19428#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19534#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20441#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19743#L1131-3 assume !(0 == ~T3_E~0); 19744#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20478#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20091#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19277#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19278#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20386#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19917#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19918#L1171-3 assume !(0 == ~T11_E~0); 19957#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19319#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19320#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20030#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20031#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20212#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20213#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19938#L1211-3 assume !(0 == ~E_7~0); 19231#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19232#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19665#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19292#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 19293#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19516#L556-39 assume 1 == ~m_pc~0; 20038#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20009#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19884#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19573#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 19574#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19967#L575-39 assume 1 == ~t1_pc~0; 19968#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20217#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20218#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20460#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19949#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19950#L594-39 assume !(1 == ~t2_pc~0); 20141#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 19952#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19633#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19634#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19450#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19451#L613-39 assume 1 == ~t3_pc~0; 20343#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18932#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18933#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20148#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19039#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19040#L632-39 assume 1 == ~t4_pc~0; 20306#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19630#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19631#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19791#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20304#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19301#L651-39 assume 1 == ~t5_pc~0; 19302#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19071#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19812#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19813#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20433#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20455#L670-39 assume !(1 == ~t6_pc~0); 20040#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 18978#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18979#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19773#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19661#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19662#L689-39 assume !(1 == ~t7_pc~0); 19780#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 19781#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19797#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20132#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19172#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19173#L708-39 assume 1 == ~t8_pc~0; 19113#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19114#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19711#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20205#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20101#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19602#L727-39 assume !(1 == ~t9_pc~0); 19603#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 19366#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19005#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19006#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 20144#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20145#L746-39 assume 1 == ~t10_pc~0; 20119#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 20120#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20382#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19871#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19872#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20262#L765-39 assume 1 == ~t11_pc~0; 18982#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18984#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 19838#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19321#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 19322#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19910#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19134#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19135#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20385#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20022#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19091#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19092#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20418#L1279-3 assume !(1 == ~T7_E~0); 19578#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19579#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19571#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19572#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 19830#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19831#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19477#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19478#L1319-3 assume !(1 == ~E_3~0); 20227#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19198#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19199#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19757#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19758#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19974#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 19456#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 19457#L1359-3 assume !(1 == ~E_11~0); 19990#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19055#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19056#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 19233#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 19234#L1709 assume !(0 == start_simulation_~tmp~3#1); 19485#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 20247#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19165#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 18942#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 18943#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19132#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19958#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 20335#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 19323#L1690-2 [2022-12-13 15:05:48,797 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:48,797 INFO L85 PathProgramCache]: Analyzing trace with hash -1751444930, now seen corresponding path program 1 times [2022-12-13 15:05:48,798 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:48,798 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [417907358] [2022-12-13 15:05:48,798 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:48,798 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:48,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:48,826 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:48,827 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:48,827 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [417907358] [2022-12-13 15:05:48,827 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [417907358] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:48,827 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:48,827 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:48,827 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [950264810] [2022-12-13 15:05:48,827 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:48,827 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:05:48,827 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:48,828 INFO L85 PathProgramCache]: Analyzing trace with hash -1946660288, now seen corresponding path program 1 times [2022-12-13 15:05:48,828 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:48,828 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1569799858] [2022-12-13 15:05:48,828 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:48,828 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:48,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:48,865 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:48,865 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:48,865 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1569799858] [2022-12-13 15:05:48,865 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1569799858] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:48,865 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:48,865 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:48,865 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1680051988] [2022-12-13 15:05:48,865 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:48,866 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:05:48,866 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:05:48,866 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:05:48,866 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:05:48,866 INFO L87 Difference]: Start difference. First operand 1571 states and 2329 transitions. cyclomatic complexity: 759 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:48,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:05:48,888 INFO L93 Difference]: Finished difference Result 1571 states and 2328 transitions. [2022-12-13 15:05:48,888 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2328 transitions. [2022-12-13 15:05:48,892 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-12-13 15:05:48,896 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2328 transitions. [2022-12-13 15:05:48,896 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2022-12-13 15:05:48,897 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2022-12-13 15:05:48,897 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2328 transitions. [2022-12-13 15:05:48,898 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:05:48,898 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2328 transitions. [2022-12-13 15:05:48,900 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2328 transitions. [2022-12-13 15:05:48,912 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2022-12-13 15:05:48,913 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.481858688733291) internal successors, (2328), 1570 states have internal predecessors, (2328), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:48,916 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2328 transitions. [2022-12-13 15:05:48,916 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2328 transitions. [2022-12-13 15:05:48,916 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:05:48,917 INFO L428 stractBuchiCegarLoop]: Abstraction has 1571 states and 2328 transitions. [2022-12-13 15:05:48,917 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 15:05:48,917 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2328 transitions. [2022-12-13 15:05:48,920 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-12-13 15:05:48,920 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:05:48,920 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:05:48,921 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:48,921 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:48,921 INFO L748 eck$LassoCheckResult]: Stem: 22289#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 22290#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 23014#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23015#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23153#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 23154#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22150#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22151#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23587#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23124#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23125#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23389#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23390#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 23488#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 23560#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 23561#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 23438#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23288#L1121 assume !(0 == ~M_E~0); 23065#L1121-2 assume !(0 == ~T1_E~0); 22430#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22431#L1131-1 assume !(0 == ~T3_E~0); 22598#L1136-1 assume !(0 == ~T4_E~0); 22703#L1141-1 assume !(0 == ~T5_E~0); 22925#L1146-1 assume !(0 == ~T6_E~0); 23220#L1151-1 assume !(0 == ~T7_E~0); 22767#L1156-1 assume !(0 == ~T8_E~0); 22136#L1161-1 assume !(0 == ~T9_E~0); 22137#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22360#L1171-1 assume !(0 == ~T11_E~0); 22361#L1176-1 assume !(0 == ~E_M~0); 23233#L1181-1 assume !(0 == ~E_1~0); 23352#L1186-1 assume !(0 == ~E_2~0); 23402#L1191-1 assume !(0 == ~E_3~0); 22391#L1196-1 assume !(0 == ~E_4~0); 22392#L1201-1 assume !(0 == ~E_5~0); 23601#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 23439#L1211-1 assume !(0 == ~E_7~0); 23440#L1216-1 assume !(0 == ~E_8~0); 22531#L1221-1 assume !(0 == ~E_9~0); 22532#L1226-1 assume !(0 == ~E_10~0); 22236#L1231-1 assume !(0 == ~E_11~0); 22237#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23234#L556 assume 1 == ~m_pc~0; 23235#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22110#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22111#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22899#L1391 assume !(0 != activate_threads_~tmp~1#1); 23379#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23380#L575 assume !(1 == ~t1_pc~0); 22065#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22066#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22203#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22545#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 22500#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22501#L594 assume 1 == ~t2_pc~0; 22433#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22434#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22432#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22125#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 22126#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22192#L613 assume !(1 == ~t3_pc~0); 22307#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22306#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22656#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22923#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 22924#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22628#L632 assume 1 == ~t4_pc~0; 22629#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23140#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22142#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22143#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 23239#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23002#L651 assume 1 == ~t5_pc~0; 23003#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22319#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22320#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22896#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 22334#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22335#L670 assume !(1 == ~t6_pc~0); 23422#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22686#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22423#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22424#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22967#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22968#L689 assume 1 == ~t7_pc~0; 23596#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23083#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23084#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23437#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 22869#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22870#L708 assume !(1 == ~t8_pc~0); 22428#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22429#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23525#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23513#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 22486#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22487#L727 assume 1 == ~t9_pc~0; 22608#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22194#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22475#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22476#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 23588#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22541#L746 assume !(1 == ~t10_pc~0); 22542#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 23194#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23305#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23474#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 23383#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22712#L765 assume 1 == ~t11_pc~0; 22713#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 22915#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23532#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23420#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 23421#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23509#L1249 assume !(1 == ~M_E~0); 23144#L1249-2 assume !(1 == ~T1_E~0); 22802#L1254-1 assume !(1 == ~T2_E~0); 22121#L1259-1 assume !(1 == ~T3_E~0); 22103#L1264-1 assume !(1 == ~T4_E~0); 22104#L1269-1 assume !(1 == ~T5_E~0); 23626#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23568#L1279-1 assume !(1 == ~T7_E~0); 22308#L1284-1 assume !(1 == ~T8_E~0); 22309#L1289-1 assume !(1 == ~T9_E~0); 22849#L1294-1 assume !(1 == ~T10_E~0); 22850#L1299-1 assume !(1 == ~T11_E~0); 22859#L1304-1 assume !(1 == ~E_M~0); 23618#L1309-1 assume !(1 == ~E_1~0); 23620#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 22257#L1319-1 assume !(1 == ~E_3~0); 22258#L1324-1 assume !(1 == ~E_4~0); 22384#L1329-1 assume !(1 == ~E_5~0); 22385#L1334-1 assume !(1 == ~E_6~0); 23469#L1339-1 assume !(1 == ~E_7~0); 23539#L1344-1 assume !(1 == ~E_8~0); 23540#L1349-1 assume !(1 == ~E_9~0); 22985#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 22986#L1359-1 assume !(1 == ~E_11~0); 23329#L1364-1 assume { :end_inline_reset_delta_events } true; 22472#L1690-2 [2022-12-13 15:05:48,922 INFO L750 eck$LassoCheckResult]: Loop: 22472#L1690-2 assume !false; 22473#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22359#L1096 assume !false; 23336#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 22212#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22213#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 23237#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22710#L937 assume !(0 != eval_~tmp~0#1); 22711#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22576#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22577#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22683#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23590#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22892#L1131-3 assume !(0 == ~T3_E~0); 22893#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23627#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23240#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22426#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22427#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 23535#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23066#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 23067#L1171-3 assume !(0 == ~T11_E~0); 23106#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22468#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22469#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23179#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23180#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23361#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23362#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23087#L1211-3 assume !(0 == ~E_7~0); 22380#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22381#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22814#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 22441#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22442#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22665#L556-39 assume 1 == ~m_pc~0; 23187#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 23158#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23033#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22722#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 22723#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23116#L575-39 assume 1 == ~t1_pc~0; 23117#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23366#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23367#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23609#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23098#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23099#L594-39 assume !(1 == ~t2_pc~0); 23290#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 23101#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22782#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22783#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22599#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22600#L613-39 assume 1 == ~t3_pc~0; 23492#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22081#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22082#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23297#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22188#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22189#L632-39 assume !(1 == ~t4_pc~0); 23330#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 22779#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22780#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22940#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23453#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22450#L651-39 assume 1 == ~t5_pc~0; 22451#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22220#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22961#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22962#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 23582#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23604#L670-39 assume !(1 == ~t6_pc~0); 23189#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 22127#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22128#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22922#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22810#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22811#L689-39 assume !(1 == ~t7_pc~0); 22929#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 22930#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22946#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23281#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22321#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22322#L708-39 assume 1 == ~t8_pc~0; 22262#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22263#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22860#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23354#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 23250#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22751#L727-39 assume !(1 == ~t9_pc~0); 22752#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 22515#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22154#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22155#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 23293#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23294#L746-39 assume 1 == ~t10_pc~0; 23268#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 23269#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23531#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23020#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23021#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23411#L765-39 assume 1 == ~t11_pc~0; 22131#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 22133#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22987#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22470#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 22471#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23059#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22283#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22284#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23534#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23171#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22240#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22241#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23567#L1279-3 assume !(1 == ~T7_E~0); 22727#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22728#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22720#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22721#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22979#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22980#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22626#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22627#L1319-3 assume !(1 == ~E_3~0); 23376#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22347#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22348#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22906#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22907#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23123#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 22605#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 22606#L1359-3 assume !(1 == ~E_11~0); 23139#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 22204#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22205#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 22382#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 22383#L1709 assume !(0 == start_simulation_~tmp~3#1); 22634#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 23396#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22314#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 22091#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 22092#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22281#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23107#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 23484#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 22472#L1690-2 [2022-12-13 15:05:48,922 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:48,922 INFO L85 PathProgramCache]: Analyzing trace with hash -803392964, now seen corresponding path program 1 times [2022-12-13 15:05:48,922 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:48,922 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1343050664] [2022-12-13 15:05:48,922 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:48,922 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:48,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:48,951 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:48,951 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:48,951 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1343050664] [2022-12-13 15:05:48,951 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1343050664] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:48,952 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:48,952 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:48,952 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [481507279] [2022-12-13 15:05:48,952 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:48,952 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:05:48,952 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:48,952 INFO L85 PathProgramCache]: Analyzing trace with hash 1131120385, now seen corresponding path program 1 times [2022-12-13 15:05:48,952 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:48,952 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [172892687] [2022-12-13 15:05:48,953 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:48,953 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:48,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:48,994 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:48,994 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:48,995 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [172892687] [2022-12-13 15:05:48,995 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [172892687] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:48,995 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:48,995 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:48,995 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2096102263] [2022-12-13 15:05:48,995 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:48,995 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:05:48,995 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:05:48,995 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:05:48,996 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:05:48,996 INFO L87 Difference]: Start difference. First operand 1571 states and 2328 transitions. cyclomatic complexity: 758 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:49,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:05:49,017 INFO L93 Difference]: Finished difference Result 1571 states and 2327 transitions. [2022-12-13 15:05:49,017 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2327 transitions. [2022-12-13 15:05:49,020 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-12-13 15:05:49,024 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2327 transitions. [2022-12-13 15:05:49,024 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2022-12-13 15:05:49,025 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2022-12-13 15:05:49,025 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2327 transitions. [2022-12-13 15:05:49,027 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:05:49,027 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2327 transitions. [2022-12-13 15:05:49,028 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2327 transitions. [2022-12-13 15:05:49,039 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2022-12-13 15:05:49,040 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4812221514958626) internal successors, (2327), 1570 states have internal predecessors, (2327), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:49,042 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2327 transitions. [2022-12-13 15:05:49,042 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2327 transitions. [2022-12-13 15:05:49,043 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:05:49,043 INFO L428 stractBuchiCegarLoop]: Abstraction has 1571 states and 2327 transitions. [2022-12-13 15:05:49,043 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 15:05:49,043 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2327 transitions. [2022-12-13 15:05:49,046 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-12-13 15:05:49,046 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:05:49,046 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:05:49,047 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:49,047 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:49,047 INFO L748 eck$LassoCheckResult]: Stem: 25438#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 25439#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 26163#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26164#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26302#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 26303#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25301#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25302#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26736#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26273#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26274#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26538#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26539#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 26637#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 26709#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 26710#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 26587#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26437#L1121 assume !(0 == ~M_E~0); 26214#L1121-2 assume !(0 == ~T1_E~0); 25579#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25580#L1131-1 assume !(0 == ~T3_E~0); 25747#L1136-1 assume !(0 == ~T4_E~0); 25852#L1141-1 assume !(0 == ~T5_E~0); 26079#L1146-1 assume !(0 == ~T6_E~0); 26369#L1151-1 assume !(0 == ~T7_E~0); 25916#L1156-1 assume !(0 == ~T8_E~0); 25285#L1161-1 assume !(0 == ~T9_E~0); 25286#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25509#L1171-1 assume !(0 == ~T11_E~0); 25510#L1176-1 assume !(0 == ~E_M~0); 26382#L1181-1 assume !(0 == ~E_1~0); 26501#L1186-1 assume !(0 == ~E_2~0); 26551#L1191-1 assume !(0 == ~E_3~0); 25540#L1196-1 assume !(0 == ~E_4~0); 25541#L1201-1 assume !(0 == ~E_5~0); 26750#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 26588#L1211-1 assume !(0 == ~E_7~0); 26589#L1216-1 assume !(0 == ~E_8~0); 25680#L1221-1 assume !(0 == ~E_9~0); 25681#L1226-1 assume !(0 == ~E_10~0); 25385#L1231-1 assume !(0 == ~E_11~0); 25386#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26383#L556 assume 1 == ~m_pc~0; 26384#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25259#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25260#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26048#L1391 assume !(0 != activate_threads_~tmp~1#1); 26528#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26529#L575 assume !(1 == ~t1_pc~0); 25214#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25215#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25352#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25694#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 25649#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25650#L594 assume 1 == ~t2_pc~0; 25582#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25583#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25581#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25276#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 25277#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25341#L613 assume !(1 == ~t3_pc~0); 25456#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25455#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25805#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26072#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 26073#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25777#L632 assume 1 == ~t4_pc~0; 25778#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26289#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25291#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25292#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 26388#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26151#L651 assume 1 == ~t5_pc~0; 26152#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25468#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25469#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26045#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 25483#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25484#L670 assume !(1 == ~t6_pc~0); 26571#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25837#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25572#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25573#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26116#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26117#L689 assume 1 == ~t7_pc~0; 26745#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26232#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26233#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26586#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 26018#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26019#L708 assume !(1 == ~t8_pc~0); 25577#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25578#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26674#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26662#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 25635#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25636#L727 assume 1 == ~t9_pc~0; 25757#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25343#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25624#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25625#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 26737#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25690#L746 assume !(1 == ~t10_pc~0); 25691#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 26343#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26454#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26623#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 26532#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25861#L765 assume 1 == ~t11_pc~0; 25862#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26064#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26681#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26569#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 26570#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26658#L1249 assume !(1 == ~M_E~0); 26293#L1249-2 assume !(1 == ~T1_E~0); 25951#L1254-1 assume !(1 == ~T2_E~0); 25270#L1259-1 assume !(1 == ~T3_E~0); 25252#L1264-1 assume !(1 == ~T4_E~0); 25253#L1269-1 assume !(1 == ~T5_E~0); 26775#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26717#L1279-1 assume !(1 == ~T7_E~0); 25457#L1284-1 assume !(1 == ~T8_E~0); 25458#L1289-1 assume !(1 == ~T9_E~0); 25998#L1294-1 assume !(1 == ~T10_E~0); 25999#L1299-1 assume !(1 == ~T11_E~0); 26008#L1304-1 assume !(1 == ~E_M~0); 26767#L1309-1 assume !(1 == ~E_1~0); 26769#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 25406#L1319-1 assume !(1 == ~E_3~0); 25407#L1324-1 assume !(1 == ~E_4~0); 25533#L1329-1 assume !(1 == ~E_5~0); 25534#L1334-1 assume !(1 == ~E_6~0); 26618#L1339-1 assume !(1 == ~E_7~0); 26688#L1344-1 assume !(1 == ~E_8~0); 26689#L1349-1 assume !(1 == ~E_9~0); 26135#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 26136#L1359-1 assume !(1 == ~E_11~0); 26478#L1364-1 assume { :end_inline_reset_delta_events } true; 25621#L1690-2 [2022-12-13 15:05:49,048 INFO L750 eck$LassoCheckResult]: Loop: 25621#L1690-2 assume !false; 25622#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25508#L1096 assume !false; 26485#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 25361#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25362#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 26386#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 25859#L937 assume !(0 != eval_~tmp~0#1); 25860#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25725#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25726#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25834#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26739#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26041#L1131-3 assume !(0 == ~T3_E~0); 26042#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26776#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26389#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25575#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25576#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 26684#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 26215#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 26216#L1171-3 assume !(0 == ~T11_E~0); 26256#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25617#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25618#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26328#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26329#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26510#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26511#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 26236#L1211-3 assume !(0 == ~E_7~0); 25529#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25530#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25963#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25590#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25591#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25814#L556-39 assume 1 == ~m_pc~0; 26336#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26307#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26182#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25871#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 25872#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26265#L575-39 assume 1 == ~t1_pc~0; 26266#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 26515#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26516#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26758#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26247#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26248#L594-39 assume !(1 == ~t2_pc~0); 26439#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 26250#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25931#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25932#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25748#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25749#L613-39 assume 1 == ~t3_pc~0; 26641#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25230#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25231#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26448#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25337#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25338#L632-39 assume 1 == ~t4_pc~0; 26604#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25928#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25929#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26089#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26602#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25596#L651-39 assume !(1 == ~t5_pc~0); 25366#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 25367#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26110#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26111#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26731#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26753#L670-39 assume !(1 == ~t6_pc~0); 26338#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 25274#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25275#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26071#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25959#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25960#L689-39 assume 1 == ~t7_pc~0; 26181#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26078#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26095#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26430#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25470#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25471#L708-39 assume 1 == ~t8_pc~0; 25411#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25412#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26009#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26503#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26399#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25900#L727-39 assume !(1 == ~t9_pc~0); 25901#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 25664#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25299#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25300#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 26441#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26442#L746-39 assume 1 == ~t10_pc~0; 26417#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 26418#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26680#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26169#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26170#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26560#L765-39 assume 1 == ~t11_pc~0; 25280#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25282#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26134#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25619#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25620#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26208#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25432#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25433#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26683#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26320#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25389#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25390#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26716#L1279-3 assume !(1 == ~T7_E~0); 25876#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25877#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25867#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25868#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 26128#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26129#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25771#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25772#L1319-3 assume !(1 == ~E_3~0); 26525#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25490#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25491#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26055#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 26056#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 26272#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25754#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25755#L1359-3 assume !(1 == ~E_11~0); 26288#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 25353#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25354#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 25531#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 25532#L1709 assume !(0 == start_simulation_~tmp~3#1); 25783#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 26545#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25463#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 25240#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 25241#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25430#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26255#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 26633#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 25621#L1690-2 [2022-12-13 15:05:49,048 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:49,048 INFO L85 PathProgramCache]: Analyzing trace with hash -218621314, now seen corresponding path program 1 times [2022-12-13 15:05:49,048 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:49,048 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1456033068] [2022-12-13 15:05:49,048 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:49,048 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:49,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:49,076 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:49,076 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:49,076 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1456033068] [2022-12-13 15:05:49,076 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1456033068] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:49,076 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:49,077 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:49,077 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1676257513] [2022-12-13 15:05:49,077 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:49,077 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:05:49,077 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:49,077 INFO L85 PathProgramCache]: Analyzing trace with hash -726214464, now seen corresponding path program 1 times [2022-12-13 15:05:49,077 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:49,077 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [185479769] [2022-12-13 15:05:49,077 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:49,077 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:49,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:49,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:49,113 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:49,113 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [185479769] [2022-12-13 15:05:49,113 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [185479769] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:49,113 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:49,113 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:49,114 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [279885390] [2022-12-13 15:05:49,114 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:49,114 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:05:49,114 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:05:49,114 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:05:49,114 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:05:49,114 INFO L87 Difference]: Start difference. First operand 1571 states and 2327 transitions. cyclomatic complexity: 757 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:49,133 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:05:49,133 INFO L93 Difference]: Finished difference Result 1571 states and 2326 transitions. [2022-12-13 15:05:49,133 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2326 transitions. [2022-12-13 15:05:49,136 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-12-13 15:05:49,140 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2326 transitions. [2022-12-13 15:05:49,140 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2022-12-13 15:05:49,141 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2022-12-13 15:05:49,141 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2326 transitions. [2022-12-13 15:05:49,142 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:05:49,142 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2326 transitions. [2022-12-13 15:05:49,144 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2326 transitions. [2022-12-13 15:05:49,155 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2022-12-13 15:05:49,156 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4805856142584342) internal successors, (2326), 1570 states have internal predecessors, (2326), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:49,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2326 transitions. [2022-12-13 15:05:49,159 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2326 transitions. [2022-12-13 15:05:49,159 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:05:49,159 INFO L428 stractBuchiCegarLoop]: Abstraction has 1571 states and 2326 transitions. [2022-12-13 15:05:49,159 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 15:05:49,159 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2326 transitions. [2022-12-13 15:05:49,162 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-12-13 15:05:49,162 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:05:49,162 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:05:49,164 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:49,164 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:49,164 INFO L748 eck$LassoCheckResult]: Stem: 28587#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 28588#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 29312#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29313#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29451#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 29452#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28448#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28449#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29885#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29422#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29423#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29687#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29688#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 29786#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29858#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29859#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29736#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29586#L1121 assume !(0 == ~M_E~0); 29363#L1121-2 assume !(0 == ~T1_E~0); 28728#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28729#L1131-1 assume !(0 == ~T3_E~0); 28896#L1136-1 assume !(0 == ~T4_E~0); 29001#L1141-1 assume !(0 == ~T5_E~0); 29223#L1146-1 assume !(0 == ~T6_E~0); 29518#L1151-1 assume !(0 == ~T7_E~0); 29065#L1156-1 assume !(0 == ~T8_E~0); 28434#L1161-1 assume !(0 == ~T9_E~0); 28435#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28658#L1171-1 assume !(0 == ~T11_E~0); 28659#L1176-1 assume !(0 == ~E_M~0); 29531#L1181-1 assume !(0 == ~E_1~0); 29650#L1186-1 assume !(0 == ~E_2~0); 29700#L1191-1 assume !(0 == ~E_3~0); 28689#L1196-1 assume !(0 == ~E_4~0); 28690#L1201-1 assume !(0 == ~E_5~0); 29899#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 29737#L1211-1 assume !(0 == ~E_7~0); 29738#L1216-1 assume !(0 == ~E_8~0); 28829#L1221-1 assume !(0 == ~E_9~0); 28830#L1226-1 assume !(0 == ~E_10~0); 28534#L1231-1 assume !(0 == ~E_11~0); 28535#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29532#L556 assume 1 == ~m_pc~0; 29533#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28408#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28409#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29197#L1391 assume !(0 != activate_threads_~tmp~1#1); 29677#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29678#L575 assume !(1 == ~t1_pc~0); 28363#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28364#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28501#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28843#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 28798#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28799#L594 assume 1 == ~t2_pc~0; 28731#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28732#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28730#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28423#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 28424#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28490#L613 assume !(1 == ~t3_pc~0); 28605#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 28604#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28954#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29221#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 29222#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28926#L632 assume 1 == ~t4_pc~0; 28927#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29438#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28440#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28441#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 29537#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29300#L651 assume 1 == ~t5_pc~0; 29301#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28617#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28618#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29194#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 28632#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28633#L670 assume !(1 == ~t6_pc~0); 29720#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 28984#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28721#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28722#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29265#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29266#L689 assume 1 == ~t7_pc~0; 29894#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29381#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29382#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29735#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 29167#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29168#L708 assume !(1 == ~t8_pc~0); 28726#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 28727#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29823#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29811#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 28784#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28785#L727 assume 1 == ~t9_pc~0; 28906#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28492#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28773#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28774#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 29886#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28839#L746 assume !(1 == ~t10_pc~0); 28840#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29492#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29603#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29772#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 29681#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29010#L765 assume 1 == ~t11_pc~0; 29011#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29213#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29830#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29718#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 29719#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29807#L1249 assume !(1 == ~M_E~0); 29442#L1249-2 assume !(1 == ~T1_E~0); 29100#L1254-1 assume !(1 == ~T2_E~0); 28419#L1259-1 assume !(1 == ~T3_E~0); 28401#L1264-1 assume !(1 == ~T4_E~0); 28402#L1269-1 assume !(1 == ~T5_E~0); 29924#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29866#L1279-1 assume !(1 == ~T7_E~0); 28606#L1284-1 assume !(1 == ~T8_E~0); 28607#L1289-1 assume !(1 == ~T9_E~0); 29147#L1294-1 assume !(1 == ~T10_E~0); 29148#L1299-1 assume !(1 == ~T11_E~0); 29157#L1304-1 assume !(1 == ~E_M~0); 29916#L1309-1 assume !(1 == ~E_1~0); 29918#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 28555#L1319-1 assume !(1 == ~E_3~0); 28556#L1324-1 assume !(1 == ~E_4~0); 28682#L1329-1 assume !(1 == ~E_5~0); 28683#L1334-1 assume !(1 == ~E_6~0); 29767#L1339-1 assume !(1 == ~E_7~0); 29837#L1344-1 assume !(1 == ~E_8~0); 29838#L1349-1 assume !(1 == ~E_9~0); 29283#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 29284#L1359-1 assume !(1 == ~E_11~0); 29627#L1364-1 assume { :end_inline_reset_delta_events } true; 28770#L1690-2 [2022-12-13 15:05:49,164 INFO L750 eck$LassoCheckResult]: Loop: 28770#L1690-2 assume !false; 28771#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28657#L1096 assume !false; 29634#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 28510#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28511#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 29535#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 29008#L937 assume !(0 != eval_~tmp~0#1); 29009#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28874#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28875#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28981#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29888#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29190#L1131-3 assume !(0 == ~T3_E~0); 29191#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29925#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29538#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28724#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28725#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29833#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29364#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29365#L1171-3 assume !(0 == ~T11_E~0); 29404#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 28766#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 28767#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29477#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29478#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29659#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29660#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29385#L1211-3 assume !(0 == ~E_7~0); 28678#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 28679#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29112#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28739#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28740#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28963#L556-39 assume 1 == ~m_pc~0; 29485#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29456#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29331#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29020#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 29021#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29414#L575-39 assume 1 == ~t1_pc~0; 29415#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29664#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29665#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29907#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29396#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29397#L594-39 assume !(1 == ~t2_pc~0); 29588#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 29399#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29080#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29081#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28897#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28898#L613-39 assume 1 == ~t3_pc~0; 29790#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28379#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28380#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29595#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28486#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28487#L632-39 assume 1 == ~t4_pc~0; 29753#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29077#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29078#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29238#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29751#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28748#L651-39 assume !(1 == ~t5_pc~0); 28517#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 28518#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29259#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29260#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29880#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29902#L670-39 assume !(1 == ~t6_pc~0); 29487#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 28425#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28426#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29220#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29108#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29109#L689-39 assume 1 == ~t7_pc~0; 29330#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29228#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29244#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29579#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28619#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28620#L708-39 assume 1 == ~t8_pc~0; 28560#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28561#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29158#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29652#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29548#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29049#L727-39 assume !(1 == ~t9_pc~0); 29050#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 28813#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28452#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28453#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 29591#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29592#L746-39 assume !(1 == ~t10_pc~0); 29568#L746-41 is_transmit10_triggered_~__retres1~10#1 := 0; 29567#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29829#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29318#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29319#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29709#L765-39 assume 1 == ~t11_pc~0; 28429#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28431#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29285#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 28768#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28769#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29357#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28581#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28582#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29832#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29469#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28538#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28539#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29865#L1279-3 assume !(1 == ~T7_E~0); 29025#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29026#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29018#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29019#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29277#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29278#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28924#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28925#L1319-3 assume !(1 == ~E_3~0); 29674#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28645#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 28646#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29204#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 29205#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 29421#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28903#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 28904#L1359-3 assume !(1 == ~E_11~0); 29437#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 28502#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28503#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 28680#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 28681#L1709 assume !(0 == start_simulation_~tmp~3#1); 28932#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 29694#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28612#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 28389#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 28390#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28579#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29405#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 29782#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 28770#L1690-2 [2022-12-13 15:05:49,164 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:49,164 INFO L85 PathProgramCache]: Analyzing trace with hash 215884284, now seen corresponding path program 1 times [2022-12-13 15:05:49,165 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:49,165 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1227281942] [2022-12-13 15:05:49,165 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:49,165 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:49,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:49,193 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:49,193 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:49,193 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1227281942] [2022-12-13 15:05:49,193 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1227281942] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:49,193 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:49,193 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:49,194 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1428248183] [2022-12-13 15:05:49,194 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:49,194 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:05:49,194 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:49,194 INFO L85 PathProgramCache]: Analyzing trace with hash 741988865, now seen corresponding path program 1 times [2022-12-13 15:05:49,195 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:49,195 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [250631147] [2022-12-13 15:05:49,195 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:49,195 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:49,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:49,232 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:49,232 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:49,232 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [250631147] [2022-12-13 15:05:49,232 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [250631147] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:49,233 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:49,233 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:49,233 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [57471341] [2022-12-13 15:05:49,233 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:49,233 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:05:49,233 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:05:49,234 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:05:49,234 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:05:49,234 INFO L87 Difference]: Start difference. First operand 1571 states and 2326 transitions. cyclomatic complexity: 756 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:49,260 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:05:49,260 INFO L93 Difference]: Finished difference Result 1571 states and 2325 transitions. [2022-12-13 15:05:49,260 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2325 transitions. [2022-12-13 15:05:49,263 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-12-13 15:05:49,267 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2325 transitions. [2022-12-13 15:05:49,267 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2022-12-13 15:05:49,268 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2022-12-13 15:05:49,268 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2325 transitions. [2022-12-13 15:05:49,269 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:05:49,269 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2325 transitions. [2022-12-13 15:05:49,271 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2325 transitions. [2022-12-13 15:05:49,281 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2022-12-13 15:05:49,283 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4799490770210058) internal successors, (2325), 1570 states have internal predecessors, (2325), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:49,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2325 transitions. [2022-12-13 15:05:49,285 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2325 transitions. [2022-12-13 15:05:49,285 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:05:49,286 INFO L428 stractBuchiCegarLoop]: Abstraction has 1571 states and 2325 transitions. [2022-12-13 15:05:49,286 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 15:05:49,286 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2325 transitions. [2022-12-13 15:05:49,289 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-12-13 15:05:49,289 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:05:49,289 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:05:49,290 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:49,290 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:49,290 INFO L748 eck$LassoCheckResult]: Stem: 31736#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 31737#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 32461#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32462#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32600#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 32601#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31597#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31598#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33034#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32571#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 32572#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32836#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32837#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 32935#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33007#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 33008#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 32885#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32735#L1121 assume !(0 == ~M_E~0); 32512#L1121-2 assume !(0 == ~T1_E~0); 31877#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31878#L1131-1 assume !(0 == ~T3_E~0); 32045#L1136-1 assume !(0 == ~T4_E~0); 32150#L1141-1 assume !(0 == ~T5_E~0); 32372#L1146-1 assume !(0 == ~T6_E~0); 32667#L1151-1 assume !(0 == ~T7_E~0); 32214#L1156-1 assume !(0 == ~T8_E~0); 31583#L1161-1 assume !(0 == ~T9_E~0); 31584#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 31807#L1171-1 assume !(0 == ~T11_E~0); 31808#L1176-1 assume !(0 == ~E_M~0); 32680#L1181-1 assume !(0 == ~E_1~0); 32799#L1186-1 assume !(0 == ~E_2~0); 32849#L1191-1 assume !(0 == ~E_3~0); 31838#L1196-1 assume !(0 == ~E_4~0); 31839#L1201-1 assume !(0 == ~E_5~0); 33048#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 32886#L1211-1 assume !(0 == ~E_7~0); 32887#L1216-1 assume !(0 == ~E_8~0); 31978#L1221-1 assume !(0 == ~E_9~0); 31979#L1226-1 assume !(0 == ~E_10~0); 31683#L1231-1 assume !(0 == ~E_11~0); 31684#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32681#L556 assume 1 == ~m_pc~0; 32682#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 31557#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31558#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32346#L1391 assume !(0 != activate_threads_~tmp~1#1); 32826#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32827#L575 assume !(1 == ~t1_pc~0); 31512#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31513#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31650#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31992#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 31947#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31948#L594 assume 1 == ~t2_pc~0; 31880#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31881#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31879#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31572#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 31573#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31639#L613 assume !(1 == ~t3_pc~0); 31754#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 31753#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32103#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32370#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 32371#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32075#L632 assume 1 == ~t4_pc~0; 32076#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32587#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31589#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31590#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 32686#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32449#L651 assume 1 == ~t5_pc~0; 32450#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31766#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31767#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32343#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 31781#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31782#L670 assume !(1 == ~t6_pc~0); 32869#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 32133#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31870#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31871#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32414#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32415#L689 assume 1 == ~t7_pc~0; 33043#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32530#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32531#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32884#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 32316#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32317#L708 assume !(1 == ~t8_pc~0); 31875#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 31876#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32972#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32960#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 31933#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31934#L727 assume 1 == ~t9_pc~0; 32055#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31641#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31922#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31923#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 33035#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31988#L746 assume !(1 == ~t10_pc~0); 31989#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 32641#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32752#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32921#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 32830#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32159#L765 assume 1 == ~t11_pc~0; 32160#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32362#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32979#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 32867#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 32868#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32956#L1249 assume !(1 == ~M_E~0); 32591#L1249-2 assume !(1 == ~T1_E~0); 32249#L1254-1 assume !(1 == ~T2_E~0); 31568#L1259-1 assume !(1 == ~T3_E~0); 31550#L1264-1 assume !(1 == ~T4_E~0); 31551#L1269-1 assume !(1 == ~T5_E~0); 33073#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33015#L1279-1 assume !(1 == ~T7_E~0); 31755#L1284-1 assume !(1 == ~T8_E~0); 31756#L1289-1 assume !(1 == ~T9_E~0); 32296#L1294-1 assume !(1 == ~T10_E~0); 32297#L1299-1 assume !(1 == ~T11_E~0); 32306#L1304-1 assume !(1 == ~E_M~0); 33065#L1309-1 assume !(1 == ~E_1~0); 33067#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 31704#L1319-1 assume !(1 == ~E_3~0); 31705#L1324-1 assume !(1 == ~E_4~0); 31831#L1329-1 assume !(1 == ~E_5~0); 31832#L1334-1 assume !(1 == ~E_6~0); 32916#L1339-1 assume !(1 == ~E_7~0); 32986#L1344-1 assume !(1 == ~E_8~0); 32987#L1349-1 assume !(1 == ~E_9~0); 32432#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 32433#L1359-1 assume !(1 == ~E_11~0); 32776#L1364-1 assume { :end_inline_reset_delta_events } true; 31919#L1690-2 [2022-12-13 15:05:49,291 INFO L750 eck$LassoCheckResult]: Loop: 31919#L1690-2 assume !false; 31920#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31806#L1096 assume !false; 32783#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 31659#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31660#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 32684#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 32157#L937 assume !(0 != eval_~tmp~0#1); 32158#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32023#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32024#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 32130#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33037#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32339#L1131-3 assume !(0 == ~T3_E~0); 32340#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33074#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32687#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 31873#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31874#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32982#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32513#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32514#L1171-3 assume !(0 == ~T11_E~0); 32553#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 31915#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 31916#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32626#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32627#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 32808#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32809#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32534#L1211-3 assume !(0 == ~E_7~0); 31827#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 31828#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32261#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31888#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 31889#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32112#L556-39 assume 1 == ~m_pc~0; 32634#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32605#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32480#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32169#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 32170#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32563#L575-39 assume 1 == ~t1_pc~0; 32564#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 32813#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32814#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33056#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32545#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32546#L594-39 assume !(1 == ~t2_pc~0); 32737#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 32548#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32229#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32230#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 32046#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32047#L613-39 assume 1 == ~t3_pc~0; 32939#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31528#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31529#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32744#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 31635#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31636#L632-39 assume 1 == ~t4_pc~0; 32902#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32226#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32227#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32387#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32900#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31897#L651-39 assume !(1 == ~t5_pc~0); 31666#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 31667#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32408#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32409#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33029#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33051#L670-39 assume !(1 == ~t6_pc~0); 32636#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 31574#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31575#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32369#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32257#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32258#L689-39 assume !(1 == ~t7_pc~0); 32376#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 32377#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32393#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32728#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 31768#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31769#L708-39 assume 1 == ~t8_pc~0; 31709#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31710#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32307#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32801#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32697#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32198#L727-39 assume !(1 == ~t9_pc~0); 32199#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 31962#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31601#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31602#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 32740#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32741#L746-39 assume 1 == ~t10_pc~0; 32715#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 32716#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32978#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32467#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32468#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32858#L765-39 assume 1 == ~t11_pc~0; 31578#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 31580#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32434#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31917#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 31918#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32506#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 31730#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31731#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32981#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32618#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31687#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31688#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33014#L1279-3 assume !(1 == ~T7_E~0); 32174#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 32175#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32167#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32168#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 32426#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 32427#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32073#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32074#L1319-3 assume !(1 == ~E_3~0); 32823#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31794#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31795#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32353#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32354#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32570#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32052#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32053#L1359-3 assume !(1 == ~E_11~0); 32586#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 31651#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31652#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 31829#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 31830#L1709 assume !(0 == start_simulation_~tmp~3#1); 32081#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 32843#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31761#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 31538#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 31539#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31728#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32554#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 32931#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 31919#L1690-2 [2022-12-13 15:05:49,291 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:49,291 INFO L85 PathProgramCache]: Analyzing trace with hash 922480890, now seen corresponding path program 1 times [2022-12-13 15:05:49,291 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:49,291 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1752686786] [2022-12-13 15:05:49,291 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:49,291 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:49,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:49,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:49,320 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:49,320 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1752686786] [2022-12-13 15:05:49,320 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1752686786] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:49,320 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:49,320 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:49,321 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2038106012] [2022-12-13 15:05:49,321 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:49,321 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:05:49,321 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:49,321 INFO L85 PathProgramCache]: Analyzing trace with hash 1411279809, now seen corresponding path program 2 times [2022-12-13 15:05:49,322 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:49,322 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [695152828] [2022-12-13 15:05:49,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:49,322 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:49,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:49,365 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:49,365 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:49,365 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [695152828] [2022-12-13 15:05:49,366 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [695152828] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:49,366 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:49,366 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:49,366 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [614262703] [2022-12-13 15:05:49,366 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:49,366 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:05:49,366 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:05:49,367 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:05:49,367 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:05:49,367 INFO L87 Difference]: Start difference. First operand 1571 states and 2325 transitions. cyclomatic complexity: 755 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:49,384 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:05:49,385 INFO L93 Difference]: Finished difference Result 1571 states and 2324 transitions. [2022-12-13 15:05:49,385 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2324 transitions. [2022-12-13 15:05:49,388 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-12-13 15:05:49,392 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2324 transitions. [2022-12-13 15:05:49,392 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2022-12-13 15:05:49,392 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2022-12-13 15:05:49,392 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2324 transitions. [2022-12-13 15:05:49,394 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:05:49,394 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2324 transitions. [2022-12-13 15:05:49,395 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2324 transitions. [2022-12-13 15:05:49,406 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2022-12-13 15:05:49,407 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4793125397835774) internal successors, (2324), 1570 states have internal predecessors, (2324), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:49,410 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2324 transitions. [2022-12-13 15:05:49,410 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1571 states and 2324 transitions. [2022-12-13 15:05:49,410 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:05:49,410 INFO L428 stractBuchiCegarLoop]: Abstraction has 1571 states and 2324 transitions. [2022-12-13 15:05:49,410 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 15:05:49,410 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2324 transitions. [2022-12-13 15:05:49,414 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2022-12-13 15:05:49,414 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:05:49,414 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:05:49,415 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:49,415 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:49,415 INFO L748 eck$LassoCheckResult]: Stem: 34885#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 34886#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 35610#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35611#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35749#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 35750#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34746#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34747#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36183#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35720#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35721#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35985#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35986#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36084#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36156#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36157#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 36034#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35884#L1121 assume !(0 == ~M_E~0); 35661#L1121-2 assume !(0 == ~T1_E~0); 35026#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35027#L1131-1 assume !(0 == ~T3_E~0); 35194#L1136-1 assume !(0 == ~T4_E~0); 35299#L1141-1 assume !(0 == ~T5_E~0); 35521#L1146-1 assume !(0 == ~T6_E~0); 35816#L1151-1 assume !(0 == ~T7_E~0); 35363#L1156-1 assume !(0 == ~T8_E~0); 34732#L1161-1 assume !(0 == ~T9_E~0); 34733#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 34956#L1171-1 assume !(0 == ~T11_E~0); 34957#L1176-1 assume !(0 == ~E_M~0); 35829#L1181-1 assume !(0 == ~E_1~0); 35948#L1186-1 assume !(0 == ~E_2~0); 35998#L1191-1 assume !(0 == ~E_3~0); 34987#L1196-1 assume !(0 == ~E_4~0); 34988#L1201-1 assume !(0 == ~E_5~0); 36197#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 36035#L1211-1 assume !(0 == ~E_7~0); 36036#L1216-1 assume !(0 == ~E_8~0); 35127#L1221-1 assume !(0 == ~E_9~0); 35128#L1226-1 assume !(0 == ~E_10~0); 34832#L1231-1 assume !(0 == ~E_11~0); 34833#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35830#L556 assume 1 == ~m_pc~0; 35831#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 34706#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34707#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35495#L1391 assume !(0 != activate_threads_~tmp~1#1); 35975#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35976#L575 assume !(1 == ~t1_pc~0); 34661#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34662#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34799#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35141#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 35096#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35097#L594 assume 1 == ~t2_pc~0; 35029#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35030#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35028#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34721#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 34722#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34788#L613 assume !(1 == ~t3_pc~0); 34903#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 34902#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35252#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35519#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 35520#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35224#L632 assume 1 == ~t4_pc~0; 35225#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 35736#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34738#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34739#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 35835#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35598#L651 assume 1 == ~t5_pc~0; 35599#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34915#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34916#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35492#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 34930#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34931#L670 assume !(1 == ~t6_pc~0); 36018#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 35282#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35019#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35020#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35563#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35564#L689 assume 1 == ~t7_pc~0; 36192#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35679#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35680#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36033#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 35465#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35466#L708 assume !(1 == ~t8_pc~0); 35024#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 35025#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36121#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36109#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 35082#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35083#L727 assume 1 == ~t9_pc~0; 35204#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34790#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35071#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35072#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 36184#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35137#L746 assume !(1 == ~t10_pc~0); 35138#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 35790#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35901#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36070#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 35979#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35308#L765 assume 1 == ~t11_pc~0; 35309#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 35511#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36128#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 36016#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 36017#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36105#L1249 assume !(1 == ~M_E~0); 35740#L1249-2 assume !(1 == ~T1_E~0); 35398#L1254-1 assume !(1 == ~T2_E~0); 34717#L1259-1 assume !(1 == ~T3_E~0); 34699#L1264-1 assume !(1 == ~T4_E~0); 34700#L1269-1 assume !(1 == ~T5_E~0); 36222#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36164#L1279-1 assume !(1 == ~T7_E~0); 34904#L1284-1 assume !(1 == ~T8_E~0); 34905#L1289-1 assume !(1 == ~T9_E~0); 35445#L1294-1 assume !(1 == ~T10_E~0); 35446#L1299-1 assume !(1 == ~T11_E~0); 35455#L1304-1 assume !(1 == ~E_M~0); 36214#L1309-1 assume !(1 == ~E_1~0); 36216#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 34853#L1319-1 assume !(1 == ~E_3~0); 34854#L1324-1 assume !(1 == ~E_4~0); 34980#L1329-1 assume !(1 == ~E_5~0); 34981#L1334-1 assume !(1 == ~E_6~0); 36065#L1339-1 assume !(1 == ~E_7~0); 36135#L1344-1 assume !(1 == ~E_8~0); 36136#L1349-1 assume !(1 == ~E_9~0); 35581#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 35582#L1359-1 assume !(1 == ~E_11~0); 35925#L1364-1 assume { :end_inline_reset_delta_events } true; 35068#L1690-2 [2022-12-13 15:05:49,415 INFO L750 eck$LassoCheckResult]: Loop: 35068#L1690-2 assume !false; 35069#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34955#L1096 assume !false; 35932#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 34808#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34809#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 35833#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 35306#L937 assume !(0 != eval_~tmp~0#1); 35307#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35172#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35173#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 35279#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36186#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35488#L1131-3 assume !(0 == ~T3_E~0); 35489#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36223#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 35836#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35022#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 35023#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36131#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35662#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 35663#L1171-3 assume !(0 == ~T11_E~0); 35702#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35064#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35065#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35775#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35776#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 35957#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 35958#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 35683#L1211-3 assume !(0 == ~E_7~0); 34976#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 34977#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35410#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 35037#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 35038#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35261#L556-39 assume 1 == ~m_pc~0; 35783#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 35754#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35629#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35318#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 35319#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35712#L575-39 assume 1 == ~t1_pc~0; 35713#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35962#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35963#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36205#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 35694#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35695#L594-39 assume !(1 == ~t2_pc~0); 35886#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 35697#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35378#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35379#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35195#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35196#L613-39 assume 1 == ~t3_pc~0; 36088#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34677#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34678#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35893#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34784#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34785#L632-39 assume 1 == ~t4_pc~0; 36051#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 35375#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35376#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35536#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36049#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35046#L651-39 assume 1 == ~t5_pc~0; 35047#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34816#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35557#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35558#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 36178#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36200#L670-39 assume !(1 == ~t6_pc~0); 35785#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 34723#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34724#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35518#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35406#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35407#L689-39 assume !(1 == ~t7_pc~0); 35525#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 35526#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35542#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35877#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 34917#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 34918#L708-39 assume 1 == ~t8_pc~0; 34858#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34859#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35456#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35950#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35846#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35347#L727-39 assume !(1 == ~t9_pc~0); 35348#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 35111#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34750#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34751#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 35889#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35890#L746-39 assume 1 == ~t10_pc~0; 35864#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35865#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36127#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35616#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35617#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36007#L765-39 assume 1 == ~t11_pc~0; 34727#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34729#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35583#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35066#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35067#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35655#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 34879#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34880#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36130#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35767#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 34836#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 34837#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36163#L1279-3 assume !(1 == ~T7_E~0); 35323#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 35324#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 35316#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 35317#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35575#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 35576#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35222#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35223#L1319-3 assume !(1 == ~E_3~0); 35972#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34943#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 34944#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35502#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35503#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 35719#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 35201#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 35202#L1359-3 assume !(1 == ~E_11~0); 35735#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 34800#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34801#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 34978#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 34979#L1709 assume !(0 == start_simulation_~tmp~3#1); 35230#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35992#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34910#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 34687#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 34688#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34877#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35703#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 36080#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 35068#L1690-2 [2022-12-13 15:05:49,416 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:49,416 INFO L85 PathProgramCache]: Analyzing trace with hash -24556996, now seen corresponding path program 1 times [2022-12-13 15:05:49,416 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:49,416 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [765578838] [2022-12-13 15:05:49,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:49,416 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:49,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:49,469 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:49,469 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:49,469 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [765578838] [2022-12-13 15:05:49,469 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [765578838] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:49,469 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:49,469 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:49,470 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2045212257] [2022-12-13 15:05:49,470 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:49,470 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:05:49,470 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:49,470 INFO L85 PathProgramCache]: Analyzing trace with hash -1946660288, now seen corresponding path program 2 times [2022-12-13 15:05:49,471 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:49,471 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1814836228] [2022-12-13 15:05:49,471 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:49,471 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:49,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:49,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:49,518 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:49,518 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1814836228] [2022-12-13 15:05:49,518 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1814836228] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:49,518 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:49,518 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:49,518 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [532454473] [2022-12-13 15:05:49,518 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:49,519 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:05:49,519 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:05:49,519 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 15:05:49,519 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 15:05:49,520 INFO L87 Difference]: Start difference. First operand 1571 states and 2324 transitions. cyclomatic complexity: 754 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:49,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:05:49,642 INFO L93 Difference]: Finished difference Result 2905 states and 4283 transitions. [2022-12-13 15:05:49,642 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2905 states and 4283 transitions. [2022-12-13 15:05:49,653 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2730 [2022-12-13 15:05:49,665 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2905 states to 2905 states and 4283 transitions. [2022-12-13 15:05:49,665 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2905 [2022-12-13 15:05:49,667 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2905 [2022-12-13 15:05:49,668 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2905 states and 4283 transitions. [2022-12-13 15:05:49,672 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:05:49,672 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2905 states and 4283 transitions. [2022-12-13 15:05:49,676 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2905 states and 4283 transitions. [2022-12-13 15:05:49,718 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2905 to 2905. [2022-12-13 15:05:49,723 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2905 states, 2905 states have (on average 1.474354561101549) internal successors, (4283), 2904 states have internal predecessors, (4283), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:49,729 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2905 states to 2905 states and 4283 transitions. [2022-12-13 15:05:49,729 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2905 states and 4283 transitions. [2022-12-13 15:05:49,730 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 15:05:49,730 INFO L428 stractBuchiCegarLoop]: Abstraction has 2905 states and 4283 transitions. [2022-12-13 15:05:49,730 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-12-13 15:05:49,730 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2905 states and 4283 transitions. [2022-12-13 15:05:49,739 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2730 [2022-12-13 15:05:49,740 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:05:49,740 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:05:49,742 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:49,742 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:49,742 INFO L748 eck$LassoCheckResult]: Stem: 39374#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 39375#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 40112#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40113#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 40255#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 40256#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39236#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39237#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40741#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40226#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40227#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40517#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 40518#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 40625#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 40705#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 40706#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 40572#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40403#L1121 assume !(0 == ~M_E~0); 40161#L1121-2 assume !(0 == ~T1_E~0); 39515#L1126-1 assume !(0 == ~T2_E~0); 39516#L1131-1 assume !(0 == ~T3_E~0); 39683#L1136-1 assume !(0 == ~T4_E~0); 39789#L1141-1 assume !(0 == ~T5_E~0); 40022#L1146-1 assume !(0 == ~T6_E~0); 40324#L1151-1 assume !(0 == ~T7_E~0); 39854#L1156-1 assume !(0 == ~T8_E~0); 39218#L1161-1 assume !(0 == ~T9_E~0); 39219#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 39445#L1171-1 assume !(0 == ~T11_E~0); 39446#L1176-1 assume !(0 == ~E_M~0); 40340#L1181-1 assume !(0 == ~E_1~0); 40480#L1186-1 assume !(0 == ~E_2~0); 40532#L1191-1 assume !(0 == ~E_3~0); 39476#L1196-1 assume !(0 == ~E_4~0); 39477#L1201-1 assume !(0 == ~E_5~0); 40757#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 40573#L1211-1 assume !(0 == ~E_7~0); 40574#L1216-1 assume !(0 == ~E_8~0); 39619#L1221-1 assume !(0 == ~E_9~0); 39620#L1226-1 assume !(0 == ~E_10~0); 39318#L1231-1 assume !(0 == ~E_11~0); 39319#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40342#L556 assume 1 == ~m_pc~0; 40343#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 39192#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39193#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39991#L1391 assume !(0 != activate_threads_~tmp~1#1); 40508#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40509#L575 assume !(1 == ~t1_pc~0); 39147#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39148#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39285#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39632#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 39585#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39586#L594 assume 1 == ~t2_pc~0; 39518#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39519#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39517#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39209#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 39210#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39274#L613 assume !(1 == ~t3_pc~0); 39392#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 39391#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39741#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40015#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 40016#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39713#L632 assume 1 == ~t4_pc~0; 39714#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 40242#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39228#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39229#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 40347#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40097#L651 assume 1 == ~t5_pc~0; 40098#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39404#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39405#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39988#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 39419#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39420#L670 assume !(1 == ~t6_pc~0); 40555#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 39777#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39509#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39510#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40061#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40062#L689 assume 1 == ~t7_pc~0; 40750#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 40179#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40180#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40571#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 39961#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39962#L708 assume !(1 == ~t8_pc~0); 39513#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 39514#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40666#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40653#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 39571#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39572#L727 assume 1 == ~t9_pc~0; 39693#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39276#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39560#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39561#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 40742#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39627#L746 assume !(1 == ~t10_pc~0); 39628#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 40297#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40426#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40610#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 40511#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39802#L765 assume 1 == ~t11_pc~0; 39803#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 40007#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40672#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40552#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 40553#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40648#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 40649#L1249-2 assume !(1 == ~T1_E~0); 40972#L1254-1 assume !(1 == ~T2_E~0); 39890#L1259-1 assume !(1 == ~T3_E~0); 40971#L1264-1 assume !(1 == ~T4_E~0); 40970#L1269-1 assume !(1 == ~T5_E~0); 40969#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 40968#L1279-1 assume !(1 == ~T7_E~0); 40967#L1284-1 assume !(1 == ~T8_E~0); 40966#L1289-1 assume !(1 == ~T9_E~0); 39940#L1294-1 assume !(1 == ~T10_E~0); 39941#L1299-1 assume !(1 == ~T11_E~0); 39950#L1304-1 assume !(1 == ~E_M~0); 40786#L1309-1 assume !(1 == ~E_1~0); 40788#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 39341#L1319-1 assume !(1 == ~E_3~0); 39342#L1324-1 assume !(1 == ~E_4~0); 40449#L1329-1 assume !(1 == ~E_5~0); 40952#L1334-1 assume !(1 == ~E_6~0); 40940#L1339-1 assume !(1 == ~E_7~0); 40679#L1344-1 assume !(1 == ~E_8~0); 40680#L1349-1 assume !(1 == ~E_9~0); 40804#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 40453#L1359-1 assume !(1 == ~E_11~0); 40454#L1364-1 assume { :end_inline_reset_delta_events } true; 39557#L1690-2 [2022-12-13 15:05:49,742 INFO L750 eck$LassoCheckResult]: Loop: 39557#L1690-2 assume !false; 39558#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40825#L1096 assume !false; 40794#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 40795#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 40345#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 40346#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 39796#L937 assume !(0 != eval_~tmp~0#1); 39798#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 39661#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 39662#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40803#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40744#L1126-3 assume !(0 == ~T2_E~0); 39984#L1131-3 assume !(0 == ~T3_E~0); 39985#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40800#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40348#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 39511#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 39512#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40675#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 40162#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 40163#L1171-3 assume !(0 == ~T11_E~0); 40207#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 39553#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 39554#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40282#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40283#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40489#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40490#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 40183#L1211-3 assume !(0 == ~E_7~0); 39465#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 39466#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 39902#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 39526#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 39527#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39750#L556-39 assume 1 == ~m_pc~0; 40290#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 40261#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40128#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39809#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 39810#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40218#L575-39 assume 1 == ~t1_pc~0; 40219#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40494#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40495#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40770#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40196#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40197#L594-39 assume !(1 == ~t2_pc~0); 40407#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 40199#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39869#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39870#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 39684#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39685#L613-39 assume 1 == ~t3_pc~0; 40629#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 39163#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39164#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40416#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 39270#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39271#L632-39 assume !(1 == ~t4_pc~0); 40455#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 39866#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39867#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40032#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40587#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39534#L651-39 assume !(1 == ~t5_pc~0); 39301#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 39302#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40053#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40054#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 40729#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40763#L670-39 assume !(1 == ~t6_pc~0); 40292#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 39207#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39208#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40014#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 39898#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39899#L689-39 assume !(1 == ~t7_pc~0); 40020#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 40021#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40038#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40396#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 39406#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39407#L708-39 assume 1 == ~t8_pc~0; 40328#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41031#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41030#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41029#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41028#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41027#L727-39 assume 1 == ~t9_pc~0; 41025#L728-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41024#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41023#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41022#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 41021#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41020#L746-39 assume 1 == ~t10_pc~0; 41018#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41017#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41016#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41015#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41014#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41013#L765-39 assume !(1 == ~t11_pc~0); 41011#L765-41 is_transmit11_triggered_~__retres1~11#1 := 0; 41010#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41009#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41008#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 41007#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41006#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 40155#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41005#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40758#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41004#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41003#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41002#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41001#L1279-3 assume !(1 == ~T7_E~0); 41000#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 40999#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 40998#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40997#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40996#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 40995#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 40994#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 40993#L1319-3 assume !(1 == ~E_3~0); 40992#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 40991#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40990#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 40989#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 40988#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 40987#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 40986#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 40985#L1359-3 assume !(1 == ~E_11~0); 40984#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 39286#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 39287#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 39467#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 39468#L1709 assume !(0 == start_simulation_~tmp~3#1); 39719#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 40738#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 40805#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 40806#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 39365#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 39366#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40633#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 40634#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 39557#L1690-2 [2022-12-13 15:05:49,743 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:49,743 INFO L85 PathProgramCache]: Analyzing trace with hash -1257740808, now seen corresponding path program 1 times [2022-12-13 15:05:49,743 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:49,743 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [896092104] [2022-12-13 15:05:49,743 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:49,743 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:49,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:49,808 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:49,808 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:49,808 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [896092104] [2022-12-13 15:05:49,808 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [896092104] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:49,808 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:49,808 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:49,809 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [142956316] [2022-12-13 15:05:49,809 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:49,809 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:05:49,809 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:49,809 INFO L85 PathProgramCache]: Analyzing trace with hash -805395776, now seen corresponding path program 1 times [2022-12-13 15:05:49,810 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:49,810 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1647311087] [2022-12-13 15:05:49,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:49,810 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:49,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:49,864 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:49,864 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:49,864 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1647311087] [2022-12-13 15:05:49,864 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1647311087] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:49,864 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:49,864 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:49,864 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1771894672] [2022-12-13 15:05:49,864 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:49,865 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:05:49,865 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:05:49,865 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 15:05:49,865 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 15:05:49,865 INFO L87 Difference]: Start difference. First operand 2905 states and 4283 transitions. cyclomatic complexity: 1380 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:49,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:05:49,991 INFO L93 Difference]: Finished difference Result 5561 states and 8178 transitions. [2022-12-13 15:05:49,991 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5561 states and 8178 transitions. [2022-12-13 15:05:50,017 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5350 [2022-12-13 15:05:50,040 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5561 states to 5561 states and 8178 transitions. [2022-12-13 15:05:50,040 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5561 [2022-12-13 15:05:50,044 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5561 [2022-12-13 15:05:50,044 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5561 states and 8178 transitions. [2022-12-13 15:05:50,051 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:05:50,051 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5561 states and 8178 transitions. [2022-12-13 15:05:50,058 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5561 states and 8178 transitions. [2022-12-13 15:05:50,151 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5561 to 5561. [2022-12-13 15:05:50,159 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5561 states, 5561 states have (on average 1.4705988131631003) internal successors, (8178), 5560 states have internal predecessors, (8178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:50,171 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5561 states to 5561 states and 8178 transitions. [2022-12-13 15:05:50,171 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5561 states and 8178 transitions. [2022-12-13 15:05:50,171 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 15:05:50,172 INFO L428 stractBuchiCegarLoop]: Abstraction has 5561 states and 8178 transitions. [2022-12-13 15:05:50,172 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-12-13 15:05:50,172 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5561 states and 8178 transitions. [2022-12-13 15:05:50,189 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5350 [2022-12-13 15:05:50,190 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:05:50,190 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:05:50,192 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:50,192 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:50,192 INFO L748 eck$LassoCheckResult]: Stem: 47848#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 47849#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 48579#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48580#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48723#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 48724#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47709#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47710#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49176#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48693#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48694#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48962#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48963#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49065#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49144#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49145#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 49012#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 48860#L1121 assume !(0 == ~M_E~0); 48632#L1121-2 assume !(0 == ~T1_E~0); 47989#L1126-1 assume !(0 == ~T2_E~0); 47990#L1131-1 assume !(0 == ~T3_E~0); 48158#L1136-1 assume !(0 == ~T4_E~0); 48263#L1141-1 assume !(0 == ~T5_E~0); 48489#L1146-1 assume !(0 == ~T6_E~0); 48790#L1151-1 assume !(0 == ~T7_E~0); 48328#L1156-1 assume !(0 == ~T8_E~0); 47695#L1161-1 assume !(0 == ~T9_E~0); 47696#L1166-1 assume !(0 == ~T10_E~0); 47919#L1171-1 assume !(0 == ~T11_E~0); 47920#L1176-1 assume !(0 == ~E_M~0); 48805#L1181-1 assume !(0 == ~E_1~0); 48925#L1186-1 assume !(0 == ~E_2~0); 48975#L1191-1 assume !(0 == ~E_3~0); 47950#L1196-1 assume !(0 == ~E_4~0); 47951#L1201-1 assume !(0 == ~E_5~0); 49190#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 49013#L1211-1 assume !(0 == ~E_7~0); 49014#L1216-1 assume !(0 == ~E_8~0); 48091#L1221-1 assume !(0 == ~E_9~0); 48092#L1226-1 assume !(0 == ~E_10~0); 47795#L1231-1 assume !(0 == ~E_11~0); 47796#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48806#L556 assume 1 == ~m_pc~0; 48807#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 47668#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47669#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 48463#L1391 assume !(0 != activate_threads_~tmp~1#1); 48952#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48953#L575 assume !(1 == ~t1_pc~0); 47623#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47624#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47762#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48105#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 48059#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48060#L594 assume 1 == ~t2_pc~0; 47992#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47993#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47991#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47684#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 47685#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47751#L613 assume !(1 == ~t3_pc~0); 47866#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 47865#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48216#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 48487#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 48488#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48188#L632 assume 1 == ~t4_pc~0; 48189#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 48709#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47701#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47702#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 48811#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48567#L651 assume 1 == ~t5_pc~0; 48568#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47878#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47879#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48460#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 47893#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47894#L670 assume !(1 == ~t6_pc~0); 48996#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 48246#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47982#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47983#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 48531#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48532#L689 assume 1 == ~t7_pc~0; 49185#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 48650#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48651#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49011#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 48433#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 48434#L708 assume !(1 == ~t8_pc~0); 47987#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 47988#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49105#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49093#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 48045#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48046#L727 assume 1 == ~t9_pc~0; 48168#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47753#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48034#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48035#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 49177#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48101#L746 assume !(1 == ~t10_pc~0); 48102#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 48764#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48877#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49051#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 48956#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48273#L765 assume 1 == ~t11_pc~0; 48274#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 48479#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49114#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 48994#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 48995#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49088#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 48713#L1249-2 assume !(1 == ~T1_E~0); 48714#L1254-1 assume !(1 == ~T2_E~0); 50126#L1259-1 assume !(1 == ~T3_E~0); 50110#L1264-1 assume !(1 == ~T4_E~0); 50108#L1269-1 assume !(1 == ~T5_E~0); 50107#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50105#L1279-1 assume !(1 == ~T7_E~0); 50103#L1284-1 assume !(1 == ~T8_E~0); 49195#L1289-1 assume !(1 == ~T9_E~0); 49196#L1294-1 assume !(1 == ~T10_E~0); 50067#L1299-1 assume !(1 == ~T11_E~0); 50065#L1304-1 assume !(1 == ~E_M~0); 50063#L1309-1 assume !(1 == ~E_1~0); 50049#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 50036#L1319-1 assume !(1 == ~E_3~0); 50023#L1324-1 assume !(1 == ~E_4~0); 50013#L1329-1 assume !(1 == ~E_5~0); 49343#L1334-1 assume !(1 == ~E_6~0); 49341#L1339-1 assume !(1 == ~E_7~0); 49316#L1344-1 assume !(1 == ~E_8~0); 49314#L1349-1 assume !(1 == ~E_9~0); 49297#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 49283#L1359-1 assume !(1 == ~E_11~0); 49274#L1364-1 assume { :end_inline_reset_delta_events } true; 49266#L1690-2 [2022-12-13 15:05:50,193 INFO L750 eck$LassoCheckResult]: Loop: 49266#L1690-2 assume !false; 49259#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49256#L1096 assume !false; 49255#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49245#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 49242#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49241#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 49239#L937 assume !(0 != eval_~tmp~0#1); 49238#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49237#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49235#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 49236#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 52895#L1126-3 assume !(0 == ~T2_E~0); 52894#L1131-3 assume !(0 == ~T3_E~0); 52893#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 52892#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 52891#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 52890#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 52889#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 52888#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 52887#L1166-3 assume !(0 == ~T10_E~0); 52886#L1171-3 assume !(0 == ~T11_E~0); 52885#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 52884#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 52883#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 52882#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 52881#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 52880#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 52879#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 52878#L1211-3 assume !(0 == ~E_7~0); 52877#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 52876#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 52875#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 52874#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 52873#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52872#L556-39 assume 1 == ~m_pc~0; 48757#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 48728#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48599#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 48283#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 48284#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48685#L575-39 assume 1 == ~t1_pc~0; 48686#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 48939#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48940#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49204#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 48665#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48666#L594-39 assume !(1 == ~t2_pc~0); 48862#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 48668#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48344#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48345#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 48159#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48160#L613-39 assume 1 == ~t3_pc~0; 49070#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47639#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47640#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 48869#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47747#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47748#L632-39 assume 1 == ~t4_pc~0; 49029#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 48341#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48342#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48504#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49027#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48009#L651-39 assume !(1 == ~t5_pc~0); 47778#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 47779#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48525#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48526#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 49167#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49197#L670-39 assume !(1 == ~t6_pc~0); 48759#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 47686#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47687#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48486#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 48373#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48374#L689-39 assume 1 == ~t7_pc~0; 48598#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 48494#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48510#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48853#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 47880#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47881#L708-39 assume 1 == ~t8_pc~0; 47821#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 47822#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48424#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 48927#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 48822#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48312#L727-39 assume !(1 == ~t9_pc~0); 48313#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 50219#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50201#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50199#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 50179#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50177#L746-39 assume 1 == ~t10_pc~0; 50174#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 50172#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50169#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50167#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 48984#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48985#L765-39 assume !(1 == ~t11_pc~0); 49225#L765-41 is_transmit11_triggered_~__retres1~11#1 := 0; 50132#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50116#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50114#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50112#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50090#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 48626#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50071#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50058#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50055#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50053#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50051#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50039#L1279-3 assume !(1 == ~T7_E~0); 50027#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49171#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49172#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50005#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50002#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 49997#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 49994#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 49991#L1319-3 assume !(1 == ~E_3~0); 49988#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49985#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49982#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 49977#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49975#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49973#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 49972#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 49971#L1359-3 assume !(1 == ~E_11~0); 49970#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49956#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 49949#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49946#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 49943#L1709 assume !(0 == start_simulation_~tmp~3#1); 48194#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49938#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 49927#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49340#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 49313#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49296#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49282#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 49273#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 49266#L1690-2 [2022-12-13 15:05:50,193 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:50,193 INFO L85 PathProgramCache]: Analyzing trace with hash -786384458, now seen corresponding path program 1 times [2022-12-13 15:05:50,193 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:50,193 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1203504512] [2022-12-13 15:05:50,193 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:50,193 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:50,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:50,258 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:50,258 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:50,258 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1203504512] [2022-12-13 15:05:50,258 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1203504512] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:50,258 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:50,258 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:50,258 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2098781656] [2022-12-13 15:05:50,258 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:50,259 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:05:50,259 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:50,259 INFO L85 PathProgramCache]: Analyzing trace with hash -1886794179, now seen corresponding path program 1 times [2022-12-13 15:05:50,259 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:50,259 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1549593714] [2022-12-13 15:05:50,260 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:50,260 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:50,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:50,310 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:50,310 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:50,310 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1549593714] [2022-12-13 15:05:50,310 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1549593714] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:50,310 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:50,310 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:50,310 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [169856900] [2022-12-13 15:05:50,310 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:50,311 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:05:50,311 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:05:50,311 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 15:05:50,311 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 15:05:50,311 INFO L87 Difference]: Start difference. First operand 5561 states and 8178 transitions. cyclomatic complexity: 2621 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:50,460 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:05:50,460 INFO L93 Difference]: Finished difference Result 10493 states and 15401 transitions. [2022-12-13 15:05:50,460 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10493 states and 15401 transitions. [2022-12-13 15:05:50,517 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10246 [2022-12-13 15:05:50,546 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10493 states to 10493 states and 15401 transitions. [2022-12-13 15:05:50,546 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10493 [2022-12-13 15:05:50,550 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10493 [2022-12-13 15:05:50,550 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10493 states and 15401 transitions. [2022-12-13 15:05:50,556 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:05:50,556 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10493 states and 15401 transitions. [2022-12-13 15:05:50,563 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10493 states and 15401 transitions. [2022-12-13 15:05:50,640 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10493 to 10489. [2022-12-13 15:05:50,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10489 states, 10489 states have (on average 1.4679187720469062) internal successors, (15397), 10488 states have internal predecessors, (15397), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:50,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10489 states to 10489 states and 15397 transitions. [2022-12-13 15:05:50,666 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10489 states and 15397 transitions. [2022-12-13 15:05:50,666 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 15:05:50,666 INFO L428 stractBuchiCegarLoop]: Abstraction has 10489 states and 15397 transitions. [2022-12-13 15:05:50,666 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-12-13 15:05:50,666 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10489 states and 15397 transitions. [2022-12-13 15:05:50,691 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10246 [2022-12-13 15:05:50,691 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:05:50,691 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:05:50,692 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:50,692 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:50,693 INFO L748 eck$LassoCheckResult]: Stem: 63912#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 63913#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 64653#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 64654#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 64810#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 64811#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 63773#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 63774#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 65311#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 64780#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 64781#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 65075#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 65076#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 65183#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 65271#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 65272#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 65131#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 64964#L1121 assume !(0 == ~M_E~0); 64713#L1121-2 assume !(0 == ~T1_E~0); 64056#L1126-1 assume !(0 == ~T2_E~0); 64057#L1131-1 assume !(0 == ~T3_E~0); 64226#L1136-1 assume !(0 == ~T4_E~0); 64331#L1141-1 assume !(0 == ~T5_E~0); 64560#L1146-1 assume !(0 == ~T6_E~0); 64887#L1151-1 assume !(0 == ~T7_E~0); 64396#L1156-1 assume !(0 == ~T8_E~0); 63759#L1161-1 assume !(0 == ~T9_E~0); 63760#L1166-1 assume !(0 == ~T10_E~0); 63984#L1171-1 assume !(0 == ~T11_E~0); 63985#L1176-1 assume !(0 == ~E_M~0); 64905#L1181-1 assume !(0 == ~E_1~0); 65033#L1186-1 assume !(0 == ~E_2~0); 65093#L1191-1 assume !(0 == ~E_3~0); 64016#L1196-1 assume !(0 == ~E_4~0); 64017#L1201-1 assume !(0 == ~E_5~0); 65330#L1206-1 assume !(0 == ~E_6~0); 65132#L1211-1 assume !(0 == ~E_7~0); 65133#L1216-1 assume !(0 == ~E_8~0); 64159#L1221-1 assume !(0 == ~E_9~0); 64160#L1226-1 assume !(0 == ~E_10~0); 63859#L1231-1 assume !(0 == ~E_11~0); 63860#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64906#L556 assume 1 == ~m_pc~0; 64907#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 63732#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63733#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 64533#L1391 assume !(0 != activate_threads_~tmp~1#1); 65065#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65066#L575 assume !(1 == ~t1_pc~0); 63687#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 63688#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63826#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 64173#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 64126#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64127#L594 assume 1 == ~t2_pc~0; 64059#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 64060#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64058#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 63748#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 63749#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63815#L613 assume !(1 == ~t3_pc~0); 63930#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 63929#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64284#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 64558#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 64559#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64256#L632 assume 1 == ~t4_pc~0; 64257#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 64796#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 63765#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 63766#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 64911#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64641#L651 assume 1 == ~t5_pc~0; 64642#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 63943#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63944#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64530#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 63958#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63959#L670 assume !(1 == ~t6_pc~0); 65114#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 64314#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64049#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 64050#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 64602#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64603#L689 assume 1 == ~t7_pc~0; 65325#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 64731#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64732#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 65130#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 64503#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64504#L708 assume !(1 == ~t8_pc~0); 64054#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 64055#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65226#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 65210#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 64112#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 64113#L727 assume 1 == ~t9_pc~0; 64236#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 63817#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 64101#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 64102#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 65312#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 64169#L746 assume !(1 == ~t10_pc~0); 64170#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 64856#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 64982#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 65169#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 65069#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 64341#L765 assume 1 == ~t11_pc~0; 64342#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 64549#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 65235#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 65112#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 65113#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65204#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 64800#L1249-2 assume !(1 == ~T1_E~0); 64801#L1254-1 assume !(1 == ~T2_E~0); 65574#L1259-1 assume !(1 == ~T3_E~0); 65571#L1264-1 assume !(1 == ~T4_E~0); 65568#L1269-1 assume !(1 == ~T5_E~0); 65565#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 65562#L1279-1 assume !(1 == ~T7_E~0); 65559#L1284-1 assume !(1 == ~T8_E~0); 65556#L1289-1 assume !(1 == ~T9_E~0); 65553#L1294-1 assume !(1 == ~T10_E~0); 65550#L1299-1 assume !(1 == ~T11_E~0); 65547#L1304-1 assume !(1 == ~E_M~0); 65544#L1309-1 assume !(1 == ~E_1~0); 65542#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 65541#L1319-1 assume !(1 == ~E_3~0); 65527#L1324-1 assume !(1 == ~E_4~0); 65524#L1329-1 assume !(1 == ~E_5~0); 65521#L1334-1 assume !(1 == ~E_6~0); 65517#L1339-1 assume !(1 == ~E_7~0); 65516#L1344-1 assume !(1 == ~E_8~0); 65487#L1349-1 assume !(1 == ~E_9~0); 65464#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 65448#L1359-1 assume !(1 == ~E_11~0); 65439#L1364-1 assume { :end_inline_reset_delta_events } true; 65431#L1690-2 [2022-12-13 15:05:50,693 INFO L750 eck$LassoCheckResult]: Loop: 65431#L1690-2 assume !false; 65424#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 65421#L1096 assume !false; 65420#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 65410#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 65407#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 65406#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 65404#L937 assume !(0 != eval_~tmp~0#1); 65403#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 65402#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 65400#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 65401#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 66602#L1126-3 assume !(0 == ~T2_E~0); 66600#L1131-3 assume !(0 == ~T3_E~0); 66598#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 66597#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 66596#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 66593#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 66591#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 66589#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 66587#L1166-3 assume !(0 == ~T10_E~0); 66585#L1171-3 assume !(0 == ~T11_E~0); 66438#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 66435#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 66433#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 64840#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 64841#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 65043#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 65044#L1206-3 assume !(0 == ~E_6~0); 64736#L1211-3 assume !(0 == ~E_7~0); 64005#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 64006#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 64445#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 66299#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 66297#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 65369#L556-39 assume 1 == ~m_pc~0; 64848#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 64816#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64676#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 64677#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 66182#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 64771#L575-39 assume 1 == ~t1_pc~0; 64772#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 65159#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66165#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 66161#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 66156#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66152#L594-39 assume !(1 == ~t2_pc~0); 66147#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 64752#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64412#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 64413#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 66141#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66139#L613-39 assume !(1 == ~t3_pc~0); 66137#L613-41 is_transmit3_triggered_~__retres1~3#1 := 0; 63703#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63704#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 64973#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 63811#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63812#L632-39 assume !(1 == ~t4_pc~0); 65008#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 65009#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 65973#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65971#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 65969#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65967#L651-39 assume !(1 == ~t5_pc~0); 65965#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 65963#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 65960#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 65958#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 65956#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 65954#L670-39 assume 1 == ~t6_pc~0; 65952#L671-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 65949#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 65947#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 65945#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 65944#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 65943#L689-39 assume 1 == ~t7_pc~0; 65939#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 65937#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64956#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 64957#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 65374#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 65838#L708-39 assume 1 == ~t8_pc~0; 63885#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 63886#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65035#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 65036#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 65810#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 65807#L727-39 assume !(1 == ~t9_pc~0); 65805#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 65802#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 63777#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 63778#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 64969#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 64970#L746-39 assume !(1 == ~t10_pc~0); 64945#L746-41 is_transmit10_triggered_~__retres1~10#1 := 0; 64944#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 65234#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 64660#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 64661#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 65102#L765-39 assume !(1 == ~t11_pc~0); 65370#L765-41 is_transmit11_triggered_~__retres1~11#1 := 0; 65657#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 65650#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 65643#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 65636#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64706#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 64707#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 65622#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 65331#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 65610#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 65606#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 65602#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 65598#L1279-3 assume !(1 == ~T7_E~0); 65594#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 65590#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 65586#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 65580#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 65578#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 65576#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 65573#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 65570#L1319-3 assume !(1 == ~E_3~0); 65567#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 65564#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 65561#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 65558#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 65555#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 65552#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 65549#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 65546#L1359-3 assume !(1 == ~E_11~0); 65543#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 65530#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 65525#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 65522#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 65518#L1709 assume !(0 == start_simulation_~tmp~3#1); 64262#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 65513#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 65486#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 65484#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 65482#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 65463#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 65447#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 65438#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 65431#L1690-2 [2022-12-13 15:05:50,693 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:50,694 INFO L85 PathProgramCache]: Analyzing trace with hash 602909556, now seen corresponding path program 1 times [2022-12-13 15:05:50,694 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:50,694 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1979673160] [2022-12-13 15:05:50,694 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:50,694 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:50,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:50,733 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:50,733 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:50,733 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1979673160] [2022-12-13 15:05:50,734 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1979673160] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:50,734 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:50,734 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 15:05:50,734 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [183474637] [2022-12-13 15:05:50,734 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:50,734 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:05:50,735 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:50,735 INFO L85 PathProgramCache]: Analyzing trace with hash -966288707, now seen corresponding path program 1 times [2022-12-13 15:05:50,735 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:50,735 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1386313924] [2022-12-13 15:05:50,735 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:50,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:50,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:50,784 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:50,784 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:50,784 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1386313924] [2022-12-13 15:05:50,784 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1386313924] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:50,785 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:50,785 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:50,785 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1801745247] [2022-12-13 15:05:50,785 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:50,785 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:05:50,785 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:05:50,785 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:05:50,785 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:05:50,785 INFO L87 Difference]: Start difference. First operand 10489 states and 15397 transitions. cyclomatic complexity: 4916 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:50,938 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:05:50,938 INFO L93 Difference]: Finished difference Result 20569 states and 29966 transitions. [2022-12-13 15:05:50,938 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20569 states and 29966 transitions. [2022-12-13 15:05:50,997 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 20319 [2022-12-13 15:05:51,041 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20569 states to 20569 states and 29966 transitions. [2022-12-13 15:05:51,041 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20569 [2022-12-13 15:05:51,052 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20569 [2022-12-13 15:05:51,052 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20569 states and 29966 transitions. [2022-12-13 15:05:51,064 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:05:51,064 INFO L218 hiAutomatonCegarLoop]: Abstraction has 20569 states and 29966 transitions. [2022-12-13 15:05:51,108 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20569 states and 29966 transitions. [2022-12-13 15:05:51,302 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20569 to 19905. [2022-12-13 15:05:51,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19905 states, 19905 states have (on average 1.458427530771163) internal successors, (29030), 19904 states have internal predecessors, (29030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:51,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19905 states to 19905 states and 29030 transitions. [2022-12-13 15:05:51,370 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19905 states and 29030 transitions. [2022-12-13 15:05:51,370 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:05:51,371 INFO L428 stractBuchiCegarLoop]: Abstraction has 19905 states and 29030 transitions. [2022-12-13 15:05:51,371 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-12-13 15:05:51,371 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19905 states and 29030 transitions. [2022-12-13 15:05:51,421 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19655 [2022-12-13 15:05:51,421 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:05:51,421 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:05:51,422 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:51,422 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:51,423 INFO L748 eck$LassoCheckResult]: Stem: 94975#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 94976#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 95718#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 95719#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 95871#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 95872#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 94836#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 94837#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 96418#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 95842#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 95843#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 96139#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 96140#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 96267#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 96365#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 96366#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 96204#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 96018#L1121 assume !(0 == ~M_E~0); 95774#L1121-2 assume !(0 == ~T1_E~0); 95113#L1126-1 assume !(0 == ~T2_E~0); 95114#L1131-1 assume !(0 == ~T3_E~0); 95283#L1136-1 assume !(0 == ~T4_E~0); 95392#L1141-1 assume !(0 == ~T5_E~0); 95624#L1146-1 assume !(0 == ~T6_E~0); 95944#L1151-1 assume !(0 == ~T7_E~0); 95457#L1156-1 assume !(0 == ~T8_E~0); 94822#L1161-1 assume !(0 == ~T9_E~0); 94823#L1166-1 assume !(0 == ~T10_E~0); 95043#L1171-1 assume !(0 == ~T11_E~0); 95044#L1176-1 assume !(0 == ~E_M~0); 95959#L1181-1 assume !(0 == ~E_1~0); 96096#L1186-1 assume !(0 == ~E_2~0); 96156#L1191-1 assume !(0 == ~E_3~0); 95074#L1196-1 assume !(0 == ~E_4~0); 95075#L1201-1 assume !(0 == ~E_5~0); 96448#L1206-1 assume !(0 == ~E_6~0); 96205#L1211-1 assume !(0 == ~E_7~0); 96206#L1216-1 assume !(0 == ~E_8~0); 95215#L1221-1 assume !(0 == ~E_9~0); 95216#L1226-1 assume !(0 == ~E_10~0); 94922#L1231-1 assume !(0 == ~E_11~0); 94923#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95960#L556 assume !(1 == ~m_pc~0); 95961#L556-2 is_master_triggered_~__retres1~0#1 := 0; 94796#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 94797#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 95592#L1391 assume !(0 != activate_threads_~tmp~1#1); 96129#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 96130#L575 assume !(1 == ~t1_pc~0); 94752#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 94753#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 94889#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 95229#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 95184#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95185#L594 assume 1 == ~t2_pc~0; 95116#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 95117#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95115#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 94811#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 94812#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 94878#L613 assume !(1 == ~t3_pc~0); 94993#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 94992#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 95343#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 95622#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 95623#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 95315#L632 assume 1 == ~t4_pc~0; 95316#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 95858#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 94828#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 94829#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 95964#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95705#L651 assume 1 == ~t5_pc~0; 95706#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 95004#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 95005#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 95589#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 95018#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 95019#L670 assume !(1 == ~t6_pc~0); 96185#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 95374#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 95106#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 95107#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 95666#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 95667#L689 assume 1 == ~t7_pc~0; 96434#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 95794#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 95795#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 96203#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 95562#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 95563#L708 assume !(1 == ~t8_pc~0); 95111#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 95112#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 96314#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 96300#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 95169#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 95170#L727 assume 1 == ~t9_pc~0; 95293#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 94880#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 95158#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 95159#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 96419#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 95225#L746 assume !(1 == ~t10_pc~0); 95226#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 95918#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 96039#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 96248#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 96133#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 95401#L765 assume 1 == ~t11_pc~0; 95402#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 95611#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 96325#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 96183#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 96184#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96295#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 95862#L1249-2 assume !(1 == ~T1_E~0); 95492#L1254-1 assume !(1 == ~T2_E~0); 94807#L1259-1 assume !(1 == ~T3_E~0); 94789#L1264-1 assume !(1 == ~T4_E~0); 94790#L1269-1 assume !(1 == ~T5_E~0); 96516#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 96381#L1279-1 assume !(1 == ~T7_E~0); 94994#L1284-1 assume !(1 == ~T8_E~0); 94995#L1289-1 assume !(1 == ~T9_E~0); 95541#L1294-1 assume !(1 == ~T10_E~0); 95542#L1299-1 assume !(1 == ~T11_E~0); 95551#L1304-1 assume !(1 == ~E_M~0); 96487#L1309-1 assume !(1 == ~E_1~0); 96491#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 94943#L1319-1 assume !(1 == ~E_3~0); 94944#L1324-1 assume !(1 == ~E_4~0); 95067#L1329-1 assume !(1 == ~E_5~0); 95068#L1334-1 assume !(1 == ~E_6~0); 97600#L1339-1 assume !(1 == ~E_7~0); 97599#L1344-1 assume !(1 == ~E_8~0); 97598#L1349-1 assume !(1 == ~E_9~0); 97563#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 97536#L1359-1 assume !(1 == ~E_11~0); 97514#L1364-1 assume { :end_inline_reset_delta_events } true; 97493#L1690-2 [2022-12-13 15:05:51,423 INFO L750 eck$LassoCheckResult]: Loop: 97493#L1690-2 assume !false; 97479#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 97470#L1096 assume !false; 97462#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 97440#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 97436#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 97434#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 97429#L937 assume !(0 != eval_~tmp~0#1); 97431#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 97425#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 97426#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 99927#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 99919#L1126-3 assume !(0 == ~T2_E~0); 99909#L1131-3 assume !(0 == ~T3_E~0); 99901#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 99893#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 99885#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 99876#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 99868#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 99858#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 99850#L1166-3 assume !(0 == ~T10_E~0); 99840#L1171-3 assume !(0 == ~T11_E~0); 99838#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 99836#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 99834#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 99831#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 99829#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 99827#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 99825#L1206-3 assume !(0 == ~E_6~0); 99771#L1211-3 assume !(0 == ~E_7~0); 99762#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 99756#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 99750#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 99735#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 99733#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 99731#L556-39 assume !(1 == ~m_pc~0); 99728#L556-41 is_master_triggered_~__retres1~0#1 := 0; 99726#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 99724#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 99722#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 99720#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 99718#L575-39 assume 1 == ~t1_pc~0; 99713#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 99711#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 99709#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 99707#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 99705#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 99702#L594-39 assume !(1 == ~t2_pc~0); 99689#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 99680#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 99671#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 99664#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 99656#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 99649#L613-39 assume !(1 == ~t3_pc~0); 99611#L613-41 is_transmit3_triggered_~__retres1~3#1 := 0; 99608#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 99606#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 99604#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 99594#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 99583#L632-39 assume 1 == ~t4_pc~0; 99575#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 99568#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 99563#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 99562#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 99561#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 99560#L651-39 assume 1 == ~t5_pc~0; 99557#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 99555#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 99552#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 99550#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 99548#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 99546#L670-39 assume !(1 == ~t6_pc~0); 99543#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 99542#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 99540#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 99538#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 99535#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 99533#L689-39 assume !(1 == ~t7_pc~0); 99531#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 99528#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 99526#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 99524#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 99523#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 99522#L708-39 assume 1 == ~t8_pc~0; 99520#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 99517#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 99514#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 99512#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 99510#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 99508#L727-39 assume 1 == ~t9_pc~0; 99505#L728-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 99503#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 99502#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 99500#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 99498#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 99497#L746-39 assume !(1 == ~t10_pc~0); 99447#L746-41 is_transmit10_triggered_~__retres1~10#1 := 0; 99437#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 99429#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 99420#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 99414#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 99407#L765-39 assume !(1 == ~t11_pc~0); 99395#L765-41 is_transmit11_triggered_~__retres1~11#1 := 0; 99384#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 99376#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 99367#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 99359#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 99350#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 95768#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 99207#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 99203#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 99201#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 99199#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 99197#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 99195#L1279-3 assume !(1 == ~T7_E~0); 99193#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 99191#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 99187#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 99183#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 99181#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 99179#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 99177#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 99175#L1319-3 assume !(1 == ~E_3~0); 99173#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 99171#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 99170#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 99167#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 99164#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 99162#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 99160#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 99158#L1359-3 assume !(1 == ~E_11~0); 99156#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 99143#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 99138#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 99134#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 99131#L1709 assume !(0 == start_simulation_~tmp~3#1); 95321#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 99124#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 99111#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 99108#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 97597#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 97562#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 97535#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 97513#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 97493#L1690-2 [2022-12-13 15:05:51,423 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:51,423 INFO L85 PathProgramCache]: Analyzing trace with hash -1258502475, now seen corresponding path program 1 times [2022-12-13 15:05:51,424 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:51,424 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1111163167] [2022-12-13 15:05:51,424 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:51,424 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:51,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:51,480 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:51,480 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:51,480 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1111163167] [2022-12-13 15:05:51,480 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1111163167] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:51,481 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:51,481 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:51,481 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2075541603] [2022-12-13 15:05:51,481 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:51,481 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:05:51,482 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:51,482 INFO L85 PathProgramCache]: Analyzing trace with hash 1305961213, now seen corresponding path program 1 times [2022-12-13 15:05:51,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:51,482 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [185056999] [2022-12-13 15:05:51,482 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:51,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:51,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:51,525 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:51,525 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:51,525 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [185056999] [2022-12-13 15:05:51,526 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [185056999] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:51,526 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:51,526 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:51,526 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2035618979] [2022-12-13 15:05:51,526 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:51,526 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:05:51,527 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:05:51,527 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 15:05:51,527 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 15:05:51,527 INFO L87 Difference]: Start difference. First operand 19905 states and 29030 transitions. cyclomatic complexity: 9141 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:51,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:05:51,913 INFO L93 Difference]: Finished difference Result 48409 states and 70033 transitions. [2022-12-13 15:05:51,913 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48409 states and 70033 transitions. [2022-12-13 15:05:52,070 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 47432 [2022-12-13 15:05:52,186 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48409 states to 48409 states and 70033 transitions. [2022-12-13 15:05:52,186 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 48409 [2022-12-13 15:05:52,213 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 48409 [2022-12-13 15:05:52,214 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48409 states and 70033 transitions. [2022-12-13 15:05:52,242 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:05:52,242 INFO L218 hiAutomatonCegarLoop]: Abstraction has 48409 states and 70033 transitions. [2022-12-13 15:05:52,278 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48409 states and 70033 transitions. [2022-12-13 15:05:52,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48409 to 37973. [2022-12-13 15:05:52,689 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37973 states, 37973 states have (on average 1.4516630237273853) internal successors, (55124), 37972 states have internal predecessors, (55124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:52,752 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37973 states to 37973 states and 55124 transitions. [2022-12-13 15:05:52,752 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37973 states and 55124 transitions. [2022-12-13 15:05:52,753 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 15:05:52,753 INFO L428 stractBuchiCegarLoop]: Abstraction has 37973 states and 55124 transitions. [2022-12-13 15:05:52,753 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-12-13 15:05:52,753 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37973 states and 55124 transitions. [2022-12-13 15:05:52,896 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 37716 [2022-12-13 15:05:52,896 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:05:52,896 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:05:52,897 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:52,898 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:52,898 INFO L748 eck$LassoCheckResult]: Stem: 163299#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 163300#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 164036#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 164037#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 164186#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 164187#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 163165#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 163166#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 164689#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 164154#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 164155#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 164458#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 164459#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 164569#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 164653#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 164654#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 164513#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 164337#L1121 assume !(0 == ~M_E~0); 164087#L1121-2 assume !(0 == ~T1_E~0); 163437#L1126-1 assume !(0 == ~T2_E~0); 163438#L1131-1 assume !(0 == ~T3_E~0); 163603#L1136-1 assume !(0 == ~T4_E~0); 163710#L1141-1 assume !(0 == ~T5_E~0); 163949#L1146-1 assume !(0 == ~T6_E~0); 164269#L1151-1 assume !(0 == ~T7_E~0); 163775#L1156-1 assume !(0 == ~T8_E~0); 163147#L1161-1 assume !(0 == ~T9_E~0); 163148#L1166-1 assume !(0 == ~T10_E~0); 163366#L1171-1 assume !(0 == ~T11_E~0); 163367#L1176-1 assume !(0 == ~E_M~0); 164282#L1181-1 assume !(0 == ~E_1~0); 164415#L1186-1 assume !(0 == ~E_2~0); 164475#L1191-1 assume !(0 == ~E_3~0); 163398#L1196-1 assume !(0 == ~E_4~0); 163399#L1201-1 assume !(0 == ~E_5~0); 164712#L1206-1 assume !(0 == ~E_6~0); 164514#L1211-1 assume !(0 == ~E_7~0); 164515#L1216-1 assume !(0 == ~E_8~0); 163539#L1221-1 assume !(0 == ~E_9~0); 163540#L1226-1 assume !(0 == ~E_10~0); 163247#L1231-1 assume !(0 == ~E_11~0); 163248#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 164285#L556 assume !(1 == ~m_pc~0); 164286#L556-2 is_master_triggered_~__retres1~0#1 := 0; 163120#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 163121#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 163917#L1391 assume !(0 != activate_threads_~tmp~1#1); 164447#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 164448#L575 assume !(1 == ~t1_pc~0); 163076#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 163077#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 163214#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 163552#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 163505#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 163506#L594 assume !(1 == ~t2_pc~0); 164253#L594-2 is_transmit2_triggered_~__retres1~2#1 := 0; 164348#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 163439#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 163138#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 163139#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 163203#L613 assume !(1 == ~t3_pc~0); 163316#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 163315#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 163663#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 163942#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 163943#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 163635#L632 assume 1 == ~t4_pc~0; 163636#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 164170#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 163157#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 163158#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 164288#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 164022#L651 assume 1 == ~t5_pc~0; 164023#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 163328#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 163329#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 163914#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 163342#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 163343#L670 assume !(1 == ~t6_pc~0); 164498#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 163698#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 163431#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 163432#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 163986#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 163987#L689 assume 1 == ~t7_pc~0; 164705#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 164108#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 164109#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 164512#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 163886#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 163887#L708 assume !(1 == ~t8_pc~0); 163435#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 163436#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 164615#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 164601#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 163490#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 163491#L727 assume 1 == ~t9_pc~0; 163614#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 163205#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 163479#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 163480#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 164695#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 163547#L746 assume !(1 == ~t10_pc~0); 163548#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 164236#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 164357#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 164552#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 164452#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 163722#L765 assume 1 == ~t11_pc~0; 163723#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 163933#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 164622#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 164495#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 164496#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 164596#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 164175#L1249-2 assume !(1 == ~T1_E~0); 164176#L1254-1 assume !(1 == ~T2_E~0); 188014#L1259-1 assume !(1 == ~T3_E~0); 188012#L1264-1 assume !(1 == ~T4_E~0); 188010#L1269-1 assume !(1 == ~T5_E~0); 188008#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 188006#L1279-1 assume !(1 == ~T7_E~0); 188004#L1284-1 assume !(1 == ~T8_E~0); 188002#L1289-1 assume !(1 == ~T9_E~0); 188000#L1294-1 assume !(1 == ~T10_E~0); 187982#L1299-1 assume !(1 == ~T11_E~0); 187981#L1304-1 assume !(1 == ~E_M~0); 187980#L1309-1 assume !(1 == ~E_1~0); 187979#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 187978#L1319-1 assume !(1 == ~E_3~0); 187977#L1324-1 assume !(1 == ~E_4~0); 187976#L1329-1 assume !(1 == ~E_5~0); 187971#L1334-1 assume !(1 == ~E_6~0); 187969#L1339-1 assume !(1 == ~E_7~0); 187968#L1344-1 assume !(1 == ~E_8~0); 187967#L1349-1 assume !(1 == ~E_9~0); 187966#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 187965#L1359-1 assume !(1 == ~E_11~0); 187964#L1364-1 assume { :end_inline_reset_delta_events } true; 187949#L1690-2 [2022-12-13 15:05:52,898 INFO L750 eck$LassoCheckResult]: Loop: 187949#L1690-2 assume !false; 187939#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 187890#L1096 assume !false; 187877#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 187863#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 187856#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 187852#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 187844#L937 assume !(0 != eval_~tmp~0#1); 187845#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 199919#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 199917#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 199916#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 199699#L1126-3 assume !(0 == ~T2_E~0); 197424#L1131-3 assume !(0 == ~T3_E~0); 197421#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 197419#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 197417#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 197415#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 197413#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 197411#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 197408#L1166-3 assume !(0 == ~T10_E~0); 197406#L1171-3 assume !(0 == ~T11_E~0); 197404#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 197402#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 197400#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 197398#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 197395#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 197393#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 197391#L1206-3 assume !(0 == ~E_6~0); 197389#L1211-3 assume !(0 == ~E_7~0); 197387#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 197385#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 197382#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 197380#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 197378#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 197376#L556-39 assume !(1 == ~m_pc~0); 197374#L556-41 is_master_triggered_~__retres1~0#1 := 0; 197372#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 197369#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 197367#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 197365#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 197363#L575-39 assume !(1 == ~t1_pc~0); 197361#L575-41 is_transmit1_triggered_~__retres1~1#1 := 0; 197358#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 197355#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 197353#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 197351#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 197349#L594-39 assume !(1 == ~t2_pc~0); 190057#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 197346#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 197343#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 197341#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 197339#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 197337#L613-39 assume !(1 == ~t3_pc~0); 197335#L613-41 is_transmit3_triggered_~__retres1~3#1 := 0; 197332#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 197329#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 197327#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 197325#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 197323#L632-39 assume 1 == ~t4_pc~0; 197321#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 197318#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 197316#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 197315#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 197314#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 197313#L651-39 assume !(1 == ~t5_pc~0); 197312#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 197310#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 197309#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 197308#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 197307#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 197306#L670-39 assume 1 == ~t6_pc~0; 197305#L671-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 197303#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 197302#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 197301#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 197299#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 197297#L689-39 assume !(1 == ~t7_pc~0); 197295#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 197292#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 197290#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 197288#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 197286#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 197283#L708-39 assume 1 == ~t8_pc~0; 197281#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 197278#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 197276#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 197274#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 197272#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 197271#L727-39 assume !(1 == ~t9_pc~0); 197269#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 197266#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 197264#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 197262#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 197260#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 197257#L746-39 assume !(1 == ~t10_pc~0); 197255#L746-41 is_transmit10_triggered_~__retres1~10#1 := 0; 197252#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 197250#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 197248#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 197246#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 197243#L765-39 assume 1 == ~t11_pc~0; 197241#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 197238#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 197236#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 197234#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 197232#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 197229#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 164081#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 197226#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 197222#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 197220#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 197218#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 197217#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 197216#L1279-3 assume !(1 == ~T7_E~0); 197215#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 197213#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 197211#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 191979#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 197208#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 197206#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 197204#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 197202#L1319-3 assume !(1 == ~E_3~0); 197199#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 191370#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 189331#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 189327#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 189325#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 189323#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 189320#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 189318#L1359-3 assume !(1 == ~E_11~0); 189316#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 189214#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 189205#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 189198#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 189192#L1709 assume !(0 == start_simulation_~tmp~3#1); 189186#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 188177#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 188166#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 188164#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 188161#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 188083#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 188063#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 187963#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 187949#L1690-2 [2022-12-13 15:05:52,898 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:52,899 INFO L85 PathProgramCache]: Analyzing trace with hash 1819278198, now seen corresponding path program 1 times [2022-12-13 15:05:52,899 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:52,899 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1274720309] [2022-12-13 15:05:52,899 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:52,899 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:52,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:52,981 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:52,982 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:52,982 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1274720309] [2022-12-13 15:05:52,982 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1274720309] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:52,982 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:52,982 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 15:05:52,982 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1157387447] [2022-12-13 15:05:52,982 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:52,982 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:05:52,983 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:52,983 INFO L85 PathProgramCache]: Analyzing trace with hash 1840634686, now seen corresponding path program 1 times [2022-12-13 15:05:52,983 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:52,983 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [943800857] [2022-12-13 15:05:52,983 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:52,983 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:52,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:53,014 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:53,014 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:53,014 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [943800857] [2022-12-13 15:05:53,014 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [943800857] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:53,014 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:53,014 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:53,014 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1786250789] [2022-12-13 15:05:53,014 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:53,015 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:05:53,015 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:05:53,015 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:05:53,015 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:05:53,015 INFO L87 Difference]: Start difference. First operand 37973 states and 55124 transitions. cyclomatic complexity: 17167 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:53,240 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:05:53,241 INFO L93 Difference]: Finished difference Result 72612 states and 104949 transitions. [2022-12-13 15:05:53,241 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 72612 states and 104949 transitions. [2022-12-13 15:05:53,493 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 72276 [2022-12-13 15:05:53,618 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 72612 states to 72612 states and 104949 transitions. [2022-12-13 15:05:53,618 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 72612 [2022-12-13 15:05:53,647 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 72612 [2022-12-13 15:05:53,647 INFO L73 IsDeterministic]: Start isDeterministic. Operand 72612 states and 104949 transitions. [2022-12-13 15:05:53,679 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:05:53,679 INFO L218 hiAutomatonCegarLoop]: Abstraction has 72612 states and 104949 transitions. [2022-12-13 15:05:53,712 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72612 states and 104949 transitions. [2022-12-13 15:05:54,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72612 to 72548. [2022-12-13 15:05:54,350 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72548 states, 72548 states have (on average 1.4457324805645917) internal successors, (104885), 72547 states have internal predecessors, (104885), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:54,472 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72548 states to 72548 states and 104885 transitions. [2022-12-13 15:05:54,473 INFO L240 hiAutomatonCegarLoop]: Abstraction has 72548 states and 104885 transitions. [2022-12-13 15:05:54,473 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:05:54,473 INFO L428 stractBuchiCegarLoop]: Abstraction has 72548 states and 104885 transitions. [2022-12-13 15:05:54,474 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-12-13 15:05:54,474 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72548 states and 104885 transitions. [2022-12-13 15:05:54,726 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 72212 [2022-12-13 15:05:54,727 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:05:54,727 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:05:54,728 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:54,728 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:54,728 INFO L748 eck$LassoCheckResult]: Stem: 273894#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 273895#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 274655#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 274656#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 274813#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 274814#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 273755#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 273756#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 275433#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 274778#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 274779#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 275110#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 275111#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 275249#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 275366#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 275367#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 275180#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 274973#L1121 assume !(0 == ~M_E~0); 274710#L1121-2 assume !(0 == ~T1_E~0); 274035#L1126-1 assume !(0 == ~T2_E~0); 274036#L1131-1 assume !(0 == ~T3_E~0); 274207#L1136-1 assume !(0 == ~T4_E~0); 274318#L1141-1 assume !(0 == ~T5_E~0); 274561#L1146-1 assume !(0 == ~T6_E~0); 274900#L1151-1 assume !(0 == ~T7_E~0); 274384#L1156-1 assume !(0 == ~T8_E~0); 273739#L1161-1 assume !(0 == ~T9_E~0); 273740#L1166-1 assume !(0 == ~T10_E~0); 273963#L1171-1 assume !(0 == ~T11_E~0); 273964#L1176-1 assume !(0 == ~E_M~0); 274913#L1181-1 assume !(0 == ~E_1~0); 275058#L1186-1 assume !(0 == ~E_2~0); 275131#L1191-1 assume !(0 == ~E_3~0); 273995#L1196-1 assume !(0 == ~E_4~0); 273996#L1201-1 assume !(0 == ~E_5~0); 275464#L1206-1 assume !(0 == ~E_6~0); 275181#L1211-1 assume !(0 == ~E_7~0); 275182#L1216-1 assume !(0 == ~E_8~0); 274136#L1221-1 assume !(0 == ~E_9~0); 274137#L1226-1 assume !(0 == ~E_10~0); 273839#L1231-1 assume !(0 == ~E_11~0); 273840#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 274914#L556 assume !(1 == ~m_pc~0); 274915#L556-2 is_master_triggered_~__retres1~0#1 := 0; 273713#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 273714#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 274531#L1391 assume !(0 != activate_threads_~tmp~1#1); 275098#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 275099#L575 assume !(1 == ~t1_pc~0); 273668#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 273669#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 273806#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 274151#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 274105#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 274106#L594 assume !(1 == ~t2_pc~0); 274884#L594-2 is_transmit2_triggered_~__retres1~2#1 := 0; 274986#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 274037#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 273730#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 273731#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 273795#L613 assume !(1 == ~t3_pc~0); 273911#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 273910#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 274270#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 274557#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 274558#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 274242#L632 assume !(1 == ~t4_pc~0); 274243#L632-2 is_transmit4_triggered_~__retres1~4#1 := 0; 274974#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 273745#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 273746#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 274918#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 274640#L651 assume 1 == ~t5_pc~0; 274641#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 273923#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 273924#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 274528#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 273938#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 273939#L670 assume !(1 == ~t6_pc~0); 275161#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 274303#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 274028#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 274029#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 274602#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 274603#L689 assume 1 == ~t7_pc~0; 275449#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 274729#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 274730#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 275179#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 274499#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 274500#L708 assume !(1 == ~t8_pc~0); 274033#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 274034#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 275300#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 275281#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 274090#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 274091#L727 assume 1 == ~t9_pc~0; 274218#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 273797#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 274078#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 274079#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 275434#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 274146#L746 assume !(1 == ~t10_pc~0); 274147#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 274869#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 274996#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 275232#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 275102#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 274327#L765 assume 1 == ~t11_pc~0; 274328#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 274548#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 275316#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 275159#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 275160#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 275276#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 275277#L1249-2 assume !(1 == ~T1_E~0); 279227#L1254-1 assume !(1 == ~T2_E~0); 279225#L1259-1 assume !(1 == ~T3_E~0); 279222#L1264-1 assume !(1 == ~T4_E~0); 279220#L1269-1 assume !(1 == ~T5_E~0); 279218#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 279216#L1279-1 assume !(1 == ~T7_E~0); 279214#L1284-1 assume !(1 == ~T8_E~0); 279212#L1289-1 assume !(1 == ~T9_E~0); 279210#L1294-1 assume !(1 == ~T10_E~0); 279209#L1299-1 assume !(1 == ~T11_E~0); 279208#L1304-1 assume !(1 == ~E_M~0); 279207#L1309-1 assume !(1 == ~E_1~0); 279205#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 279203#L1319-1 assume !(1 == ~E_3~0); 279201#L1324-1 assume !(1 == ~E_4~0); 279199#L1329-1 assume !(1 == ~E_5~0); 279197#L1334-1 assume !(1 == ~E_6~0); 278697#L1339-1 assume !(1 == ~E_7~0); 279194#L1344-1 assume !(1 == ~E_8~0); 279192#L1349-1 assume !(1 == ~E_9~0); 279190#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 279188#L1359-1 assume !(1 == ~E_11~0); 279186#L1364-1 assume { :end_inline_reset_delta_events } true; 279183#L1690-2 [2022-12-13 15:05:54,728 INFO L750 eck$LassoCheckResult]: Loop: 279183#L1690-2 assume !false; 278977#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 278974#L1096 assume !false; 278973#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 278956#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 278952#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 278950#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 278947#L937 assume !(0 != eval_~tmp~0#1); 278948#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 282811#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 282809#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 282807#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 282805#L1126-3 assume !(0 == ~T2_E~0); 282803#L1131-3 assume !(0 == ~T3_E~0); 282801#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 282799#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 282797#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 282795#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 282793#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 282791#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 282789#L1166-3 assume !(0 == ~T10_E~0); 282787#L1171-3 assume !(0 == ~T11_E~0); 282785#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 282783#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 282781#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 282779#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 282777#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 282775#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 282773#L1206-3 assume !(0 == ~E_6~0); 282771#L1211-3 assume !(0 == ~E_7~0); 282769#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 282767#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 282765#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 282763#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 282761#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 282759#L556-39 assume !(1 == ~m_pc~0); 282757#L556-41 is_master_triggered_~__retres1~0#1 := 0; 282755#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 282753#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 282751#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 282749#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 282747#L575-39 assume 1 == ~t1_pc~0; 282743#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 282741#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 282739#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 282737#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 282735#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 282731#L594-39 assume !(1 == ~t2_pc~0); 278354#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 282728#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 282726#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 282724#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 282722#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 282720#L613-39 assume 1 == ~t3_pc~0; 282716#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 282714#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 282712#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 282710#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 282708#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 282706#L632-39 assume !(1 == ~t4_pc~0); 282704#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 282702#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 282700#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 282698#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 282696#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 282694#L651-39 assume 1 == ~t5_pc~0; 282690#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 282688#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 282686#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 282684#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 282682#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 282680#L670-39 assume !(1 == ~t6_pc~0); 282676#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 282674#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 282672#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 282670#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 282668#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 282666#L689-39 assume 1 == ~t7_pc~0; 282662#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 282660#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 282658#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 282656#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 282654#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 282652#L708-39 assume !(1 == ~t8_pc~0); 282648#L708-41 is_transmit8_triggered_~__retres1~8#1 := 0; 282646#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 282644#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 282642#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 282640#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 282638#L727-39 assume 1 == ~t9_pc~0; 282634#L728-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 282632#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 282630#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 282628#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 282626#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 282624#L746-39 assume 1 == ~t10_pc~0; 282620#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 282618#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 282616#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 282614#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 282612#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 282610#L765-39 assume !(1 == ~t11_pc~0); 282606#L765-41 is_transmit11_triggered_~__retres1~11#1 := 0; 282604#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 282602#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 282600#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 282598#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 282596#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 281239#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 282589#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 282585#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 282583#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 282581#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 282579#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 282577#L1279-3 assume !(1 == ~T7_E~0); 282575#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 282573#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 282572#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 282566#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 282564#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 282562#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 282561#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 282560#L1319-3 assume !(1 == ~E_3~0); 282559#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 282558#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 282557#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 279224#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 282556#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 282555#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 282554#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 282553#L1359-3 assume !(1 == ~E_11~0); 282552#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 282542#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 282539#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 282538#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 282357#L1709 assume !(0 == start_simulation_~tmp~3#1); 282355#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 282346#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 282335#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 282334#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 282333#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 279464#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 279460#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 279185#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 279183#L1690-2 [2022-12-13 15:05:54,728 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:54,728 INFO L85 PathProgramCache]: Analyzing trace with hash -343701065, now seen corresponding path program 1 times [2022-12-13 15:05:54,728 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:54,729 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1659364522] [2022-12-13 15:05:54,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:54,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:54,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:54,760 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:54,760 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:54,760 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1659364522] [2022-12-13 15:05:54,760 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1659364522] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:54,760 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:54,760 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 15:05:54,760 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [505276883] [2022-12-13 15:05:54,760 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:54,761 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:05:54,761 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:54,761 INFO L85 PathProgramCache]: Analyzing trace with hash -1327543492, now seen corresponding path program 1 times [2022-12-13 15:05:54,761 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:54,761 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1513799011] [2022-12-13 15:05:54,761 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:54,761 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:54,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:54,790 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:54,790 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:54,790 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1513799011] [2022-12-13 15:05:54,790 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1513799011] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:54,790 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:54,790 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:54,791 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1870418950] [2022-12-13 15:05:54,791 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:54,791 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:05:54,791 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:05:54,791 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:05:54,791 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:05:54,792 INFO L87 Difference]: Start difference. First operand 72548 states and 104885 transitions. cyclomatic complexity: 32369 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:55,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:05:55,188 INFO L93 Difference]: Finished difference Result 141407 states and 203438 transitions. [2022-12-13 15:05:55,188 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 141407 states and 203438 transitions. [2022-12-13 15:05:55,775 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 140848 [2022-12-13 15:05:55,979 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 141407 states to 141407 states and 203438 transitions. [2022-12-13 15:05:55,979 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 141407 [2022-12-13 15:05:56,028 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 141407 [2022-12-13 15:05:56,028 INFO L73 IsDeterministic]: Start isDeterministic. Operand 141407 states and 203438 transitions. [2022-12-13 15:05:56,072 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:05:56,072 INFO L218 hiAutomatonCegarLoop]: Abstraction has 141407 states and 203438 transitions. [2022-12-13 15:05:56,129 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141407 states and 203438 transitions. [2022-12-13 15:05:57,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141407 to 141279. [2022-12-13 15:05:57,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 141279 states, 141279 states have (on average 1.4390673773172233) internal successors, (203310), 141278 states have internal predecessors, (203310), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:57,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141279 states to 141279 states and 203310 transitions. [2022-12-13 15:05:57,530 INFO L240 hiAutomatonCegarLoop]: Abstraction has 141279 states and 203310 transitions. [2022-12-13 15:05:57,531 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:05:57,531 INFO L428 stractBuchiCegarLoop]: Abstraction has 141279 states and 203310 transitions. [2022-12-13 15:05:57,531 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-12-13 15:05:57,531 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 141279 states and 203310 transitions. [2022-12-13 15:05:58,030 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 140720 [2022-12-13 15:05:58,030 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:05:58,030 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:05:58,032 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:58,032 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:05:58,032 INFO L748 eck$LassoCheckResult]: Stem: 487852#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 487853#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 488593#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 488594#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 488745#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 488746#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 487714#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 487715#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 489315#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 488716#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 488717#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 489043#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 489044#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 489166#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 489264#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 489265#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 489102#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 488920#L1121 assume !(0 == ~M_E~0); 488650#L1121-2 assume !(0 == ~T1_E~0); 487990#L1126-1 assume !(0 == ~T2_E~0); 487991#L1131-1 assume !(0 == ~T3_E~0); 488158#L1136-1 assume !(0 == ~T4_E~0); 488266#L1141-1 assume !(0 == ~T5_E~0); 488503#L1146-1 assume !(0 == ~T6_E~0); 488838#L1151-1 assume !(0 == ~T7_E~0); 488329#L1156-1 assume !(0 == ~T8_E~0); 487700#L1161-1 assume !(0 == ~T9_E~0); 487701#L1166-1 assume !(0 == ~T10_E~0); 487919#L1171-1 assume !(0 == ~T11_E~0); 487920#L1176-1 assume !(0 == ~E_M~0); 488859#L1181-1 assume !(0 == ~E_1~0); 488999#L1186-1 assume !(0 == ~E_2~0); 489062#L1191-1 assume !(0 == ~E_3~0); 487950#L1196-1 assume !(0 == ~E_4~0); 487951#L1201-1 assume !(0 == ~E_5~0); 489340#L1206-1 assume !(0 == ~E_6~0); 489103#L1211-1 assume !(0 == ~E_7~0); 489104#L1216-1 assume !(0 == ~E_8~0); 488090#L1221-1 assume !(0 == ~E_9~0); 488091#L1226-1 assume !(0 == ~E_10~0); 487800#L1231-1 assume !(0 == ~E_11~0); 487801#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 488860#L556 assume !(1 == ~m_pc~0); 488861#L556-2 is_master_triggered_~__retres1~0#1 := 0; 487674#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 487675#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 488472#L1391 assume !(0 != activate_threads_~tmp~1#1); 489033#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 489034#L575 assume !(1 == ~t1_pc~0); 487630#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 487631#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 487767#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 488104#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 488057#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 488058#L594 assume !(1 == ~t2_pc~0); 488822#L594-2 is_transmit2_triggered_~__retres1~2#1 := 0; 488935#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 487992#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 487689#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 487690#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 487756#L613 assume !(1 == ~t3_pc~0); 487869#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 487868#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 488216#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 488501#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 488502#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 488190#L632 assume !(1 == ~t4_pc~0); 488191#L632-2 is_transmit4_triggered_~__retres1~4#1 := 0; 488921#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 487706#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 487707#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 488864#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 488583#L651 assume !(1 == ~t5_pc~0); 488584#L651-2 is_transmit5_triggered_~__retres1~5#1 := 0; 487881#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 487882#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 488469#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 487895#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 487896#L670 assume !(1 == ~t6_pc~0); 489083#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 488248#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 487983#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 487984#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 488546#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 488547#L689 assume 1 == ~t7_pc~0; 489332#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 488668#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 488669#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 489101#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 488441#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 488442#L708 assume !(1 == ~t8_pc~0); 487988#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 487989#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 489214#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 489198#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 488043#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 488044#L727 assume 1 == ~t9_pc~0; 488169#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 487758#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 488032#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 488033#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 489316#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 488100#L746 assume !(1 == ~t10_pc~0); 488101#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 488807#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 488945#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 489150#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 489037#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 488275#L765 assume 1 == ~t11_pc~0; 488276#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 488492#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 489224#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 489081#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 489082#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 489193#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 488736#L1249-2 assume !(1 == ~T1_E~0); 488367#L1254-1 assume !(1 == ~T2_E~0); 487685#L1259-1 assume !(1 == ~T3_E~0); 487667#L1264-1 assume !(1 == ~T4_E~0); 487668#L1269-1 assume !(1 == ~T5_E~0); 489402#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 489275#L1279-1 assume !(1 == ~T7_E~0); 487870#L1284-1 assume !(1 == ~T8_E~0); 487871#L1289-1 assume !(1 == ~T9_E~0); 488420#L1294-1 assume !(1 == ~T10_E~0); 488421#L1299-1 assume !(1 == ~T11_E~0); 542383#L1304-1 assume !(1 == ~E_M~0); 542381#L1309-1 assume !(1 == ~E_1~0); 542380#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 542378#L1319-1 assume !(1 == ~E_3~0); 542376#L1324-1 assume !(1 == ~E_4~0); 542374#L1329-1 assume !(1 == ~E_5~0); 542372#L1334-1 assume !(1 == ~E_6~0); 489142#L1339-1 assume !(1 == ~E_7~0); 505191#L1344-1 assume !(1 == ~E_8~0); 499203#L1349-1 assume !(1 == ~E_9~0); 499201#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 499198#L1359-1 assume !(1 == ~E_11~0); 499196#L1364-1 assume { :end_inline_reset_delta_events } true; 499193#L1690-2 [2022-12-13 15:05:58,032 INFO L750 eck$LassoCheckResult]: Loop: 499193#L1690-2 assume !false; 499162#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 499158#L1096 assume !false; 499157#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 496197#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 496193#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 496191#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 496188#L937 assume !(0 != eval_~tmp~0#1); 496189#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 551056#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 551053#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 551051#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 551049#L1126-3 assume !(0 == ~T2_E~0); 551047#L1131-3 assume !(0 == ~T3_E~0); 551045#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 551043#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 551040#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 551038#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 551036#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 551034#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 551032#L1166-3 assume !(0 == ~T10_E~0); 551030#L1171-3 assume !(0 == ~T11_E~0); 551027#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 551025#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 551023#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 551021#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 551019#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 551017#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 551014#L1206-3 assume !(0 == ~E_6~0); 551012#L1211-3 assume !(0 == ~E_7~0); 551010#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 551008#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 551006#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 551005#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 545443#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 545440#L556-39 assume !(1 == ~m_pc~0); 545438#L556-41 is_master_triggered_~__retres1~0#1 := 0; 545436#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 545434#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 545432#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 545430#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 545428#L575-39 assume !(1 == ~t1_pc~0); 505616#L575-41 is_transmit1_triggered_~__retres1~1#1 := 0; 505613#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 505611#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 505609#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 505607#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 505605#L594-39 assume !(1 == ~t2_pc~0); 505603#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 505601#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 505599#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 505597#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 505595#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 505593#L613-39 assume !(1 == ~t3_pc~0); 505591#L613-41 is_transmit3_triggered_~__retres1~3#1 := 0; 505588#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 505585#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 505583#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 505581#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 505579#L632-39 assume !(1 == ~t4_pc~0); 505577#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 505575#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 505572#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 505570#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 505568#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 505566#L651-39 assume !(1 == ~t5_pc~0); 505564#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 505562#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 505559#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 505557#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 505555#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 505553#L670-39 assume 1 == ~t6_pc~0; 505551#L671-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 505548#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 505545#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 505543#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 505541#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 505539#L689-39 assume !(1 == ~t7_pc~0); 505537#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 505534#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 505531#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 505529#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 505527#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 505525#L708-39 assume 1 == ~t8_pc~0; 505523#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 505520#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 505517#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 505515#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 505513#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 505511#L727-39 assume !(1 == ~t9_pc~0); 505509#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 505506#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 505504#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 505503#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 505502#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 505501#L746-39 assume !(1 == ~t10_pc~0); 505500#L746-41 is_transmit10_triggered_~__retres1~10#1 := 0; 505498#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 505497#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 505495#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 505493#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 505491#L765-39 assume 1 == ~t11_pc~0; 505489#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 505486#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 505484#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 505482#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 505479#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 505477#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 505473#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 505471#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 505467#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 505465#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 505463#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 505461#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 505459#L1279-3 assume !(1 == ~T7_E~0); 505457#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 505455#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 505453#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 505448#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 505446#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 505444#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 505442#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 505440#L1319-3 assume !(1 == ~E_3~0); 505438#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 505436#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 505434#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 505430#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 505428#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 505426#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 505424#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 505422#L1359-3 assume !(1 == ~E_11~0); 505420#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 505397#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 505393#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 505391#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 505200#L1709 assume !(0 == start_simulation_~tmp~3#1); 505199#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 499230#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 499219#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 499217#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 499215#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 499213#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 499211#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 499195#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 499193#L1690-2 [2022-12-13 15:05:58,033 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:58,033 INFO L85 PathProgramCache]: Analyzing trace with hash 1793793208, now seen corresponding path program 1 times [2022-12-13 15:05:58,033 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:58,033 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2078256356] [2022-12-13 15:05:58,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:58,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:58,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:58,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:58,089 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:58,089 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2078256356] [2022-12-13 15:05:58,089 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2078256356] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:58,089 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:58,090 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 15:05:58,090 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [67897876] [2022-12-13 15:05:58,090 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:58,090 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:05:58,090 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:05:58,090 INFO L85 PathProgramCache]: Analyzing trace with hash 623448063, now seen corresponding path program 1 times [2022-12-13 15:05:58,091 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:05:58,091 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1728964965] [2022-12-13 15:05:58,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:05:58,091 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:05:58,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:05:58,128 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:05:58,128 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:05:58,128 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1728964965] [2022-12-13 15:05:58,128 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1728964965] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:05:58,128 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:05:58,128 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:05:58,128 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [69926509] [2022-12-13 15:05:58,128 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:05:58,129 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:05:58,129 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:05:58,129 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 15:05:58,129 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 15:05:58,129 INFO L87 Difference]: Start difference. First operand 141279 states and 203310 transitions. cyclomatic complexity: 62095 Second operand has 5 states, 5 states have (on average 27.8) internal successors, (139), 5 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:05:59,134 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:05:59,134 INFO L93 Difference]: Finished difference Result 355284 states and 513243 transitions. [2022-12-13 15:05:59,134 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 355284 states and 513243 transitions. [2022-12-13 15:06:00,471 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 353776 [2022-12-13 15:06:01,195 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 355284 states to 355284 states and 513243 transitions. [2022-12-13 15:06:01,195 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 355284 [2022-12-13 15:06:01,292 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 355284 [2022-12-13 15:06:01,292 INFO L73 IsDeterministic]: Start isDeterministic. Operand 355284 states and 513243 transitions. [2022-12-13 15:06:01,381 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:06:01,381 INFO L218 hiAutomatonCegarLoop]: Abstraction has 355284 states and 513243 transitions. [2022-12-13 15:06:01,513 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 355284 states and 513243 transitions. [2022-12-13 15:06:02,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 355284 to 145458. [2022-12-13 15:06:02,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 145458 states, 145458 states have (on average 1.4264529967413273) internal successors, (207489), 145457 states have internal predecessors, (207489), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:06:03,226 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 145458 states to 145458 states and 207489 transitions. [2022-12-13 15:06:03,226 INFO L240 hiAutomatonCegarLoop]: Abstraction has 145458 states and 207489 transitions. [2022-12-13 15:06:03,227 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 15:06:03,227 INFO L428 stractBuchiCegarLoop]: Abstraction has 145458 states and 207489 transitions. [2022-12-13 15:06:03,227 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-12-13 15:06:03,227 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 145458 states and 207489 transitions. [2022-12-13 15:06:03,650 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 144896 [2022-12-13 15:06:03,650 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:06:03,650 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:06:03,651 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:06:03,651 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:06:03,652 INFO L748 eck$LassoCheckResult]: Stem: 984427#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 984428#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 985173#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 985174#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 985330#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 985331#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 984290#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 984291#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 985883#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 985297#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 985298#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 985603#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 985604#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 985729#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 985828#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 985829#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 985666#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 985483#L1121 assume !(0 == ~M_E~0); 985231#L1121-2 assume !(0 == ~T1_E~0); 984566#L1126-1 assume !(0 == ~T2_E~0); 984567#L1131-1 assume !(0 == ~T3_E~0); 984734#L1136-1 assume !(0 == ~T4_E~0); 984843#L1141-1 assume !(0 == ~T5_E~0); 985081#L1146-1 assume !(0 == ~T6_E~0); 985409#L1151-1 assume !(0 == ~T7_E~0); 984911#L1156-1 assume !(0 == ~T8_E~0); 984276#L1161-1 assume !(0 == ~T9_E~0); 984277#L1166-1 assume !(0 == ~T10_E~0); 984496#L1171-1 assume !(0 == ~T11_E~0); 984497#L1176-1 assume !(0 == ~E_M~0); 985422#L1181-1 assume !(0 == ~E_1~0); 985558#L1186-1 assume !(0 == ~E_2~0); 985622#L1191-1 assume !(0 == ~E_3~0); 984527#L1196-1 assume !(0 == ~E_4~0); 984528#L1201-1 assume !(0 == ~E_5~0); 985908#L1206-1 assume !(0 == ~E_6~0); 985667#L1211-1 assume !(0 == ~E_7~0); 985668#L1216-1 assume !(0 == ~E_8~0); 984666#L1221-1 assume !(0 == ~E_9~0); 984667#L1226-1 assume !(0 == ~E_10~0); 984376#L1231-1 assume !(0 == ~E_11~0); 984377#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 985423#L556 assume !(1 == ~m_pc~0); 985424#L556-2 is_master_triggered_~__retres1~0#1 := 0; 984250#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 984251#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 985052#L1391 assume !(0 != activate_threads_~tmp~1#1); 985591#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 985592#L575 assume !(1 == ~t1_pc~0); 984206#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 984207#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 984343#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 984680#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 984635#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 984636#L594 assume !(1 == ~t2_pc~0); 985394#L594-2 is_transmit2_triggered_~__retres1~2#1 := 0; 985494#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 984568#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 984265#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 984266#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 984332#L613 assume !(1 == ~t3_pc~0); 984444#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 984443#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 984793#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 985079#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 985080#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 984766#L632 assume !(1 == ~t4_pc~0); 984767#L632-2 is_transmit4_triggered_~__retres1~4#1 := 0; 985484#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 984282#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 984283#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 985427#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 985163#L651 assume !(1 == ~t5_pc~0); 985164#L651-2 is_transmit5_triggered_~__retres1~5#1 := 0; 984456#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 984457#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 985049#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 984471#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 984472#L670 assume !(1 == ~t6_pc~0); 985644#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 984824#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 984825#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 985884#L1439 assume !(0 != activate_threads_~tmp___5~0#1); 985125#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 985126#L689 assume 1 == ~t7_pc~0; 985897#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 985250#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 985251#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 985665#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 985022#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 985023#L708 assume !(1 == ~t8_pc~0); 984564#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 984565#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 985773#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 985759#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 984621#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 984622#L727 assume 1 == ~t9_pc~0; 984744#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 984334#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 984610#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 984611#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 985885#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 984676#L746 assume !(1 == ~t10_pc~0); 984677#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 985379#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 985504#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 985713#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 985597#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 984852#L765 assume 1 == ~t11_pc~0; 984853#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 985070#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 985785#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 985642#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 985643#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 985754#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 985317#L1249-2 assume !(1 == ~T1_E~0); 984949#L1254-1 assume !(1 == ~T2_E~0); 984261#L1259-1 assume !(1 == ~T3_E~0); 984243#L1264-1 assume !(1 == ~T4_E~0); 984244#L1269-1 assume !(1 == ~T5_E~0); 985978#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 985842#L1279-1 assume !(1 == ~T7_E~0); 984445#L1284-1 assume !(1 == ~T8_E~0); 984446#L1289-1 assume !(1 == ~T9_E~0); 985001#L1294-1 assume !(1 == ~T10_E~0); 985002#L1299-1 assume !(1 == ~T11_E~0); 985011#L1304-1 assume !(1 == ~E_M~0); 985956#L1309-1 assume !(1 == ~E_1~0); 985959#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 984397#L1319-1 assume !(1 == ~E_3~0); 984398#L1324-1 assume !(1 == ~E_4~0); 984520#L1329-1 assume !(1 == ~E_5~0); 984521#L1334-1 assume !(1 == ~E_6~0); 985708#L1339-1 assume !(1 == ~E_7~0); 1031403#L1344-1 assume !(1 == ~E_8~0); 1031401#L1349-1 assume !(1 == ~E_9~0); 1031399#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1031398#L1359-1 assume !(1 == ~E_11~0); 1031394#L1364-1 assume { :end_inline_reset_delta_events } true; 1031391#L1690-2 [2022-12-13 15:06:03,652 INFO L750 eck$LassoCheckResult]: Loop: 1031391#L1690-2 assume !false; 1031387#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1031384#L1096 assume !false; 1031382#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1030531#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1030527#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1030466#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1030449#L937 assume !(0 != eval_~tmp~0#1); 1030450#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1055772#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1055770#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1055768#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1055766#L1126-3 assume !(0 == ~T2_E~0); 1055764#L1131-3 assume !(0 == ~T3_E~0); 1055762#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1055760#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1055758#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1055756#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1055754#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1055752#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1055750#L1166-3 assume !(0 == ~T10_E~0); 1055748#L1171-3 assume !(0 == ~T11_E~0); 1055746#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1055744#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1055742#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1055740#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1055738#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1055736#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1055734#L1206-3 assume !(0 == ~E_6~0); 1055732#L1211-3 assume !(0 == ~E_7~0); 1055730#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1055728#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1055726#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1055724#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1055722#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1055720#L556-39 assume !(1 == ~m_pc~0); 1055718#L556-41 is_master_triggered_~__retres1~0#1 := 0; 1055716#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1055714#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1055712#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 1055710#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1055708#L575-39 assume 1 == ~t1_pc~0; 1055705#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1055702#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1055700#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1055698#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1055696#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1033665#L594-39 assume !(1 == ~t2_pc~0); 1033664#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 1033663#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1033662#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1033661#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1033660#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1033659#L613-39 assume !(1 == ~t3_pc~0); 1033658#L613-41 is_transmit3_triggered_~__retres1~3#1 := 0; 1033656#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1033655#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1033654#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1033653#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1033652#L632-39 assume !(1 == ~t4_pc~0); 1033651#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 1033650#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1033649#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1033648#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1033647#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1033646#L651-39 assume !(1 == ~t5_pc~0); 1033645#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 1033644#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1033643#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1033641#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1033640#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1033637#L670-39 assume 1 == ~t6_pc~0; 1033638#L671-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1033639#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1033642#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1033627#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1033625#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1033623#L689-39 assume !(1 == ~t7_pc~0); 1033621#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 1033618#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1033615#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1033613#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1033611#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1033609#L708-39 assume 1 == ~t8_pc~0; 1033607#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1033604#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1033601#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1033599#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1033597#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1033595#L727-39 assume !(1 == ~t9_pc~0); 1033593#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 1033590#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1033587#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1033585#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 1033583#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1033581#L746-39 assume !(1 == ~t10_pc~0); 1033579#L746-41 is_transmit10_triggered_~__retres1~10#1 := 0; 1033576#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1033573#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1033571#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1033569#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1033567#L765-39 assume 1 == ~t11_pc~0; 1033565#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1033563#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1033562#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1033560#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1033559#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1033557#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 994437#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1033552#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1022071#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1033549#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1033547#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1033546#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1033510#L1279-3 assume !(1 == ~T7_E~0); 1033508#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1033506#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1033503#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1033499#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1033497#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1033495#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1033493#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1033491#L1319-3 assume !(1 == ~E_3~0); 1033488#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1033486#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1033484#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 994391#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1033481#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1033479#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1033476#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1033474#L1359-3 assume !(1 == ~E_11~0); 1033472#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1033447#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1033443#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1033439#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 1031501#L1709 assume !(0 == start_simulation_~tmp~3#1); 1031499#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1031430#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1031419#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1031416#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 1031414#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1031412#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1031410#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1031393#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 1031391#L1690-2 [2022-12-13 15:06:03,652 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:06:03,652 INFO L85 PathProgramCache]: Analyzing trace with hash -1240256838, now seen corresponding path program 1 times [2022-12-13 15:06:03,653 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:06:03,653 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2108363912] [2022-12-13 15:06:03,653 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:06:03,653 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:06:03,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:06:03,705 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:06:03,706 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:06:03,706 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2108363912] [2022-12-13 15:06:03,706 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2108363912] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:06:03,706 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:06:03,706 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:06:03,706 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [523210913] [2022-12-13 15:06:03,706 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:06:03,706 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:06:03,707 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:06:03,707 INFO L85 PathProgramCache]: Analyzing trace with hash -1691932290, now seen corresponding path program 1 times [2022-12-13 15:06:03,707 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:06:03,707 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1939734648] [2022-12-13 15:06:03,707 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:06:03,707 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:06:03,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:06:03,743 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:06:03,743 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:06:03,744 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1939734648] [2022-12-13 15:06:03,744 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1939734648] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:06:03,744 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:06:03,744 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:06:03,744 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2006555480] [2022-12-13 15:06:03,744 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:06:03,744 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:06:03,744 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:06:03,745 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 15:06:03,745 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 15:06:03,745 INFO L87 Difference]: Start difference. First operand 145458 states and 207489 transitions. cyclomatic complexity: 62095 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:06:05,059 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:06:05,059 INFO L93 Difference]: Finished difference Result 350925 states and 497370 transitions. [2022-12-13 15:06:05,060 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 350925 states and 497370 transitions. [2022-12-13 15:06:06,134 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 344060 [2022-12-13 15:06:06,793 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 350925 states to 350925 states and 497370 transitions. [2022-12-13 15:06:06,793 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 350925 [2022-12-13 15:06:06,887 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 350925 [2022-12-13 15:06:06,887 INFO L73 IsDeterministic]: Start isDeterministic. Operand 350925 states and 497370 transitions. [2022-12-13 15:06:06,988 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:06:06,988 INFO L218 hiAutomatonCegarLoop]: Abstraction has 350925 states and 497370 transitions. [2022-12-13 15:06:07,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 350925 states and 497370 transitions. [2022-12-13 15:06:09,170 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 350925 to 277889. [2022-12-13 15:06:09,338 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 277889 states, 277889 states have (on average 1.4215676043312258) internal successors, (395038), 277888 states have internal predecessors, (395038), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:06:10,031 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 277889 states to 277889 states and 395038 transitions. [2022-12-13 15:06:10,031 INFO L240 hiAutomatonCegarLoop]: Abstraction has 277889 states and 395038 transitions. [2022-12-13 15:06:10,032 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 15:06:10,032 INFO L428 stractBuchiCegarLoop]: Abstraction has 277889 states and 395038 transitions. [2022-12-13 15:06:10,032 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-12-13 15:06:10,032 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 277889 states and 395038 transitions. [2022-12-13 15:06:10,810 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 277008 [2022-12-13 15:06:10,811 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:06:10,811 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:06:10,812 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:06:10,812 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:06:10,812 INFO L748 eck$LassoCheckResult]: Stem: 1480822#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 1480823#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1481578#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1481579#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1481752#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 1481753#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1480684#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1480685#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1482411#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1481719#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1481720#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1482075#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1482076#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1482224#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1482348#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1482349#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1482158#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1481932#L1121 assume !(0 == ~M_E~0); 1481646#L1121-2 assume !(0 == ~T1_E~0); 1480964#L1126-1 assume !(0 == ~T2_E~0); 1480965#L1131-1 assume !(0 == ~T3_E~0); 1481134#L1136-1 assume !(0 == ~T4_E~0); 1481247#L1141-1 assume !(0 == ~T5_E~0); 1481486#L1146-1 assume !(0 == ~T6_E~0); 1481851#L1151-1 assume !(0 == ~T7_E~0); 1481316#L1156-1 assume !(0 == ~T8_E~0); 1480671#L1161-1 assume !(0 == ~T9_E~0); 1480672#L1166-1 assume !(0 == ~T10_E~0); 1480892#L1171-1 assume !(0 == ~T11_E~0); 1480893#L1176-1 assume !(0 == ~E_M~0); 1481869#L1181-1 assume !(0 == ~E_1~0); 1482024#L1186-1 assume !(0 == ~E_2~0); 1482093#L1191-1 assume !(0 == ~E_3~0); 1480924#L1196-1 assume !(0 == ~E_4~0); 1480925#L1201-1 assume !(0 == ~E_5~0); 1482444#L1206-1 assume !(0 == ~E_6~0); 1482159#L1211-1 assume !(0 == ~E_7~0); 1482160#L1216-1 assume !(0 == ~E_8~0); 1481062#L1221-1 assume !(0 == ~E_9~0); 1481063#L1226-1 assume !(0 == ~E_10~0); 1480771#L1231-1 assume !(0 == ~E_11~0); 1480772#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1481870#L556 assume !(1 == ~m_pc~0); 1481871#L556-2 is_master_triggered_~__retres1~0#1 := 0; 1480644#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1480645#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1481457#L1391 assume !(0 != activate_threads_~tmp~1#1); 1482064#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1482065#L575 assume !(1 == ~t1_pc~0); 1480599#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1480600#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1480737#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1481077#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 1481031#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1481032#L594 assume !(1 == ~t2_pc~0); 1481833#L594-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1481945#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1480966#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1480660#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 1480661#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1480726#L613 assume !(1 == ~t3_pc~0); 1480839#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1480838#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1481197#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1481484#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 1481485#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1481170#L632 assume !(1 == ~t4_pc~0); 1481171#L632-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1481933#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1480676#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1480677#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 1481875#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1481567#L651 assume !(1 == ~t5_pc~0); 1481568#L651-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1480851#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1480852#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1481454#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 1480867#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1480868#L670 assume !(1 == ~t6_pc~0); 1482128#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1481228#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1481229#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1482412#L1439 assume !(0 != activate_threads_~tmp___5~0#1); 1481528#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1481529#L689 assume !(1 == ~t7_pc~0); 1481797#L689-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1481666#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1481667#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1482157#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 1481427#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1481428#L708 assume !(1 == ~t8_pc~0); 1480962#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1480963#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1482277#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1482259#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 1481016#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1481017#L727 assume 1 == ~t9_pc~0; 1481148#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1480728#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1481005#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1481006#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 1482413#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1481072#L746 assume !(1 == ~t10_pc~0); 1481073#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1481816#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1481957#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1482206#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 1482069#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1481256#L765 assume 1 == ~t11_pc~0; 1481257#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1481474#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1482295#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1482126#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 1482127#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1482253#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 1482254#L1249-2 assume !(1 == ~T1_E~0); 1481352#L1254-1 assume !(1 == ~T2_E~0); 1481353#L1259-1 assume !(1 == ~T3_E~0); 1480637#L1264-1 assume !(1 == ~T4_E~0); 1480638#L1269-1 assume !(1 == ~T5_E~0); 1482562#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1482563#L1279-1 assume !(1 == ~T7_E~0); 1480840#L1284-1 assume !(1 == ~T8_E~0); 1480841#L1289-1 assume !(1 == ~T9_E~0); 1481406#L1294-1 assume !(1 == ~T10_E~0); 1481407#L1299-1 assume !(1 == ~T11_E~0); 1481416#L1304-1 assume !(1 == ~E_M~0); 1482534#L1309-1 assume !(1 == ~E_1~0); 1482535#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1480792#L1319-1 assume !(1 == ~E_3~0); 1480793#L1324-1 assume !(1 == ~E_4~0); 1480917#L1329-1 assume !(1 == ~E_5~0); 1480918#L1334-1 assume !(1 == ~E_6~0); 1482200#L1339-1 assume !(1 == ~E_7~0); 1482481#L1344-1 assume !(1 == ~E_8~0); 1482571#L1349-1 assume !(1 == ~E_9~0); 1482572#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1481992#L1359-1 assume !(1 == ~E_11~0); 1481993#L1364-1 assume { :end_inline_reset_delta_events } true; 1537964#L1690-2 [2022-12-13 15:06:10,812 INFO L750 eck$LassoCheckResult]: Loop: 1537964#L1690-2 assume !false; 1537953#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1537948#L1096 assume !false; 1537946#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1537692#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1537688#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1537686#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1537683#L937 assume !(0 != eval_~tmp~0#1); 1537684#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1541659#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1541656#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1541654#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1541652#L1126-3 assume !(0 == ~T2_E~0); 1541650#L1131-3 assume !(0 == ~T3_E~0); 1541648#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1541627#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1541619#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1541612#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1541604#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1541597#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1541590#L1166-3 assume !(0 == ~T10_E~0); 1541583#L1171-3 assume !(0 == ~T11_E~0); 1541574#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1541564#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1541555#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1541546#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1541538#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1541528#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1541520#L1206-3 assume !(0 == ~E_6~0); 1541510#L1211-3 assume !(0 == ~E_7~0); 1541507#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1541505#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1541503#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1541501#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1541499#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1541497#L556-39 assume !(1 == ~m_pc~0); 1541487#L556-41 is_master_triggered_~__retres1~0#1 := 0; 1541478#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1541469#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1541459#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 1541450#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1541441#L575-39 assume !(1 == ~t1_pc~0); 1541433#L575-41 is_transmit1_triggered_~__retres1~1#1 := 0; 1541423#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1541416#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1541415#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1541244#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1539337#L594-39 assume !(1 == ~t2_pc~0); 1539336#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 1539335#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1539334#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1539333#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1539331#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1539329#L613-39 assume !(1 == ~t3_pc~0); 1539327#L613-41 is_transmit3_triggered_~__retres1~3#1 := 0; 1539324#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1539322#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1539320#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1539318#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1539315#L632-39 assume !(1 == ~t4_pc~0); 1539313#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 1539311#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1539309#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1539308#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1539307#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1539306#L651-39 assume !(1 == ~t5_pc~0); 1539305#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 1539304#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1539303#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1539302#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1539301#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1539300#L670-39 assume !(1 == ~t6_pc~0); 1539298#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 1540307#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1540299#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1539293#L1439-39 assume !(0 != activate_threads_~tmp___5~0#1); 1539290#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1539288#L689-39 assume !(1 == ~t7_pc~0); 1489734#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 1539285#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1539283#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1539281#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1539279#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1539277#L708-39 assume 1 == ~t8_pc~0; 1539275#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1539272#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1539270#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1539268#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1539266#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1539262#L727-39 assume !(1 == ~t9_pc~0); 1539259#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 1539256#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1539253#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1539251#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 1539249#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1539248#L746-39 assume !(1 == ~t10_pc~0); 1539246#L746-41 is_transmit10_triggered_~__retres1~10#1 := 0; 1539243#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1539241#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1539239#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1539237#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1538421#L765-39 assume 1 == ~t11_pc~0; 1538418#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1538415#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1538413#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1538411#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1538409#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1538407#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1514393#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1538404#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1514389#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1538401#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1538399#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1538397#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1538395#L1279-3 assume !(1 == ~T7_E~0); 1538368#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1538362#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1538356#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1517073#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1538346#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1538340#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1538333#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1538326#L1319-3 assume !(1 == ~E_3~0); 1538320#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1538312#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1538212#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1538208#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1538206#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1538204#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1538202#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1538198#L1359-3 assume !(1 == ~E_11~0); 1538196#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1538112#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1538102#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1538094#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 1538087#L1709 assume !(0 == start_simulation_~tmp~3#1); 1538081#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1538046#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1538035#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1538034#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 1538030#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1537984#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1537975#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1537974#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 1537964#L1690-2 [2022-12-13 15:06:10,813 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:06:10,813 INFO L85 PathProgramCache]: Analyzing trace with hash 1946581819, now seen corresponding path program 1 times [2022-12-13 15:06:10,813 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:06:10,813 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [508344604] [2022-12-13 15:06:10,813 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:06:10,813 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:06:10,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:06:10,873 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:06:10,873 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:06:10,873 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [508344604] [2022-12-13 15:06:10,873 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [508344604] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:06:10,873 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:06:10,873 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:06:10,874 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [168225965] [2022-12-13 15:06:10,874 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:06:10,874 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:06:10,874 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:06:10,874 INFO L85 PathProgramCache]: Analyzing trace with hash -2032157374, now seen corresponding path program 1 times [2022-12-13 15:06:10,874 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:06:10,875 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1564187301] [2022-12-13 15:06:10,875 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:06:10,875 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:06:10,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:06:10,902 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:06:10,902 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:06:10,902 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1564187301] [2022-12-13 15:06:10,902 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1564187301] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:06:10,902 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:06:10,902 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:06:10,902 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [919608373] [2022-12-13 15:06:10,902 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:06:10,902 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:06:10,903 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:06:10,903 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 15:06:10,903 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 15:06:10,903 INFO L87 Difference]: Start difference. First operand 277889 states and 395038 transitions. cyclomatic complexity: 117213 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:06:12,959 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:06:12,959 INFO L93 Difference]: Finished difference Result 666448 states and 941531 transitions. [2022-12-13 15:06:12,959 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 666448 states and 941531 transitions. [2022-12-13 15:06:15,365 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 653024 [2022-12-13 15:06:16,691 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 666448 states to 666448 states and 941531 transitions. [2022-12-13 15:06:16,692 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 666448 [2022-12-13 15:06:16,879 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 666448 [2022-12-13 15:06:16,879 INFO L73 IsDeterministic]: Start isDeterministic. Operand 666448 states and 941531 transitions. [2022-12-13 15:06:17,070 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:06:17,070 INFO L218 hiAutomatonCegarLoop]: Abstraction has 666448 states and 941531 transitions. [2022-12-13 15:06:17,332 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 666448 states and 941531 transitions. [2022-12-13 15:06:21,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 666448 to 530224. [2022-12-13 15:06:21,450 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 530224 states, 530224 states have (on average 1.417082214309424) internal successors, (751371), 530223 states have internal predecessors, (751371), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:06:22,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 530224 states to 530224 states and 751371 transitions. [2022-12-13 15:06:22,632 INFO L240 hiAutomatonCegarLoop]: Abstraction has 530224 states and 751371 transitions. [2022-12-13 15:06:22,633 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 15:06:22,633 INFO L428 stractBuchiCegarLoop]: Abstraction has 530224 states and 751371 transitions. [2022-12-13 15:06:22,633 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-12-13 15:06:22,633 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 530224 states and 751371 transitions. [2022-12-13 15:06:24,132 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 528704 [2022-12-13 15:06:24,132 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:06:24,133 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:06:24,135 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:06:24,135 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:06:24,135 INFO L748 eck$LassoCheckResult]: Stem: 2425171#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 2425172#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 2425910#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2425911#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2426072#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 2426073#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2425037#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2425038#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2426677#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2426042#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2426043#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2426377#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2426378#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2426515#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2426623#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 2426624#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 2426449#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2426241#L1121 assume !(0 == ~M_E~0); 2425978#L1121-2 assume !(0 == ~T1_E~0); 2425310#L1126-1 assume !(0 == ~T2_E~0); 2425311#L1131-1 assume !(0 == ~T3_E~0); 2425478#L1136-1 assume !(0 == ~T4_E~0); 2425586#L1141-1 assume !(0 == ~T5_E~0); 2425826#L1146-1 assume !(0 == ~T6_E~0); 2426160#L1151-1 assume !(0 == ~T7_E~0); 2425651#L1156-1 assume !(0 == ~T8_E~0); 2425019#L1161-1 assume !(0 == ~T9_E~0); 2425020#L1166-1 assume !(0 == ~T10_E~0); 2425240#L1171-1 assume !(0 == ~T11_E~0); 2425241#L1176-1 assume !(0 == ~E_M~0); 2426180#L1181-1 assume !(0 == ~E_1~0); 2426334#L1186-1 assume !(0 == ~E_2~0); 2426399#L1191-1 assume !(0 == ~E_3~0); 2425271#L1196-1 assume !(0 == ~E_4~0); 2425272#L1201-1 assume !(0 == ~E_5~0); 2426696#L1206-1 assume !(0 == ~E_6~0); 2426450#L1211-1 assume !(0 == ~E_7~0); 2426451#L1216-1 assume !(0 == ~E_8~0); 2425411#L1221-1 assume !(0 == ~E_9~0); 2425412#L1226-1 assume !(0 == ~E_10~0); 2425120#L1231-1 assume !(0 == ~E_11~0); 2425121#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2426182#L556 assume !(1 == ~m_pc~0); 2426183#L556-2 is_master_triggered_~__retres1~0#1 := 0; 2424991#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2424992#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2425793#L1391 assume !(0 != activate_threads_~tmp~1#1); 2426368#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2426369#L575 assume !(1 == ~t1_pc~0); 2424946#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2424947#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2425086#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2425425#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 2425377#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2425378#L594 assume !(1 == ~t2_pc~0); 2426145#L594-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2426255#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2425312#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2425010#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 2425011#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2425075#L613 assume !(1 == ~t3_pc~0); 2425188#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2425187#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2425538#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2425819#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 2425820#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2425512#L632 assume !(1 == ~t4_pc~0); 2425513#L632-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2426242#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2425029#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2425030#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 2426185#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2425897#L651 assume !(1 == ~t5_pc~0); 2425898#L651-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2425200#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2425201#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2425790#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 2425215#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2425216#L670 assume !(1 == ~t6_pc~0); 2426428#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2425573#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2425574#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2426678#L1439 assume !(0 != activate_threads_~tmp___5~0#1); 2425864#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2425865#L689 assume !(1 == ~t7_pc~0); 2426110#L689-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2425996#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2425997#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2426448#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 2425762#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2425763#L708 assume !(1 == ~t8_pc~0); 2425308#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2425309#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2426566#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2426550#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 2425362#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2425363#L727 assume !(1 == ~t9_pc~0); 2425076#L727-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2425077#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2425351#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2425352#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 2426680#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2425420#L746 assume !(1 == ~t10_pc~0); 2425421#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 2426125#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2426265#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 2426497#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 2426371#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2425598#L765 assume 1 == ~t11_pc~0; 2425599#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 2425811#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2426580#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 2426425#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 2426426#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2426544#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 2426545#L1249-2 assume !(1 == ~T1_E~0); 2425687#L1254-1 assume !(1 == ~T2_E~0); 2425688#L1259-1 assume !(1 == ~T3_E~0); 2424984#L1264-1 assume !(1 == ~T4_E~0); 2424985#L1269-1 assume !(1 == ~T5_E~0); 2426784#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2426785#L1279-1 assume !(1 == ~T7_E~0); 2425189#L1284-1 assume !(1 == ~T8_E~0); 2425190#L1289-1 assume !(1 == ~T9_E~0); 2425741#L1294-1 assume !(1 == ~T10_E~0); 2425742#L1299-1 assume !(1 == ~T11_E~0); 2425751#L1304-1 assume !(1 == ~E_M~0); 2426758#L1309-1 assume !(1 == ~E_1~0); 2426761#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 2425140#L1319-1 assume !(1 == ~E_3~0); 2425141#L1324-1 assume !(1 == ~E_4~0); 2425264#L1329-1 assume !(1 == ~E_5~0); 2425265#L1334-1 assume !(1 == ~E_6~0); 2426492#L1339-1 assume !(1 == ~E_7~0); 2426590#L1344-1 assume !(1 == ~E_8~0); 2426591#L1349-1 assume !(1 == ~E_9~0); 2425881#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 2425882#L1359-1 assume !(1 == ~E_11~0); 2426300#L1364-1 assume { :end_inline_reset_delta_events } true; 2426716#L1690-2 [2022-12-13 15:06:24,136 INFO L750 eck$LassoCheckResult]: Loop: 2426716#L1690-2 assume !false; 2659789#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2659781#L1096 assume !false; 2659775#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2659625#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 2659621#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2659619#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2659616#L937 assume !(0 != eval_~tmp~0#1); 2659617#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2675172#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2675167#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2675162#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2675154#L1126-3 assume !(0 == ~T2_E~0); 2675147#L1131-3 assume !(0 == ~T3_E~0); 2675139#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2675130#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2675121#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2675112#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2675103#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2675095#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2675086#L1166-3 assume !(0 == ~T10_E~0); 2675063#L1171-3 assume !(0 == ~T11_E~0); 2675057#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2675051#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2675045#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2675039#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2675033#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2675025#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2675019#L1206-3 assume !(0 == ~E_6~0); 2675013#L1211-3 assume !(0 == ~E_7~0); 2675007#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2674872#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2674866#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 2674860#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 2674854#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2674845#L556-39 assume !(1 == ~m_pc~0); 2674834#L556-41 is_master_triggered_~__retres1~0#1 := 0; 2674814#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2674800#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2674788#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 2674779#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2674757#L575-39 assume 1 == ~t1_pc~0; 2674749#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2674739#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2674708#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2674696#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2674686#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2674678#L594-39 assume !(1 == ~t2_pc~0); 2662798#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 2674651#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2674629#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2674623#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2674617#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2674608#L613-39 assume 1 == ~t3_pc~0; 2674598#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2674576#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2674359#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2674357#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2674355#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2674353#L632-39 assume !(1 == ~t4_pc~0); 2674351#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 2674349#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2674346#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2674344#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2674342#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2674340#L651-39 assume !(1 == ~t5_pc~0); 2674338#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 2674336#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2674333#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2674331#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2674329#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2674318#L670-39 assume !(1 == ~t6_pc~0); 2674315#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 2674313#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2674311#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2674309#L1439-39 assume !(0 != activate_threads_~tmp___5~0#1); 2674306#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2660639#L689-39 assume !(1 == ~t7_pc~0); 2660637#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 2660635#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2660527#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2660505#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2660471#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2660447#L708-39 assume !(1 == ~t8_pc~0); 2660427#L708-41 is_transmit8_triggered_~__retres1~8#1 := 0; 2660424#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2660422#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2660420#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2660418#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2660416#L727-39 assume !(1 == ~t9_pc~0); 2503323#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 2660331#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2660329#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2660328#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 2660327#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2660319#L746-39 assume 1 == ~t10_pc~0; 2660307#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 2660302#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2660300#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 2660299#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2660298#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2660297#L765-39 assume 1 == ~t11_pc~0; 2660296#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 2660294#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2660292#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 2660290#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2660289#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2660288#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2602908#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2660286#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2614566#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2660285#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2660284#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2660282#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2660280#L1279-3 assume !(1 == ~T7_E~0); 2660278#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2660276#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2660274#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2653186#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 2660271#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2660268#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2660266#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2660264#L1319-3 assume !(1 == ~E_3~0); 2660262#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2660260#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2660258#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2659203#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2660255#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2660253#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2660251#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2660249#L1359-3 assume !(1 == ~E_11~0); 2660247#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2660076#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 2660064#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2660056#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 2660048#L1709 assume !(0 == start_simulation_~tmp~3#1); 2660043#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2659975#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 2659964#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2659962#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 2659956#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2659810#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2659806#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 2659804#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 2426716#L1690-2 [2022-12-13 15:06:24,136 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:06:24,136 INFO L85 PathProgramCache]: Analyzing trace with hash -449855172, now seen corresponding path program 1 times [2022-12-13 15:06:24,136 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:06:24,136 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [968708214] [2022-12-13 15:06:24,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:06:24,137 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:06:24,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:06:24,192 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:06:24,192 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:06:24,192 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [968708214] [2022-12-13 15:06:24,192 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [968708214] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:06:24,193 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:06:24,193 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:06:24,193 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1876767786] [2022-12-13 15:06:24,193 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:06:24,193 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:06:24,194 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:06:24,194 INFO L85 PathProgramCache]: Analyzing trace with hash 668605760, now seen corresponding path program 1 times [2022-12-13 15:06:24,194 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:06:24,194 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1600907955] [2022-12-13 15:06:24,194 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:06:24,194 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:06:24,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:06:24,228 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:06:24,229 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:06:24,229 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1600907955] [2022-12-13 15:06:24,229 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1600907955] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:06:24,229 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:06:24,229 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:06:24,229 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1367297823] [2022-12-13 15:06:24,229 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:06:24,230 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:06:24,230 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:06:24,230 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 15:06:24,230 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 15:06:24,230 INFO L87 Difference]: Start difference. First operand 530224 states and 751371 transitions. cyclomatic complexity: 221211 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:06:28,079 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:06:28,079 INFO L93 Difference]: Finished difference Result 1262975 states and 1778968 transitions. [2022-12-13 15:06:28,079 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1262975 states and 1778968 transitions. [2022-12-13 15:06:32,909 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 1236496 [2022-12-13 15:06:35,775 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1262975 states to 1262975 states and 1778968 transitions. [2022-12-13 15:06:35,776 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1262975 [2022-12-13 15:06:36,272 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1262975 [2022-12-13 15:06:36,273 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1262975 states and 1778968 transitions. [2022-12-13 15:06:36,691 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:06:36,691 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1262975 states and 1778968 transitions. [2022-12-13 15:06:37,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1262975 states and 1778968 transitions. [2022-12-13 15:06:44,698 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1262975 to 1010095. [2022-12-13 15:06:45,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1010095 states, 1010095 states have (on average 1.41300768739574) internal successors, (1427272), 1010094 states have internal predecessors, (1427272), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:06:47,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1010095 states to 1010095 states and 1427272 transitions. [2022-12-13 15:06:47,721 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1010095 states and 1427272 transitions. [2022-12-13 15:06:47,721 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 15:06:47,722 INFO L428 stractBuchiCegarLoop]: Abstraction has 1010095 states and 1427272 transitions. [2022-12-13 15:06:47,722 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-12-13 15:06:47,722 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1010095 states and 1427272 transitions. [2022-12-13 15:06:49,942 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 1007296 [2022-12-13 15:06:49,942 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:06:49,942 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:06:49,945 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:06:49,945 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:06:49,945 INFO L748 eck$LassoCheckResult]: Stem: 4218376#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 4218377#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 4219125#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4219126#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4219298#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 4219299#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4218240#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4218241#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4219935#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4219263#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4219264#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4219616#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4219617#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4219756#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4219871#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 4219872#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 4219687#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4219478#L1121 assume !(0 == ~M_E~0); 4219195#L1121-2 assume !(0 == ~T1_E~0); 4218513#L1126-1 assume !(0 == ~T2_E~0); 4218514#L1131-1 assume !(0 == ~T3_E~0); 4218686#L1136-1 assume !(0 == ~T4_E~0); 4218796#L1141-1 assume !(0 == ~T5_E~0); 4219037#L1146-1 assume !(0 == ~T6_E~0); 4219391#L1151-1 assume !(0 == ~T7_E~0); 4218861#L1156-1 assume !(0 == ~T8_E~0); 4218226#L1161-1 assume !(0 == ~T9_E~0); 4218227#L1166-1 assume !(0 == ~T10_E~0); 4218443#L1171-1 assume !(0 == ~T11_E~0); 4218444#L1176-1 assume !(0 == ~E_M~0); 4219412#L1181-1 assume !(0 == ~E_1~0); 4219571#L1186-1 assume !(0 == ~E_2~0); 4219634#L1191-1 assume !(0 == ~E_3~0); 4218475#L1196-1 assume !(0 == ~E_4~0); 4218476#L1201-1 assume !(0 == ~E_5~0); 4219962#L1206-1 assume !(0 == ~E_6~0); 4219688#L1211-1 assume !(0 == ~E_7~0); 4219689#L1216-1 assume !(0 == ~E_8~0); 4218615#L1221-1 assume !(0 == ~E_9~0); 4218616#L1226-1 assume !(0 == ~E_10~0); 4218325#L1231-1 assume !(0 == ~E_11~0); 4218326#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4219413#L556 assume !(1 == ~m_pc~0); 4219414#L556-2 is_master_triggered_~__retres1~0#1 := 0; 4218199#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4218200#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4219006#L1391 assume !(0 != activate_threads_~tmp~1#1); 4219606#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4219607#L575 assume !(1 == ~t1_pc~0); 4218155#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4218156#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4218292#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4218629#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 4218583#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4218584#L594 assume !(1 == ~t2_pc~0); 4219375#L594-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4219492#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4218515#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4218215#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 4218216#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4218281#L613 assume !(1 == ~t3_pc~0); 4218393#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4218392#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4218747#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4219035#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 4219036#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4218722#L632 assume !(1 == ~t4_pc~0); 4218723#L632-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4219479#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4218232#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4218233#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 4219418#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4219114#L651 assume !(1 == ~t5_pc~0); 4219115#L651-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4218405#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4218406#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4219003#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 4218419#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4218420#L670 assume !(1 == ~t6_pc~0); 4219666#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4218778#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4218779#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4219936#L1439 assume !(0 != activate_threads_~tmp___5~0#1); 4219078#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4219079#L689 assume !(1 == ~t7_pc~0); 4219339#L689-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4219213#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4219214#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4219686#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 4218974#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4218975#L708 assume !(1 == ~t8_pc~0); 4218511#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4218512#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4219811#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4219793#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 4218568#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4218569#L727 assume !(1 == ~t9_pc~0); 4218282#L727-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4218283#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4218557#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4218558#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 4219937#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4218625#L746 assume !(1 == ~t10_pc~0); 4218626#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4219355#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4219502#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4219737#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 4219610#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4218805#L765 assume !(1 == ~t11_pc~0); 4218806#L765-2 is_transmit11_triggered_~__retres1~11#1 := 0; 4219024#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4219823#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4219664#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 4219665#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4219788#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 4219789#L1249-2 assume !(1 == ~T1_E~0); 4218898#L1254-1 assume !(1 == ~T2_E~0); 4218899#L1259-1 assume !(1 == ~T3_E~0); 4218192#L1264-1 assume !(1 == ~T4_E~0); 4218193#L1269-1 assume !(1 == ~T5_E~0); 4220059#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4220060#L1279-1 assume !(1 == ~T7_E~0); 4218394#L1284-1 assume !(1 == ~T8_E~0); 4218395#L1289-1 assume !(1 == ~T9_E~0); 4218952#L1294-1 assume !(1 == ~T10_E~0); 4218953#L1299-1 assume !(1 == ~T11_E~0); 4218963#L1304-1 assume !(1 == ~E_M~0); 4220041#L1309-1 assume !(1 == ~E_1~0); 4220042#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 4218345#L1319-1 assume !(1 == ~E_3~0); 4218346#L1324-1 assume !(1 == ~E_4~0); 4564347#L1329-1 assume !(1 == ~E_5~0); 4219731#L1334-1 assume !(1 == ~E_6~0); 4219732#L1339-1 assume !(1 == ~E_7~0); 4583753#L1344-1 assume !(1 == ~E_8~0); 4583752#L1349-1 assume !(1 == ~E_9~0); 4583748#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 4583746#L1359-1 assume !(1 == ~E_11~0); 4583744#L1364-1 assume { :end_inline_reset_delta_events } true; 4583739#L1690-2 [2022-12-13 15:06:49,945 INFO L750 eck$LassoCheckResult]: Loop: 4583739#L1690-2 assume !false; 4583737#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4583733#L1096 assume !false; 4583731#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4583705#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 4583701#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4583699#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4583696#L937 assume !(0 != eval_~tmp~0#1); 4583697#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4678822#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4678818#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4678817#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4678816#L1126-3 assume !(0 == ~T2_E~0); 4678814#L1131-3 assume !(0 == ~T3_E~0); 4678812#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4678810#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4678729#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4678725#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4678721#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4678718#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4678715#L1166-3 assume !(0 == ~T10_E~0); 4678712#L1171-3 assume !(0 == ~T11_E~0); 4678709#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4678703#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4678700#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4678697#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4678691#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4678685#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4678678#L1206-3 assume !(0 == ~E_6~0); 4678670#L1211-3 assume !(0 == ~E_7~0); 4678662#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4678653#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4678645#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4678638#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4678630#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4678620#L556-39 assume !(1 == ~m_pc~0); 4678611#L556-41 is_master_triggered_~__retres1~0#1 := 0; 4678601#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4678592#is_master_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4678585#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 4678578#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4678568#L575-39 assume 1 == ~t1_pc~0; 4678559#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4678549#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4678540#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4678532#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4678524#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4678516#L594-39 assume !(1 == ~t2_pc~0); 4590023#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 4678501#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4678493#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4678485#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4678477#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4678467#L613-39 assume !(1 == ~t3_pc~0); 4678458#L613-41 is_transmit3_triggered_~__retres1~3#1 := 0; 4678449#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4678441#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4678433#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4678424#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4678413#L632-39 assume !(1 == ~t4_pc~0); 4678396#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 4678376#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4678360#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4678359#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4678336#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4678322#L651-39 assume !(1 == ~t5_pc~0); 4678311#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 4678297#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4678285#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4678275#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4678266#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4678257#L670-39 assume !(1 == ~t6_pc~0); 4678245#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 4678246#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4678182#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4678169#L1439-39 assume !(0 != activate_threads_~tmp___5~0#1); 4678025#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4591785#L689-39 assume !(1 == ~t7_pc~0); 4591783#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 4591781#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4591779#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4591777#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4591775#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4591773#L708-39 assume !(1 == ~t8_pc~0); 4591770#L708-41 is_transmit8_triggered_~__retres1~8#1 := 0; 4591768#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4591766#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4591764#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4591762#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4591760#L727-39 assume !(1 == ~t9_pc~0); 4579367#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 4591757#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4591605#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4591520#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 4591516#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4591514#L746-39 assume 1 == ~t10_pc~0; 4591511#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4591509#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4591506#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4591504#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4591502#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4583871#L765-39 assume !(1 == ~t11_pc~0); 4583869#L765-41 is_transmit11_triggered_~__retres1~11#1 := 0; 4583867#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4583865#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4583863#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4583861#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4583858#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4481150#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4583853#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4583849#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4583847#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4583845#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4583844#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4583842#L1279-3 assume !(1 == ~T7_E~0); 4583840#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4583836#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4583834#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4481124#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4583831#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4583829#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4583827#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4583825#L1319-3 assume !(1 == ~E_3~0); 4583823#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4583821#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4583819#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4529226#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4583816#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4583814#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4583812#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4583810#L1359-3 assume !(1 == ~E_11~0); 4583808#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4583787#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 4583783#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4583781#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 4583778#L1709 assume !(0 == start_simulation_~tmp~3#1); 4583777#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4583774#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 4583764#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4583763#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 4583762#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4583760#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4583758#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 4583743#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 4583739#L1690-2 [2022-12-13 15:06:49,946 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:06:49,946 INFO L85 PathProgramCache]: Analyzing trace with hash 2073641149, now seen corresponding path program 1 times [2022-12-13 15:06:49,946 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:06:49,946 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1978910372] [2022-12-13 15:06:49,946 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:06:49,946 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:06:49,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:06:49,986 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:06:49,986 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:06:49,986 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1978910372] [2022-12-13 15:06:49,986 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1978910372] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:06:49,986 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:06:49,986 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 15:06:49,986 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1305443672] [2022-12-13 15:06:49,987 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:06:49,987 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:06:49,987 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:06:49,987 INFO L85 PathProgramCache]: Analyzing trace with hash 1406288706, now seen corresponding path program 1 times [2022-12-13 15:06:49,987 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:06:49,987 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [560455199] [2022-12-13 15:06:49,988 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:06:49,988 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:06:49,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:06:50,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:06:50,015 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:06:50,015 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [560455199] [2022-12-13 15:06:50,015 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [560455199] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:06:50,015 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:06:50,015 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:06:50,016 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2033014001] [2022-12-13 15:06:50,016 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:06:50,016 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:06:50,016 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:06:50,016 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:06:50,016 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:06:50,017 INFO L87 Difference]: Start difference. First operand 1010095 states and 1427272 transitions. cyclomatic complexity: 417241 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:06:53,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:06:53,486 INFO L93 Difference]: Finished difference Result 1140381 states and 1611683 transitions. [2022-12-13 15:06:53,486 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1140381 states and 1611683 transitions. [2022-12-13 15:06:57,536 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 1137280