./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.12.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db906840-240b-4d5d-9821-f3e9e6d130c7/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db906840-240b-4d5d-9821-f3e9e6d130c7/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db906840-240b-4d5d-9821-f3e9e6d130c7/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db906840-240b-4d5d-9821-f3e9e6d130c7/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.12.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db906840-240b-4d5d-9821-f3e9e6d130c7/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db906840-240b-4d5d-9821-f3e9e6d130c7/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bc6dc2c99e05b6915f0a2e5b5d96221c996d96767aaa6be997dea59c4d6f5f0a --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 15:37:36,105 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 15:37:36,106 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 15:37:36,119 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 15:37:36,119 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 15:37:36,120 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 15:37:36,120 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 15:37:36,121 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 15:37:36,122 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 15:37:36,123 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 15:37:36,124 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 15:37:36,124 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 15:37:36,125 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 15:37:36,125 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 15:37:36,126 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 15:37:36,127 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 15:37:36,127 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 15:37:36,128 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 15:37:36,129 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 15:37:36,130 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 15:37:36,131 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 15:37:36,132 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 15:37:36,132 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 15:37:36,133 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 15:37:36,135 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 15:37:36,135 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 15:37:36,135 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 15:37:36,136 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 15:37:36,136 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 15:37:36,137 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 15:37:36,137 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 15:37:36,138 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 15:37:36,138 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 15:37:36,139 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 15:37:36,139 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 15:37:36,139 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 15:37:36,140 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 15:37:36,140 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 15:37:36,140 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 15:37:36,141 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 15:37:36,141 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 15:37:36,142 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db906840-240b-4d5d-9821-f3e9e6d130c7/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 15:37:36,155 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 15:37:36,156 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 15:37:36,156 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 15:37:36,156 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 15:37:36,163 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 15:37:36,163 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 15:37:36,163 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 15:37:36,164 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 15:37:36,164 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 15:37:36,164 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 15:37:36,164 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 15:37:36,164 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 15:37:36,164 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 15:37:36,165 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 15:37:36,165 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 15:37:36,165 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 15:37:36,165 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 15:37:36,165 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 15:37:36,166 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 15:37:36,166 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 15:37:36,166 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 15:37:36,166 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 15:37:36,166 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 15:37:36,166 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 15:37:36,166 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 15:37:36,167 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 15:37:36,167 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 15:37:36,167 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 15:37:36,167 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 15:37:36,167 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 15:37:36,168 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 15:37:36,168 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 15:37:36,169 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db906840-240b-4d5d-9821-f3e9e6d130c7/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db906840-240b-4d5d-9821-f3e9e6d130c7/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bc6dc2c99e05b6915f0a2e5b5d96221c996d96767aaa6be997dea59c4d6f5f0a [2022-12-13 15:37:36,330 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 15:37:36,349 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 15:37:36,352 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 15:37:36,353 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 15:37:36,353 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 15:37:36,355 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db906840-240b-4d5d-9821-f3e9e6d130c7/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/token_ring.12.cil-2.c [2022-12-13 15:37:38,946 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 15:37:39,157 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 15:37:39,158 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db906840-240b-4d5d-9821-f3e9e6d130c7/sv-benchmarks/c/systemc/token_ring.12.cil-2.c [2022-12-13 15:37:39,173 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db906840-240b-4d5d-9821-f3e9e6d130c7/bin/uautomizer-uyxdKDjOR8/data/378ca9109/f27d037709664076982aaef601d34b18/FLAG18a6bceb3 [2022-12-13 15:37:39,543 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db906840-240b-4d5d-9821-f3e9e6d130c7/bin/uautomizer-uyxdKDjOR8/data/378ca9109/f27d037709664076982aaef601d34b18 [2022-12-13 15:37:39,546 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 15:37:39,548 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 15:37:39,549 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 15:37:39,549 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 15:37:39,553 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 15:37:39,554 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 03:37:39" (1/1) ... [2022-12-13 15:37:39,555 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@399b9a3f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:37:39, skipping insertion in model container [2022-12-13 15:37:39,555 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 03:37:39" (1/1) ... [2022-12-13 15:37:39,561 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 15:37:39,589 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 15:37:39,686 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db906840-240b-4d5d-9821-f3e9e6d130c7/sv-benchmarks/c/systemc/token_ring.12.cil-2.c[671,684] [2022-12-13 15:37:39,783 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 15:37:39,794 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 15:37:39,802 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db906840-240b-4d5d-9821-f3e9e6d130c7/sv-benchmarks/c/systemc/token_ring.12.cil-2.c[671,684] [2022-12-13 15:37:39,843 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 15:37:39,856 INFO L208 MainTranslator]: Completed translation [2022-12-13 15:37:39,857 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:37:39 WrapperNode [2022-12-13 15:37:39,857 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 15:37:39,857 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 15:37:39,858 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 15:37:39,858 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 15:37:39,863 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:37:39" (1/1) ... [2022-12-13 15:37:39,871 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:37:39" (1/1) ... [2022-12-13 15:37:39,954 INFO L138 Inliner]: procedures = 52, calls = 67, calls flagged for inlining = 62, calls inlined = 269, statements flattened = 4134 [2022-12-13 15:37:39,955 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 15:37:39,957 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 15:37:39,957 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 15:37:39,957 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 15:37:39,965 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:37:39" (1/1) ... [2022-12-13 15:37:39,965 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:37:39" (1/1) ... [2022-12-13 15:37:39,983 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:37:39" (1/1) ... [2022-12-13 15:37:39,983 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:37:39" (1/1) ... [2022-12-13 15:37:40,013 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:37:39" (1/1) ... [2022-12-13 15:37:40,041 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:37:39" (1/1) ... [2022-12-13 15:37:40,047 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:37:39" (1/1) ... [2022-12-13 15:37:40,053 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:37:39" (1/1) ... [2022-12-13 15:37:40,062 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 15:37:40,063 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 15:37:40,063 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 15:37:40,063 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 15:37:40,064 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:37:39" (1/1) ... [2022-12-13 15:37:40,070 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 15:37:40,079 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db906840-240b-4d5d-9821-f3e9e6d130c7/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 15:37:40,090 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db906840-240b-4d5d-9821-f3e9e6d130c7/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 15:37:40,092 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db906840-240b-4d5d-9821-f3e9e6d130c7/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 15:37:40,124 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 15:37:40,124 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 15:37:40,124 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 15:37:40,124 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 15:37:40,218 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 15:37:40,220 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 15:37:41,665 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 15:37:41,684 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 15:37:41,684 INFO L300 CfgBuilder]: Removed 15 assume(true) statements. [2022-12-13 15:37:41,687 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 03:37:41 BoogieIcfgContainer [2022-12-13 15:37:41,688 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 15:37:41,688 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 15:37:41,688 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 15:37:41,692 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 15:37:41,693 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 15:37:41,693 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 03:37:39" (1/3) ... [2022-12-13 15:37:41,694 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@59f5ce67 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 03:37:41, skipping insertion in model container [2022-12-13 15:37:41,694 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 15:37:41,694 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:37:39" (2/3) ... [2022-12-13 15:37:41,694 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@59f5ce67 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 03:37:41, skipping insertion in model container [2022-12-13 15:37:41,694 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 15:37:41,694 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 03:37:41" (3/3) ... [2022-12-13 15:37:41,696 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.12.cil-2.c [2022-12-13 15:37:41,775 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 15:37:41,775 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 15:37:41,775 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 15:37:41,775 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 15:37:41,775 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 15:37:41,775 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 15:37:41,776 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 15:37:41,776 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 15:37:41,784 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1791 states, 1790 states have (on average 1.4988826815642458) internal successors, (2683), 1790 states have internal predecessors, (2683), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:41,828 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1624 [2022-12-13 15:37:41,829 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:37:41,829 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:37:41,842 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:41,842 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:41,842 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 15:37:41,844 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1791 states, 1790 states have (on average 1.4988826815642458) internal successors, (2683), 1790 states have internal predecessors, (2683), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:41,861 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1624 [2022-12-13 15:37:41,862 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:37:41,862 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:37:41,866 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:41,866 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:41,875 INFO L748 eck$LassoCheckResult]: Stem: 120#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1708#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 680#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1706#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 154#L841true assume !(1 == ~m_i~0);~m_st~0 := 2; 555#L841-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 109#L846-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1724#L851-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1022#L856-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 454#L861-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 487#L866-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 393#L871-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 757#L876-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 748#L881-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 1314#L886-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 252#L891-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 1304#L896-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 514#L901-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1192#L1194true assume !(0 == ~M_E~0); 614#L1194-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 874#L1199-1true assume !(0 == ~T2_E~0); 1064#L1204-1true assume !(0 == ~T3_E~0); 797#L1209-1true assume !(0 == ~T4_E~0); 1350#L1214-1true assume !(0 == ~T5_E~0); 1740#L1219-1true assume !(0 == ~T6_E~0); 1661#L1224-1true assume !(0 == ~T7_E~0); 292#L1229-1true assume !(0 == ~T8_E~0); 70#L1234-1true assume 0 == ~T9_E~0;~T9_E~0 := 1; 501#L1239-1true assume !(0 == ~T10_E~0); 90#L1244-1true assume !(0 == ~T11_E~0); 1445#L1249-1true assume !(0 == ~T12_E~0); 475#L1254-1true assume !(0 == ~E_M~0); 41#L1259-1true assume !(0 == ~E_1~0); 24#L1264-1true assume !(0 == ~E_2~0); 1781#L1269-1true assume !(0 == ~E_3~0); 1711#L1274-1true assume 0 == ~E_4~0;~E_4~0 := 1; 1436#L1279-1true assume !(0 == ~E_5~0); 125#L1284-1true assume !(0 == ~E_6~0); 1569#L1289-1true assume !(0 == ~E_7~0); 520#L1294-1true assume !(0 == ~E_8~0); 527#L1299-1true assume !(0 == ~E_9~0); 1632#L1304-1true assume !(0 == ~E_10~0); 1672#L1309-1true assume !(0 == ~E_11~0); 1648#L1314-1true assume 0 == ~E_12~0;~E_12~0 := 1; 105#L1319-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69#L586true assume 1 == ~m_pc~0; 1226#L587true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 775#L597true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 568#is_master_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 203#L1485true assume !(0 != activate_threads_~tmp~1#1); 1032#L1485-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1730#L605true assume !(1 == ~t1_pc~0); 1182#L605-2true is_transmit1_triggered_~__retres1~1#1 := 0; 411#L616true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 925#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1342#L1493true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 848#L1493-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 357#L624true assume 1 == ~t2_pc~0; 92#L625true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 459#L635true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 215#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1426#L1501true assume !(0 != activate_threads_~tmp___1~0#1); 1086#L1501-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 922#L643true assume !(1 == ~t3_pc~0); 771#L643-2true is_transmit3_triggered_~__retres1~3#1 := 0; 539#L654true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 905#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 256#L1509true assume !(0 != activate_threads_~tmp___2~0#1); 1275#L1509-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 135#L662true assume 1 == ~t4_pc~0; 450#L663true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 116#L673true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 559#L1517true assume !(0 != activate_threads_~tmp___3~0#1); 63#L1517-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 379#L681true assume !(1 == ~t5_pc~0); 2#L681-2true is_transmit5_triggered_~__retres1~5#1 := 0; 597#L692true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1479#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1274#L1525true assume !(0 != activate_threads_~tmp___4~0#1); 263#L1525-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 727#L700true assume 1 == ~t6_pc~0; 1780#L701true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 131#L711true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 205#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 155#L1533true assume !(0 != activate_threads_~tmp___5~0#1); 1161#L1533-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1293#L719true assume 1 == ~t7_pc~0; 1586#L720true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1605#L730true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1725#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1398#L1541true assume !(0 != activate_threads_~tmp___6~0#1); 8#L1541-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1606#L738true assume !(1 == ~t8_pc~0); 881#L738-2true is_transmit8_triggered_~__retres1~8#1 := 0; 790#L749true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1423#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 612#L1549true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1203#L1549-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 944#L757true assume 1 == ~t9_pc~0; 1643#L758true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6#L768true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 236#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1059#L1557true assume !(0 != activate_threads_~tmp___8~0#1); 591#L1557-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1587#L776true assume !(1 == ~t10_pc~0); 1095#L776-2true is_transmit10_triggered_~__retres1~10#1 := 0; 206#L787true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1197#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 126#L1565true assume !(0 != activate_threads_~tmp___9~0#1); 764#L1565-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 106#L795true assume 1 == ~t11_pc~0; 274#L796true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1056#L806true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1335#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1324#L1573true assume !(0 != activate_threads_~tmp___10~0#1); 766#L1573-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 751#L814true assume !(1 == ~t12_pc~0); 904#L814-2true is_transmit12_triggered_~__retres1~12#1 := 0; 996#L825true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30#is_transmit12_triggered_returnLabel#1true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1313#L1581true assume !(0 != activate_threads_~tmp___11~0#1); 229#L1581-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1101#L1332true assume !(1 == ~M_E~0); 1488#L1332-2true assume !(1 == ~T1_E~0); 1521#L1337-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 692#L1342-1true assume !(1 == ~T3_E~0); 1430#L1347-1true assume !(1 == ~T4_E~0); 1143#L1352-1true assume !(1 == ~T5_E~0); 949#L1357-1true assume !(1 == ~T6_E~0); 392#L1362-1true assume !(1 == ~T7_E~0); 1213#L1367-1true assume !(1 == ~T8_E~0); 171#L1372-1true assume !(1 == ~T9_E~0); 492#L1377-1true assume 1 == ~T10_E~0;~T10_E~0 := 2; 343#L1382-1true assume !(1 == ~T11_E~0); 845#L1387-1true assume !(1 == ~T12_E~0); 1376#L1392-1true assume !(1 == ~E_M~0); 358#L1397-1true assume !(1 == ~E_1~0); 1494#L1402-1true assume !(1 == ~E_2~0); 179#L1407-1true assume !(1 == ~E_3~0); 1624#L1412-1true assume !(1 == ~E_4~0); 1055#L1417-1true assume 1 == ~E_5~0;~E_5~0 := 2; 1792#L1422-1true assume !(1 == ~E_6~0); 1493#L1427-1true assume !(1 == ~E_7~0); 275#L1432-1true assume !(1 == ~E_8~0); 1382#L1437-1true assume !(1 == ~E_9~0); 987#L1442-1true assume !(1 == ~E_10~0); 1298#L1447-1true assume !(1 == ~E_11~0); 834#L1452-1true assume !(1 == ~E_12~0); 77#L1457-1true assume { :end_inline_reset_delta_events } true; 1431#L1803-2true [2022-12-13 15:37:41,878 INFO L750 eck$LassoCheckResult]: Loop: 1431#L1803-2true assume !false; 242#L1804true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 315#L1169true assume false; 512#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 304#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 615#L1194-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1642#L1194-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 159#L1199-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 880#L1204-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 290#L1209-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 12#L1214-3true assume !(0 == ~T5_E~0); 676#L1219-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 410#L1224-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1787#L1229-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 428#L1234-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 94#L1239-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 323#L1244-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 711#L1249-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 1546#L1254-3true assume !(0 == ~E_M~0); 1343#L1259-3true assume 0 == ~E_1~0;~E_1~0 := 1; 820#L1264-3true assume 0 == ~E_2~0;~E_2~0 := 1; 97#L1269-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1611#L1274-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1429#L1279-3true assume 0 == ~E_5~0;~E_5~0 := 1; 409#L1284-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1484#L1289-3true assume 0 == ~E_7~0;~E_7~0 := 1; 397#L1294-3true assume !(0 == ~E_8~0); 1663#L1299-3true assume 0 == ~E_9~0;~E_9~0 := 1; 655#L1304-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1010#L1309-3true assume 0 == ~E_11~0;~E_11~0 := 1; 344#L1314-3true assume 0 == ~E_12~0;~E_12~0 := 1; 1741#L1319-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 347#L586-42true assume !(1 == ~m_pc~0); 887#L586-44true is_master_triggered_~__retres1~0#1 := 0; 130#L597-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 381#is_master_triggered_returnLabel#15true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1421#L1485-42true assume !(0 != activate_threads_~tmp~1#1); 424#L1485-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 889#L605-42true assume !(1 == ~t1_pc~0); 1746#L605-44true is_transmit1_triggered_~__retres1~1#1 := 0; 631#L616-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1640#is_transmit1_triggered_returnLabel#15true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 425#L1493-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 473#L1493-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 430#L624-42true assume !(1 == ~t2_pc~0); 525#L624-44true is_transmit2_triggered_~__retres1~2#1 := 0; 1440#L635-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 590#is_transmit2_triggered_returnLabel#15true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1690#L1501-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 322#L1501-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1286#L643-42true assume !(1 == ~t3_pc~0); 970#L643-44true is_transmit3_triggered_~__retres1~3#1 := 0; 513#L654-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 895#is_transmit3_triggered_returnLabel#15true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 407#L1509-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 997#L1509-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1310#L662-42true assume 1 == ~t4_pc~0; 1347#L663-14true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 139#L673-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 968#is_transmit4_triggered_returnLabel#15true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1464#L1517-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1409#L1517-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1326#L681-42true assume !(1 == ~t5_pc~0); 75#L681-44true is_transmit5_triggered_~__retres1~5#1 := 0; 749#L692-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 650#is_transmit5_triggered_returnLabel#15true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1625#L1525-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1063#L1525-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 335#L700-42true assume 1 == ~t6_pc~0; 518#L701-14true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 951#L711-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 185#is_transmit6_triggered_returnLabel#15true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1077#L1533-42true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1694#L1533-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1450#L719-42true assume !(1 == ~t7_pc~0); 166#L719-44true is_transmit7_triggered_~__retres1~7#1 := 0; 373#L730-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 665#is_transmit7_triggered_returnLabel#15true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 538#L1541-42true assume !(0 != activate_threads_~tmp___6~0#1); 382#L1541-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1435#L738-42true assume !(1 == ~t8_pc~0); 1200#L738-44true is_transmit8_triggered_~__retres1~8#1 := 0; 352#L749-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 779#is_transmit8_triggered_returnLabel#15true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 96#L1549-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 376#L1549-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1244#L757-42true assume !(1 == ~t9_pc~0); 1330#L757-44true is_transmit9_triggered_~__retres1~9#1 := 0; 186#L768-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1652#is_transmit9_triggered_returnLabel#15true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 638#L1557-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 246#L1557-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1035#L776-42true assume 1 == ~t10_pc~0; 983#L777-14true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1023#L787-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 767#is_transmit10_triggered_returnLabel#15true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1601#L1565-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1785#L1565-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 789#L795-42true assume 1 == ~t11_pc~0; 1453#L796-14true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 164#L806-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1402#is_transmit11_triggered_returnLabel#15true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 213#L1573-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 388#L1573-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1116#L814-42true assume !(1 == ~t12_pc~0); 310#L814-44true is_transmit12_triggered_~__retres1~12#1 := 0; 121#L825-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 633#is_transmit12_triggered_returnLabel#15true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28#L1581-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1742#L1581-44true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 103#L1332-3true assume 1 == ~M_E~0;~M_E~0 := 2; 708#L1332-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 91#L1337-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 560#L1342-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1030#L1347-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 683#L1352-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1194#L1357-3true assume !(1 == ~T6_E~0); 1779#L1362-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1646#L1367-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1615#L1372-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 20#L1377-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 432#L1382-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 333#L1387-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 993#L1392-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1701#L1397-3true assume !(1 == ~E_1~0); 1483#L1402-3true assume 1 == ~E_2~0;~E_2~0 := 2; 640#L1407-3true assume 1 == ~E_3~0;~E_3~0 := 2; 143#L1412-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1231#L1417-3true assume 1 == ~E_5~0;~E_5~0 := 2; 573#L1422-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1188#L1427-3true assume 1 == ~E_7~0;~E_7~0 := 2; 1384#L1432-3true assume 1 == ~E_8~0;~E_8~0 := 2; 869#L1437-3true assume !(1 == ~E_9~0); 657#L1442-3true assume 1 == ~E_10~0;~E_10~0 := 2; 883#L1447-3true assume 1 == ~E_11~0;~E_11~0 := 2; 45#L1452-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1753#L1457-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 367#L914-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1394#L981-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 178#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 138#L1822true assume !(0 == start_simulation_~tmp~3#1); 740#L1822-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 765#L914-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 271#L981-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 699#L1777true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 792#L1784true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1230#stop_simulation_returnLabel#1true start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1238#L1835true assume !(0 != start_simulation_~tmp___0~1#1); 1431#L1803-2true [2022-12-13 15:37:41,885 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:41,885 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 1 times [2022-12-13 15:37:41,894 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:41,895 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1008393570] [2022-12-13 15:37:41,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:41,895 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:42,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:42,134 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:42,134 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:42,134 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1008393570] [2022-12-13 15:37:42,135 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1008393570] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:42,135 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:42,135 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:42,136 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1558825909] [2022-12-13 15:37:42,137 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:42,140 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:37:42,141 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:42,141 INFO L85 PathProgramCache]: Analyzing trace with hash -1984056805, now seen corresponding path program 1 times [2022-12-13 15:37:42,141 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:42,141 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [230669423] [2022-12-13 15:37:42,141 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:42,141 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:42,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:42,197 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:42,197 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:42,197 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [230669423] [2022-12-13 15:37:42,198 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [230669423] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:42,198 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:42,198 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 15:37:42,198 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2021748931] [2022-12-13 15:37:42,198 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:42,200 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:37:42,201 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:37:42,229 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-12-13 15:37:42,230 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-12-13 15:37:42,236 INFO L87 Difference]: Start difference. First operand has 1791 states, 1790 states have (on average 1.4988826815642458) internal successors, (2683), 1790 states have internal predecessors, (2683), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 74.5) internal successors, (149), 2 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:42,292 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:37:42,292 INFO L93 Difference]: Finished difference Result 1790 states and 2651 transitions. [2022-12-13 15:37:42,293 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1790 states and 2651 transitions. [2022-12-13 15:37:42,310 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-12-13 15:37:42,331 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1790 states to 1785 states and 2646 transitions. [2022-12-13 15:37:42,332 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2022-12-13 15:37:42,335 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2022-12-13 15:37:42,336 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2646 transitions. [2022-12-13 15:37:42,345 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:37:42,345 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2646 transitions. [2022-12-13 15:37:42,365 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2646 transitions. [2022-12-13 15:37:42,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2022-12-13 15:37:42,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4823529411764707) internal successors, (2646), 1784 states have internal predecessors, (2646), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:42,430 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2646 transitions. [2022-12-13 15:37:42,431 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2646 transitions. [2022-12-13 15:37:42,432 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-12-13 15:37:42,435 INFO L428 stractBuchiCegarLoop]: Abstraction has 1785 states and 2646 transitions. [2022-12-13 15:37:42,435 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 15:37:42,436 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2646 transitions. [2022-12-13 15:37:42,447 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-12-13 15:37:42,447 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:37:42,447 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:37:42,451 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:42,451 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:42,452 INFO L748 eck$LassoCheckResult]: Stem: 3840#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 3841#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 4758#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4759#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3910#L841 assume !(1 == ~m_i~0);~m_st~0 := 2; 3911#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3815#L846-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3816#L851-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5082#L856-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4442#L861-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4443#L866-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4340#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4341#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4840#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4841#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4103#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4104#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4528#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4529#L1194 assume !(0 == ~M_E~0); 4680#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4681#L1199-1 assume !(0 == ~T2_E~0); 4963#L1204-1 assume !(0 == ~T3_E~0); 4889#L1209-1 assume !(0 == ~T4_E~0); 4890#L1214-1 assume !(0 == ~T5_E~0); 5284#L1219-1 assume !(0 == ~T6_E~0); 5371#L1224-1 assume !(0 == ~T7_E~0); 4176#L1229-1 assume !(0 == ~T8_E~0); 3733#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3734#L1239-1 assume !(0 == ~T10_E~0); 3778#L1244-1 assume !(0 == ~T11_E~0); 3779#L1249-1 assume !(0 == ~T12_E~0); 4472#L1254-1 assume !(0 == ~E_M~0); 3675#L1259-1 assume !(0 == ~E_1~0); 3640#L1264-1 assume !(0 == ~E_2~0); 3641#L1269-1 assume !(0 == ~E_3~0); 5373#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 5316#L1279-1 assume !(0 == ~E_5~0); 3851#L1284-1 assume !(0 == ~E_6~0); 3852#L1289-1 assume !(0 == ~E_7~0); 4535#L1294-1 assume !(0 == ~E_8~0); 4536#L1299-1 assume !(0 == ~E_9~0); 4547#L1304-1 assume !(0 == ~E_10~0); 5364#L1309-1 assume !(0 == ~E_11~0); 5369#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 3808#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3730#L586 assume 1 == ~m_pc~0; 3731#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3800#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4607#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4009#L1485 assume !(0 != activate_threads_~tmp~1#1); 4010#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5088#L605 assume !(1 == ~t1_pc~0); 4621#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4367#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4368#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5001#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4937#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4277#L624 assume 1 == ~t2_pc~0; 3782#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3783#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4033#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4034#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 5120#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4999#L643 assume !(1 == ~t3_pc~0); 4859#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4565#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4566#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4110#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 4111#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3872#L662 assume 1 == ~t4_pc~0; 3873#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3831#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3692#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3693#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 3719#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3720#L681 assume !(1 == ~t5_pc~0); 3590#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3591#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4647#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5245#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 4122#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4123#L700 assume 1 == ~t6_pc~0; 4820#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3864#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3865#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3912#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 3913#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5174#L719 assume 1 == ~t7_pc~0; 5254#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4079#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5361#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5302#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 3604#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3605#L738 assume !(1 == ~t8_pc~0); 4970#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4880#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4881#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4676#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4677#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5021#L757 assume 1 == ~t9_pc~0; 5022#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3599#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3600#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4077#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 4639#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4640#L776 assume !(1 == ~t10_pc~0); 3624#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3623#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4013#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3853#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 3854#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3809#L795 assume 1 == ~t11_pc~0; 3810#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4142#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5102#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5272#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 4853#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4843#L814 assume !(1 == ~t12_pc~0); 4706#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4707#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3653#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3654#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 4061#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4062#L1332 assume !(1 == ~M_E~0); 5133#L1332-2 assume !(1 == ~T1_E~0); 5334#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4775#L1342-1 assume !(1 == ~T3_E~0); 4776#L1347-1 assume !(1 == ~T4_E~0); 5161#L1352-1 assume !(1 == ~T5_E~0); 5027#L1357-1 assume !(1 == ~T6_E~0); 4338#L1362-1 assume !(1 == ~T7_E~0); 4339#L1367-1 assume !(1 == ~T8_E~0); 3948#L1372-1 assume !(1 == ~T9_E~0); 3949#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4251#L1382-1 assume !(1 == ~T11_E~0); 4252#L1387-1 assume !(1 == ~T12_E~0); 4935#L1392-1 assume !(1 == ~E_M~0); 4278#L1397-1 assume !(1 == ~E_1~0); 4279#L1402-1 assume !(1 == ~E_2~0); 3963#L1407-1 assume !(1 == ~E_3~0); 3964#L1412-1 assume !(1 == ~E_4~0); 5100#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 5101#L1422-1 assume !(1 == ~E_6~0); 5336#L1427-1 assume !(1 == ~E_7~0); 4143#L1432-1 assume !(1 == ~E_8~0); 4144#L1437-1 assume !(1 == ~E_9~0); 5053#L1442-1 assume !(1 == ~E_10~0); 5054#L1447-1 assume !(1 == ~E_11~0); 4927#L1452-1 assume !(1 == ~E_12~0); 3750#L1457-1 assume { :end_inline_reset_delta_events } true; 3751#L1803-2 [2022-12-13 15:37:42,453 INFO L750 eck$LassoCheckResult]: Loop: 3751#L1803-2 assume !false; 4085#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3621#L1169 assume !false; 4206#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4320#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3817#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3818#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5141#L996 assume !(0 != eval_~tmp~0#1); 4525#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4195#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4196#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4682#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3919#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3920#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4172#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3613#L1214-3 assume !(0 == ~T5_E~0); 3614#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4365#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4366#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4400#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3788#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3789#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4219#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4799#L1254-3 assume !(0 == ~E_M~0); 5278#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4910#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3794#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3795#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5313#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4363#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4364#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4346#L1294-3 assume !(0 == ~E_8~0); 4347#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4731#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4732#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4253#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4254#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4259#L586-42 assume !(1 == ~m_pc~0); 4260#L586-44 is_master_triggered_~__retres1~0#1 := 0; 3862#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3863#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4321#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 4393#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4394#L605-42 assume !(1 == ~t1_pc~0); 4976#L605-44 is_transmit1_triggered_~__retres1~1#1 := 0; 4699#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4700#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4395#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4396#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4404#L624-42 assume !(1 == ~t2_pc~0); 4405#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 4545#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4637#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4638#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4217#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4218#L643-42 assume 1 == ~t3_pc~0; 4569#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4526#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4527#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4361#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4362#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5063#L662-42 assume !(1 == ~t4_pc~0); 5265#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 3883#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3884#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5042#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5306#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5273#L681-42 assume !(1 == ~t5_pc~0); 3746#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 3747#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4724#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4725#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5109#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4237#L700-42 assume !(1 == ~t6_pc~0); 4048#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 4049#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3975#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3976#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5116#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5323#L719-42 assume !(1 == ~t7_pc~0); 3936#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 3937#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4307#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4564#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 4322#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4323#L738-42 assume 1 == ~t8_pc~0; 4515#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4268#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4269#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3792#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3793#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4316#L757-42 assume 1 == ~t9_pc~0; 4652#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3977#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3978#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4711#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4090#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4091#L776-42 assume !(1 == ~t10_pc~0); 5034#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 5035#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4854#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4855#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5359#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4877#L795-42 assume !(1 == ~t11_pc~0); 4878#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 3931#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3932#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4028#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4029#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4332#L814-42 assume 1 == ~t12_pc~0; 5091#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 3842#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3843#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3648#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 3649#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3804#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3805#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3780#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3781#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4596#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4763#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4764#L1357-3 assume !(1 == ~T6_E~0); 5194#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5367#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5363#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3631#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3632#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4234#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4235#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5059#L1397-3 assume !(1 == ~E_1~0); 5333#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4713#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3888#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3889#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4616#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4617#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5192#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4956#L1437-3 assume !(1 == ~E_9~0); 4733#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4734#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 3682#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 3683#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4295#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4140#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3962#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 3880#L1822 assume !(0 == start_simulation_~tmp~3#1); 3881#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4829#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4137#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3633#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 3634#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4785#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4883#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 5219#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 3751#L1803-2 [2022-12-13 15:37:42,454 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:42,454 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 2 times [2022-12-13 15:37:42,454 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:42,454 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [881220414] [2022-12-13 15:37:42,454 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:42,455 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:42,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:42,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:42,531 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:42,532 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [881220414] [2022-12-13 15:37:42,532 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [881220414] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:42,532 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:42,532 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:42,533 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [315355822] [2022-12-13 15:37:42,533 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:42,533 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:37:42,534 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:42,534 INFO L85 PathProgramCache]: Analyzing trace with hash 1501608824, now seen corresponding path program 1 times [2022-12-13 15:37:42,535 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:42,535 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1287468099] [2022-12-13 15:37:42,535 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:42,535 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:42,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:42,637 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:42,637 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:42,637 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1287468099] [2022-12-13 15:37:42,638 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1287468099] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:42,638 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:42,638 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:42,638 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [239908521] [2022-12-13 15:37:42,638 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:42,639 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:37:42,639 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:37:42,640 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:37:42,640 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:37:42,640 INFO L87 Difference]: Start difference. First operand 1785 states and 2646 transitions. cyclomatic complexity: 862 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:42,683 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:37:42,683 INFO L93 Difference]: Finished difference Result 1785 states and 2645 transitions. [2022-12-13 15:37:42,683 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2645 transitions. [2022-12-13 15:37:42,689 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-12-13 15:37:42,695 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2645 transitions. [2022-12-13 15:37:42,695 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2022-12-13 15:37:42,696 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2022-12-13 15:37:42,696 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2645 transitions. [2022-12-13 15:37:42,698 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:37:42,698 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2645 transitions. [2022-12-13 15:37:42,699 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2645 transitions. [2022-12-13 15:37:42,713 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2022-12-13 15:37:42,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4817927170868348) internal successors, (2645), 1784 states have internal predecessors, (2645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:42,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2645 transitions. [2022-12-13 15:37:42,718 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2645 transitions. [2022-12-13 15:37:42,719 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:37:42,719 INFO L428 stractBuchiCegarLoop]: Abstraction has 1785 states and 2645 transitions. [2022-12-13 15:37:42,719 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 15:37:42,719 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2645 transitions. [2022-12-13 15:37:42,724 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-12-13 15:37:42,725 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:37:42,725 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:37:42,726 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:42,726 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:42,727 INFO L748 eck$LassoCheckResult]: Stem: 7417#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 7418#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 8335#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8336#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7487#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 7488#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7392#L846-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 7393#L851-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8659#L856-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8019#L861-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8020#L866-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7917#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7918#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8417#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8418#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7680#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 7681#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 8105#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8106#L1194 assume !(0 == ~M_E~0); 8257#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8258#L1199-1 assume !(0 == ~T2_E~0); 8540#L1204-1 assume !(0 == ~T3_E~0); 8466#L1209-1 assume !(0 == ~T4_E~0); 8467#L1214-1 assume !(0 == ~T5_E~0); 8861#L1219-1 assume !(0 == ~T6_E~0); 8948#L1224-1 assume !(0 == ~T7_E~0); 7753#L1229-1 assume !(0 == ~T8_E~0); 7310#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7311#L1239-1 assume !(0 == ~T10_E~0); 7355#L1244-1 assume !(0 == ~T11_E~0); 7356#L1249-1 assume !(0 == ~T12_E~0); 8049#L1254-1 assume !(0 == ~E_M~0); 7252#L1259-1 assume !(0 == ~E_1~0); 7217#L1264-1 assume !(0 == ~E_2~0); 7218#L1269-1 assume !(0 == ~E_3~0); 8950#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 8893#L1279-1 assume !(0 == ~E_5~0); 7428#L1284-1 assume !(0 == ~E_6~0); 7429#L1289-1 assume !(0 == ~E_7~0); 8112#L1294-1 assume !(0 == ~E_8~0); 8113#L1299-1 assume !(0 == ~E_9~0); 8124#L1304-1 assume !(0 == ~E_10~0); 8941#L1309-1 assume !(0 == ~E_11~0); 8946#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 7385#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7307#L586 assume 1 == ~m_pc~0; 7308#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7377#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8184#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7586#L1485 assume !(0 != activate_threads_~tmp~1#1); 7587#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8665#L605 assume !(1 == ~t1_pc~0); 8198#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7944#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7945#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8578#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8514#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7854#L624 assume 1 == ~t2_pc~0; 7359#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7360#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7610#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7611#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 8697#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8576#L643 assume !(1 == ~t3_pc~0); 8436#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8142#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8143#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7687#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 7688#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7449#L662 assume 1 == ~t4_pc~0; 7450#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7408#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7269#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7270#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 7296#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7297#L681 assume !(1 == ~t5_pc~0); 7167#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7168#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8224#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8822#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 7699#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7700#L700 assume 1 == ~t6_pc~0; 8397#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7441#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7442#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7489#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 7490#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8751#L719 assume 1 == ~t7_pc~0; 8831#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7656#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8938#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8879#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 7181#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7182#L738 assume !(1 == ~t8_pc~0); 8547#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8457#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8458#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8253#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8254#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8598#L757 assume 1 == ~t9_pc~0; 8599#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7176#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7177#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7654#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 8216#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8217#L776 assume !(1 == ~t10_pc~0); 7201#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 7200#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7590#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7430#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 7431#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7386#L795 assume 1 == ~t11_pc~0; 7387#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7719#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8679#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8849#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 8430#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8420#L814 assume !(1 == ~t12_pc~0); 8283#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 8284#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7230#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7231#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 7638#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7639#L1332 assume !(1 == ~M_E~0); 8710#L1332-2 assume !(1 == ~T1_E~0); 8911#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8352#L1342-1 assume !(1 == ~T3_E~0); 8353#L1347-1 assume !(1 == ~T4_E~0); 8738#L1352-1 assume !(1 == ~T5_E~0); 8604#L1357-1 assume !(1 == ~T6_E~0); 7915#L1362-1 assume !(1 == ~T7_E~0); 7916#L1367-1 assume !(1 == ~T8_E~0); 7525#L1372-1 assume !(1 == ~T9_E~0); 7526#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 7828#L1382-1 assume !(1 == ~T11_E~0); 7829#L1387-1 assume !(1 == ~T12_E~0); 8512#L1392-1 assume !(1 == ~E_M~0); 7855#L1397-1 assume !(1 == ~E_1~0); 7856#L1402-1 assume !(1 == ~E_2~0); 7540#L1407-1 assume !(1 == ~E_3~0); 7541#L1412-1 assume !(1 == ~E_4~0); 8677#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 8678#L1422-1 assume !(1 == ~E_6~0); 8913#L1427-1 assume !(1 == ~E_7~0); 7720#L1432-1 assume !(1 == ~E_8~0); 7721#L1437-1 assume !(1 == ~E_9~0); 8630#L1442-1 assume !(1 == ~E_10~0); 8631#L1447-1 assume !(1 == ~E_11~0); 8504#L1452-1 assume !(1 == ~E_12~0); 7327#L1457-1 assume { :end_inline_reset_delta_events } true; 7328#L1803-2 [2022-12-13 15:37:42,727 INFO L750 eck$LassoCheckResult]: Loop: 7328#L1803-2 assume !false; 7662#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7198#L1169 assume !false; 7783#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 7897#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7394#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7395#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8718#L996 assume !(0 != eval_~tmp~0#1); 8102#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7772#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7773#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8259#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7496#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7497#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7749#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7190#L1214-3 assume !(0 == ~T5_E~0); 7191#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7942#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7943#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7977#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7365#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 7366#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 7796#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8376#L1254-3 assume !(0 == ~E_M~0); 8855#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8487#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7371#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7372#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8890#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7940#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7941#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7923#L1294-3 assume !(0 == ~E_8~0); 7924#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8308#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8309#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7830#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 7831#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7836#L586-42 assume !(1 == ~m_pc~0); 7837#L586-44 is_master_triggered_~__retres1~0#1 := 0; 7439#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7440#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7898#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 7970#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7971#L605-42 assume 1 == ~t1_pc~0; 8552#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8276#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8277#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7972#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7973#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7981#L624-42 assume !(1 == ~t2_pc~0); 7982#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 8122#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8214#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8215#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7794#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7795#L643-42 assume 1 == ~t3_pc~0; 8146#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8103#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8104#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7938#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7939#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8640#L662-42 assume !(1 == ~t4_pc~0); 8842#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 7460#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7461#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8619#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8883#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8850#L681-42 assume !(1 == ~t5_pc~0); 7323#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 7324#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8301#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8302#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8686#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7814#L700-42 assume 1 == ~t6_pc~0; 7815#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7626#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7552#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7553#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8693#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8900#L719-42 assume !(1 == ~t7_pc~0); 7513#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 7514#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7884#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8141#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 7899#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7900#L738-42 assume 1 == ~t8_pc~0; 8092#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7845#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7846#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7369#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7370#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7893#L757-42 assume 1 == ~t9_pc~0; 8229#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7554#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7555#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8288#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7667#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7668#L776-42 assume !(1 == ~t10_pc~0); 8611#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 8612#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8431#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8432#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8936#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8454#L795-42 assume !(1 == ~t11_pc~0); 8455#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 7508#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7509#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 7605#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7606#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7909#L814-42 assume !(1 == ~t12_pc~0); 7778#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 7419#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7420#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7225#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 7226#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7381#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7382#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7357#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7358#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8173#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8340#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8341#L1357-3 assume !(1 == ~T6_E~0); 8771#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8944#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8940#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7208#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 7209#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 7811#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 7812#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8636#L1397-3 assume !(1 == ~E_1~0); 8910#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8290#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7465#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7466#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8193#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8194#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8769#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8533#L1437-3 assume !(1 == ~E_9~0); 8310#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 8311#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 7259#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 7260#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 7872#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7717#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7539#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 7457#L1822 assume !(0 == start_simulation_~tmp~3#1); 7458#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8406#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7714#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7210#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 7211#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8362#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8460#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 8796#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 7328#L1803-2 [2022-12-13 15:37:42,728 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:42,728 INFO L85 PathProgramCache]: Analyzing trace with hash -494851220, now seen corresponding path program 1 times [2022-12-13 15:37:42,728 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:42,728 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2070212366] [2022-12-13 15:37:42,728 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:42,728 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:42,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:42,792 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:42,792 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:42,793 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2070212366] [2022-12-13 15:37:42,793 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2070212366] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:42,793 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:42,793 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:42,793 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [832162892] [2022-12-13 15:37:42,793 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:42,794 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:37:42,794 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:42,795 INFO L85 PathProgramCache]: Analyzing trace with hash -1556942217, now seen corresponding path program 1 times [2022-12-13 15:37:42,795 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:42,795 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [863838988] [2022-12-13 15:37:42,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:42,796 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:42,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:42,860 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:42,861 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:42,861 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [863838988] [2022-12-13 15:37:42,861 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [863838988] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:42,861 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:42,861 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:42,862 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [712029971] [2022-12-13 15:37:42,862 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:42,862 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:37:42,862 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:37:42,863 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:37:42,863 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:37:42,863 INFO L87 Difference]: Start difference. First operand 1785 states and 2645 transitions. cyclomatic complexity: 861 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:42,893 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:37:42,893 INFO L93 Difference]: Finished difference Result 1785 states and 2644 transitions. [2022-12-13 15:37:42,893 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2644 transitions. [2022-12-13 15:37:42,900 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-12-13 15:37:42,904 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2644 transitions. [2022-12-13 15:37:42,904 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2022-12-13 15:37:42,905 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2022-12-13 15:37:42,905 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2644 transitions. [2022-12-13 15:37:42,907 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:37:42,907 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2644 transitions. [2022-12-13 15:37:42,909 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2644 transitions. [2022-12-13 15:37:42,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2022-12-13 15:37:42,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.481232492997199) internal successors, (2644), 1784 states have internal predecessors, (2644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:42,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2644 transitions. [2022-12-13 15:37:42,926 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2644 transitions. [2022-12-13 15:37:42,927 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:37:42,927 INFO L428 stractBuchiCegarLoop]: Abstraction has 1785 states and 2644 transitions. [2022-12-13 15:37:42,928 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 15:37:42,928 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2644 transitions. [2022-12-13 15:37:42,938 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-12-13 15:37:42,939 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:37:42,939 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:37:42,941 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:42,941 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:42,942 INFO L748 eck$LassoCheckResult]: Stem: 10994#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 10995#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 11912#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11913#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11064#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 11065#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10969#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10970#L851-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 12236#L856-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 11596#L861-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11597#L866-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11494#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11495#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11994#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11995#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 11257#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 11258#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 11682#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11683#L1194 assume !(0 == ~M_E~0); 11834#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11835#L1199-1 assume !(0 == ~T2_E~0); 12117#L1204-1 assume !(0 == ~T3_E~0); 12043#L1209-1 assume !(0 == ~T4_E~0); 12044#L1214-1 assume !(0 == ~T5_E~0); 12438#L1219-1 assume !(0 == ~T6_E~0); 12525#L1224-1 assume !(0 == ~T7_E~0); 11330#L1229-1 assume !(0 == ~T8_E~0); 10887#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10888#L1239-1 assume !(0 == ~T10_E~0); 10932#L1244-1 assume !(0 == ~T11_E~0); 10933#L1249-1 assume !(0 == ~T12_E~0); 11626#L1254-1 assume !(0 == ~E_M~0); 10829#L1259-1 assume !(0 == ~E_1~0); 10794#L1264-1 assume !(0 == ~E_2~0); 10795#L1269-1 assume !(0 == ~E_3~0); 12527#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 12470#L1279-1 assume !(0 == ~E_5~0); 11005#L1284-1 assume !(0 == ~E_6~0); 11006#L1289-1 assume !(0 == ~E_7~0); 11689#L1294-1 assume !(0 == ~E_8~0); 11690#L1299-1 assume !(0 == ~E_9~0); 11701#L1304-1 assume !(0 == ~E_10~0); 12518#L1309-1 assume !(0 == ~E_11~0); 12523#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 10962#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10884#L586 assume 1 == ~m_pc~0; 10885#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10954#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11761#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11163#L1485 assume !(0 != activate_threads_~tmp~1#1); 11164#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12242#L605 assume !(1 == ~t1_pc~0); 11775#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11521#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11522#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12155#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12091#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11431#L624 assume 1 == ~t2_pc~0; 10936#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10937#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11187#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11188#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 12274#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12153#L643 assume !(1 == ~t3_pc~0); 12013#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 11719#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11720#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11264#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 11265#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11026#L662 assume 1 == ~t4_pc~0; 11027#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10985#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10846#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10847#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 10873#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10874#L681 assume !(1 == ~t5_pc~0); 10744#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 10745#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11801#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12399#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 11276#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11277#L700 assume 1 == ~t6_pc~0; 11974#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11018#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11019#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11066#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 11067#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12328#L719 assume 1 == ~t7_pc~0; 12408#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11233#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12515#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12456#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 10758#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10759#L738 assume !(1 == ~t8_pc~0); 12124#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12034#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12035#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11830#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11831#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12175#L757 assume 1 == ~t9_pc~0; 12176#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10753#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10754#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11231#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 11793#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11794#L776 assume !(1 == ~t10_pc~0); 10778#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 10777#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11167#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11007#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 11008#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10963#L795 assume 1 == ~t11_pc~0; 10964#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11296#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12256#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12426#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 12007#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11997#L814 assume !(1 == ~t12_pc~0); 11860#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 11861#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10807#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 10808#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 11215#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11216#L1332 assume !(1 == ~M_E~0); 12287#L1332-2 assume !(1 == ~T1_E~0); 12488#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11929#L1342-1 assume !(1 == ~T3_E~0); 11930#L1347-1 assume !(1 == ~T4_E~0); 12315#L1352-1 assume !(1 == ~T5_E~0); 12181#L1357-1 assume !(1 == ~T6_E~0); 11492#L1362-1 assume !(1 == ~T7_E~0); 11493#L1367-1 assume !(1 == ~T8_E~0); 11102#L1372-1 assume !(1 == ~T9_E~0); 11103#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11405#L1382-1 assume !(1 == ~T11_E~0); 11406#L1387-1 assume !(1 == ~T12_E~0); 12089#L1392-1 assume !(1 == ~E_M~0); 11432#L1397-1 assume !(1 == ~E_1~0); 11433#L1402-1 assume !(1 == ~E_2~0); 11117#L1407-1 assume !(1 == ~E_3~0); 11118#L1412-1 assume !(1 == ~E_4~0); 12254#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 12255#L1422-1 assume !(1 == ~E_6~0); 12490#L1427-1 assume !(1 == ~E_7~0); 11297#L1432-1 assume !(1 == ~E_8~0); 11298#L1437-1 assume !(1 == ~E_9~0); 12207#L1442-1 assume !(1 == ~E_10~0); 12208#L1447-1 assume !(1 == ~E_11~0); 12081#L1452-1 assume !(1 == ~E_12~0); 10904#L1457-1 assume { :end_inline_reset_delta_events } true; 10905#L1803-2 [2022-12-13 15:37:42,942 INFO L750 eck$LassoCheckResult]: Loop: 10905#L1803-2 assume !false; 11239#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10775#L1169 assume !false; 11360#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11474#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10971#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 10972#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12295#L996 assume !(0 != eval_~tmp~0#1); 11679#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11349#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11350#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11836#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11073#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11074#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11326#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10767#L1214-3 assume !(0 == ~T5_E~0); 10768#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11519#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11520#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11554#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10942#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 10943#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 11373#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 11953#L1254-3 assume !(0 == ~E_M~0); 12432#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12064#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10948#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10949#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12467#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11517#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11518#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11500#L1294-3 assume !(0 == ~E_8~0); 11501#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11885#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 11886#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 11407#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 11408#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11413#L586-42 assume !(1 == ~m_pc~0); 11414#L586-44 is_master_triggered_~__retres1~0#1 := 0; 11016#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11017#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11475#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 11547#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11548#L605-42 assume 1 == ~t1_pc~0; 12129#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11853#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11854#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11549#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11550#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11558#L624-42 assume !(1 == ~t2_pc~0); 11559#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 11699#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11791#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11792#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11371#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11372#L643-42 assume 1 == ~t3_pc~0; 11723#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11680#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11681#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11515#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11516#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12217#L662-42 assume !(1 == ~t4_pc~0); 12419#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 11037#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11038#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12196#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12460#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12427#L681-42 assume !(1 == ~t5_pc~0); 10900#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 10901#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11878#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11879#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12263#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11391#L700-42 assume 1 == ~t6_pc~0; 11392#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11203#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11129#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11130#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12270#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12477#L719-42 assume !(1 == ~t7_pc~0); 11090#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 11091#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11461#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11718#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 11476#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11477#L738-42 assume 1 == ~t8_pc~0; 11669#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11422#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11423#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10946#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10947#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11470#L757-42 assume 1 == ~t9_pc~0; 11806#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11131#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11132#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11865#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11244#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11245#L776-42 assume !(1 == ~t10_pc~0); 12188#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 12189#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12008#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12009#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12513#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12031#L795-42 assume !(1 == ~t11_pc~0); 12032#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 11085#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 11086#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11182#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11183#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11486#L814-42 assume 1 == ~t12_pc~0; 12245#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 10996#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10997#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 10802#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 10803#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10958#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10959#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10934#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10935#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11750#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11917#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11918#L1357-3 assume !(1 == ~T6_E~0); 12348#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12521#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12517#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10785#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 10786#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 11388#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 11389#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12213#L1397-3 assume !(1 == ~E_1~0); 12487#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11867#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11042#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11043#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11770#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11771#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12346#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12110#L1437-3 assume !(1 == ~E_9~0); 11887#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 11888#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 10836#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 10837#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11449#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11294#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11116#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 11034#L1822 assume !(0 == start_simulation_~tmp~3#1); 11035#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11983#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11291#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 10787#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 10788#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11939#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12037#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 12373#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 10905#L1803-2 [2022-12-13 15:37:42,943 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:42,943 INFO L85 PathProgramCache]: Analyzing trace with hash -833138770, now seen corresponding path program 1 times [2022-12-13 15:37:42,943 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:42,943 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [639331346] [2022-12-13 15:37:42,943 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:42,944 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:42,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:42,988 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:42,988 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:42,989 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [639331346] [2022-12-13 15:37:42,989 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [639331346] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:42,989 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:42,989 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:42,989 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1013846086] [2022-12-13 15:37:42,989 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:42,990 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:37:42,990 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:42,990 INFO L85 PathProgramCache]: Analyzing trace with hash -683464522, now seen corresponding path program 1 times [2022-12-13 15:37:42,990 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:42,991 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [494011108] [2022-12-13 15:37:42,991 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:42,991 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:43,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:43,041 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:43,041 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:43,041 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [494011108] [2022-12-13 15:37:43,041 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [494011108] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:43,041 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:43,041 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:43,042 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [184846763] [2022-12-13 15:37:43,042 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:43,042 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:37:43,042 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:37:43,043 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:37:43,043 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:37:43,043 INFO L87 Difference]: Start difference. First operand 1785 states and 2644 transitions. cyclomatic complexity: 860 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:43,071 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:37:43,071 INFO L93 Difference]: Finished difference Result 1785 states and 2643 transitions. [2022-12-13 15:37:43,071 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2643 transitions. [2022-12-13 15:37:43,077 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-12-13 15:37:43,082 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2643 transitions. [2022-12-13 15:37:43,082 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2022-12-13 15:37:43,083 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2022-12-13 15:37:43,083 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2643 transitions. [2022-12-13 15:37:43,085 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:37:43,085 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2643 transitions. [2022-12-13 15:37:43,087 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2643 transitions. [2022-12-13 15:37:43,100 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2022-12-13 15:37:43,103 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.480672268907563) internal successors, (2643), 1784 states have internal predecessors, (2643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:43,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2643 transitions. [2022-12-13 15:37:43,106 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2643 transitions. [2022-12-13 15:37:43,106 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:37:43,107 INFO L428 stractBuchiCegarLoop]: Abstraction has 1785 states and 2643 transitions. [2022-12-13 15:37:43,107 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 15:37:43,107 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2643 transitions. [2022-12-13 15:37:43,117 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-12-13 15:37:43,117 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:37:43,117 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:37:43,118 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:43,118 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:43,118 INFO L748 eck$LassoCheckResult]: Stem: 14571#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 14572#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 15489#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15490#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14641#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 14642#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14546#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14547#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15813#L856-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 15173#L861-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 15174#L866-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 15071#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 15072#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15571#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15572#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 14834#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 14835#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 15259#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15260#L1194 assume !(0 == ~M_E~0); 15411#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15412#L1199-1 assume !(0 == ~T2_E~0); 15694#L1204-1 assume !(0 == ~T3_E~0); 15620#L1209-1 assume !(0 == ~T4_E~0); 15621#L1214-1 assume !(0 == ~T5_E~0); 16015#L1219-1 assume !(0 == ~T6_E~0); 16102#L1224-1 assume !(0 == ~T7_E~0); 14907#L1229-1 assume !(0 == ~T8_E~0); 14464#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14465#L1239-1 assume !(0 == ~T10_E~0); 14509#L1244-1 assume !(0 == ~T11_E~0); 14510#L1249-1 assume !(0 == ~T12_E~0); 15203#L1254-1 assume !(0 == ~E_M~0); 14406#L1259-1 assume !(0 == ~E_1~0); 14371#L1264-1 assume !(0 == ~E_2~0); 14372#L1269-1 assume !(0 == ~E_3~0); 16104#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 16047#L1279-1 assume !(0 == ~E_5~0); 14582#L1284-1 assume !(0 == ~E_6~0); 14583#L1289-1 assume !(0 == ~E_7~0); 15266#L1294-1 assume !(0 == ~E_8~0); 15267#L1299-1 assume !(0 == ~E_9~0); 15278#L1304-1 assume !(0 == ~E_10~0); 16095#L1309-1 assume !(0 == ~E_11~0); 16100#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 14539#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14461#L586 assume 1 == ~m_pc~0; 14462#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14531#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15338#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14740#L1485 assume !(0 != activate_threads_~tmp~1#1); 14741#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15819#L605 assume !(1 == ~t1_pc~0); 15352#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15098#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15099#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15732#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15668#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15008#L624 assume 1 == ~t2_pc~0; 14513#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14514#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14764#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14765#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 15851#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15730#L643 assume !(1 == ~t3_pc~0); 15590#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15296#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15297#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14841#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 14842#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14603#L662 assume 1 == ~t4_pc~0; 14604#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14562#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14423#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14424#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 14450#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14451#L681 assume !(1 == ~t5_pc~0); 14321#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 14322#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15378#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15976#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 14853#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14854#L700 assume 1 == ~t6_pc~0; 15551#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14595#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14596#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14643#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 14644#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15905#L719 assume 1 == ~t7_pc~0; 15985#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14810#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16092#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16033#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 14335#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14336#L738 assume !(1 == ~t8_pc~0); 15701#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 15611#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15612#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15407#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15408#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15752#L757 assume 1 == ~t9_pc~0; 15753#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14330#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14331#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14808#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 15370#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15371#L776 assume !(1 == ~t10_pc~0); 14355#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 14354#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14744#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14584#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 14585#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14540#L795 assume 1 == ~t11_pc~0; 14541#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14873#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15833#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16003#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 15584#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15574#L814 assume !(1 == ~t12_pc~0); 15437#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 15438#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14384#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14385#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 14792#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14793#L1332 assume !(1 == ~M_E~0); 15864#L1332-2 assume !(1 == ~T1_E~0); 16065#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15506#L1342-1 assume !(1 == ~T3_E~0); 15507#L1347-1 assume !(1 == ~T4_E~0); 15892#L1352-1 assume !(1 == ~T5_E~0); 15758#L1357-1 assume !(1 == ~T6_E~0); 15069#L1362-1 assume !(1 == ~T7_E~0); 15070#L1367-1 assume !(1 == ~T8_E~0); 14679#L1372-1 assume !(1 == ~T9_E~0); 14680#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14982#L1382-1 assume !(1 == ~T11_E~0); 14983#L1387-1 assume !(1 == ~T12_E~0); 15666#L1392-1 assume !(1 == ~E_M~0); 15009#L1397-1 assume !(1 == ~E_1~0); 15010#L1402-1 assume !(1 == ~E_2~0); 14694#L1407-1 assume !(1 == ~E_3~0); 14695#L1412-1 assume !(1 == ~E_4~0); 15831#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 15832#L1422-1 assume !(1 == ~E_6~0); 16067#L1427-1 assume !(1 == ~E_7~0); 14874#L1432-1 assume !(1 == ~E_8~0); 14875#L1437-1 assume !(1 == ~E_9~0); 15784#L1442-1 assume !(1 == ~E_10~0); 15785#L1447-1 assume !(1 == ~E_11~0); 15658#L1452-1 assume !(1 == ~E_12~0); 14481#L1457-1 assume { :end_inline_reset_delta_events } true; 14482#L1803-2 [2022-12-13 15:37:43,119 INFO L750 eck$LassoCheckResult]: Loop: 14482#L1803-2 assume !false; 14816#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14352#L1169 assume !false; 14937#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15051#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14548#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14549#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 15872#L996 assume !(0 != eval_~tmp~0#1); 15256#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14926#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14927#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15413#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14650#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14651#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14903#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14344#L1214-3 assume !(0 == ~T5_E~0); 14345#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15096#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15097#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15131#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14519#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 14520#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 14950#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 15530#L1254-3 assume !(0 == ~E_M~0); 16009#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15641#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14525#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14526#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16044#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15094#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15095#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15077#L1294-3 assume !(0 == ~E_8~0); 15078#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15462#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15463#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14984#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 14985#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14990#L586-42 assume 1 == ~m_pc~0; 14992#L587-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14593#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14594#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15052#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 15124#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15125#L605-42 assume 1 == ~t1_pc~0; 15706#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15430#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15431#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15126#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15127#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15135#L624-42 assume !(1 == ~t2_pc~0); 15136#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 15276#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15368#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15369#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14948#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14949#L643-42 assume 1 == ~t3_pc~0; 15300#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15257#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15258#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15092#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15093#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15794#L662-42 assume !(1 == ~t4_pc~0); 15996#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 14614#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14615#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15773#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16037#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16004#L681-42 assume !(1 == ~t5_pc~0); 14477#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 14478#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15455#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15456#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15840#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14968#L700-42 assume 1 == ~t6_pc~0; 14969#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14780#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14706#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14707#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15847#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16054#L719-42 assume 1 == ~t7_pc~0; 15568#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14668#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15038#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15295#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 15053#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15054#L738-42 assume 1 == ~t8_pc~0; 15246#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14999#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15000#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14523#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14524#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15047#L757-42 assume 1 == ~t9_pc~0; 15383#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14708#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14709#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15442#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14821#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14822#L776-42 assume !(1 == ~t10_pc~0); 15765#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 15766#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15585#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 15586#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16090#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15608#L795-42 assume !(1 == ~t11_pc~0); 15609#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 14662#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14663#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 14759#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14760#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15063#L814-42 assume !(1 == ~t12_pc~0); 14932#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 14573#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14574#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14379#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 14380#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14535#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14536#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14511#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14512#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15327#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15494#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15495#L1357-3 assume !(1 == ~T6_E~0); 15925#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16098#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16094#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14362#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14363#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 14965#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 14966#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15790#L1397-3 assume !(1 == ~E_1~0); 16064#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15444#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14619#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14620#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15347#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15348#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15923#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15687#L1437-3 assume !(1 == ~E_9~0); 15464#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15465#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 14413#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 14414#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15026#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14871#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14693#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 14611#L1822 assume !(0 == start_simulation_~tmp~3#1); 14612#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15560#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14868#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14364#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 14365#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15516#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15614#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 15950#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 14482#L1803-2 [2022-12-13 15:37:43,119 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:43,119 INFO L85 PathProgramCache]: Analyzing trace with hash -1259693268, now seen corresponding path program 1 times [2022-12-13 15:37:43,119 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:43,119 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1565835908] [2022-12-13 15:37:43,119 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:43,120 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:43,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:43,158 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:43,159 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:43,159 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1565835908] [2022-12-13 15:37:43,159 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1565835908] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:43,159 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:43,159 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:43,159 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1890308375] [2022-12-13 15:37:43,160 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:43,160 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:37:43,160 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:43,161 INFO L85 PathProgramCache]: Analyzing trace with hash -1115553867, now seen corresponding path program 1 times [2022-12-13 15:37:43,161 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:43,161 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [360303487] [2022-12-13 15:37:43,161 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:43,161 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:43,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:43,207 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:43,207 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:43,207 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [360303487] [2022-12-13 15:37:43,207 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [360303487] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:43,207 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:43,208 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:43,208 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [115628994] [2022-12-13 15:37:43,208 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:43,208 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:37:43,208 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:37:43,209 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:37:43,209 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:37:43,209 INFO L87 Difference]: Start difference. First operand 1785 states and 2643 transitions. cyclomatic complexity: 859 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:43,250 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:37:43,251 INFO L93 Difference]: Finished difference Result 1785 states and 2642 transitions. [2022-12-13 15:37:43,251 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2642 transitions. [2022-12-13 15:37:43,263 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-12-13 15:37:43,277 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2642 transitions. [2022-12-13 15:37:43,277 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2022-12-13 15:37:43,279 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2022-12-13 15:37:43,279 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2642 transitions. [2022-12-13 15:37:43,283 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:37:43,283 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2642 transitions. [2022-12-13 15:37:43,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2642 transitions. [2022-12-13 15:37:43,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2022-12-13 15:37:43,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4801120448179272) internal successors, (2642), 1784 states have internal predecessors, (2642), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:43,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2642 transitions. [2022-12-13 15:37:43,303 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2642 transitions. [2022-12-13 15:37:43,303 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:37:43,303 INFO L428 stractBuchiCegarLoop]: Abstraction has 1785 states and 2642 transitions. [2022-12-13 15:37:43,303 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 15:37:43,304 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2642 transitions. [2022-12-13 15:37:43,308 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-12-13 15:37:43,308 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:37:43,308 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:37:43,310 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:43,310 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:43,310 INFO L748 eck$LassoCheckResult]: Stem: 18150#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 18151#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 19067#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19068#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18218#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 18219#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18123#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18124#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19390#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18750#L861-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 18751#L866-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 18648#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 18649#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19148#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19149#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18411#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 18412#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 18838#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18839#L1194 assume !(0 == ~M_E~0); 18988#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18989#L1199-1 assume !(0 == ~T2_E~0); 19271#L1204-1 assume !(0 == ~T3_E~0); 19197#L1209-1 assume !(0 == ~T4_E~0); 19198#L1214-1 assume !(0 == ~T5_E~0); 19592#L1219-1 assume !(0 == ~T6_E~0); 19679#L1224-1 assume !(0 == ~T7_E~0); 18486#L1229-1 assume !(0 == ~T8_E~0); 18049#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18050#L1239-1 assume !(0 == ~T10_E~0); 18088#L1244-1 assume !(0 == ~T11_E~0); 18089#L1249-1 assume !(0 == ~T12_E~0); 18780#L1254-1 assume !(0 == ~E_M~0); 17983#L1259-1 assume !(0 == ~E_1~0); 17948#L1264-1 assume !(0 == ~E_2~0); 17949#L1269-1 assume !(0 == ~E_3~0); 19681#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 19624#L1279-1 assume !(0 == ~E_5~0); 18159#L1284-1 assume !(0 == ~E_6~0); 18160#L1289-1 assume !(0 == ~E_7~0); 18845#L1294-1 assume !(0 == ~E_8~0); 18846#L1299-1 assume !(0 == ~E_9~0); 18857#L1304-1 assume !(0 == ~E_10~0); 19672#L1309-1 assume !(0 == ~E_11~0); 19677#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 18117#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18038#L586 assume 1 == ~m_pc~0; 18039#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18108#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18915#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18317#L1485 assume !(0 != activate_threads_~tmp~1#1); 18318#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19396#L605 assume !(1 == ~t1_pc~0); 18929#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 18675#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18676#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19309#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19246#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18585#L624 assume 1 == ~t2_pc~0; 18093#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18094#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18341#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18342#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 19428#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19307#L643 assume !(1 == ~t3_pc~0); 19167#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 18879#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18880#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18418#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 18419#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18180#L662 assume 1 == ~t4_pc~0; 18181#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18139#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18003#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18004#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 18029#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18030#L681 assume !(1 == ~t5_pc~0); 17898#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 17899#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18955#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19553#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 18430#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18431#L700 assume 1 == ~t6_pc~0; 19128#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18172#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18173#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18220#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 18221#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19482#L719 assume 1 == ~t7_pc~0; 19565#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18387#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19669#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19610#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 17912#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17913#L738 assume !(1 == ~t8_pc~0); 19278#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19188#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19189#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18984#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18985#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19329#L757 assume 1 == ~t9_pc~0; 19330#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17907#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17908#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18385#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 18947#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18948#L776 assume !(1 == ~t10_pc~0); 17932#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 17931#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18324#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18161#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 18162#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18118#L795 assume 1 == ~t11_pc~0; 18119#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18452#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 19410#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19581#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 19161#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19151#L814 assume !(1 == ~t12_pc~0); 19014#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 19015#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 17964#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17965#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 18369#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18370#L1332 assume !(1 == ~M_E~0); 19441#L1332-2 assume !(1 == ~T1_E~0); 19643#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19085#L1342-1 assume !(1 == ~T3_E~0); 19086#L1347-1 assume !(1 == ~T4_E~0); 19470#L1352-1 assume !(1 == ~T5_E~0); 19335#L1357-1 assume !(1 == ~T6_E~0); 18646#L1362-1 assume !(1 == ~T7_E~0); 18647#L1367-1 assume !(1 == ~T8_E~0); 18258#L1372-1 assume !(1 == ~T9_E~0); 18259#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18559#L1382-1 assume !(1 == ~T11_E~0); 18560#L1387-1 assume !(1 == ~T12_E~0); 19243#L1392-1 assume !(1 == ~E_M~0); 18586#L1397-1 assume !(1 == ~E_1~0); 18587#L1402-1 assume !(1 == ~E_2~0); 18273#L1407-1 assume !(1 == ~E_3~0); 18274#L1412-1 assume !(1 == ~E_4~0); 19408#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 19409#L1422-1 assume !(1 == ~E_6~0); 19644#L1427-1 assume !(1 == ~E_7~0); 18453#L1432-1 assume !(1 == ~E_8~0); 18454#L1437-1 assume !(1 == ~E_9~0); 19361#L1442-1 assume !(1 == ~E_10~0); 19362#L1447-1 assume !(1 == ~E_11~0); 19235#L1452-1 assume !(1 == ~E_12~0); 18058#L1457-1 assume { :end_inline_reset_delta_events } true; 18059#L1803-2 [2022-12-13 15:37:43,310 INFO L750 eck$LassoCheckResult]: Loop: 18059#L1803-2 assume !false; 18393#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17929#L1169 assume !false; 18516#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18628#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18125#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18126#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 19449#L996 assume !(0 != eval_~tmp~0#1); 18835#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18506#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18507#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18990#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18227#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18228#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18480#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17925#L1214-3 assume !(0 == ~T5_E~0); 17926#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18673#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18674#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18708#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18096#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 18097#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 18527#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 19107#L1254-3 assume !(0 == ~E_M~0); 19586#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19218#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18102#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18103#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19621#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18671#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18672#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18654#L1294-3 assume !(0 == ~E_8~0); 18655#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19039#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19040#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18561#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 18562#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18567#L586-42 assume !(1 == ~m_pc~0); 18568#L586-44 is_master_triggered_~__retres1~0#1 := 0; 18170#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18171#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18629#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 18701#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18702#L605-42 assume 1 == ~t1_pc~0; 19283#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19007#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19008#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18703#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18704#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18712#L624-42 assume !(1 == ~t2_pc~0); 18713#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 18853#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18945#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18946#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18525#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18526#L643-42 assume 1 == ~t3_pc~0; 18875#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18833#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18834#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18669#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18670#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19371#L662-42 assume !(1 == ~t4_pc~0); 19573#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 18191#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18192#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19350#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19614#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19580#L681-42 assume !(1 == ~t5_pc~0); 18054#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 18055#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19032#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19033#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19417#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18545#L700-42 assume 1 == ~t6_pc~0; 18546#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18357#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18283#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18284#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19424#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19631#L719-42 assume !(1 == ~t7_pc~0); 18244#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 18245#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18615#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18872#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 18630#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18631#L738-42 assume 1 == ~t8_pc~0; 18823#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18576#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18577#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18100#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18101#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18624#L757-42 assume 1 == ~t9_pc~0; 18960#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18285#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18286#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19019#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18397#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18398#L776-42 assume !(1 == ~t10_pc~0); 19342#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 19343#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19162#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19163#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19667#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19185#L795-42 assume !(1 == ~t11_pc~0); 19186#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 18239#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18240#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18336#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18337#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 18640#L814-42 assume 1 == ~t12_pc~0; 19399#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 18148#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18149#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17956#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17957#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18112#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18113#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18086#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18087#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18904#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19071#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19072#L1357-3 assume !(1 == ~T6_E~0); 19502#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19675#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19671#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17939#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17940#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18542#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18543#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19367#L1397-3 assume !(1 == ~E_1~0); 19641#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19021#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18196#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18197#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18924#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18925#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19500#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19264#L1437-3 assume !(1 == ~E_9~0); 19041#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 19042#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 17990#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 17991#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18603#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18448#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18270#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 18188#L1822 assume !(0 == start_simulation_~tmp~3#1); 18189#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 19137#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18445#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 17941#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 17942#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19093#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19191#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 19526#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 18059#L1803-2 [2022-12-13 15:37:43,311 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:43,311 INFO L85 PathProgramCache]: Analyzing trace with hash -719263762, now seen corresponding path program 1 times [2022-12-13 15:37:43,311 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:43,311 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1591721304] [2022-12-13 15:37:43,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:43,311 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:43,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:43,350 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:43,350 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:43,350 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1591721304] [2022-12-13 15:37:43,350 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1591721304] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:43,350 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:43,350 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:43,351 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1052588884] [2022-12-13 15:37:43,351 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:43,351 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:37:43,351 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:43,351 INFO L85 PathProgramCache]: Analyzing trace with hash -683464522, now seen corresponding path program 2 times [2022-12-13 15:37:43,351 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:43,351 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [225704495] [2022-12-13 15:37:43,352 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:43,352 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:43,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:43,394 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:43,394 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:43,394 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [225704495] [2022-12-13 15:37:43,395 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [225704495] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:43,395 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:43,395 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:43,395 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [652237181] [2022-12-13 15:37:43,395 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:43,395 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:37:43,395 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:37:43,396 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:37:43,396 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:37:43,396 INFO L87 Difference]: Start difference. First operand 1785 states and 2642 transitions. cyclomatic complexity: 858 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:43,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:37:43,419 INFO L93 Difference]: Finished difference Result 1785 states and 2641 transitions. [2022-12-13 15:37:43,419 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2641 transitions. [2022-12-13 15:37:43,425 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-12-13 15:37:43,429 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2641 transitions. [2022-12-13 15:37:43,429 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2022-12-13 15:37:43,430 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2022-12-13 15:37:43,430 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2641 transitions. [2022-12-13 15:37:43,432 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:37:43,432 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2641 transitions. [2022-12-13 15:37:43,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2641 transitions. [2022-12-13 15:37:43,446 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2022-12-13 15:37:43,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4795518207282914) internal successors, (2641), 1784 states have internal predecessors, (2641), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:43,451 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2641 transitions. [2022-12-13 15:37:43,451 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2641 transitions. [2022-12-13 15:37:43,451 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:37:43,452 INFO L428 stractBuchiCegarLoop]: Abstraction has 1785 states and 2641 transitions. [2022-12-13 15:37:43,452 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 15:37:43,452 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2641 transitions. [2022-12-13 15:37:43,456 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-12-13 15:37:43,456 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:37:43,456 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:37:43,458 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:43,458 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:43,458 INFO L748 eck$LassoCheckResult]: Stem: 21727#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 21728#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 22643#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22644#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21795#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 21796#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21700#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21701#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22967#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22327#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22328#L866-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 22225#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 22226#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 22725#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22726#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21988#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21989#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 22415#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22416#L1194 assume !(0 == ~M_E~0); 22565#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22566#L1199-1 assume !(0 == ~T2_E~0); 22848#L1204-1 assume !(0 == ~T3_E~0); 22774#L1209-1 assume !(0 == ~T4_E~0); 22775#L1214-1 assume !(0 == ~T5_E~0); 23169#L1219-1 assume !(0 == ~T6_E~0); 23256#L1224-1 assume !(0 == ~T7_E~0); 22061#L1229-1 assume !(0 == ~T8_E~0); 21626#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21627#L1239-1 assume !(0 == ~T10_E~0); 21665#L1244-1 assume !(0 == ~T11_E~0); 21666#L1249-1 assume !(0 == ~T12_E~0); 22357#L1254-1 assume !(0 == ~E_M~0); 21560#L1259-1 assume !(0 == ~E_1~0); 21525#L1264-1 assume !(0 == ~E_2~0); 21526#L1269-1 assume !(0 == ~E_3~0); 23258#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 23201#L1279-1 assume !(0 == ~E_5~0); 21736#L1284-1 assume !(0 == ~E_6~0); 21737#L1289-1 assume !(0 == ~E_7~0); 22420#L1294-1 assume !(0 == ~E_8~0); 22421#L1299-1 assume !(0 == ~E_9~0); 22434#L1304-1 assume !(0 == ~E_10~0); 23249#L1309-1 assume !(0 == ~E_11~0); 23254#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 21694#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21615#L586 assume 1 == ~m_pc~0; 21616#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21685#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22492#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21894#L1485 assume !(0 != activate_threads_~tmp~1#1); 21895#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22973#L605 assume !(1 == ~t1_pc~0); 22506#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22252#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22253#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22886#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22823#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22162#L624 assume 1 == ~t2_pc~0; 21670#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21671#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21918#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21919#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 23005#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22884#L643 assume !(1 == ~t3_pc~0); 22744#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22456#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22457#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21995#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 21996#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21757#L662 assume 1 == ~t4_pc~0; 21758#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21716#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21577#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21578#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 21606#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21607#L681 assume !(1 == ~t5_pc~0); 21475#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21476#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22532#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23130#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 22007#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22008#L700 assume 1 == ~t6_pc~0; 22705#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21749#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21750#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21797#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 21798#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23059#L719 assume 1 == ~t7_pc~0; 23139#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21964#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23246#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23187#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 21489#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21490#L738 assume !(1 == ~t8_pc~0); 22855#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22765#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22766#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22561#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22562#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22906#L757 assume 1 == ~t9_pc~0; 22907#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21484#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21485#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21962#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 22524#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22525#L776 assume !(1 == ~t10_pc~0); 21509#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 21508#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21898#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21738#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 21739#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21695#L795 assume 1 == ~t11_pc~0; 21696#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 22027#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22987#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23158#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 22738#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22728#L814 assume !(1 == ~t12_pc~0); 22591#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 22592#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21538#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21539#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 21946#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21947#L1332 assume !(1 == ~M_E~0); 23018#L1332-2 assume !(1 == ~T1_E~0); 23220#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22660#L1342-1 assume !(1 == ~T3_E~0); 22661#L1347-1 assume !(1 == ~T4_E~0); 23046#L1352-1 assume !(1 == ~T5_E~0); 22912#L1357-1 assume !(1 == ~T6_E~0); 22223#L1362-1 assume !(1 == ~T7_E~0); 22224#L1367-1 assume !(1 == ~T8_E~0); 21835#L1372-1 assume !(1 == ~T9_E~0); 21836#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22136#L1382-1 assume !(1 == ~T11_E~0); 22137#L1387-1 assume !(1 == ~T12_E~0); 22820#L1392-1 assume !(1 == ~E_M~0); 22163#L1397-1 assume !(1 == ~E_1~0); 22164#L1402-1 assume !(1 == ~E_2~0); 21850#L1407-1 assume !(1 == ~E_3~0); 21851#L1412-1 assume !(1 == ~E_4~0); 22985#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 22986#L1422-1 assume !(1 == ~E_6~0); 23221#L1427-1 assume !(1 == ~E_7~0); 22028#L1432-1 assume !(1 == ~E_8~0); 22029#L1437-1 assume !(1 == ~E_9~0); 22938#L1442-1 assume !(1 == ~E_10~0); 22939#L1447-1 assume !(1 == ~E_11~0); 22812#L1452-1 assume !(1 == ~E_12~0); 21635#L1457-1 assume { :end_inline_reset_delta_events } true; 21636#L1803-2 [2022-12-13 15:37:43,458 INFO L750 eck$LassoCheckResult]: Loop: 21636#L1803-2 assume !false; 21970#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21506#L1169 assume !false; 22093#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22205#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21702#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21703#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 23026#L996 assume !(0 != eval_~tmp~0#1); 22412#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22083#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22084#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22567#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21804#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21805#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22057#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21502#L1214-3 assume !(0 == ~T5_E~0); 21503#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22250#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22251#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22288#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21673#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21674#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 22104#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 22684#L1254-3 assume !(0 == ~E_M~0); 23163#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22795#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21679#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21680#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23198#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22248#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22249#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22231#L1294-3 assume !(0 == ~E_8~0); 22232#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22616#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 22617#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22138#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 22139#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22144#L586-42 assume !(1 == ~m_pc~0); 22145#L586-44 is_master_triggered_~__retres1~0#1 := 0; 21747#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21748#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22208#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 22278#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22279#L605-42 assume 1 == ~t1_pc~0; 22861#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22586#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22587#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22283#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22284#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22285#L624-42 assume !(1 == ~t2_pc~0); 22286#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 22427#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22522#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22523#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22100#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22101#L643-42 assume 1 == ~t3_pc~0; 22452#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22410#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22411#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22246#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22247#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22948#L662-42 assume !(1 == ~t4_pc~0); 23147#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 21768#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21769#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22927#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23191#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23157#L681-42 assume 1 == ~t5_pc~0; 22464#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21632#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22609#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22610#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22994#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22122#L700-42 assume 1 == ~t6_pc~0; 22123#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21934#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21860#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21861#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23001#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23208#L719-42 assume 1 == ~t7_pc~0; 22722#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21822#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22192#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22449#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 22206#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22207#L738-42 assume 1 == ~t8_pc~0; 22400#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22153#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22154#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21677#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21678#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22201#L757-42 assume 1 == ~t9_pc~0; 22534#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21862#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21863#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22596#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21974#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21975#L776-42 assume !(1 == ~t10_pc~0); 22919#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 22920#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22739#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22740#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23244#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22762#L795-42 assume !(1 == ~t11_pc~0); 22763#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 21816#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21817#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21911#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 21912#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22217#L814-42 assume 1 == ~t12_pc~0; 22976#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 21725#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21726#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21533#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 21534#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21689#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21690#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21663#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21664#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22481#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22648#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22649#L1357-3 assume !(1 == ~T6_E~0); 23079#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23252#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 23248#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21516#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21517#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22119#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 22120#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22944#L1397-3 assume !(1 == ~E_1~0); 23218#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22598#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21773#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21774#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22501#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22502#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 23077#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 22840#L1437-3 assume !(1 == ~E_9~0); 22618#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 22619#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21567#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 21568#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22178#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 22025#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21847#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 21765#L1822 assume !(0 == start_simulation_~tmp~3#1); 21766#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22714#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 22019#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21518#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 21519#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22670#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22768#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 23103#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 21636#L1803-2 [2022-12-13 15:37:43,459 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:43,459 INFO L85 PathProgramCache]: Analyzing trace with hash -563283220, now seen corresponding path program 1 times [2022-12-13 15:37:43,459 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:43,459 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1255772285] [2022-12-13 15:37:43,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:43,459 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:43,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:43,496 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:43,496 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:43,496 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1255772285] [2022-12-13 15:37:43,496 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1255772285] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:43,496 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:43,496 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:43,496 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [449809702] [2022-12-13 15:37:43,496 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:43,497 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:37:43,497 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:43,497 INFO L85 PathProgramCache]: Analyzing trace with hash 660676148, now seen corresponding path program 1 times [2022-12-13 15:37:43,497 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:43,497 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [628286090] [2022-12-13 15:37:43,497 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:43,497 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:43,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:43,538 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:43,539 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:43,539 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [628286090] [2022-12-13 15:37:43,539 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [628286090] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:43,539 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:43,539 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:43,539 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1741096458] [2022-12-13 15:37:43,539 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:43,539 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:37:43,540 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:37:43,540 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:37:43,540 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:37:43,540 INFO L87 Difference]: Start difference. First operand 1785 states and 2641 transitions. cyclomatic complexity: 857 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:43,562 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:37:43,562 INFO L93 Difference]: Finished difference Result 1785 states and 2640 transitions. [2022-12-13 15:37:43,562 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2640 transitions. [2022-12-13 15:37:43,567 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-12-13 15:37:43,572 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2640 transitions. [2022-12-13 15:37:43,572 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2022-12-13 15:37:43,573 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2022-12-13 15:37:43,573 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2640 transitions. [2022-12-13 15:37:43,574 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:37:43,574 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2640 transitions. [2022-12-13 15:37:43,576 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2640 transitions. [2022-12-13 15:37:43,589 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2022-12-13 15:37:43,591 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4789915966386555) internal successors, (2640), 1784 states have internal predecessors, (2640), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:43,593 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2640 transitions. [2022-12-13 15:37:43,594 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2640 transitions. [2022-12-13 15:37:43,594 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:37:43,594 INFO L428 stractBuchiCegarLoop]: Abstraction has 1785 states and 2640 transitions. [2022-12-13 15:37:43,594 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 15:37:43,594 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2640 transitions. [2022-12-13 15:37:43,598 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-12-13 15:37:43,598 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:37:43,598 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:37:43,599 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:43,599 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:43,600 INFO L748 eck$LassoCheckResult]: Stem: 25304#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 25305#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 26220#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26221#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25372#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 25373#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25277#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25278#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26544#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25904#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25905#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25802#L871-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 25803#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 26302#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 26303#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25565#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25566#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 25992#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25993#L1194 assume !(0 == ~M_E~0); 26142#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26143#L1199-1 assume !(0 == ~T2_E~0); 26425#L1204-1 assume !(0 == ~T3_E~0); 26351#L1209-1 assume !(0 == ~T4_E~0); 26352#L1214-1 assume !(0 == ~T5_E~0); 26746#L1219-1 assume !(0 == ~T6_E~0); 26833#L1224-1 assume !(0 == ~T7_E~0); 25638#L1229-1 assume !(0 == ~T8_E~0); 25201#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25202#L1239-1 assume !(0 == ~T10_E~0); 25242#L1244-1 assume !(0 == ~T11_E~0); 25243#L1249-1 assume !(0 == ~T12_E~0); 25934#L1254-1 assume !(0 == ~E_M~0); 25137#L1259-1 assume !(0 == ~E_1~0); 25102#L1264-1 assume !(0 == ~E_2~0); 25103#L1269-1 assume !(0 == ~E_3~0); 26835#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 26778#L1279-1 assume !(0 == ~E_5~0); 25313#L1284-1 assume !(0 == ~E_6~0); 25314#L1289-1 assume !(0 == ~E_7~0); 25997#L1294-1 assume !(0 == ~E_8~0); 25998#L1299-1 assume !(0 == ~E_9~0); 26009#L1304-1 assume !(0 == ~E_10~0); 26826#L1309-1 assume !(0 == ~E_11~0); 26831#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 25271#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25192#L586 assume 1 == ~m_pc~0; 25193#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25262#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26069#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25471#L1485 assume !(0 != activate_threads_~tmp~1#1); 25472#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26550#L605 assume !(1 == ~t1_pc~0); 26083#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25829#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25830#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26463#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26400#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25739#L624 assume 1 == ~t2_pc~0; 25247#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25248#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25495#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25496#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 26582#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26461#L643 assume !(1 == ~t3_pc~0); 26321#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26029#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26030#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25572#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 25573#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25334#L662 assume 1 == ~t4_pc~0; 25335#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25293#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25154#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25155#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 25183#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25184#L681 assume !(1 == ~t5_pc~0); 25052#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 25053#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26109#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26707#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 25584#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25585#L700 assume 1 == ~t6_pc~0; 26282#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25326#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25327#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25374#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 25375#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26636#L719 assume 1 == ~t7_pc~0; 26716#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25541#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26823#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26764#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 25066#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25067#L738 assume !(1 == ~t8_pc~0); 26432#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 26342#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26343#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26138#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26139#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26483#L757 assume 1 == ~t9_pc~0; 26484#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25061#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25062#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25539#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 26101#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26102#L776 assume !(1 == ~t10_pc~0); 25086#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25085#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25475#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25315#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 25316#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25272#L795 assume 1 == ~t11_pc~0; 25273#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25604#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26564#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26734#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 26315#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 26305#L814 assume !(1 == ~t12_pc~0); 26168#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 26169#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25115#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25116#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 25523#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25524#L1332 assume !(1 == ~M_E~0); 26595#L1332-2 assume !(1 == ~T1_E~0); 26797#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26237#L1342-1 assume !(1 == ~T3_E~0); 26238#L1347-1 assume !(1 == ~T4_E~0); 26623#L1352-1 assume !(1 == ~T5_E~0); 26489#L1357-1 assume !(1 == ~T6_E~0); 25800#L1362-1 assume !(1 == ~T7_E~0); 25801#L1367-1 assume !(1 == ~T8_E~0); 25410#L1372-1 assume !(1 == ~T9_E~0); 25411#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25713#L1382-1 assume !(1 == ~T11_E~0); 25714#L1387-1 assume !(1 == ~T12_E~0); 26397#L1392-1 assume !(1 == ~E_M~0); 25740#L1397-1 assume !(1 == ~E_1~0); 25741#L1402-1 assume !(1 == ~E_2~0); 25425#L1407-1 assume !(1 == ~E_3~0); 25426#L1412-1 assume !(1 == ~E_4~0); 26562#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 26563#L1422-1 assume !(1 == ~E_6~0); 26798#L1427-1 assume !(1 == ~E_7~0); 25605#L1432-1 assume !(1 == ~E_8~0); 25606#L1437-1 assume !(1 == ~E_9~0); 26515#L1442-1 assume !(1 == ~E_10~0); 26516#L1447-1 assume !(1 == ~E_11~0); 26389#L1452-1 assume !(1 == ~E_12~0); 25212#L1457-1 assume { :end_inline_reset_delta_events } true; 25213#L1803-2 [2022-12-13 15:37:43,600 INFO L750 eck$LassoCheckResult]: Loop: 25213#L1803-2 assume !false; 25547#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25083#L1169 assume !false; 25668#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25782#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25279#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25280#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 26603#L996 assume !(0 != eval_~tmp~0#1); 25987#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25660#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25661#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26144#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25381#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25382#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25634#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25079#L1214-3 assume !(0 == ~T5_E~0); 25080#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25827#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25828#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25862#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25250#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25251#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 25681#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 26261#L1254-3 assume !(0 == ~E_M~0); 26740#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26372#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25256#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25257#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26775#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25825#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25826#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25808#L1294-3 assume !(0 == ~E_8~0); 25809#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26193#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 26194#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25715#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 25716#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25721#L586-42 assume !(1 == ~m_pc~0); 25722#L586-44 is_master_triggered_~__retres1~0#1 := 0; 25324#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25325#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25785#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 25855#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25856#L605-42 assume 1 == ~t1_pc~0; 26438#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 26161#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26162#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25859#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25860#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25866#L624-42 assume !(1 == ~t2_pc~0); 25867#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 26007#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26099#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26100#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25679#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25680#L643-42 assume 1 == ~t3_pc~0; 26033#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25988#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25989#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25823#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25824#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26525#L662-42 assume !(1 == ~t4_pc~0); 26727#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 25345#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25346#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26504#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26768#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26735#L681-42 assume !(1 == ~t5_pc~0); 25208#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 25209#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26186#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26187#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26571#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25699#L700-42 assume 1 == ~t6_pc~0; 25700#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25511#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25437#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25438#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26578#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26785#L719-42 assume !(1 == ~t7_pc~0); 25395#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 25396#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25769#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26026#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 25783#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25784#L738-42 assume 1 == ~t8_pc~0; 25977#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25728#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25729#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25254#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25255#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25776#L757-42 assume !(1 == ~t9_pc~0); 26112#L757-44 is_transmit9_triggered_~__retres1~9#1 := 0; 25439#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25440#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26173#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25551#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25552#L776-42 assume !(1 == ~t10_pc~0); 26496#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 26497#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26316#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26317#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26821#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26339#L795-42 assume !(1 == ~t11_pc~0); 26340#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 25391#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25392#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25488#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25489#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25794#L814-42 assume 1 == ~t12_pc~0; 26553#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 25302#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25303#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25110#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 25111#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25266#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25267#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25240#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25241#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26058#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26223#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26224#L1357-3 assume !(1 == ~T6_E~0); 26655#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26829#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26825#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25093#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25094#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25693#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 25694#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26521#L1397-3 assume !(1 == ~E_1~0); 26795#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26175#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25350#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25351#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26078#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26079#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 26654#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 26417#L1437-3 assume !(1 == ~E_9~0); 26195#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 26196#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 25144#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 25145#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25753#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25602#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25422#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 25342#L1822 assume !(0 == start_simulation_~tmp~3#1); 25343#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26291#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25596#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25095#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 25096#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26247#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26345#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 26679#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 25213#L1803-2 [2022-12-13 15:37:43,600 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:43,600 INFO L85 PathProgramCache]: Analyzing trace with hash -973893586, now seen corresponding path program 1 times [2022-12-13 15:37:43,601 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:43,601 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [925891622] [2022-12-13 15:37:43,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:43,601 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:43,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:43,636 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:43,636 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:43,636 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [925891622] [2022-12-13 15:37:43,636 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [925891622] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:43,636 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:43,636 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:43,637 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1015637046] [2022-12-13 15:37:43,637 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:43,637 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:37:43,637 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:43,637 INFO L85 PathProgramCache]: Analyzing trace with hash -106535881, now seen corresponding path program 1 times [2022-12-13 15:37:43,637 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:43,637 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [411210975] [2022-12-13 15:37:43,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:43,638 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:43,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:43,713 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:43,714 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:43,714 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [411210975] [2022-12-13 15:37:43,714 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [411210975] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:43,714 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:43,714 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:43,714 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [162822117] [2022-12-13 15:37:43,714 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:43,715 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:37:43,715 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:37:43,715 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:37:43,715 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:37:43,715 INFO L87 Difference]: Start difference. First operand 1785 states and 2640 transitions. cyclomatic complexity: 856 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:43,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:37:43,736 INFO L93 Difference]: Finished difference Result 1785 states and 2639 transitions. [2022-12-13 15:37:43,736 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2639 transitions. [2022-12-13 15:37:43,740 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-12-13 15:37:43,745 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2639 transitions. [2022-12-13 15:37:43,745 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2022-12-13 15:37:43,746 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2022-12-13 15:37:43,746 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2639 transitions. [2022-12-13 15:37:43,747 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:37:43,748 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2639 transitions. [2022-12-13 15:37:43,749 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2639 transitions. [2022-12-13 15:37:43,761 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2022-12-13 15:37:43,763 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4784313725490197) internal successors, (2639), 1784 states have internal predecessors, (2639), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:43,766 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2639 transitions. [2022-12-13 15:37:43,766 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2639 transitions. [2022-12-13 15:37:43,766 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:37:43,767 INFO L428 stractBuchiCegarLoop]: Abstraction has 1785 states and 2639 transitions. [2022-12-13 15:37:43,767 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 15:37:43,767 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2639 transitions. [2022-12-13 15:37:43,770 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-12-13 15:37:43,771 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:37:43,771 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:37:43,772 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:43,772 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:43,772 INFO L748 eck$LassoCheckResult]: Stem: 28879#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 28880#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 29797#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29798#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28949#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 28950#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28854#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28855#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30121#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29481#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29482#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29379#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29380#L876-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 29879#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29880#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29142#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29143#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29567#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29568#L1194 assume !(0 == ~M_E~0); 29719#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29720#L1199-1 assume !(0 == ~T2_E~0); 30002#L1204-1 assume !(0 == ~T3_E~0); 29928#L1209-1 assume !(0 == ~T4_E~0); 29929#L1214-1 assume !(0 == ~T5_E~0); 30323#L1219-1 assume !(0 == ~T6_E~0); 30410#L1224-1 assume !(0 == ~T7_E~0); 29215#L1229-1 assume !(0 == ~T8_E~0); 28772#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28773#L1239-1 assume !(0 == ~T10_E~0); 28817#L1244-1 assume !(0 == ~T11_E~0); 28818#L1249-1 assume !(0 == ~T12_E~0); 29511#L1254-1 assume !(0 == ~E_M~0); 28714#L1259-1 assume !(0 == ~E_1~0); 28679#L1264-1 assume !(0 == ~E_2~0); 28680#L1269-1 assume !(0 == ~E_3~0); 30412#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 30355#L1279-1 assume !(0 == ~E_5~0); 28890#L1284-1 assume !(0 == ~E_6~0); 28891#L1289-1 assume !(0 == ~E_7~0); 29574#L1294-1 assume !(0 == ~E_8~0); 29575#L1299-1 assume !(0 == ~E_9~0); 29586#L1304-1 assume !(0 == ~E_10~0); 30403#L1309-1 assume !(0 == ~E_11~0); 30408#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 28847#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28769#L586 assume 1 == ~m_pc~0; 28770#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28839#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29646#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29048#L1485 assume !(0 != activate_threads_~tmp~1#1); 29049#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30127#L605 assume !(1 == ~t1_pc~0); 29660#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29406#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29407#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30040#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29976#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29316#L624 assume 1 == ~t2_pc~0; 28821#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28822#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29072#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29073#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 30159#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30038#L643 assume !(1 == ~t3_pc~0); 29898#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29604#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29605#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29149#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 29150#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28911#L662 assume 1 == ~t4_pc~0; 28912#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28870#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28731#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28732#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 28758#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28759#L681 assume !(1 == ~t5_pc~0); 28629#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 28630#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29686#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30284#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 29161#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29162#L700 assume 1 == ~t6_pc~0; 29859#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28903#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28904#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28951#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 28952#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30213#L719 assume 1 == ~t7_pc~0; 30293#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29118#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30400#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30341#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 28643#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28644#L738 assume !(1 == ~t8_pc~0); 30009#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 29919#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29920#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29715#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29716#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30060#L757 assume 1 == ~t9_pc~0; 30061#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28638#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28639#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29116#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 29678#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29679#L776 assume !(1 == ~t10_pc~0); 28663#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 28662#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29052#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28892#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 28893#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28848#L795 assume 1 == ~t11_pc~0; 28849#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29181#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30141#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30311#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 29892#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29882#L814 assume !(1 == ~t12_pc~0); 29745#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 29746#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28692#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28693#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 29100#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29101#L1332 assume !(1 == ~M_E~0); 30172#L1332-2 assume !(1 == ~T1_E~0); 30373#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29814#L1342-1 assume !(1 == ~T3_E~0); 29815#L1347-1 assume !(1 == ~T4_E~0); 30200#L1352-1 assume !(1 == ~T5_E~0); 30066#L1357-1 assume !(1 == ~T6_E~0); 29377#L1362-1 assume !(1 == ~T7_E~0); 29378#L1367-1 assume !(1 == ~T8_E~0); 28987#L1372-1 assume !(1 == ~T9_E~0); 28988#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29290#L1382-1 assume !(1 == ~T11_E~0); 29291#L1387-1 assume !(1 == ~T12_E~0); 29974#L1392-1 assume !(1 == ~E_M~0); 29317#L1397-1 assume !(1 == ~E_1~0); 29318#L1402-1 assume !(1 == ~E_2~0); 29002#L1407-1 assume !(1 == ~E_3~0); 29003#L1412-1 assume !(1 == ~E_4~0); 30139#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 30140#L1422-1 assume !(1 == ~E_6~0); 30375#L1427-1 assume !(1 == ~E_7~0); 29182#L1432-1 assume !(1 == ~E_8~0); 29183#L1437-1 assume !(1 == ~E_9~0); 30092#L1442-1 assume !(1 == ~E_10~0); 30093#L1447-1 assume !(1 == ~E_11~0); 29966#L1452-1 assume !(1 == ~E_12~0); 28789#L1457-1 assume { :end_inline_reset_delta_events } true; 28790#L1803-2 [2022-12-13 15:37:43,772 INFO L750 eck$LassoCheckResult]: Loop: 28790#L1803-2 assume !false; 29124#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28660#L1169 assume !false; 29245#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29359#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 28856#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 28857#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 30180#L996 assume !(0 != eval_~tmp~0#1); 29564#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29234#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29235#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29721#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28958#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28959#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29211#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28652#L1214-3 assume !(0 == ~T5_E~0); 28653#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29404#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29405#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29439#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28827#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28828#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29258#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 29838#L1254-3 assume !(0 == ~E_M~0); 30317#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29949#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28833#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28834#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30352#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29402#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29403#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29385#L1294-3 assume !(0 == ~E_8~0); 29386#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29770#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 29771#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 29292#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 29293#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29298#L586-42 assume !(1 == ~m_pc~0); 29299#L586-44 is_master_triggered_~__retres1~0#1 := 0; 28901#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28902#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29360#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 29432#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29433#L605-42 assume 1 == ~t1_pc~0; 30014#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29738#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29739#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29434#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29435#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29443#L624-42 assume !(1 == ~t2_pc~0); 29444#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 29584#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29676#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29677#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29256#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29257#L643-42 assume 1 == ~t3_pc~0; 29608#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29565#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29566#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29400#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29401#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30102#L662-42 assume !(1 == ~t4_pc~0); 30304#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 28922#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28923#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30081#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30345#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30312#L681-42 assume !(1 == ~t5_pc~0); 28785#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 28786#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29763#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29764#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30148#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29276#L700-42 assume 1 == ~t6_pc~0; 29277#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29088#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29014#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29015#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30155#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30362#L719-42 assume 1 == ~t7_pc~0; 29876#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28976#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29346#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29603#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 29361#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29362#L738-42 assume 1 == ~t8_pc~0; 29554#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29307#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29308#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28831#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28832#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29355#L757-42 assume 1 == ~t9_pc~0; 29691#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29016#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29017#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29750#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29129#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29130#L776-42 assume !(1 == ~t10_pc~0); 30073#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 30074#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29893#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29894#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30398#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29916#L795-42 assume !(1 == ~t11_pc~0); 29917#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 28970#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28971#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29067#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 29068#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29371#L814-42 assume 1 == ~t12_pc~0; 30130#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 28881#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28882#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28687#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 28688#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28843#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28844#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28819#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28820#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29635#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29802#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29803#L1357-3 assume !(1 == ~T6_E~0); 30233#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30406#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30402#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28670#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28671#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29273#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 29274#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30098#L1397-3 assume !(1 == ~E_1~0); 30372#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 29752#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28927#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28928#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29655#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29656#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30231#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 29995#L1437-3 assume !(1 == ~E_9~0); 29772#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29773#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28721#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 28722#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29334#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29179#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29001#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 28919#L1822 assume !(0 == start_simulation_~tmp~3#1); 28920#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29868#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29176#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 28672#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 28673#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29824#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29922#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 30258#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 28790#L1803-2 [2022-12-13 15:37:43,773 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:43,773 INFO L85 PathProgramCache]: Analyzing trace with hash 813976236, now seen corresponding path program 1 times [2022-12-13 15:37:43,773 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:43,773 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1103828913] [2022-12-13 15:37:43,773 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:43,773 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:43,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:43,806 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:43,806 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:43,806 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1103828913] [2022-12-13 15:37:43,806 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1103828913] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:43,807 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:43,807 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:43,807 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1079408882] [2022-12-13 15:37:43,807 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:43,807 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:37:43,808 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:43,808 INFO L85 PathProgramCache]: Analyzing trace with hash -824564043, now seen corresponding path program 1 times [2022-12-13 15:37:43,808 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:43,808 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1124093156] [2022-12-13 15:37:43,808 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:43,808 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:43,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:43,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:43,870 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:43,870 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1124093156] [2022-12-13 15:37:43,870 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1124093156] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:43,870 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:43,870 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:43,870 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [104688695] [2022-12-13 15:37:43,871 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:43,871 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:37:43,871 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:37:43,872 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:37:43,872 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:37:43,872 INFO L87 Difference]: Start difference. First operand 1785 states and 2639 transitions. cyclomatic complexity: 855 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:43,899 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:37:43,900 INFO L93 Difference]: Finished difference Result 1785 states and 2638 transitions. [2022-12-13 15:37:43,900 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2638 transitions. [2022-12-13 15:37:43,906 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-12-13 15:37:43,910 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2638 transitions. [2022-12-13 15:37:43,911 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2022-12-13 15:37:43,911 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2022-12-13 15:37:43,912 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2638 transitions. [2022-12-13 15:37:43,913 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:37:43,914 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2638 transitions. [2022-12-13 15:37:43,916 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2638 transitions. [2022-12-13 15:37:43,928 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2022-12-13 15:37:43,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4778711484593838) internal successors, (2638), 1784 states have internal predecessors, (2638), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:43,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2638 transitions. [2022-12-13 15:37:43,932 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2638 transitions. [2022-12-13 15:37:43,933 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:37:43,933 INFO L428 stractBuchiCegarLoop]: Abstraction has 1785 states and 2638 transitions. [2022-12-13 15:37:43,933 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 15:37:43,933 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2638 transitions. [2022-12-13 15:37:43,937 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-12-13 15:37:43,937 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:37:43,937 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:37:43,938 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:43,938 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:43,938 INFO L748 eck$LassoCheckResult]: Stem: 32456#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 32457#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 33374#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33375#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32526#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 32527#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32431#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32432#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33698#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33058#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33059#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32956#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32957#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33456#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33457#L886-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 32719#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 32720#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33144#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33145#L1194 assume !(0 == ~M_E~0); 33296#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33297#L1199-1 assume !(0 == ~T2_E~0); 33579#L1204-1 assume !(0 == ~T3_E~0); 33505#L1209-1 assume !(0 == ~T4_E~0); 33506#L1214-1 assume !(0 == ~T5_E~0); 33900#L1219-1 assume !(0 == ~T6_E~0); 33987#L1224-1 assume !(0 == ~T7_E~0); 32792#L1229-1 assume !(0 == ~T8_E~0); 32349#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32350#L1239-1 assume !(0 == ~T10_E~0); 32394#L1244-1 assume !(0 == ~T11_E~0); 32395#L1249-1 assume !(0 == ~T12_E~0); 33088#L1254-1 assume !(0 == ~E_M~0); 32291#L1259-1 assume !(0 == ~E_1~0); 32256#L1264-1 assume !(0 == ~E_2~0); 32257#L1269-1 assume !(0 == ~E_3~0); 33989#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 33932#L1279-1 assume !(0 == ~E_5~0); 32467#L1284-1 assume !(0 == ~E_6~0); 32468#L1289-1 assume !(0 == ~E_7~0); 33151#L1294-1 assume !(0 == ~E_8~0); 33152#L1299-1 assume !(0 == ~E_9~0); 33163#L1304-1 assume !(0 == ~E_10~0); 33980#L1309-1 assume !(0 == ~E_11~0); 33985#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 32424#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32346#L586 assume 1 == ~m_pc~0; 32347#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32416#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33223#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32625#L1485 assume !(0 != activate_threads_~tmp~1#1); 32626#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33704#L605 assume !(1 == ~t1_pc~0); 33237#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 32983#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32984#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33617#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33553#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32893#L624 assume 1 == ~t2_pc~0; 32398#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32399#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32649#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32650#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 33736#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33615#L643 assume !(1 == ~t3_pc~0); 33475#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33181#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33182#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32726#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 32727#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32488#L662 assume 1 == ~t4_pc~0; 32489#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32447#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32308#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32309#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 32335#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32336#L681 assume !(1 == ~t5_pc~0); 32206#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 32207#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33263#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33861#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 32738#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32739#L700 assume 1 == ~t6_pc~0; 33436#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32480#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32481#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32528#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 32529#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33790#L719 assume 1 == ~t7_pc~0; 33870#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32695#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33977#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33918#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 32220#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32221#L738 assume !(1 == ~t8_pc~0); 33586#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 33496#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33497#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33292#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33293#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33637#L757 assume 1 == ~t9_pc~0; 33638#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32215#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32216#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32693#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 33255#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33256#L776 assume !(1 == ~t10_pc~0); 32240#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 32239#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32629#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32469#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 32470#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32425#L795 assume 1 == ~t11_pc~0; 32426#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32758#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33718#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33888#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 33469#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33459#L814 assume !(1 == ~t12_pc~0); 33322#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 33323#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32269#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32270#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 32677#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32678#L1332 assume !(1 == ~M_E~0); 33749#L1332-2 assume !(1 == ~T1_E~0); 33950#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33391#L1342-1 assume !(1 == ~T3_E~0); 33392#L1347-1 assume !(1 == ~T4_E~0); 33777#L1352-1 assume !(1 == ~T5_E~0); 33643#L1357-1 assume !(1 == ~T6_E~0); 32954#L1362-1 assume !(1 == ~T7_E~0); 32955#L1367-1 assume !(1 == ~T8_E~0); 32564#L1372-1 assume !(1 == ~T9_E~0); 32565#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32867#L1382-1 assume !(1 == ~T11_E~0); 32868#L1387-1 assume !(1 == ~T12_E~0); 33551#L1392-1 assume !(1 == ~E_M~0); 32894#L1397-1 assume !(1 == ~E_1~0); 32895#L1402-1 assume !(1 == ~E_2~0); 32579#L1407-1 assume !(1 == ~E_3~0); 32580#L1412-1 assume !(1 == ~E_4~0); 33716#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 33717#L1422-1 assume !(1 == ~E_6~0); 33952#L1427-1 assume !(1 == ~E_7~0); 32759#L1432-1 assume !(1 == ~E_8~0); 32760#L1437-1 assume !(1 == ~E_9~0); 33669#L1442-1 assume !(1 == ~E_10~0); 33670#L1447-1 assume !(1 == ~E_11~0); 33543#L1452-1 assume !(1 == ~E_12~0); 32366#L1457-1 assume { :end_inline_reset_delta_events } true; 32367#L1803-2 [2022-12-13 15:37:43,939 INFO L750 eck$LassoCheckResult]: Loop: 32367#L1803-2 assume !false; 32701#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32237#L1169 assume !false; 32822#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 32936#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32433#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32434#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 33757#L996 assume !(0 != eval_~tmp~0#1); 33141#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32811#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32812#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33298#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 32535#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32536#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32788#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32229#L1214-3 assume !(0 == ~T5_E~0); 32230#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32981#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32982#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33016#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32404#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32405#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32835#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 33415#L1254-3 assume !(0 == ~E_M~0); 33894#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33526#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32410#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32411#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33929#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32979#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32980#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 32962#L1294-3 assume !(0 == ~E_8~0); 32963#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 33347#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 33348#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32869#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 32870#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32875#L586-42 assume !(1 == ~m_pc~0); 32876#L586-44 is_master_triggered_~__retres1~0#1 := 0; 32478#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32479#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32937#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 33009#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33010#L605-42 assume 1 == ~t1_pc~0; 33591#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33315#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33316#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33011#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33012#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33020#L624-42 assume !(1 == ~t2_pc~0); 33021#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 33161#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33253#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33254#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 32833#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32834#L643-42 assume 1 == ~t3_pc~0; 33185#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33142#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33143#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32977#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32978#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33679#L662-42 assume !(1 == ~t4_pc~0); 33881#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 32499#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32500#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33658#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33922#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33889#L681-42 assume !(1 == ~t5_pc~0); 32362#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 32363#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33340#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33341#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33725#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32853#L700-42 assume 1 == ~t6_pc~0; 32854#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32665#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32591#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32592#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33732#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33939#L719-42 assume !(1 == ~t7_pc~0); 32552#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 32553#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32923#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33180#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 32938#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32939#L738-42 assume 1 == ~t8_pc~0; 33131#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32884#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32885#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32408#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32409#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32932#L757-42 assume 1 == ~t9_pc~0; 33268#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32593#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32594#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33327#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 32706#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32707#L776-42 assume !(1 == ~t10_pc~0); 33650#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 33651#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33470#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33471#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 33975#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33493#L795-42 assume !(1 == ~t11_pc~0); 33494#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 32547#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32548#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 32644#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32645#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32948#L814-42 assume !(1 == ~t12_pc~0); 32817#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 32458#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32459#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32264#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 32265#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32420#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32421#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32396#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32397#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33212#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33379#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33380#L1357-3 assume !(1 == ~T6_E~0); 33810#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33983#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33979#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32247#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32248#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 32850#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 32851#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33675#L1397-3 assume !(1 == ~E_1~0); 33949#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33329#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 32504#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32505#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33232#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33233#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33808#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33572#L1437-3 assume !(1 == ~E_9~0); 33349#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 33350#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 32298#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 32299#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 32911#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32756#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32578#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 32496#L1822 assume !(0 == start_simulation_~tmp~3#1); 32497#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33445#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32753#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32249#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 32250#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33401#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33499#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 33835#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 32367#L1803-2 [2022-12-13 15:37:43,939 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:43,939 INFO L85 PathProgramCache]: Analyzing trace with hash -1345107858, now seen corresponding path program 1 times [2022-12-13 15:37:43,939 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:43,939 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1276393063] [2022-12-13 15:37:43,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:43,939 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:43,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:43,971 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:43,971 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:43,972 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1276393063] [2022-12-13 15:37:43,972 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1276393063] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:43,972 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:43,972 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:43,972 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1019555230] [2022-12-13 15:37:43,972 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:43,973 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:37:43,973 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:43,973 INFO L85 PathProgramCache]: Analyzing trace with hash -1556942217, now seen corresponding path program 2 times [2022-12-13 15:37:43,973 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:43,973 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1649624151] [2022-12-13 15:37:43,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:43,974 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:43,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:44,032 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:44,032 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:44,032 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1649624151] [2022-12-13 15:37:44,032 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1649624151] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:44,032 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:44,032 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:44,033 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1558429284] [2022-12-13 15:37:44,033 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:44,033 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:37:44,033 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:37:44,033 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:37:44,034 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:37:44,034 INFO L87 Difference]: Start difference. First operand 1785 states and 2638 transitions. cyclomatic complexity: 854 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:44,061 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:37:44,061 INFO L93 Difference]: Finished difference Result 1785 states and 2637 transitions. [2022-12-13 15:37:44,061 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2637 transitions. [2022-12-13 15:37:44,067 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-12-13 15:37:44,074 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2637 transitions. [2022-12-13 15:37:44,074 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2022-12-13 15:37:44,075 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2022-12-13 15:37:44,075 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2637 transitions. [2022-12-13 15:37:44,078 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:37:44,078 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2637 transitions. [2022-12-13 15:37:44,081 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2637 transitions. [2022-12-13 15:37:44,113 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2022-12-13 15:37:44,115 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.477310924369748) internal successors, (2637), 1784 states have internal predecessors, (2637), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:44,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2637 transitions. [2022-12-13 15:37:44,119 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2637 transitions. [2022-12-13 15:37:44,120 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:37:44,120 INFO L428 stractBuchiCegarLoop]: Abstraction has 1785 states and 2637 transitions. [2022-12-13 15:37:44,120 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 15:37:44,120 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2637 transitions. [2022-12-13 15:37:44,125 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-12-13 15:37:44,125 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:37:44,125 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:37:44,128 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:44,128 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:44,128 INFO L748 eck$LassoCheckResult]: Stem: 36033#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 36034#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 36951#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 36952#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36103#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 36104#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36008#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36009#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37275#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36635#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36636#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36533#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36534#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37033#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 37034#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36296#L891-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 36297#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 36721#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36722#L1194 assume !(0 == ~M_E~0); 36873#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36874#L1199-1 assume !(0 == ~T2_E~0); 37156#L1204-1 assume !(0 == ~T3_E~0); 37082#L1209-1 assume !(0 == ~T4_E~0); 37083#L1214-1 assume !(0 == ~T5_E~0); 37477#L1219-1 assume !(0 == ~T6_E~0); 37564#L1224-1 assume !(0 == ~T7_E~0); 36369#L1229-1 assume !(0 == ~T8_E~0); 35926#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35927#L1239-1 assume !(0 == ~T10_E~0); 35971#L1244-1 assume !(0 == ~T11_E~0); 35972#L1249-1 assume !(0 == ~T12_E~0); 36665#L1254-1 assume !(0 == ~E_M~0); 35868#L1259-1 assume !(0 == ~E_1~0); 35833#L1264-1 assume !(0 == ~E_2~0); 35834#L1269-1 assume !(0 == ~E_3~0); 37566#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 37509#L1279-1 assume !(0 == ~E_5~0); 36044#L1284-1 assume !(0 == ~E_6~0); 36045#L1289-1 assume !(0 == ~E_7~0); 36728#L1294-1 assume !(0 == ~E_8~0); 36729#L1299-1 assume !(0 == ~E_9~0); 36740#L1304-1 assume !(0 == ~E_10~0); 37557#L1309-1 assume !(0 == ~E_11~0); 37562#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 36001#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35923#L586 assume 1 == ~m_pc~0; 35924#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 35993#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36800#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36202#L1485 assume !(0 != activate_threads_~tmp~1#1); 36203#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37281#L605 assume !(1 == ~t1_pc~0); 36814#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 36560#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36561#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37194#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37130#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36470#L624 assume 1 == ~t2_pc~0; 35975#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35976#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36226#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36227#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 37313#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37192#L643 assume !(1 == ~t3_pc~0); 37052#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 36758#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36759#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36303#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 36304#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36065#L662 assume 1 == ~t4_pc~0; 36066#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 36024#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35885#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35886#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 35912#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35913#L681 assume !(1 == ~t5_pc~0); 35783#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 35784#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36840#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37438#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 36315#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36316#L700 assume 1 == ~t6_pc~0; 37013#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36057#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36058#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36105#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 36106#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37367#L719 assume 1 == ~t7_pc~0; 37447#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36272#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37554#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37495#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 35797#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35798#L738 assume !(1 == ~t8_pc~0); 37163#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 37073#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37074#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36869#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36870#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37214#L757 assume 1 == ~t9_pc~0; 37215#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35792#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35793#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36270#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 36832#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36833#L776 assume !(1 == ~t10_pc~0); 35817#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 35816#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36206#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36046#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 36047#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36002#L795 assume 1 == ~t11_pc~0; 36003#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 36335#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37295#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37465#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 37046#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37036#L814 assume !(1 == ~t12_pc~0); 36899#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 36900#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35846#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 35847#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 36254#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36255#L1332 assume !(1 == ~M_E~0); 37326#L1332-2 assume !(1 == ~T1_E~0); 37527#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36968#L1342-1 assume !(1 == ~T3_E~0); 36969#L1347-1 assume !(1 == ~T4_E~0); 37354#L1352-1 assume !(1 == ~T5_E~0); 37220#L1357-1 assume !(1 == ~T6_E~0); 36531#L1362-1 assume !(1 == ~T7_E~0); 36532#L1367-1 assume !(1 == ~T8_E~0); 36141#L1372-1 assume !(1 == ~T9_E~0); 36142#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36444#L1382-1 assume !(1 == ~T11_E~0); 36445#L1387-1 assume !(1 == ~T12_E~0); 37128#L1392-1 assume !(1 == ~E_M~0); 36471#L1397-1 assume !(1 == ~E_1~0); 36472#L1402-1 assume !(1 == ~E_2~0); 36156#L1407-1 assume !(1 == ~E_3~0); 36157#L1412-1 assume !(1 == ~E_4~0); 37293#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 37294#L1422-1 assume !(1 == ~E_6~0); 37529#L1427-1 assume !(1 == ~E_7~0); 36336#L1432-1 assume !(1 == ~E_8~0); 36337#L1437-1 assume !(1 == ~E_9~0); 37246#L1442-1 assume !(1 == ~E_10~0); 37247#L1447-1 assume !(1 == ~E_11~0); 37120#L1452-1 assume !(1 == ~E_12~0); 35943#L1457-1 assume { :end_inline_reset_delta_events } true; 35944#L1803-2 [2022-12-13 15:37:44,128 INFO L750 eck$LassoCheckResult]: Loop: 35944#L1803-2 assume !false; 36278#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35814#L1169 assume !false; 36399#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 36513#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36010#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36011#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 37334#L996 assume !(0 != eval_~tmp~0#1); 36718#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36388#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36389#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 36875#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36112#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36113#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36365#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35806#L1214-3 assume !(0 == ~T5_E~0); 35807#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36558#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36559#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36593#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35981#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 35982#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36412#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 36992#L1254-3 assume !(0 == ~E_M~0); 37471#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37103#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35987#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35988#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 37506#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36556#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36557#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36539#L1294-3 assume !(0 == ~E_8~0); 36540#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 36924#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 36925#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36446#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 36447#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36452#L586-42 assume !(1 == ~m_pc~0); 36453#L586-44 is_master_triggered_~__retres1~0#1 := 0; 36055#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36056#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36514#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 36586#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36587#L605-42 assume 1 == ~t1_pc~0; 37168#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36892#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36893#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36588#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36589#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36597#L624-42 assume !(1 == ~t2_pc~0); 36598#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 36738#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36830#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36831#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36410#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36411#L643-42 assume 1 == ~t3_pc~0; 36762#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36719#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36720#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36554#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36555#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37256#L662-42 assume !(1 == ~t4_pc~0); 37458#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 36076#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36077#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37235#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37499#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37466#L681-42 assume !(1 == ~t5_pc~0); 35939#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 35940#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36917#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36918#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 37302#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36430#L700-42 assume !(1 == ~t6_pc~0); 36241#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 36242#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36168#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36169#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37309#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37516#L719-42 assume !(1 == ~t7_pc~0); 36129#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 36130#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36500#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36757#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 36515#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36516#L738-42 assume 1 == ~t8_pc~0; 36708#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36461#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36462#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35985#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35986#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36509#L757-42 assume 1 == ~t9_pc~0; 36845#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36170#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36171#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36904#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36283#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36284#L776-42 assume !(1 == ~t10_pc~0); 37227#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 37228#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37047#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37048#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37552#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37070#L795-42 assume 1 == ~t11_pc~0; 37072#L796-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 36124#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36125#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 36221#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 36222#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36525#L814-42 assume 1 == ~t12_pc~0; 37284#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 36035#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36036#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 35841#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 35842#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35997#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 35998#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35973#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35974#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36789#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36956#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36957#L1357-3 assume !(1 == ~T6_E~0); 37387#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37560#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37556#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 35824#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 35825#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 36427#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 36428#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37252#L1397-3 assume !(1 == ~E_1~0); 37526#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 36906#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36081#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36082#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36809#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36810#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37385#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37149#L1437-3 assume !(1 == ~E_9~0); 36926#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 36927#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 35875#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 35876#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 36488#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36333#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36155#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 36073#L1822 assume !(0 == start_simulation_~tmp~3#1); 36074#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37022#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36330#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 35826#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 35827#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 36978#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37076#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 37412#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 35944#L1803-2 [2022-12-13 15:37:44,129 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:44,129 INFO L85 PathProgramCache]: Analyzing trace with hash -1762996560, now seen corresponding path program 1 times [2022-12-13 15:37:44,129 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:44,129 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1271989463] [2022-12-13 15:37:44,129 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:44,129 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:44,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:44,173 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:44,173 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:44,173 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1271989463] [2022-12-13 15:37:44,173 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1271989463] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:44,173 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:44,174 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:44,174 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1107983618] [2022-12-13 15:37:44,174 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:44,174 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:37:44,174 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:44,175 INFO L85 PathProgramCache]: Analyzing trace with hash -1417596682, now seen corresponding path program 1 times [2022-12-13 15:37:44,175 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:44,175 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [825820271] [2022-12-13 15:37:44,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:44,175 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:44,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:44,229 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:44,229 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:44,230 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [825820271] [2022-12-13 15:37:44,230 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [825820271] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:44,230 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:44,230 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:44,230 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [830519020] [2022-12-13 15:37:44,230 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:44,231 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:37:44,231 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:37:44,231 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:37:44,231 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:37:44,231 INFO L87 Difference]: Start difference. First operand 1785 states and 2637 transitions. cyclomatic complexity: 853 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:44,256 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:37:44,256 INFO L93 Difference]: Finished difference Result 1785 states and 2636 transitions. [2022-12-13 15:37:44,256 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2636 transitions. [2022-12-13 15:37:44,262 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-12-13 15:37:44,269 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2636 transitions. [2022-12-13 15:37:44,269 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2022-12-13 15:37:44,270 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2022-12-13 15:37:44,270 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2636 transitions. [2022-12-13 15:37:44,273 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:37:44,273 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2636 transitions. [2022-12-13 15:37:44,275 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2636 transitions. [2022-12-13 15:37:44,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2022-12-13 15:37:44,294 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4767507002801121) internal successors, (2636), 1784 states have internal predecessors, (2636), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:44,298 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2636 transitions. [2022-12-13 15:37:44,298 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2636 transitions. [2022-12-13 15:37:44,298 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:37:44,299 INFO L428 stractBuchiCegarLoop]: Abstraction has 1785 states and 2636 transitions. [2022-12-13 15:37:44,299 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 15:37:44,299 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2636 transitions. [2022-12-13 15:37:44,304 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-12-13 15:37:44,304 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:37:44,304 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:37:44,307 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:44,307 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:44,307 INFO L748 eck$LassoCheckResult]: Stem: 39610#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 39611#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 40528#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40529#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39680#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 39681#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39585#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39586#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40852#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40212#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40213#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40110#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 40111#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 40610#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 40611#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 39873#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 39874#L896-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 40298#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40299#L1194 assume !(0 == ~M_E~0); 40450#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40451#L1199-1 assume !(0 == ~T2_E~0); 40733#L1204-1 assume !(0 == ~T3_E~0); 40659#L1209-1 assume !(0 == ~T4_E~0); 40660#L1214-1 assume !(0 == ~T5_E~0); 41054#L1219-1 assume !(0 == ~T6_E~0); 41141#L1224-1 assume !(0 == ~T7_E~0); 39946#L1229-1 assume !(0 == ~T8_E~0); 39503#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 39504#L1239-1 assume !(0 == ~T10_E~0); 39548#L1244-1 assume !(0 == ~T11_E~0); 39549#L1249-1 assume !(0 == ~T12_E~0); 40242#L1254-1 assume !(0 == ~E_M~0); 39445#L1259-1 assume !(0 == ~E_1~0); 39410#L1264-1 assume !(0 == ~E_2~0); 39411#L1269-1 assume !(0 == ~E_3~0); 41143#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 41086#L1279-1 assume !(0 == ~E_5~0); 39621#L1284-1 assume !(0 == ~E_6~0); 39622#L1289-1 assume !(0 == ~E_7~0); 40305#L1294-1 assume !(0 == ~E_8~0); 40306#L1299-1 assume !(0 == ~E_9~0); 40317#L1304-1 assume !(0 == ~E_10~0); 41134#L1309-1 assume !(0 == ~E_11~0); 41139#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 39578#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39500#L586 assume 1 == ~m_pc~0; 39501#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 39570#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40377#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39779#L1485 assume !(0 != activate_threads_~tmp~1#1); 39780#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40858#L605 assume !(1 == ~t1_pc~0); 40391#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40137#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40138#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40771#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40707#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40047#L624 assume 1 == ~t2_pc~0; 39552#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39553#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39803#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39804#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 40890#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40769#L643 assume !(1 == ~t3_pc~0); 40629#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 40335#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40336#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39880#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 39881#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39642#L662 assume 1 == ~t4_pc~0; 39643#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39601#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39462#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39463#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 39489#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39490#L681 assume !(1 == ~t5_pc~0); 39360#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 39361#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40417#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41015#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 39892#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39893#L700 assume 1 == ~t6_pc~0; 40590#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 39634#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39635#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39682#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 39683#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40944#L719 assume 1 == ~t7_pc~0; 41024#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39849#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41131#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41072#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 39374#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39375#L738 assume !(1 == ~t8_pc~0); 40740#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 40650#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40651#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40446#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40447#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40791#L757 assume 1 == ~t9_pc~0; 40792#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39369#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39370#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39847#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 40409#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40410#L776 assume !(1 == ~t10_pc~0); 39394#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 39393#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39783#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39623#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 39624#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39579#L795 assume 1 == ~t11_pc~0; 39580#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39912#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40872#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41042#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 40623#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40613#L814 assume !(1 == ~t12_pc~0); 40476#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 40477#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 39423#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39424#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 39831#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39832#L1332 assume !(1 == ~M_E~0); 40903#L1332-2 assume !(1 == ~T1_E~0); 41104#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40545#L1342-1 assume !(1 == ~T3_E~0); 40546#L1347-1 assume !(1 == ~T4_E~0); 40931#L1352-1 assume !(1 == ~T5_E~0); 40797#L1357-1 assume !(1 == ~T6_E~0); 40108#L1362-1 assume !(1 == ~T7_E~0); 40109#L1367-1 assume !(1 == ~T8_E~0); 39718#L1372-1 assume !(1 == ~T9_E~0); 39719#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40021#L1382-1 assume !(1 == ~T11_E~0); 40022#L1387-1 assume !(1 == ~T12_E~0); 40705#L1392-1 assume !(1 == ~E_M~0); 40048#L1397-1 assume !(1 == ~E_1~0); 40049#L1402-1 assume !(1 == ~E_2~0); 39733#L1407-1 assume !(1 == ~E_3~0); 39734#L1412-1 assume !(1 == ~E_4~0); 40870#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 40871#L1422-1 assume !(1 == ~E_6~0); 41106#L1427-1 assume !(1 == ~E_7~0); 39913#L1432-1 assume !(1 == ~E_8~0); 39914#L1437-1 assume !(1 == ~E_9~0); 40823#L1442-1 assume !(1 == ~E_10~0); 40824#L1447-1 assume !(1 == ~E_11~0); 40697#L1452-1 assume !(1 == ~E_12~0); 39520#L1457-1 assume { :end_inline_reset_delta_events } true; 39521#L1803-2 [2022-12-13 15:37:44,307 INFO L750 eck$LassoCheckResult]: Loop: 39521#L1803-2 assume !false; 39855#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 39391#L1169 assume !false; 39976#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40090#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39587#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 39588#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 40911#L996 assume !(0 != eval_~tmp~0#1); 40295#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 39965#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 39966#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40452#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 39689#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 39690#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 39942#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 39383#L1214-3 assume !(0 == ~T5_E~0); 39384#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40135#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40136#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40170#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 39558#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 39559#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 39989#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 40569#L1254-3 assume !(0 == ~E_M~0); 41048#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40680#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 39564#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 39565#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 41083#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40133#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 40134#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40116#L1294-3 assume !(0 == ~E_8~0); 40117#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 40501#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 40502#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 40023#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 40024#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40029#L586-42 assume !(1 == ~m_pc~0); 40030#L586-44 is_master_triggered_~__retres1~0#1 := 0; 39632#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39633#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40091#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 40163#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40164#L605-42 assume 1 == ~t1_pc~0; 40745#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40469#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40470#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40165#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40166#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40174#L624-42 assume 1 == ~t2_pc~0; 40176#L625-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 40315#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40407#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40408#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 39987#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39988#L643-42 assume 1 == ~t3_pc~0; 40339#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40296#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40297#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40131#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40132#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40833#L662-42 assume !(1 == ~t4_pc~0); 41035#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 39653#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39654#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40812#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41076#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41043#L681-42 assume !(1 == ~t5_pc~0); 39516#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 39517#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40494#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40495#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 40879#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40007#L700-42 assume 1 == ~t6_pc~0; 40008#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 39819#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39745#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39746#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40886#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41093#L719-42 assume !(1 == ~t7_pc~0); 39706#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 39707#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40077#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40334#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 40092#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40093#L738-42 assume 1 == ~t8_pc~0; 40285#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40038#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40039#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39562#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39563#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40086#L757-42 assume 1 == ~t9_pc~0; 40422#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39747#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39748#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40481#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 39860#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39861#L776-42 assume !(1 == ~t10_pc~0); 40804#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 40805#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40624#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40625#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41129#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40647#L795-42 assume !(1 == ~t11_pc~0); 40648#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 39701#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39702#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39798#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39799#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40102#L814-42 assume !(1 == ~t12_pc~0); 39971#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 39612#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 39613#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39418#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 39419#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39574#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 39575#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 39550#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 39551#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40366#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40533#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40534#L1357-3 assume !(1 == ~T6_E~0); 40964#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41137#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41133#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 39401#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 39402#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40004#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 40005#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 40829#L1397-3 assume !(1 == ~E_1~0); 41103#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 40483#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 39658#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39659#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40386#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 40387#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 40962#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 40726#L1437-3 assume !(1 == ~E_9~0); 40503#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 40504#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 39452#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 39453#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40065#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39910#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 39732#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 39650#L1822 assume !(0 == start_simulation_~tmp~3#1); 39651#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40599#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39907#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 39403#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 39404#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40555#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40653#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 40989#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 39521#L1803-2 [2022-12-13 15:37:44,308 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:44,308 INFO L85 PathProgramCache]: Analyzing trace with hash 1133017134, now seen corresponding path program 1 times [2022-12-13 15:37:44,308 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:44,308 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [414253798] [2022-12-13 15:37:44,308 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:44,308 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:44,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:44,351 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:44,351 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:44,351 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [414253798] [2022-12-13 15:37:44,351 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [414253798] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:44,351 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:44,352 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:44,352 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [365636581] [2022-12-13 15:37:44,352 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:44,352 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:37:44,352 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:44,353 INFO L85 PathProgramCache]: Analyzing trace with hash -1844402122, now seen corresponding path program 1 times [2022-12-13 15:37:44,353 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:44,353 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2064627298] [2022-12-13 15:37:44,353 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:44,353 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:44,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:44,407 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:44,407 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:44,407 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2064627298] [2022-12-13 15:37:44,407 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2064627298] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:44,407 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:44,407 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:44,407 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [923151941] [2022-12-13 15:37:44,408 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:44,408 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:37:44,408 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:37:44,408 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:37:44,408 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:37:44,409 INFO L87 Difference]: Start difference. First operand 1785 states and 2636 transitions. cyclomatic complexity: 852 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:44,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:37:44,434 INFO L93 Difference]: Finished difference Result 1785 states and 2635 transitions. [2022-12-13 15:37:44,434 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2635 transitions. [2022-12-13 15:37:44,440 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-12-13 15:37:44,446 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2635 transitions. [2022-12-13 15:37:44,446 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2022-12-13 15:37:44,448 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2022-12-13 15:37:44,448 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2635 transitions. [2022-12-13 15:37:44,450 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:37:44,450 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2635 transitions. [2022-12-13 15:37:44,453 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2635 transitions. [2022-12-13 15:37:44,469 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2022-12-13 15:37:44,473 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4761904761904763) internal successors, (2635), 1784 states have internal predecessors, (2635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:44,476 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2635 transitions. [2022-12-13 15:37:44,477 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2635 transitions. [2022-12-13 15:37:44,477 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:37:44,477 INFO L428 stractBuchiCegarLoop]: Abstraction has 1785 states and 2635 transitions. [2022-12-13 15:37:44,478 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-12-13 15:37:44,478 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2635 transitions. [2022-12-13 15:37:44,483 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-12-13 15:37:44,483 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:37:44,483 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:37:44,485 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:44,485 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:44,486 INFO L748 eck$LassoCheckResult]: Stem: 43187#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 43188#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 44105#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 44106#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43257#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 43258#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43162#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43163#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 44429#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43789#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43790#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43687#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 43688#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 44187#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 44188#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 43450#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 43451#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 43875#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43876#L1194 assume !(0 == ~M_E~0); 44027#L1194-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44028#L1199-1 assume !(0 == ~T2_E~0); 44310#L1204-1 assume !(0 == ~T3_E~0); 44236#L1209-1 assume !(0 == ~T4_E~0); 44237#L1214-1 assume !(0 == ~T5_E~0); 44631#L1219-1 assume !(0 == ~T6_E~0); 44718#L1224-1 assume !(0 == ~T7_E~0); 43523#L1229-1 assume !(0 == ~T8_E~0); 43080#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 43081#L1239-1 assume !(0 == ~T10_E~0); 43125#L1244-1 assume !(0 == ~T11_E~0); 43126#L1249-1 assume !(0 == ~T12_E~0); 43819#L1254-1 assume !(0 == ~E_M~0); 43022#L1259-1 assume !(0 == ~E_1~0); 42987#L1264-1 assume !(0 == ~E_2~0); 42988#L1269-1 assume !(0 == ~E_3~0); 44720#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 44663#L1279-1 assume !(0 == ~E_5~0); 43198#L1284-1 assume !(0 == ~E_6~0); 43199#L1289-1 assume !(0 == ~E_7~0); 43882#L1294-1 assume !(0 == ~E_8~0); 43883#L1299-1 assume !(0 == ~E_9~0); 43894#L1304-1 assume !(0 == ~E_10~0); 44711#L1309-1 assume !(0 == ~E_11~0); 44716#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 43155#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43077#L586 assume 1 == ~m_pc~0; 43078#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 43147#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43954#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43356#L1485 assume !(0 != activate_threads_~tmp~1#1); 43357#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44435#L605 assume !(1 == ~t1_pc~0); 43968#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 43714#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43715#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44348#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44284#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43624#L624 assume 1 == ~t2_pc~0; 43129#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43130#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43380#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43381#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 44467#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44346#L643 assume !(1 == ~t3_pc~0); 44206#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 43912#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43913#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43457#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 43458#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43219#L662 assume 1 == ~t4_pc~0; 43220#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43178#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43039#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43040#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 43066#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43067#L681 assume !(1 == ~t5_pc~0); 42937#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 42938#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43994#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44592#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 43469#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43470#L700 assume 1 == ~t6_pc~0; 44167#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 43211#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43212#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43259#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 43260#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44521#L719 assume 1 == ~t7_pc~0; 44601#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 43426#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44708#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44649#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 42951#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42952#L738 assume !(1 == ~t8_pc~0); 44317#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 44227#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44228#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44023#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 44024#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44368#L757 assume 1 == ~t9_pc~0; 44369#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 42946#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42947#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43424#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 43986#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43987#L776 assume !(1 == ~t10_pc~0); 42971#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 42970#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43360#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43200#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 43201#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43156#L795 assume 1 == ~t11_pc~0; 43157#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 43489#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44449#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44619#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 44200#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44190#L814 assume !(1 == ~t12_pc~0); 44053#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 44054#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 43000#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43001#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 43408#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43409#L1332 assume !(1 == ~M_E~0); 44480#L1332-2 assume !(1 == ~T1_E~0); 44681#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44122#L1342-1 assume !(1 == ~T3_E~0); 44123#L1347-1 assume !(1 == ~T4_E~0); 44508#L1352-1 assume !(1 == ~T5_E~0); 44374#L1357-1 assume !(1 == ~T6_E~0); 43685#L1362-1 assume !(1 == ~T7_E~0); 43686#L1367-1 assume !(1 == ~T8_E~0); 43295#L1372-1 assume !(1 == ~T9_E~0); 43296#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43598#L1382-1 assume !(1 == ~T11_E~0); 43599#L1387-1 assume !(1 == ~T12_E~0); 44282#L1392-1 assume !(1 == ~E_M~0); 43625#L1397-1 assume !(1 == ~E_1~0); 43626#L1402-1 assume !(1 == ~E_2~0); 43310#L1407-1 assume !(1 == ~E_3~0); 43311#L1412-1 assume !(1 == ~E_4~0); 44447#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 44448#L1422-1 assume !(1 == ~E_6~0); 44683#L1427-1 assume !(1 == ~E_7~0); 43490#L1432-1 assume !(1 == ~E_8~0); 43491#L1437-1 assume !(1 == ~E_9~0); 44400#L1442-1 assume !(1 == ~E_10~0); 44401#L1447-1 assume !(1 == ~E_11~0); 44274#L1452-1 assume !(1 == ~E_12~0); 43097#L1457-1 assume { :end_inline_reset_delta_events } true; 43098#L1803-2 [2022-12-13 15:37:44,486 INFO L750 eck$LassoCheckResult]: Loop: 43098#L1803-2 assume !false; 43432#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 42968#L1169 assume !false; 43553#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 43667#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43164#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43165#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 44488#L996 assume !(0 != eval_~tmp~0#1); 43872#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 43542#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43543#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44029#L1194-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 43266#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 43267#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 43519#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 42960#L1214-3 assume !(0 == ~T5_E~0); 42961#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43712#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 43713#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 43747#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 43135#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 43136#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 43566#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 44146#L1254-3 assume !(0 == ~E_M~0); 44625#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 44257#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43141#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 43142#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 44660#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 43710#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 43711#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 43693#L1294-3 assume !(0 == ~E_8~0); 43694#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 44078#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 44079#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43600#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 43601#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43606#L586-42 assume !(1 == ~m_pc~0); 43607#L586-44 is_master_triggered_~__retres1~0#1 := 0; 43209#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43210#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43668#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 43740#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43741#L605-42 assume 1 == ~t1_pc~0; 44322#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 44046#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44047#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43742#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43743#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43751#L624-42 assume !(1 == ~t2_pc~0); 43752#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 43892#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43984#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43985#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 43564#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43565#L643-42 assume 1 == ~t3_pc~0; 43916#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43873#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43874#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43708#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43709#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44410#L662-42 assume !(1 == ~t4_pc~0); 44612#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 43230#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43231#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 44389#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44653#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44620#L681-42 assume !(1 == ~t5_pc~0); 43093#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 43094#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44071#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44072#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 44456#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43584#L700-42 assume 1 == ~t6_pc~0; 43585#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 43396#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43322#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43323#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 44463#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44670#L719-42 assume !(1 == ~t7_pc~0); 43283#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 43284#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43654#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43911#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 43669#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43670#L738-42 assume 1 == ~t8_pc~0; 43862#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 43615#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43616#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43139#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43140#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43663#L757-42 assume !(1 == ~t9_pc~0); 44000#L757-44 is_transmit9_triggered_~__retres1~9#1 := 0; 43324#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43325#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44058#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 43437#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43438#L776-42 assume !(1 == ~t10_pc~0); 44381#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 44382#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44201#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 44202#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 44706#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44224#L795-42 assume !(1 == ~t11_pc~0); 44225#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 43278#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43279#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43375#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 43376#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43679#L814-42 assume 1 == ~t12_pc~0; 44438#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 43189#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 43190#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42995#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 42996#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43151#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 43152#L1332-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 43127#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 43128#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43943#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 44110#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44111#L1357-3 assume !(1 == ~T6_E~0); 44541#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44714#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 44710#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42978#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 42979#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43581#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 43582#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 44406#L1397-3 assume !(1 == ~E_1~0); 44680#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44060#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 43235#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43236#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43963#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43964#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 44539#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 44303#L1437-3 assume !(1 == ~E_9~0); 44080#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 44081#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 43029#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 43030#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 43642#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43487#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43309#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 43227#L1822 assume !(0 == start_simulation_~tmp~3#1); 43228#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44176#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43484#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 42980#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 42981#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44132#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44230#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 44566#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 43098#L1803-2 [2022-12-13 15:37:44,486 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:44,486 INFO L85 PathProgramCache]: Analyzing trace with hash -1544509712, now seen corresponding path program 1 times [2022-12-13 15:37:44,487 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:44,487 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1192836362] [2022-12-13 15:37:44,487 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:44,487 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:44,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:44,546 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:44,547 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:44,547 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1192836362] [2022-12-13 15:37:44,547 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1192836362] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:44,547 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:44,547 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 15:37:44,547 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [437360461] [2022-12-13 15:37:44,547 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:44,548 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:37:44,548 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:44,548 INFO L85 PathProgramCache]: Analyzing trace with hash -106535881, now seen corresponding path program 2 times [2022-12-13 15:37:44,548 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:44,548 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1415710305] [2022-12-13 15:37:44,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:44,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:44,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:44,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:44,614 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:44,614 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1415710305] [2022-12-13 15:37:44,614 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1415710305] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:44,614 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:44,614 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:44,615 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2132404612] [2022-12-13 15:37:44,615 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:44,615 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:37:44,615 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:37:44,615 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:37:44,616 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:37:44,616 INFO L87 Difference]: Start difference. First operand 1785 states and 2635 transitions. cyclomatic complexity: 851 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:44,645 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:37:44,646 INFO L93 Difference]: Finished difference Result 1785 states and 2630 transitions. [2022-12-13 15:37:44,646 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2630 transitions. [2022-12-13 15:37:44,652 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-12-13 15:37:44,658 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2630 transitions. [2022-12-13 15:37:44,658 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2022-12-13 15:37:44,660 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2022-12-13 15:37:44,660 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2630 transitions. [2022-12-13 15:37:44,662 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:37:44,663 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2630 transitions. [2022-12-13 15:37:44,665 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2630 transitions. [2022-12-13 15:37:44,682 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2022-12-13 15:37:44,685 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.473389355742297) internal successors, (2630), 1784 states have internal predecessors, (2630), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:44,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2630 transitions. [2022-12-13 15:37:44,689 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2630 transitions. [2022-12-13 15:37:44,690 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:37:44,690 INFO L428 stractBuchiCegarLoop]: Abstraction has 1785 states and 2630 transitions. [2022-12-13 15:37:44,690 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-12-13 15:37:44,690 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2630 transitions. [2022-12-13 15:37:44,695 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1622 [2022-12-13 15:37:44,696 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:37:44,696 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:37:44,697 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:44,697 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:44,698 INFO L748 eck$LassoCheckResult]: Stem: 46766#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 46767#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 47683#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 47684#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46834#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 46835#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46739#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46740#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 48006#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47366#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 47367#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 47264#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 47265#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 47764#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47765#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47027#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 47028#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 47454#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47455#L1194 assume !(0 == ~M_E~0); 47604#L1194-2 assume !(0 == ~T1_E~0); 47605#L1199-1 assume !(0 == ~T2_E~0); 47887#L1204-1 assume !(0 == ~T3_E~0); 47813#L1209-1 assume !(0 == ~T4_E~0); 47814#L1214-1 assume !(0 == ~T5_E~0); 48208#L1219-1 assume !(0 == ~T6_E~0); 48295#L1224-1 assume !(0 == ~T7_E~0); 47102#L1229-1 assume !(0 == ~T8_E~0); 46665#L1234-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 46666#L1239-1 assume !(0 == ~T10_E~0); 46704#L1244-1 assume !(0 == ~T11_E~0); 46705#L1249-1 assume !(0 == ~T12_E~0); 47396#L1254-1 assume !(0 == ~E_M~0); 46599#L1259-1 assume !(0 == ~E_1~0); 46564#L1264-1 assume !(0 == ~E_2~0); 46565#L1269-1 assume !(0 == ~E_3~0); 48297#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 48240#L1279-1 assume !(0 == ~E_5~0); 46775#L1284-1 assume !(0 == ~E_6~0); 46776#L1289-1 assume !(0 == ~E_7~0); 47461#L1294-1 assume !(0 == ~E_8~0); 47462#L1299-1 assume !(0 == ~E_9~0); 47473#L1304-1 assume !(0 == ~E_10~0); 48288#L1309-1 assume !(0 == ~E_11~0); 48293#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 46733#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46654#L586 assume 1 == ~m_pc~0; 46655#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 46724#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47531#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46933#L1485 assume !(0 != activate_threads_~tmp~1#1); 46934#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48012#L605 assume !(1 == ~t1_pc~0); 47545#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47291#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47292#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47925#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47862#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47201#L624 assume 1 == ~t2_pc~0; 46709#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46710#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46957#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46958#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 48044#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47923#L643 assume !(1 == ~t3_pc~0); 47783#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 47495#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47496#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47034#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 47035#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46796#L662 assume 1 == ~t4_pc~0; 46797#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46755#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46619#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46620#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 46645#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46646#L681 assume !(1 == ~t5_pc~0); 46514#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 46515#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47571#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48169#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 47046#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47047#L700 assume 1 == ~t6_pc~0; 47744#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46788#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46789#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46836#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 46837#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48098#L719 assume 1 == ~t7_pc~0; 48181#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 47003#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48285#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48226#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 46528#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46529#L738 assume !(1 == ~t8_pc~0); 47894#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 47804#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47805#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47600#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47601#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47945#L757 assume 1 == ~t9_pc~0; 47946#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46523#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46524#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47001#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 47563#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47564#L776 assume !(1 == ~t10_pc~0); 46548#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 46547#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 46940#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46777#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 46778#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46734#L795 assume 1 == ~t11_pc~0; 46735#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 47068#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48026#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 48197#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 47777#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47767#L814 assume !(1 == ~t12_pc~0); 47630#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 47631#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46580#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46581#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 46985#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46986#L1332 assume !(1 == ~M_E~0); 48057#L1332-2 assume !(1 == ~T1_E~0); 48259#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47701#L1342-1 assume !(1 == ~T3_E~0); 47702#L1347-1 assume !(1 == ~T4_E~0); 48086#L1352-1 assume !(1 == ~T5_E~0); 47951#L1357-1 assume !(1 == ~T6_E~0); 47262#L1362-1 assume !(1 == ~T7_E~0); 47263#L1367-1 assume !(1 == ~T8_E~0); 46874#L1372-1 assume !(1 == ~T9_E~0); 46875#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47175#L1382-1 assume !(1 == ~T11_E~0); 47176#L1387-1 assume !(1 == ~T12_E~0); 47859#L1392-1 assume !(1 == ~E_M~0); 47202#L1397-1 assume !(1 == ~E_1~0); 47203#L1402-1 assume !(1 == ~E_2~0); 46889#L1407-1 assume !(1 == ~E_3~0); 46890#L1412-1 assume !(1 == ~E_4~0); 48024#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 48025#L1422-1 assume !(1 == ~E_6~0); 48260#L1427-1 assume !(1 == ~E_7~0); 47069#L1432-1 assume !(1 == ~E_8~0); 47070#L1437-1 assume !(1 == ~E_9~0); 47977#L1442-1 assume !(1 == ~E_10~0); 47978#L1447-1 assume !(1 == ~E_11~0); 47851#L1452-1 assume !(1 == ~E_12~0); 46674#L1457-1 assume { :end_inline_reset_delta_events } true; 46675#L1803-2 [2022-12-13 15:37:44,698 INFO L750 eck$LassoCheckResult]: Loop: 46675#L1803-2 assume !false; 47009#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 46545#L1169 assume !false; 47132#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47244#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 46741#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 46742#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 48065#L996 assume !(0 != eval_~tmp~0#1); 47451#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 47122#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 47123#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 47606#L1194-5 assume !(0 == ~T1_E~0); 46843#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46844#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47096#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46541#L1214-3 assume !(0 == ~T5_E~0); 46542#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47289#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 47290#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47330#L1234-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 46712#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 46713#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 47143#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 47723#L1254-3 assume !(0 == ~E_M~0); 48202#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 47834#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 46718#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46719#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 48237#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47287#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47288#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 47270#L1294-3 assume !(0 == ~E_8~0); 47271#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 47655#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 47656#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 47177#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 47178#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47183#L586-42 assume !(1 == ~m_pc~0); 47184#L586-44 is_master_triggered_~__retres1~0#1 := 0; 46783#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46784#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47245#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 47317#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47318#L605-42 assume 1 == ~t1_pc~0; 47899#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 47623#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47624#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47319#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47320#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47327#L624-42 assume !(1 == ~t2_pc~0); 47328#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 47469#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47561#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47562#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 47141#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47142#L643-42 assume 1 == ~t3_pc~0; 47491#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47449#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47450#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47285#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47286#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47987#L662-42 assume !(1 == ~t4_pc~0); 48189#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 46807#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46808#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47966#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 48230#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48196#L681-42 assume !(1 == ~t5_pc~0); 46670#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 46671#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47648#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47649#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 48033#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47161#L700-42 assume 1 == ~t6_pc~0; 47162#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46973#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46899#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46900#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 48040#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48247#L719-42 assume 1 == ~t7_pc~0; 47761#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46861#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47231#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47488#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 47246#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47247#L738-42 assume !(1 == ~t8_pc~0); 47440#L738-44 is_transmit8_triggered_~__retres1~8#1 := 0; 47192#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47193#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 46716#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 46717#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47240#L757-42 assume 1 == ~t9_pc~0; 47573#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46901#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46902#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47635#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 47013#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47014#L776-42 assume !(1 == ~t10_pc~0); 47958#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 47959#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47778#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47779#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 48283#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47801#L795-42 assume !(1 == ~t11_pc~0); 47802#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 46855#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46856#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46952#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 46953#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47256#L814-42 assume !(1 == ~t12_pc~0); 47125#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 46764#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46765#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46572#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 46573#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46728#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 46729#L1332-5 assume !(1 == ~T1_E~0); 46702#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46703#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47520#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47687#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47688#L1357-3 assume !(1 == ~T6_E~0); 48118#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 48291#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 48287#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46555#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 46556#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 47158#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47159#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 47983#L1397-3 assume !(1 == ~E_1~0); 48257#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 47637#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46812#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 46813#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 47540#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 47541#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 48116#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 47880#L1437-3 assume !(1 == ~E_9~0); 47657#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 47658#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 46606#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 46607#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47219#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47064#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 46886#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 46804#L1822 assume !(0 == start_simulation_~tmp~3#1); 46805#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47753#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47061#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 46557#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 46558#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 47709#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 47807#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 48142#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 46675#L1803-2 [2022-12-13 15:37:44,698 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:44,698 INFO L85 PathProgramCache]: Analyzing trace with hash -2089382286, now seen corresponding path program 1 times [2022-12-13 15:37:44,699 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:44,699 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [503052905] [2022-12-13 15:37:44,699 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:44,699 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:44,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:44,779 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:44,779 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:44,779 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [503052905] [2022-12-13 15:37:44,779 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [503052905] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:44,780 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:44,780 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:44,780 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [422001745] [2022-12-13 15:37:44,780 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:44,780 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:37:44,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:44,781 INFO L85 PathProgramCache]: Analyzing trace with hash -1163217673, now seen corresponding path program 1 times [2022-12-13 15:37:44,781 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:44,781 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1939821910] [2022-12-13 15:37:44,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:44,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:44,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:44,834 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:44,834 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:44,834 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1939821910] [2022-12-13 15:37:44,834 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1939821910] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:44,834 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:44,835 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:44,835 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [357534782] [2022-12-13 15:37:44,835 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:44,835 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:37:44,835 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:37:44,836 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 15:37:44,836 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 15:37:44,836 INFO L87 Difference]: Start difference. First operand 1785 states and 2630 transitions. cyclomatic complexity: 846 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:44,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:37:44,972 INFO L93 Difference]: Finished difference Result 3314 states and 4868 transitions. [2022-12-13 15:37:44,972 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3314 states and 4868 transitions. [2022-12-13 15:37:44,986 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3125 [2022-12-13 15:37:45,003 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3314 states to 3314 states and 4868 transitions. [2022-12-13 15:37:45,004 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3314 [2022-12-13 15:37:45,007 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3314 [2022-12-13 15:37:45,007 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3314 states and 4868 transitions. [2022-12-13 15:37:45,011 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:37:45,011 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3314 states and 4868 transitions. [2022-12-13 15:37:45,015 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3314 states and 4868 transitions. [2022-12-13 15:37:45,060 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3314 to 3314. [2022-12-13 15:37:45,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3314 states, 3314 states have (on average 1.4689197344598672) internal successors, (4868), 3313 states have internal predecessors, (4868), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:45,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3314 states to 3314 states and 4868 transitions. [2022-12-13 15:37:45,070 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3314 states and 4868 transitions. [2022-12-13 15:37:45,071 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 15:37:45,071 INFO L428 stractBuchiCegarLoop]: Abstraction has 3314 states and 4868 transitions. [2022-12-13 15:37:45,071 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-12-13 15:37:45,071 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3314 states and 4868 transitions. [2022-12-13 15:37:45,081 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3125 [2022-12-13 15:37:45,081 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:37:45,081 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:37:45,082 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:45,083 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:45,083 INFO L748 eck$LassoCheckResult]: Stem: 51876#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 51877#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 52822#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 52823#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 51944#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 51945#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51849#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 51850#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53182#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 52488#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 52489#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 52385#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 52386#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 52908#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 52909#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 52142#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 52143#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 52581#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 52582#L1194 assume !(0 == ~M_E~0); 52738#L1194-2 assume !(0 == ~T1_E~0); 52739#L1199-1 assume !(0 == ~T2_E~0); 53045#L1204-1 assume !(0 == ~T3_E~0); 52960#L1209-1 assume !(0 == ~T4_E~0); 52961#L1214-1 assume !(0 == ~T5_E~0); 53418#L1219-1 assume !(0 == ~T6_E~0); 53530#L1224-1 assume !(0 == ~T7_E~0); 52219#L1229-1 assume !(0 == ~T8_E~0); 51774#L1234-1 assume !(0 == ~T9_E~0); 51775#L1239-1 assume !(0 == ~T10_E~0); 51814#L1244-1 assume !(0 == ~T11_E~0); 51815#L1249-1 assume !(0 == ~T12_E~0); 52520#L1254-1 assume !(0 == ~E_M~0); 51708#L1259-1 assume !(0 == ~E_1~0); 51673#L1264-1 assume !(0 == ~E_2~0); 51674#L1269-1 assume !(0 == ~E_3~0); 53534#L1274-1 assume 0 == ~E_4~0;~E_4~0 := 1; 53453#L1279-1 assume !(0 == ~E_5~0); 51885#L1284-1 assume !(0 == ~E_6~0); 51886#L1289-1 assume !(0 == ~E_7~0); 52586#L1294-1 assume !(0 == ~E_8~0); 52587#L1299-1 assume !(0 == ~E_9~0); 52600#L1304-1 assume !(0 == ~E_10~0); 53518#L1309-1 assume !(0 == ~E_11~0); 53524#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 51843#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51763#L586 assume 1 == ~m_pc~0; 51764#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 51834#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52659#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 52046#L1485 assume !(0 != activate_threads_~tmp~1#1); 52047#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53188#L605 assume !(1 == ~t1_pc~0); 52675#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 52413#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52414#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53085#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 53013#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52320#L624 assume 1 == ~t2_pc~0; 51819#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 51820#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52071#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 52072#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 53224#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53083#L643 assume !(1 == ~t3_pc~0); 52927#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 52623#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52624#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52149#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 52150#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51906#L662 assume 1 == ~t4_pc~0; 51907#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 51865#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51728#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51729#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 51754#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51755#L681 assume !(1 == ~t5_pc~0); 51623#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 51624#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 52705#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53372#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 52163#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52164#L700 assume 1 == ~t6_pc~0; 52885#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 51898#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 51899#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51946#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 51947#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53287#L719 assume 1 == ~t7_pc~0; 53387#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 52117#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53514#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53437#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 51637#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 51638#L738 assume !(1 == ~t8_pc~0); 53052#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 52951#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 52952#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 52734#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 52735#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53108#L757 assume 1 == ~t9_pc~0; 53109#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 51632#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51633#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 52115#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 52696#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 52697#L776 assume !(1 == ~t10_pc~0); 51657#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 51656#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52050#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 51887#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 51888#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51844#L795 assume 1 == ~t11_pc~0; 51845#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 52185#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53205#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53405#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 52921#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 52911#L814 assume !(1 == ~t12_pc~0); 52768#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 52769#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 51689#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 51690#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 52099#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52100#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 53237#L1332-2 assume !(1 == ~T1_E~0); 53586#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 53585#L1342-1 assume !(1 == ~T3_E~0); 53584#L1347-1 assume !(1 == ~T4_E~0); 53583#L1352-1 assume !(1 == ~T5_E~0); 53582#L1357-1 assume !(1 == ~T6_E~0); 53581#L1362-1 assume !(1 == ~T7_E~0); 53580#L1367-1 assume !(1 == ~T8_E~0); 53579#L1372-1 assume !(1 == ~T9_E~0); 51986#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 53578#L1382-1 assume !(1 == ~T11_E~0); 53577#L1387-1 assume !(1 == ~T12_E~0); 53576#L1392-1 assume !(1 == ~E_M~0); 53575#L1397-1 assume !(1 == ~E_1~0); 53574#L1402-1 assume !(1 == ~E_2~0); 53573#L1407-1 assume !(1 == ~E_3~0); 53572#L1412-1 assume !(1 == ~E_4~0); 53571#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 53570#L1422-1 assume !(1 == ~E_6~0); 53569#L1427-1 assume !(1 == ~E_7~0); 53568#L1432-1 assume !(1 == ~E_8~0); 53567#L1437-1 assume !(1 == ~E_9~0); 53566#L1442-1 assume !(1 == ~E_10~0); 53565#L1447-1 assume !(1 == ~E_11~0); 53564#L1452-1 assume !(1 == ~E_12~0); 53563#L1457-1 assume { :end_inline_reset_delta_events } true; 53561#L1803-2 [2022-12-13 15:37:45,084 INFO L750 eck$LassoCheckResult]: Loop: 53561#L1803-2 assume !false; 52123#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 51654#L1169 assume !false; 52364#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 52365#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 51851#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 51852#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 53247#L996 assume !(0 != eval_~tmp~0#1); 53249#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 52239#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 52240#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 53521#L1194-5 assume !(0 == ~T1_E~0); 51954#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 51955#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 52213#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 51650#L1214-3 assume !(0 == ~T5_E~0); 51651#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 52411#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 52412#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 52452#L1234-3 assume !(0 == ~T9_E~0); 51822#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 51823#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 52262#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 52862#L1254-3 assume !(0 == ~E_M~0); 53410#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 52982#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 51828#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 51829#L1274-3 assume 0 == ~E_4~0;~E_4~0 := 1; 53449#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 52409#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 52410#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 52391#L1294-3 assume !(0 == ~E_8~0); 52392#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 52793#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 52794#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 52296#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 52297#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52299#L586-42 assume !(1 == ~m_pc~0); 52300#L586-44 is_master_triggered_~__retres1~0#1 := 0; 51893#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51894#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 52366#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 52439#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52440#L605-42 assume 1 == ~t1_pc~0; 53057#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 52760#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52761#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 52441#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52442#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52449#L624-42 assume !(1 == ~t2_pc~0); 52450#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 52596#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52694#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 52695#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 52260#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52261#L643-42 assume 1 == ~t3_pc~0; 52619#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 52575#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52576#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52407#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 52408#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53159#L662-42 assume !(1 == ~t4_pc~0); 53395#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 51917#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51918#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53132#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 53442#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53404#L681-42 assume !(1 == ~t5_pc~0); 51779#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 51780#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 52786#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 52787#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 53212#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52280#L700-42 assume !(1 == ~t6_pc~0); 52086#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 52087#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52011#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 52012#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 53219#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53460#L719-42 assume !(1 == ~t7_pc~0); 51971#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 51972#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 52351#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 52616#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 52367#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52368#L738-42 assume 1 == ~t8_pc~0; 52565#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 52311#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 52312#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51826#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 51827#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 52360#L757-42 assume 1 == ~t9_pc~0; 52707#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52013#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 52014#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 52773#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 52127#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 52128#L776-42 assume !(1 == ~t10_pc~0); 53122#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 53123#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52922#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 52923#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53512#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 52948#L795-42 assume !(1 == ~t11_pc~0); 52949#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 51966#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 51967#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 52066#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 52067#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 52377#L814-42 assume !(1 == ~t12_pc~0); 52243#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 51874#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 51875#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 51681#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 51682#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51838#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 51839#L1332-5 assume !(1 == ~T1_E~0); 51812#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 51813#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 52648#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 52826#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 52827#L1357-3 assume !(1 == ~T6_E~0); 53308#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 53522#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 53516#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 51664#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 51665#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 52277#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 52278#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 53154#L1397-3 assume !(1 == ~E_1~0); 53476#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 52775#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 51922#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 51923#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 52670#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 52671#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 53305#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 53037#L1437-3 assume !(1 == ~E_9~0); 52795#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 52796#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 51715#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 51716#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 53538#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 54781#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 54780#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 54779#L1822 assume !(0 == start_simulation_~tmp~3#1); 53112#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 53599#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 53591#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 53590#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 53589#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 53588#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 53587#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 53562#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 53561#L1803-2 [2022-12-13 15:37:45,084 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:45,084 INFO L85 PathProgramCache]: Analyzing trace with hash 1144190578, now seen corresponding path program 1 times [2022-12-13 15:37:45,084 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:45,084 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [392954276] [2022-12-13 15:37:45,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:45,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:45,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:45,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:45,148 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:45,148 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [392954276] [2022-12-13 15:37:45,148 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [392954276] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:45,148 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:45,148 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:45,148 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [483512562] [2022-12-13 15:37:45,148 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:45,149 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:37:45,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:45,149 INFO L85 PathProgramCache]: Analyzing trace with hash 699200506, now seen corresponding path program 1 times [2022-12-13 15:37:45,150 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:45,150 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [816174100] [2022-12-13 15:37:45,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:45,150 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:45,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:45,186 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:45,186 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:45,186 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [816174100] [2022-12-13 15:37:45,186 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [816174100] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:45,186 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:45,186 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:45,186 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2141542588] [2022-12-13 15:37:45,187 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:45,187 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:37:45,187 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:37:45,187 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 15:37:45,187 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 15:37:45,188 INFO L87 Difference]: Start difference. First operand 3314 states and 4868 transitions. cyclomatic complexity: 1556 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:45,355 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:37:45,356 INFO L93 Difference]: Finished difference Result 6162 states and 9033 transitions. [2022-12-13 15:37:45,356 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6162 states and 9033 transitions. [2022-12-13 15:37:45,380 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5945 [2022-12-13 15:37:45,400 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6162 states to 6162 states and 9033 transitions. [2022-12-13 15:37:45,400 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6162 [2022-12-13 15:37:45,405 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6162 [2022-12-13 15:37:45,405 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6162 states and 9033 transitions. [2022-12-13 15:37:45,411 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:37:45,411 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6162 states and 9033 transitions. [2022-12-13 15:37:45,418 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6162 states and 9033 transitions. [2022-12-13 15:37:45,508 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6162 to 6160. [2022-12-13 15:37:45,514 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6160 states, 6160 states have (on average 1.4660714285714285) internal successors, (9031), 6159 states have internal predecessors, (9031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:45,523 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6160 states to 6160 states and 9031 transitions. [2022-12-13 15:37:45,523 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6160 states and 9031 transitions. [2022-12-13 15:37:45,524 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 15:37:45,524 INFO L428 stractBuchiCegarLoop]: Abstraction has 6160 states and 9031 transitions. [2022-12-13 15:37:45,524 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-12-13 15:37:45,524 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6160 states and 9031 transitions. [2022-12-13 15:37:45,537 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5945 [2022-12-13 15:37:45,538 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:37:45,538 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:37:45,539 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:45,539 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:45,539 INFO L748 eck$LassoCheckResult]: Stem: 61360#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 61361#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 62296#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 62297#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 61431#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 61432#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 61335#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 61336#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 62643#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 61974#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 61975#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 61871#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 61872#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 62381#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 62382#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 61626#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 61627#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 62063#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 62064#L1194 assume !(0 == ~M_E~0); 62217#L1194-2 assume !(0 == ~T1_E~0); 62218#L1199-1 assume !(0 == ~T2_E~0); 62509#L1204-1 assume !(0 == ~T3_E~0); 62432#L1209-1 assume !(0 == ~T4_E~0); 62433#L1214-1 assume !(0 == ~T5_E~0); 62875#L1219-1 assume !(0 == ~T6_E~0); 62999#L1224-1 assume !(0 == ~T7_E~0); 61699#L1229-1 assume !(0 == ~T8_E~0); 61252#L1234-1 assume !(0 == ~T9_E~0); 61253#L1239-1 assume !(0 == ~T10_E~0); 61297#L1244-1 assume !(0 == ~T11_E~0); 61298#L1249-1 assume !(0 == ~T12_E~0); 62004#L1254-1 assume !(0 == ~E_M~0); 61194#L1259-1 assume !(0 == ~E_1~0); 61159#L1264-1 assume !(0 == ~E_2~0); 61160#L1269-1 assume !(0 == ~E_3~0); 63002#L1274-1 assume !(0 == ~E_4~0); 62917#L1279-1 assume !(0 == ~E_5~0); 61371#L1284-1 assume !(0 == ~E_6~0); 61372#L1289-1 assume !(0 == ~E_7~0); 62070#L1294-1 assume !(0 == ~E_8~0); 62071#L1299-1 assume !(0 == ~E_9~0); 62082#L1304-1 assume !(0 == ~E_10~0); 62987#L1309-1 assume !(0 == ~E_11~0); 62995#L1314-1 assume 0 == ~E_12~0;~E_12~0 := 1; 61328#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61249#L586 assume 1 == ~m_pc~0; 61250#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 61319#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62143#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 61531#L1485 assume !(0 != activate_threads_~tmp~1#1); 61532#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 62649#L605 assume !(1 == ~t1_pc~0); 62157#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 61898#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61899#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 62548#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62482#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61806#L624 assume 1 == ~t2_pc~0; 61301#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 61302#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61555#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 61556#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 62682#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62546#L643 assume !(1 == ~t3_pc~0); 62401#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 62100#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62101#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 61633#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 61634#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 61392#L662 assume 1 == ~t4_pc~0; 61393#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 61351#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61211#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 61212#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 61238#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 61239#L681 assume !(1 == ~t5_pc~0); 61109#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 61110#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62184#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 62821#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 61645#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 61646#L700 assume 1 == ~t6_pc~0; 62361#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 61384#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 61385#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 61433#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 61434#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62744#L719 assume 1 == ~t7_pc~0; 62835#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 61601#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62978#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 62903#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 61123#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 61124#L738 assume !(1 == ~t8_pc~0); 62516#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 62423#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 62424#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 62213#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 62214#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 62573#L757 assume 1 == ~t9_pc~0; 62574#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 61118#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 61119#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 61599#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 62176#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 62177#L776 assume !(1 == ~t10_pc~0); 61143#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 61142#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 61535#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 61373#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 61374#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 61329#L795 assume 1 == ~t11_pc~0; 61330#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 61665#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 62664#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 62861#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 62395#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 62384#L814 assume !(1 == ~t12_pc~0); 62244#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 62245#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 61172#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 61173#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 61583#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 61584#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 62698#L1332-2 assume !(1 == ~T1_E~0); 63915#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 63914#L1342-1 assume !(1 == ~T3_E~0); 63913#L1347-1 assume !(1 == ~T4_E~0); 63912#L1352-1 assume !(1 == ~T5_E~0); 63911#L1357-1 assume !(1 == ~T6_E~0); 61869#L1362-1 assume !(1 == ~T7_E~0); 61870#L1367-1 assume !(1 == ~T8_E~0); 62780#L1372-1 assume !(1 == ~T9_E~0); 63868#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 63866#L1382-1 assume !(1 == ~T11_E~0); 63865#L1387-1 assume !(1 == ~T12_E~0); 62891#L1392-1 assume !(1 == ~E_M~0); 62892#L1397-1 assume !(1 == ~E_1~0); 63798#L1402-1 assume !(1 == ~E_2~0); 63767#L1407-1 assume !(1 == ~E_3~0); 63765#L1412-1 assume !(1 == ~E_4~0); 63362#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 63142#L1422-1 assume !(1 == ~E_6~0); 63109#L1427-1 assume !(1 == ~E_7~0); 63095#L1432-1 assume !(1 == ~E_8~0); 63093#L1437-1 assume !(1 == ~E_9~0); 63077#L1442-1 assume !(1 == ~E_10~0); 63066#L1447-1 assume !(1 == ~E_11~0); 63058#L1452-1 assume !(1 == ~E_12~0); 63051#L1457-1 assume { :end_inline_reset_delta_events } true; 63045#L1803-2 [2022-12-13 15:37:45,540 INFO L750 eck$LassoCheckResult]: Loop: 63045#L1803-2 assume !false; 63039#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 63034#L1169 assume !false; 63033#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 63030#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 63019#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 63018#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 63016#L996 assume !(0 != eval_~tmp~0#1); 63015#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 63014#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 63012#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 63013#L1194-5 assume !(0 == ~T1_E~0); 67144#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 67142#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 67140#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 67138#L1214-3 assume !(0 == ~T5_E~0); 67136#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 67134#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 67131#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 67129#L1234-3 assume !(0 == ~T9_E~0); 67127#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 67125#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 65967#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 65964#L1254-3 assume !(0 == ~E_M~0); 65961#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 65957#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 65952#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 65948#L1274-3 assume !(0 == ~E_4~0); 65943#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 65937#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 65932#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 65927#L1294-3 assume !(0 == ~E_8~0); 65921#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 65916#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 65911#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 65905#L1314-3 assume 0 == ~E_12~0;~E_12~0 := 1; 65900#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 65896#L586-42 assume !(1 == ~m_pc~0); 65877#L586-44 is_master_triggered_~__retres1~0#1 := 0; 65873#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65871#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 65858#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 65827#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65826#L605-42 assume !(1 == ~t1_pc~0); 65823#L605-44 is_transmit1_triggered_~__retres1~1#1 := 0; 65820#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65774#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 65771#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 65769#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65767#L624-42 assume !(1 == ~t2_pc~0); 65765#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 65764#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65763#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65723#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 65722#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65721#L643-42 assume !(1 == ~t3_pc~0); 65673#L643-44 is_transmit3_triggered_~__retres1~3#1 := 0; 62061#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62062#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 61892#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 61893#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62619#L662-42 assume !(1 == ~t4_pc~0); 62850#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 61403#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61404#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 62597#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 62907#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62862#L681-42 assume !(1 == ~t5_pc~0); 61265#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 61266#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62262#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 62263#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 62671#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 61765#L700-42 assume !(1 == ~t6_pc~0); 61570#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 61571#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 61497#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 61498#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 62678#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62925#L719-42 assume !(1 == ~t7_pc~0); 61457#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 61458#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 61836#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 62099#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 61851#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 61852#L738-42 assume 1 == ~t8_pc~0; 62050#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 61797#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 61798#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 61311#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 61312#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 61845#L757-42 assume 1 == ~t9_pc~0; 62189#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 61499#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 61500#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 62249#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 61612#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 61613#L776-42 assume !(1 == ~t10_pc~0); 62589#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 62590#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 62396#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 62397#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 62976#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 62420#L795-42 assume !(1 == ~t11_pc~0); 62421#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 61452#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 61453#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 61550#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 61551#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 61862#L814-42 assume 1 == ~t12_pc~0; 62652#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 61362#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 61363#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 63976#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 63974#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 63973#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 61324#L1332-5 assume !(1 == ~T1_E~0); 63970#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 63968#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 63966#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 63964#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 63963#L1357-3 assume !(1 == ~T6_E~0); 63910#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 63909#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 63908#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 62981#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 63864#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 63827#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 63792#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 63790#L1397-3 assume !(1 == ~E_1~0); 63788#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 63762#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 63359#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 63355#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 63353#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 63350#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 63345#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 63342#L1437-3 assume !(1 == ~E_9~0); 63339#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 63336#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 63333#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 63330#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 63324#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 63310#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 63307#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 63304#L1822 assume !(0 == start_simulation_~tmp~3#1); 62577#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 63134#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 63107#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 63092#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 63076#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 63065#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 63057#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 63050#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 63045#L1803-2 [2022-12-13 15:37:45,540 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:45,540 INFO L85 PathProgramCache]: Analyzing trace with hash -1221844492, now seen corresponding path program 1 times [2022-12-13 15:37:45,540 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:45,540 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1312828259] [2022-12-13 15:37:45,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:45,540 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:45,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:45,588 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:45,588 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:45,588 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1312828259] [2022-12-13 15:37:45,588 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1312828259] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:45,589 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:45,589 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:45,589 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1100801528] [2022-12-13 15:37:45,589 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:45,589 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:37:45,590 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:45,590 INFO L85 PathProgramCache]: Analyzing trace with hash -247314627, now seen corresponding path program 1 times [2022-12-13 15:37:45,590 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:45,590 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1950708143] [2022-12-13 15:37:45,590 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:45,590 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:45,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:45,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:45,628 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:45,628 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1950708143] [2022-12-13 15:37:45,628 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1950708143] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:45,628 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:45,628 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:45,629 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [471167734] [2022-12-13 15:37:45,629 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:45,629 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:37:45,629 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:37:45,629 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 15:37:45,630 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 15:37:45,630 INFO L87 Difference]: Start difference. First operand 6160 states and 9031 transitions. cyclomatic complexity: 2875 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:45,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:37:45,790 INFO L93 Difference]: Finished difference Result 11630 states and 17014 transitions. [2022-12-13 15:37:45,791 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11630 states and 17014 transitions. [2022-12-13 15:37:45,817 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11399 [2022-12-13 15:37:45,837 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11630 states to 11630 states and 17014 transitions. [2022-12-13 15:37:45,838 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11630 [2022-12-13 15:37:45,842 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11630 [2022-12-13 15:37:45,843 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11630 states and 17014 transitions. [2022-12-13 15:37:45,848 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:37:45,848 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11630 states and 17014 transitions. [2022-12-13 15:37:45,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11630 states and 17014 transitions. [2022-12-13 15:37:45,954 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11630 to 11626. [2022-12-13 15:37:45,965 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11626 states, 11626 states have (on average 1.4630999483915361) internal successors, (17010), 11625 states have internal predecessors, (17010), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:46,011 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11626 states to 11626 states and 17010 transitions. [2022-12-13 15:37:46,011 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11626 states and 17010 transitions. [2022-12-13 15:37:46,012 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 15:37:46,012 INFO L428 stractBuchiCegarLoop]: Abstraction has 11626 states and 17010 transitions. [2022-12-13 15:37:46,012 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-12-13 15:37:46,012 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11626 states and 17010 transitions. [2022-12-13 15:37:46,031 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11399 [2022-12-13 15:37:46,031 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:37:46,031 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:37:46,032 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:46,032 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:46,033 INFO L748 eck$LassoCheckResult]: Stem: 79160#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 79161#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 80130#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 80131#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 79230#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 79231#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 79135#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 79136#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 80510#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 79782#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 79783#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 79675#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 79676#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 80221#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 80222#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 79428#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 79429#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 79875#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 79876#L1194 assume !(0 == ~M_E~0); 80039#L1194-2 assume !(0 == ~T1_E~0); 80040#L1199-1 assume !(0 == ~T2_E~0); 80355#L1204-1 assume !(0 == ~T3_E~0); 80273#L1209-1 assume !(0 == ~T4_E~0); 80274#L1214-1 assume !(0 == ~T5_E~0); 80765#L1219-1 assume !(0 == ~T6_E~0); 80914#L1224-1 assume !(0 == ~T7_E~0); 79503#L1229-1 assume !(0 == ~T8_E~0); 79052#L1234-1 assume !(0 == ~T9_E~0); 79053#L1239-1 assume !(0 == ~T10_E~0); 79097#L1244-1 assume !(0 == ~T11_E~0); 79098#L1249-1 assume !(0 == ~T12_E~0); 79815#L1254-1 assume !(0 == ~E_M~0); 78994#L1259-1 assume !(0 == ~E_1~0); 78959#L1264-1 assume !(0 == ~E_2~0); 78960#L1269-1 assume !(0 == ~E_3~0); 80926#L1274-1 assume !(0 == ~E_4~0); 80812#L1279-1 assume !(0 == ~E_5~0); 79171#L1284-1 assume !(0 == ~E_6~0); 79172#L1289-1 assume !(0 == ~E_7~0); 79883#L1294-1 assume !(0 == ~E_8~0); 79884#L1299-1 assume !(0 == ~E_9~0); 79896#L1304-1 assume !(0 == ~E_10~0); 80900#L1309-1 assume !(0 == ~E_11~0); 80909#L1314-1 assume !(0 == ~E_12~0); 79128#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 79049#L586 assume 1 == ~m_pc~0; 79050#L587 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 79119#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 79961#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 79332#L1485 assume !(0 != activate_threads_~tmp~1#1); 79333#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 80521#L605 assume !(1 == ~t1_pc~0); 79976#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 79705#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 79706#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 80411#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 80326#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 79610#L624 assume 1 == ~t2_pc~0; 79101#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 79102#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 79357#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 79358#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 80562#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 80409#L643 assume !(1 == ~t3_pc~0); 80242#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 79916#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 79917#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 79435#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 79436#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 79192#L662 assume 1 == ~t4_pc~0; 79193#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 79151#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 79011#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 79012#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 79038#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 79039#L681 assume !(1 == ~t5_pc~0); 78909#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 78910#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 80004#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 80713#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 79447#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 79448#L700 assume 1 == ~t6_pc~0; 80201#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 79184#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 79185#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 79232#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 79233#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 80628#L719 assume 1 == ~t7_pc~0; 80725#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 79403#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 80888#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 80786#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 78923#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 78924#L738 assume !(1 == ~t8_pc~0); 80364#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 80264#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 80265#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 80035#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 80036#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 80432#L757 assume 1 == ~t9_pc~0; 80433#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 78918#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 78919#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 79401#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 79996#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 79997#L776 assume !(1 == ~t10_pc~0); 78943#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 78942#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 79336#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 79173#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 79174#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 79129#L795 assume 1 == ~t11_pc~0; 79130#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 79468#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 80540#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 80746#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 80236#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 80226#L814 assume !(1 == ~t12_pc~0); 80070#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 80071#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 78972#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 78973#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 79385#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 79386#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 80576#L1332-2 assume !(1 == ~T1_E~0); 80844#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 80147#L1342-1 assume !(1 == ~T3_E~0); 80148#L1347-1 assume !(1 == ~T4_E~0); 80614#L1352-1 assume !(1 == ~T5_E~0); 80615#L1357-1 assume !(1 == ~T6_E~0); 79673#L1362-1 assume !(1 == ~T7_E~0); 79674#L1367-1 assume !(1 == ~T8_E~0); 79270#L1372-1 assume !(1 == ~T9_E~0); 79271#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 83850#L1382-1 assume !(1 == ~T11_E~0); 83845#L1387-1 assume !(1 == ~T12_E~0); 83840#L1392-1 assume !(1 == ~E_M~0); 83835#L1397-1 assume !(1 == ~E_1~0); 83830#L1402-1 assume !(1 == ~E_2~0); 83825#L1407-1 assume !(1 == ~E_3~0); 83820#L1412-1 assume !(1 == ~E_4~0); 83815#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 83810#L1422-1 assume !(1 == ~E_6~0); 81869#L1427-1 assume !(1 == ~E_7~0); 81863#L1432-1 assume !(1 == ~E_8~0); 81007#L1437-1 assume !(1 == ~E_9~0); 81005#L1442-1 assume !(1 == ~E_10~0); 81004#L1447-1 assume !(1 == ~E_11~0); 81003#L1452-1 assume !(1 == ~E_12~0); 80990#L1457-1 assume { :end_inline_reset_delta_events } true; 80982#L1803-2 [2022-12-13 15:37:46,033 INFO L750 eck$LassoCheckResult]: Loop: 80982#L1803-2 assume !false; 80976#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 80971#L1169 assume !false; 80970#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 80967#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 80956#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 80955#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 80953#L996 assume !(0 != eval_~tmp~0#1); 80952#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 80951#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 80949#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 80950#L1194-5 assume !(0 == ~T1_E~0); 89202#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 89198#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 89191#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 89187#L1214-3 assume !(0 == ~T5_E~0); 89183#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 89181#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 88969#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 88966#L1234-3 assume !(0 == ~T9_E~0); 88964#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 88962#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 88960#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 88958#L1254-3 assume !(0 == ~E_M~0); 88956#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 88953#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 88951#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 88948#L1274-3 assume !(0 == ~E_4~0); 88946#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 88944#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 88942#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 88940#L1294-3 assume !(0 == ~E_8~0); 88938#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 88935#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 88933#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 88931#L1314-3 assume !(0 == ~E_12~0); 88912#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88905#L586-42 assume 1 == ~m_pc~0; 88897#L587-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 88884#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 88876#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 88866#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 88858#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88695#L605-42 assume 1 == ~t1_pc~0; 88691#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 88689#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88687#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 88685#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 88683#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88681#L624-42 assume 1 == ~t2_pc~0; 88677#L625-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 88674#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 88672#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 88670#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 88668#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 88665#L643-42 assume !(1 == ~t3_pc~0); 88663#L643-44 is_transmit3_triggered_~__retres1~3#1 := 0; 88660#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88658#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 88656#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 88654#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88651#L662-42 assume !(1 == ~t4_pc~0); 88629#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 88620#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 88613#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 88600#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 88599#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 88598#L681-42 assume !(1 == ~t5_pc~0); 88595#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 88583#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 88572#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 88563#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 88557#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 88553#L700-42 assume !(1 == ~t6_pc~0); 88493#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 88485#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 88476#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 88468#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 88463#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 88457#L719-42 assume !(1 == ~t7_pc~0); 88451#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 88443#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 88435#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 88428#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 88422#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 88416#L738-42 assume !(1 == ~t8_pc~0); 88411#L738-44 is_transmit8_triggered_~__retres1~8#1 := 0; 88177#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 88174#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 88172#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 88170#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 88168#L757-42 assume 1 == ~t9_pc~0; 88165#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 88163#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 88160#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 88158#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 88156#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 88154#L776-42 assume !(1 == ~t10_pc~0); 88151#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 88147#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 88145#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 88143#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 88141#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 88139#L795-42 assume 1 == ~t11_pc~0; 88065#L796-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 88061#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 88059#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 88048#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 88041#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 88035#L814-42 assume !(1 == ~t12_pc~0); 88029#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 88025#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 88023#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 88021#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 88019#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 88017#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 79124#L1332-5 assume !(1 == ~T1_E~0); 88014#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 88012#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 88010#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 88008#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 88006#L1357-3 assume !(1 == ~T6_E~0); 88004#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 88002#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 88000#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 80893#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 87988#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 87982#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 87977#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 87971#L1397-3 assume !(1 == ~E_1~0); 87964#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 87958#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 87950#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 82712#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 87939#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 87933#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 87926#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 87920#L1437-3 assume !(1 == ~E_9~0); 87912#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 87905#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 87866#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 87862#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 87350#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 87337#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 87335#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 87332#L1822 assume !(0 == start_simulation_~tmp~3#1); 80436#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 81877#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 81864#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 81858#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 81853#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 81279#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 81000#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 80989#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 80982#L1803-2 [2022-12-13 15:37:46,033 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:46,033 INFO L85 PathProgramCache]: Analyzing trace with hash 931262326, now seen corresponding path program 1 times [2022-12-13 15:37:46,033 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:46,033 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [440267104] [2022-12-13 15:37:46,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:46,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:46,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:46,080 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:46,080 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:46,080 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [440267104] [2022-12-13 15:37:46,080 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [440267104] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:46,080 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:46,080 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 15:37:46,080 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [916338443] [2022-12-13 15:37:46,080 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:46,081 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:37:46,081 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:46,081 INFO L85 PathProgramCache]: Analyzing trace with hash 405454013, now seen corresponding path program 1 times [2022-12-13 15:37:46,081 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:46,081 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [23098966] [2022-12-13 15:37:46,082 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:46,082 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:46,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:46,117 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:46,117 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:46,118 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [23098966] [2022-12-13 15:37:46,118 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [23098966] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:46,118 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:46,118 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:46,118 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2126063706] [2022-12-13 15:37:46,118 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:46,118 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:37:46,118 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:37:46,119 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:37:46,119 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:37:46,119 INFO L87 Difference]: Start difference. First operand 11626 states and 17010 transitions. cyclomatic complexity: 5392 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:46,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:37:46,286 INFO L93 Difference]: Finished difference Result 22895 states and 33292 transitions. [2022-12-13 15:37:46,286 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22895 states and 33292 transitions. [2022-12-13 15:37:46,367 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22661 [2022-12-13 15:37:46,422 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22895 states to 22895 states and 33292 transitions. [2022-12-13 15:37:46,423 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22895 [2022-12-13 15:37:46,434 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22895 [2022-12-13 15:37:46,435 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22895 states and 33292 transitions. [2022-12-13 15:37:46,450 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:37:46,451 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22895 states and 33292 transitions. [2022-12-13 15:37:46,464 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22895 states and 33292 transitions. [2022-12-13 15:37:46,676 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22895 to 22175. [2022-12-13 15:37:46,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22175 states, 22175 states have (on average 1.4555129650507328) internal successors, (32276), 22174 states have internal predecessors, (32276), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:46,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22175 states to 22175 states and 32276 transitions. [2022-12-13 15:37:46,736 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22175 states and 32276 transitions. [2022-12-13 15:37:46,736 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:37:46,737 INFO L428 stractBuchiCegarLoop]: Abstraction has 22175 states and 32276 transitions. [2022-12-13 15:37:46,737 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-12-13 15:37:46,737 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22175 states and 32276 transitions. [2022-12-13 15:37:46,783 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21941 [2022-12-13 15:37:46,783 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:37:46,783 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:37:46,784 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:46,784 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:46,784 INFO L748 eck$LassoCheckResult]: Stem: 113689#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 113690#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 114672#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 114673#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 113759#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 113760#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 113662#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 113663#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 115084#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 114318#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 114319#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 114206#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 114207#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 114768#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 114769#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 113955#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 113956#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 114415#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 114416#L1194 assume !(0 == ~M_E~0); 114577#L1194-2 assume !(0 == ~T1_E~0); 114578#L1199-1 assume !(0 == ~T2_E~0); 114927#L1204-1 assume !(0 == ~T3_E~0); 114828#L1209-1 assume !(0 == ~T4_E~0); 114829#L1214-1 assume !(0 == ~T5_E~0); 115408#L1219-1 assume !(0 == ~T6_E~0); 115636#L1224-1 assume !(0 == ~T7_E~0); 114035#L1229-1 assume !(0 == ~T8_E~0); 113587#L1234-1 assume !(0 == ~T9_E~0); 113588#L1239-1 assume !(0 == ~T10_E~0); 113625#L1244-1 assume !(0 == ~T11_E~0); 113626#L1249-1 assume !(0 == ~T12_E~0); 114349#L1254-1 assume !(0 == ~E_M~0); 113522#L1259-1 assume !(0 == ~E_1~0); 113487#L1264-1 assume !(0 == ~E_2~0); 113488#L1269-1 assume !(0 == ~E_3~0); 115649#L1274-1 assume !(0 == ~E_4~0); 115469#L1279-1 assume !(0 == ~E_5~0); 113698#L1284-1 assume !(0 == ~E_6~0); 113699#L1289-1 assume !(0 == ~E_7~0); 114424#L1294-1 assume !(0 == ~E_8~0); 114425#L1299-1 assume !(0 == ~E_9~0); 114436#L1304-1 assume !(0 == ~E_10~0); 115617#L1309-1 assume !(0 == ~E_11~0); 115630#L1314-1 assume !(0 == ~E_12~0); 113656#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 113577#L586 assume !(1 == ~m_pc~0); 113578#L586-2 is_master_triggered_~__retres1~0#1 := 0; 113645#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 114500#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 113860#L1485 assume !(0 != activate_threads_~tmp~1#1); 113861#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 115090#L605 assume !(1 == ~t1_pc~0); 114514#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 114237#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 114238#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 114977#L1493 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 114895#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 114137#L624 assume 1 == ~t2_pc~0; 113630#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 113631#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 113884#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 113885#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 115142#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 114975#L643 assume !(1 == ~t3_pc~0); 114795#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 114462#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 114463#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 113962#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 113963#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 113719#L662 assume 1 == ~t4_pc~0; 113720#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 113678#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 113542#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 113543#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 113568#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 113569#L681 assume !(1 == ~t5_pc~0); 113437#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 113438#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 114542#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 115347#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 113977#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 113978#L700 assume 1 == ~t6_pc~0; 114744#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 113710#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 113711#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 113761#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 113762#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 115225#L719 assume 1 == ~t7_pc~0; 115370#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 113932#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 115603#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 115445#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 113451#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 113452#L738 assume !(1 == ~t8_pc~0); 114934#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 114819#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 114820#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 114573#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 114574#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 115003#L757 assume 1 == ~t9_pc~0; 115004#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 113446#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 113447#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 113929#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 114534#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 114535#L776 assume !(1 == ~t10_pc~0); 113471#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 113470#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 113867#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 113700#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 113701#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 113657#L795 assume 1 == ~t11_pc~0; 113658#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 114000#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 115116#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 115395#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 114786#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 114771#L814 assume !(1 == ~t12_pc~0); 114606#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 114607#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 113503#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 113504#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 113913#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 113914#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 115161#L1332-2 assume !(1 == ~T1_E~0); 115517#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 114692#L1342-1 assume !(1 == ~T3_E~0); 114693#L1347-1 assume !(1 == ~T4_E~0); 115204#L1352-1 assume !(1 == ~T5_E~0); 115205#L1357-1 assume !(1 == ~T6_E~0); 114204#L1362-1 assume !(1 == ~T7_E~0); 114205#L1367-1 assume !(1 == ~T8_E~0); 113799#L1372-1 assume !(1 == ~T9_E~0); 113800#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 114112#L1382-1 assume !(1 == ~T11_E~0); 114113#L1387-1 assume !(1 == ~T12_E~0); 114892#L1392-1 assume !(1 == ~E_M~0); 114138#L1397-1 assume !(1 == ~E_1~0); 114139#L1402-1 assume !(1 == ~E_2~0); 115520#L1407-1 assume !(1 == ~E_3~0); 117034#L1412-1 assume !(1 == ~E_4~0); 117032#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 117030#L1422-1 assume !(1 == ~E_6~0); 117013#L1427-1 assume !(1 == ~E_7~0); 116994#L1432-1 assume !(1 == ~E_8~0); 116992#L1437-1 assume !(1 == ~E_9~0); 116978#L1442-1 assume !(1 == ~E_10~0); 116974#L1447-1 assume !(1 == ~E_11~0); 116960#L1452-1 assume !(1 == ~E_12~0); 116944#L1457-1 assume { :end_inline_reset_delta_events } true; 116936#L1803-2 [2022-12-13 15:37:46,784 INFO L750 eck$LassoCheckResult]: Loop: 116936#L1803-2 assume !false; 116930#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 116925#L1169 assume !false; 116924#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 116921#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 116910#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 116909#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 116907#L996 assume !(0 != eval_~tmp~0#1); 116906#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 116905#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 116902#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 116901#L1194-5 assume !(0 == ~T1_E~0); 113768#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 113769#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 114028#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 114029#L1214-3 assume !(0 == ~T5_E~0); 116897#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 116896#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 116895#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 116894#L1234-3 assume !(0 == ~T9_E~0); 116893#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 116840#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 114718#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 114719#L1254-3 assume !(0 == ~E_M~0); 115560#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 116660#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 116659#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 116658#L1274-3 assume !(0 == ~E_4~0); 116657#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 116655#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 116654#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 116653#L1294-3 assume !(0 == ~E_8~0); 116652#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 116651#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 116650#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 116649#L1314-3 assume !(0 == ~E_12~0); 116648#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 114122#L586-42 assume !(1 == ~m_pc~0); 114123#L586-44 is_master_triggered_~__retres1~0#1 := 0; 125706#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 125705#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 125704#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 125325#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 125324#L605-42 assume !(1 == ~t1_pc~0); 125323#L605-44 is_transmit1_triggered_~__retres1~1#1 := 0; 125321#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 125320#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 125319#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 125317#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 125315#L624-42 assume 1 == ~t2_pc~0; 125313#L625-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 125310#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 125308#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 125306#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 125304#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 125302#L643-42 assume 1 == ~t3_pc~0; 125299#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 125297#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 125295#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 125293#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 125291#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 125289#L662-42 assume 1 == ~t4_pc~0; 125287#L663-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 125284#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 125282#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 125280#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 125278#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 125276#L681-42 assume 1 == ~t5_pc~0; 125273#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 125271#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 125269#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 124727#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 124723#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 124719#L700-42 assume !(1 == ~t6_pc~0); 124717#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 124676#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 124675#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 124674#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 124673#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 124672#L719-42 assume 1 == ~t7_pc~0; 124665#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 124663#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 124661#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 124659#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 124657#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 124654#L738-42 assume 1 == ~t8_pc~0; 124651#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 124649#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 124647#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 124645#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 124643#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 124640#L757-42 assume 1 == ~t9_pc~0; 124637#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 120981#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 117988#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 117985#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 117935#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 117933#L776-42 assume !(1 == ~t10_pc~0); 117931#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 117876#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 117873#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 117831#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 117829#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 117794#L795-42 assume 1 == ~t11_pc~0; 117792#L796-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 117789#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 117750#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 117686#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 117683#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 117624#L814-42 assume 1 == ~t12_pc~0; 117621#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 117551#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 117549#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 117547#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 117545#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 117494#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 117403#L1332-5 assume !(1 == ~T1_E~0); 117489#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 117434#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 117379#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 117337#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 117306#L1357-3 assume !(1 == ~T6_E~0); 117304#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 117278#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 117276#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 117250#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 117220#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 117218#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 117217#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 117215#L1397-3 assume !(1 == ~E_1~0); 117213#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 117212#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 117211#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 117207#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 117205#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 117203#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 117202#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 117201#L1437-3 assume !(1 == ~E_9~0); 117199#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 117196#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 117194#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 117190#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 117158#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 117122#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 117121#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 117120#L1822 assume !(0 == start_simulation_~tmp~3#1); 116167#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 117057#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 117027#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 117008#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 116986#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 116971#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 116957#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 116943#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 116936#L1803-2 [2022-12-13 15:37:46,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:46,785 INFO L85 PathProgramCache]: Analyzing trace with hash 1218722231, now seen corresponding path program 1 times [2022-12-13 15:37:46,785 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:46,785 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1679500627] [2022-12-13 15:37:46,785 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:46,785 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:46,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:46,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:46,866 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:46,866 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1679500627] [2022-12-13 15:37:46,866 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1679500627] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:46,866 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:46,866 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 15:37:46,867 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [854617113] [2022-12-13 15:37:46,867 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:46,867 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:37:46,867 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:46,867 INFO L85 PathProgramCache]: Analyzing trace with hash -1673550535, now seen corresponding path program 1 times [2022-12-13 15:37:46,868 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:46,868 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1507279103] [2022-12-13 15:37:46,868 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:46,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:46,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:46,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:46,920 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:46,920 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1507279103] [2022-12-13 15:37:46,920 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1507279103] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:46,920 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:46,920 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:46,920 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1187118410] [2022-12-13 15:37:46,920 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:46,921 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:37:46,921 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:37:46,921 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 15:37:46,921 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 15:37:46,921 INFO L87 Difference]: Start difference. First operand 22175 states and 32276 transitions. cyclomatic complexity: 10117 Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:47,322 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:37:47,322 INFO L93 Difference]: Finished difference Result 63271 states and 91896 transitions. [2022-12-13 15:37:47,322 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63271 states and 91896 transitions. [2022-12-13 15:37:47,570 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 62680 [2022-12-13 15:37:47,774 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63271 states to 63271 states and 91896 transitions. [2022-12-13 15:37:47,774 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63271 [2022-12-13 15:37:47,802 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63271 [2022-12-13 15:37:47,802 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63271 states and 91896 transitions. [2022-12-13 15:37:47,832 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:37:47,832 INFO L218 hiAutomatonCegarLoop]: Abstraction has 63271 states and 91896 transitions. [2022-12-13 15:37:47,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63271 states and 91896 transitions. [2022-12-13 15:37:48,191 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63271 to 22784. [2022-12-13 15:37:48,208 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22784 states, 22784 states have (on average 1.4433374297752808) internal successors, (32885), 22783 states have internal predecessors, (32885), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:48,235 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22784 states to 22784 states and 32885 transitions. [2022-12-13 15:37:48,235 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22784 states and 32885 transitions. [2022-12-13 15:37:48,236 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 15:37:48,236 INFO L428 stractBuchiCegarLoop]: Abstraction has 22784 states and 32885 transitions. [2022-12-13 15:37:48,236 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-12-13 15:37:48,236 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22784 states and 32885 transitions. [2022-12-13 15:37:48,282 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22547 [2022-12-13 15:37:48,282 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:37:48,282 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:37:48,283 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:48,283 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:48,283 INFO L748 eck$LassoCheckResult]: Stem: 199147#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 199148#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 200122#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 200123#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 199219#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 199220#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 199122#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 199123#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 200541#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 199774#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 199775#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 199665#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 199666#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 200215#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 200216#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 199416#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 199417#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 199869#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 199870#L1194 assume !(0 == ~M_E~0); 200031#L1194-2 assume !(0 == ~T1_E~0); 200032#L1199-1 assume !(0 == ~T2_E~0); 200370#L1204-1 assume !(0 == ~T3_E~0); 200275#L1209-1 assume !(0 == ~T4_E~0); 200276#L1214-1 assume !(0 == ~T5_E~0); 200849#L1219-1 assume !(0 == ~T6_E~0); 201050#L1224-1 assume !(0 == ~T7_E~0); 199493#L1229-1 assume !(0 == ~T8_E~0); 199039#L1234-1 assume !(0 == ~T9_E~0); 199040#L1239-1 assume !(0 == ~T10_E~0); 199083#L1244-1 assume !(0 == ~T11_E~0); 199084#L1249-1 assume !(0 == ~T12_E~0); 199805#L1254-1 assume !(0 == ~E_M~0); 198981#L1259-1 assume !(0 == ~E_1~0); 198946#L1264-1 assume !(0 == ~E_2~0); 198947#L1269-1 assume !(0 == ~E_3~0); 201069#L1274-1 assume !(0 == ~E_4~0); 200907#L1279-1 assume !(0 == ~E_5~0); 199158#L1284-1 assume !(0 == ~E_6~0); 199159#L1289-1 assume !(0 == ~E_7~0); 199878#L1294-1 assume !(0 == ~E_8~0); 199879#L1299-1 assume !(0 == ~E_9~0); 199890#L1304-1 assume !(0 == ~E_10~0); 201033#L1309-1 assume !(0 == ~E_11~0); 201046#L1314-1 assume !(0 == ~E_12~0); 199114#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 199037#L586 assume !(1 == ~m_pc~0); 199038#L586-2 is_master_triggered_~__retres1~0#1 := 0; 199105#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 199951#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 199320#L1485 assume !(0 != activate_threads_~tmp~1#1); 199321#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 200551#L605 assume !(1 == ~t1_pc~0); 199966#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 199694#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 199695#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 200842#L1493 assume !(0 != activate_threads_~tmp___0~0#1); 200340#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 199601#L624 assume 1 == ~t2_pc~0; 199087#L625 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 199088#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 199344#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 199345#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 200603#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 200419#L643 assume !(1 == ~t3_pc~0); 200242#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 199908#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 199909#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 199423#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 199424#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 199179#L662 assume 1 == ~t4_pc~0; 199180#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 199138#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 198999#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 199000#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 199026#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 199027#L681 assume !(1 == ~t5_pc~0); 198896#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 198897#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 199995#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 200790#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 199437#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 199438#L700 assume 1 == ~t6_pc~0; 200189#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 199170#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 199171#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 199221#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 199222#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 200680#L719 assume 1 == ~t7_pc~0; 200806#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 199390#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 201021#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 200886#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 198910#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 198911#L738 assume !(1 == ~t8_pc~0); 200378#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 200266#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 200267#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 200027#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 200028#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 200449#L757 assume 1 == ~t9_pc~0; 200450#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 198905#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 198906#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 199388#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 199986#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 199987#L776 assume !(1 == ~t10_pc~0); 198930#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 198929#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 199324#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 199160#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 199161#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 199115#L795 assume 1 == ~t11_pc~0; 199116#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 199459#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 200577#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 200834#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 200233#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 200218#L814 assume !(1 == ~t12_pc~0); 200060#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 200061#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 198959#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 198960#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 199372#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 199373#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 200624#L1332-2 assume !(1 == ~T1_E~0); 200947#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 200142#L1342-1 assume !(1 == ~T3_E~0); 200143#L1347-1 assume !(1 == ~T4_E~0); 200657#L1352-1 assume !(1 == ~T5_E~0); 200658#L1357-1 assume !(1 == ~T6_E~0); 199663#L1362-1 assume !(1 == ~T7_E~0); 199664#L1367-1 assume !(1 == ~T8_E~0); 199257#L1372-1 assume !(1 == ~T9_E~0); 199258#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 199832#L1382-1 assume !(1 == ~T11_E~0); 200337#L1387-1 assume !(1 == ~T12_E~0); 200338#L1392-1 assume !(1 == ~E_M~0); 199602#L1397-1 assume !(1 == ~E_1~0); 199603#L1402-1 assume !(1 == ~E_2~0); 199273#L1407-1 assume !(1 == ~E_3~0); 199274#L1412-1 assume !(1 == ~E_4~0); 202619#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 202617#L1422-1 assume !(1 == ~E_6~0); 202615#L1427-1 assume !(1 == ~E_7~0); 202613#L1432-1 assume !(1 == ~E_8~0); 202611#L1437-1 assume !(1 == ~E_9~0); 202609#L1442-1 assume !(1 == ~E_10~0); 202607#L1447-1 assume !(1 == ~E_11~0); 202579#L1452-1 assume !(1 == ~E_12~0); 202554#L1457-1 assume { :end_inline_reset_delta_events } true; 202536#L1803-2 [2022-12-13 15:37:48,284 INFO L750 eck$LassoCheckResult]: Loop: 202536#L1803-2 assume !false; 202523#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 202513#L1169 assume !false; 202511#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 202507#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 202483#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 202481#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 202478#L996 assume !(0 != eval_~tmp~0#1); 202473#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 202474#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 202469#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 202470#L1194-5 assume !(0 == ~T1_E~0); 220582#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 220578#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 220573#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 220568#L1214-3 assume !(0 == ~T5_E~0); 220564#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 220559#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 220555#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 220554#L1234-3 assume !(0 == ~T9_E~0); 220552#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 220549#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 220547#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 220545#L1254-3 assume !(0 == ~E_M~0); 220543#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 220540#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 220537#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 220534#L1274-3 assume !(0 == ~E_4~0); 220531#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 220528#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 220525#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 220522#L1294-3 assume !(0 == ~E_8~0); 220519#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 220516#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 220513#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 220510#L1314-3 assume !(0 == ~E_12~0); 220507#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 220506#L586-42 assume !(1 == ~m_pc~0); 220505#L586-44 is_master_triggered_~__retres1~0#1 := 0; 220504#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 220503#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 220502#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 220501#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 220500#L605-42 assume !(1 == ~t1_pc~0); 220499#L605-44 is_transmit1_triggered_~__retres1~1#1 := 0; 220497#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 220495#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 220493#L1493-42 assume !(0 != activate_threads_~tmp___0~0#1); 220489#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 220486#L624-42 assume 1 == ~t2_pc~0; 220483#L625-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 220479#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 220476#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 220473#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 220470#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 220451#L643-42 assume !(1 == ~t3_pc~0); 220447#L643-44 is_transmit3_triggered_~__retres1~3#1 := 0; 220442#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 220422#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 220418#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 220414#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 220409#L662-42 assume 1 == ~t4_pc~0; 220390#L663-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 220385#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 220380#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 220375#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 220371#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 220366#L681-42 assume !(1 == ~t5_pc~0); 220362#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 220357#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 220352#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 220347#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 220343#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 220338#L700-42 assume 1 == ~t6_pc~0; 220334#L701-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 220329#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 220324#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 220319#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 220315#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 220310#L719-42 assume !(1 == ~t7_pc~0); 220306#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 220301#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 220294#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 211047#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 210357#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 210355#L738-42 assume !(1 == ~t8_pc~0); 210352#L738-44 is_transmit8_triggered_~__retres1~8#1 := 0; 210349#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 210347#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 210345#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 210344#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 210343#L757-42 assume !(1 == ~t9_pc~0); 210342#L757-44 is_transmit9_triggered_~__retres1~9#1 := 0; 210340#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 210339#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 210338#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 210337#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 210336#L776-42 assume !(1 == ~t10_pc~0); 210334#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 210331#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 210328#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 210326#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 210324#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 210322#L795-42 assume 1 == ~t11_pc~0; 210320#L796-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 210317#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 210316#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 210313#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 210311#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 210309#L814-42 assume !(1 == ~t12_pc~0); 210307#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 210304#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 210302#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 210299#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 210297#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 210295#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 199110#L1332-5 assume !(1 == ~T1_E~0); 210292#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 210290#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 210289#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 210236#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 210234#L1357-3 assume !(1 == ~T6_E~0); 210232#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 210229#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 209643#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 209638#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 209636#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 209634#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 209632#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 209630#L1397-3 assume !(1 == ~E_1~0); 209628#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 209625#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 209623#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 209619#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 209617#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 209615#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 209613#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 209612#L1437-3 assume !(1 == ~E_9~0); 209487#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 209485#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 209484#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 208797#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 208062#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 208049#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 208048#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 208045#L1822 assume !(0 == start_simulation_~tmp~3#1); 200453#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 206562#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 206041#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 206038#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 206036#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 202605#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 202576#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 202553#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 202536#L1803-2 [2022-12-13 15:37:48,284 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:48,284 INFO L85 PathProgramCache]: Analyzing trace with hash -1724859847, now seen corresponding path program 1 times [2022-12-13 15:37:48,284 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:48,284 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1759910036] [2022-12-13 15:37:48,284 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:48,284 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:48,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:48,329 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:48,329 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:48,330 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1759910036] [2022-12-13 15:37:48,330 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1759910036] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:48,330 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:48,330 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:48,330 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1323487714] [2022-12-13 15:37:48,330 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:48,330 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:37:48,331 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:48,331 INFO L85 PathProgramCache]: Analyzing trace with hash 700902144, now seen corresponding path program 1 times [2022-12-13 15:37:48,331 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:48,331 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [889590675] [2022-12-13 15:37:48,331 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:48,331 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:48,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:48,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:48,369 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:48,369 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [889590675] [2022-12-13 15:37:48,369 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [889590675] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:48,369 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:48,369 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:48,370 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1371840441] [2022-12-13 15:37:48,370 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:48,370 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:37:48,370 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:37:48,370 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 15:37:48,371 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 15:37:48,371 INFO L87 Difference]: Start difference. First operand 22784 states and 32885 transitions. cyclomatic complexity: 10117 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:48,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:37:48,761 INFO L93 Difference]: Finished difference Result 55544 states and 79620 transitions. [2022-12-13 15:37:48,761 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55544 states and 79620 transitions. [2022-12-13 15:37:48,912 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 54500 [2022-12-13 15:37:49,018 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55544 states to 55544 states and 79620 transitions. [2022-12-13 15:37:49,019 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55544 [2022-12-13 15:37:49,042 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55544 [2022-12-13 15:37:49,043 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55544 states and 79620 transitions. [2022-12-13 15:37:49,070 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:37:49,070 INFO L218 hiAutomatonCegarLoop]: Abstraction has 55544 states and 79620 transitions. [2022-12-13 15:37:49,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55544 states and 79620 transitions. [2022-12-13 15:37:49,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55544 to 43576. [2022-12-13 15:37:49,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43576 states, 43576 states have (on average 1.437465577382045) internal successors, (62639), 43575 states have internal predecessors, (62639), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:49,587 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43576 states to 43576 states and 62639 transitions. [2022-12-13 15:37:49,587 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43576 states and 62639 transitions. [2022-12-13 15:37:49,587 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 15:37:49,588 INFO L428 stractBuchiCegarLoop]: Abstraction has 43576 states and 62639 transitions. [2022-12-13 15:37:49,588 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-12-13 15:37:49,588 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43576 states and 62639 transitions. [2022-12-13 15:37:49,713 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 43332 [2022-12-13 15:37:49,713 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:37:49,713 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:37:49,716 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:49,716 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:49,717 INFO L748 eck$LassoCheckResult]: Stem: 277486#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 277487#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 278452#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 278453#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 277554#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 277555#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 277460#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 277461#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 278854#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 278105#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 278106#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 277998#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 277999#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 278550#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 278551#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 277750#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 277751#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 278203#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 278204#L1194 assume !(0 == ~M_E~0); 278363#L1194-2 assume !(0 == ~T1_E~0); 278364#L1199-1 assume !(0 == ~T2_E~0); 278698#L1204-1 assume !(0 == ~T3_E~0); 278606#L1209-1 assume !(0 == ~T4_E~0); 278607#L1214-1 assume !(0 == ~T5_E~0); 279152#L1219-1 assume !(0 == ~T6_E~0); 279330#L1224-1 assume !(0 == ~T7_E~0); 277825#L1229-1 assume !(0 == ~T8_E~0); 277387#L1234-1 assume !(0 == ~T9_E~0); 277388#L1239-1 assume !(0 == ~T10_E~0); 277425#L1244-1 assume !(0 == ~T11_E~0); 277426#L1249-1 assume !(0 == ~T12_E~0); 278138#L1254-1 assume !(0 == ~E_M~0); 277320#L1259-1 assume !(0 == ~E_1~0); 277284#L1264-1 assume !(0 == ~E_2~0); 277285#L1269-1 assume !(0 == ~E_3~0); 279348#L1274-1 assume !(0 == ~E_4~0); 279205#L1279-1 assume !(0 == ~E_5~0); 277495#L1284-1 assume !(0 == ~E_6~0); 277496#L1289-1 assume !(0 == ~E_7~0); 278210#L1294-1 assume !(0 == ~E_8~0); 278211#L1299-1 assume !(0 == ~E_9~0); 278224#L1304-1 assume !(0 == ~E_10~0); 279314#L1309-1 assume !(0 == ~E_11~0); 279326#L1314-1 assume !(0 == ~E_12~0); 277454#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 277377#L586 assume !(1 == ~m_pc~0); 277378#L586-2 is_master_triggered_~__retres1~0#1 := 0; 277442#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 278286#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 277655#L1485 assume !(0 != activate_threads_~tmp~1#1); 277656#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 278860#L605 assume !(1 == ~t1_pc~0); 278302#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 278026#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 278027#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 278745#L1493 assume !(0 != activate_threads_~tmp___0~0#1); 278672#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 277931#L624 assume !(1 == ~t2_pc~0); 277932#L624-2 is_transmit2_triggered_~__retres1~2#1 := 0; 278113#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 277678#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 277679#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 278911#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 278743#L643 assume !(1 == ~t3_pc~0); 278576#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 278248#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 278249#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 277757#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 277758#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 277516#L662 assume 1 == ~t4_pc~0; 277517#L663 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 277475#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 277342#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 277343#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 277368#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 277369#L681 assume !(1 == ~t5_pc~0); 277234#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 277235#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 278329#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 279093#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 277770#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 277771#L700 assume 1 == ~t6_pc~0; 278523#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 277507#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 277508#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 277556#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 277557#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 278981#L719 assume 1 == ~t7_pc~0; 279111#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 277723#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 279302#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 279186#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 277248#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 277249#L738 assume !(1 == ~t8_pc~0); 278706#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 278598#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 278599#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 278359#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 278360#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 278769#L757 assume 1 == ~t9_pc~0; 278770#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 277243#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 277244#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 277721#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 278321#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 278322#L776 assume !(1 == ~t10_pc~0); 277268#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 277267#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 277659#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 277497#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 277498#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 277455#L795 assume 1 == ~t11_pc~0; 277456#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 277790#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 278889#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 279135#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 278567#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 278553#L814 assume !(1 == ~t12_pc~0); 278390#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 278391#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 277297#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 277298#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 277706#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 277707#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 278925#L1332-2 assume !(1 == ~T1_E~0); 279240#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 278470#L1342-1 assume !(1 == ~T3_E~0); 278471#L1347-1 assume !(1 == ~T4_E~0); 278962#L1352-1 assume !(1 == ~T5_E~0); 278780#L1357-1 assume !(1 == ~T6_E~0); 277996#L1362-1 assume !(1 == ~T7_E~0); 277997#L1367-1 assume !(1 == ~T8_E~0); 277595#L1372-1 assume !(1 == ~T9_E~0); 277596#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 277905#L1382-1 assume !(1 == ~T11_E~0); 277906#L1387-1 assume !(1 == ~T12_E~0); 278669#L1392-1 assume !(1 == ~E_M~0); 289728#L1397-1 assume !(1 == ~E_1~0); 289726#L1402-1 assume !(1 == ~E_2~0); 289724#L1407-1 assume !(1 == ~E_3~0); 289721#L1412-1 assume !(1 == ~E_4~0); 289720#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 289719#L1422-1 assume !(1 == ~E_6~0); 289718#L1427-1 assume !(1 == ~E_7~0); 289717#L1432-1 assume !(1 == ~E_8~0); 289716#L1437-1 assume !(1 == ~E_9~0); 289715#L1442-1 assume !(1 == ~E_10~0); 289701#L1447-1 assume !(1 == ~E_11~0); 289699#L1452-1 assume !(1 == ~E_12~0); 289695#L1457-1 assume { :end_inline_reset_delta_events } true; 289692#L1803-2 [2022-12-13 15:37:49,717 INFO L750 eck$LassoCheckResult]: Loop: 289692#L1803-2 assume !false; 289690#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 289684#L1169 assume !false; 289683#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 289287#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 289276#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 289272#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 289269#L996 assume !(0 != eval_~tmp~0#1); 289270#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 294716#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 294714#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 294712#L1194-5 assume !(0 == ~T1_E~0); 294710#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 294708#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 294672#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 294506#L1214-3 assume !(0 == ~T5_E~0); 294499#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 290589#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 290575#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 290573#L1234-3 assume !(0 == ~T9_E~0); 290571#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 290569#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 290567#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 290565#L1254-3 assume !(0 == ~E_M~0); 290563#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 290561#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 290559#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 290557#L1274-3 assume !(0 == ~E_4~0); 290555#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 290553#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 290551#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 290549#L1294-3 assume !(0 == ~E_8~0); 290547#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 290545#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 290543#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 290541#L1314-3 assume !(0 == ~E_12~0); 290539#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 290537#L586-42 assume !(1 == ~m_pc~0); 290535#L586-44 is_master_triggered_~__retres1~0#1 := 0; 290533#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 290531#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 290529#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 290527#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 290525#L605-42 assume !(1 == ~t1_pc~0); 290521#L605-44 is_transmit1_triggered_~__retres1~1#1 := 0; 290519#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 290517#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 290515#L1493-42 assume !(0 != activate_threads_~tmp___0~0#1); 290512#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 290510#L624-42 assume !(1 == ~t2_pc~0); 282370#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 290507#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 290505#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 290503#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 290501#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 290499#L643-42 assume 1 == ~t3_pc~0; 290496#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 290494#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 290491#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 290489#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 290487#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 290486#L662-42 assume 1 == ~t4_pc~0; 290484#L663-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 290481#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 290479#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 290477#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 290475#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 290472#L681-42 assume 1 == ~t5_pc~0; 290298#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 290296#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 290294#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 290292#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 290290#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 290288#L700-42 assume !(1 == ~t6_pc~0); 290285#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 290283#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 290281#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 290279#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 290277#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 290275#L719-42 assume 1 == ~t7_pc~0; 290272#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 290270#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 290268#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 290266#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 290264#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 290262#L738-42 assume 1 == ~t8_pc~0; 290258#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 290256#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 290254#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 290252#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 290248#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 290246#L757-42 assume !(1 == ~t9_pc~0); 290244#L757-44 is_transmit9_triggered_~__retres1~9#1 := 0; 290241#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 290238#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 290236#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 290234#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 290233#L776-42 assume 1 == ~t10_pc~0; 290230#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 290228#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 290226#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 290224#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 290222#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 290219#L795-42 assume !(1 == ~t11_pc~0); 290216#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 290214#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 290212#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 290210#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 290208#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 290205#L814-42 assume 1 == ~t12_pc~0; 290202#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 290200#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 290198#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 290196#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 290194#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 290191#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 289956#L1332-5 assume !(1 == ~T1_E~0); 290186#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 290184#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 290182#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 290180#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 290177#L1357-3 assume !(1 == ~T6_E~0); 290175#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 290173#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 290171#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 290167#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 290165#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 290162#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 290160#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 290158#L1397-3 assume !(1 == ~E_1~0); 290156#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 290154#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 290152#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 290147#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 290145#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 290143#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 290141#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 290139#L1437-3 assume !(1 == ~E_9~0); 290137#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 290134#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 290132#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 290128#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 290123#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 290109#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 290107#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 290105#L1822 assume !(0 == start_simulation_~tmp~3#1); 290102#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 290087#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 290077#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 290075#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 290073#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 290071#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 290069#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 289694#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 289692#L1803-2 [2022-12-13 15:37:49,718 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:49,718 INFO L85 PathProgramCache]: Analyzing trace with hash -607674886, now seen corresponding path program 1 times [2022-12-13 15:37:49,718 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:49,718 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1793827613] [2022-12-13 15:37:49,718 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:49,718 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:49,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:49,785 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:49,785 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:49,785 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1793827613] [2022-12-13 15:37:49,785 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1793827613] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:49,785 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:49,785 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 15:37:49,786 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1302325364] [2022-12-13 15:37:49,786 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:49,786 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:37:49,786 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:49,787 INFO L85 PathProgramCache]: Analyzing trace with hash -997163715, now seen corresponding path program 1 times [2022-12-13 15:37:49,787 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:49,787 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1018696262] [2022-12-13 15:37:49,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:49,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:49,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:49,828 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:49,828 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:49,828 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1018696262] [2022-12-13 15:37:49,828 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1018696262] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:49,828 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:49,828 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:49,829 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1524496711] [2022-12-13 15:37:49,829 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:49,829 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:37:49,829 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:37:49,830 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:37:49,830 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:37:49,830 INFO L87 Difference]: Start difference. First operand 43576 states and 62639 transitions. cyclomatic complexity: 19079 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:50,156 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:37:50,156 INFO L93 Difference]: Finished difference Result 83495 states and 119552 transitions. [2022-12-13 15:37:50,156 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 83495 states and 119552 transitions. [2022-12-13 15:37:50,507 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 83172 [2022-12-13 15:37:50,743 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 83495 states to 83495 states and 119552 transitions. [2022-12-13 15:37:50,744 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 83495 [2022-12-13 15:37:50,797 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 83495 [2022-12-13 15:37:50,798 INFO L73 IsDeterministic]: Start isDeterministic. Operand 83495 states and 119552 transitions. [2022-12-13 15:37:50,843 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:37:50,843 INFO L218 hiAutomatonCegarLoop]: Abstraction has 83495 states and 119552 transitions. [2022-12-13 15:37:50,901 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83495 states and 119552 transitions. [2022-12-13 15:37:51,538 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83495 to 83431. [2022-12-13 15:37:51,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 83431 states, 83431 states have (on average 1.4321774879840827) internal successors, (119488), 83430 states have internal predecessors, (119488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:51,691 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83431 states to 83431 states and 119488 transitions. [2022-12-13 15:37:51,691 INFO L240 hiAutomatonCegarLoop]: Abstraction has 83431 states and 119488 transitions. [2022-12-13 15:37:51,692 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:37:51,692 INFO L428 stractBuchiCegarLoop]: Abstraction has 83431 states and 119488 transitions. [2022-12-13 15:37:51,692 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-12-13 15:37:51,692 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 83431 states and 119488 transitions. [2022-12-13 15:37:51,876 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 83108 [2022-12-13 15:37:51,877 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:37:51,877 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:37:51,878 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:51,878 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:51,878 INFO L748 eck$LassoCheckResult]: Stem: 404561#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 404562#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 405528#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 405529#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 404628#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 404629#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 404535#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 404536#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 405917#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 405181#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 405182#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 405070#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 405071#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 405619#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 405620#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 404824#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 404825#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 405279#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 405280#L1194 assume !(0 == ~M_E~0); 405437#L1194-2 assume !(0 == ~T1_E~0); 405438#L1199-1 assume !(0 == ~T2_E~0); 405765#L1204-1 assume !(0 == ~T3_E~0); 405677#L1209-1 assume !(0 == ~T4_E~0); 405678#L1214-1 assume !(0 == ~T5_E~0); 406190#L1219-1 assume !(0 == ~T6_E~0); 406367#L1224-1 assume !(0 == ~T7_E~0); 404900#L1229-1 assume !(0 == ~T8_E~0); 404460#L1234-1 assume !(0 == ~T9_E~0); 404461#L1239-1 assume !(0 == ~T10_E~0); 404501#L1244-1 assume !(0 == ~T11_E~0); 404502#L1249-1 assume !(0 == ~T12_E~0); 405214#L1254-1 assume !(0 == ~E_M~0); 404396#L1259-1 assume !(0 == ~E_1~0); 404362#L1264-1 assume !(0 == ~E_2~0); 404363#L1269-1 assume !(0 == ~E_3~0); 406389#L1274-1 assume !(0 == ~E_4~0); 406244#L1279-1 assume !(0 == ~E_5~0); 404570#L1284-1 assume !(0 == ~E_6~0); 404571#L1289-1 assume !(0 == ~E_7~0); 405287#L1294-1 assume !(0 == ~E_8~0); 405288#L1299-1 assume !(0 == ~E_9~0); 405300#L1304-1 assume !(0 == ~E_10~0); 406350#L1309-1 assume !(0 == ~E_11~0); 406362#L1314-1 assume !(0 == ~E_12~0); 404529#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 404452#L586 assume !(1 == ~m_pc~0); 404453#L586-2 is_master_triggered_~__retres1~0#1 := 0; 404518#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 405361#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 404729#L1485 assume !(0 != activate_threads_~tmp~1#1); 404730#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 405923#L605 assume !(1 == ~t1_pc~0); 405376#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 405099#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 405100#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 405808#L1493 assume !(0 != activate_threads_~tmp___0~0#1); 405737#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 405004#L624 assume !(1 == ~t2_pc~0); 405005#L624-2 is_transmit2_triggered_~__retres1~2#1 := 0; 405187#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 404752#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 404753#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 405969#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 405806#L643 assume !(1 == ~t3_pc~0); 405645#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 405320#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 405321#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 404831#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 404832#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 404591#L662 assume !(1 == ~t4_pc~0); 404592#L662-2 is_transmit4_triggered_~__retres1~4#1 := 0; 404550#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 404414#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 404415#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 404443#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 404444#L681 assume !(1 == ~t5_pc~0); 404312#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 404313#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 405403#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 406141#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 404844#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 404845#L700 assume 1 == ~t6_pc~0; 405592#L701 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 404583#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 404584#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 404630#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 404631#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 406039#L719 assume 1 == ~t7_pc~0; 406155#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 404797#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 406334#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 406223#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 404326#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 404327#L738 assume !(1 == ~t8_pc~0); 405772#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 405667#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 405668#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 405433#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 405434#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 405829#L757 assume 1 == ~t9_pc~0; 405830#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 404321#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 404322#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 404795#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 405395#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 405396#L776 assume !(1 == ~t10_pc~0); 404346#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 404345#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 404733#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 404572#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 404573#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 404530#L795 assume 1 == ~t11_pc~0; 404531#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 404864#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 405944#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 406180#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 405636#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 405622#L814 assume !(1 == ~t12_pc~0); 405467#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 405468#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 404375#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 404376#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 404780#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 404781#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 405987#L1332-2 assume !(1 == ~T1_E~0); 406272#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 405545#L1342-1 assume !(1 == ~T3_E~0); 405546#L1347-1 assume !(1 == ~T4_E~0); 406023#L1352-1 assume !(1 == ~T5_E~0); 405837#L1357-1 assume !(1 == ~T6_E~0); 405068#L1362-1 assume !(1 == ~T7_E~0); 405069#L1367-1 assume !(1 == ~T8_E~0); 404667#L1372-1 assume !(1 == ~T9_E~0); 404668#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 418437#L1382-1 assume !(1 == ~T11_E~0); 418435#L1387-1 assume !(1 == ~T12_E~0); 418433#L1392-1 assume !(1 == ~E_M~0); 418432#L1397-1 assume !(1 == ~E_1~0); 418430#L1402-1 assume !(1 == ~E_2~0); 418428#L1407-1 assume !(1 == ~E_3~0); 418426#L1412-1 assume !(1 == ~E_4~0); 418425#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 418424#L1422-1 assume !(1 == ~E_6~0); 418410#L1427-1 assume !(1 == ~E_7~0); 418408#L1432-1 assume !(1 == ~E_8~0); 418406#L1437-1 assume !(1 == ~E_9~0); 418404#L1442-1 assume !(1 == ~E_10~0); 418402#L1447-1 assume !(1 == ~E_11~0); 418400#L1452-1 assume !(1 == ~E_12~0); 418397#L1457-1 assume { :end_inline_reset_delta_events } true; 418391#L1803-2 [2022-12-13 15:37:51,879 INFO L750 eck$LassoCheckResult]: Loop: 418391#L1803-2 assume !false; 418390#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 418385#L1169 assume !false; 418384#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 414882#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 414871#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 414870#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 414868#L996 assume !(0 != eval_~tmp~0#1); 414869#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 446749#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 446748#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 446746#L1194-5 assume !(0 == ~T1_E~0); 446743#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 446741#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 446739#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 446737#L1214-3 assume !(0 == ~T5_E~0); 446735#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 446733#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 446730#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 446727#L1234-3 assume !(0 == ~T9_E~0); 446724#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 446721#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 446719#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 446717#L1254-3 assume !(0 == ~E_M~0); 446716#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 446714#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 446712#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 446710#L1274-3 assume !(0 == ~E_4~0); 446708#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 446706#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 446703#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 446701#L1294-3 assume !(0 == ~E_8~0); 446699#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 446697#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 446695#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 446693#L1314-3 assume !(0 == ~E_12~0); 446691#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 446689#L586-42 assume !(1 == ~m_pc~0); 446687#L586-44 is_master_triggered_~__retres1~0#1 := 0; 446685#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 446683#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 446681#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 446678#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 446676#L605-42 assume !(1 == ~t1_pc~0); 446674#L605-44 is_transmit1_triggered_~__retres1~1#1 := 0; 446671#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 446668#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 446665#L1493-42 assume !(0 != activate_threads_~tmp___0~0#1); 446663#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 405137#L624-42 assume !(1 == ~t2_pc~0); 405138#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 445989#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 445987#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 445984#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 445982#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 445980#L643-42 assume !(1 == ~t3_pc~0); 445978#L643-44 is_transmit3_triggered_~__retres1~3#1 := 0; 445975#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 445973#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 445970#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 445968#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 445553#L662-42 assume !(1 == ~t4_pc~0); 444433#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 444432#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 444431#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 444430#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 444429#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 444427#L681-42 assume 1 == ~t5_pc~0; 444423#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 444421#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 444419#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 444417#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 443079#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 429312#L700-42 assume !(1 == ~t6_pc~0); 429310#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 429309#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 429308#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 429307#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 429306#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 429305#L719-42 assume 1 == ~t7_pc~0; 429302#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 429300#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 429298#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 429296#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 429294#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 421768#L738-42 assume 1 == ~t8_pc~0; 421764#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 421762#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 421760#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 421758#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 421756#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 421754#L757-42 assume 1 == ~t9_pc~0; 421750#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 421748#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 421746#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 421744#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 421742#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 421740#L776-42 assume 1 == ~t10_pc~0; 421736#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 421734#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 421732#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 421730#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 421728#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 421726#L795-42 assume !(1 == ~t11_pc~0); 421722#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 421720#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 421718#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 421716#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 421714#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 421712#L814-42 assume 1 == ~t12_pc~0; 421708#L815-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 421706#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 421704#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 421702#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 421700#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 421698#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 416159#L1332-5 assume !(1 == ~T1_E~0); 421692#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 421690#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 421688#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 421686#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 421684#L1357-3 assume !(1 == ~T6_E~0); 421682#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 421680#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 421678#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 421674#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 421672#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 421670#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 421668#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 421666#L1397-3 assume !(1 == ~E_1~0); 421664#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 421662#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 421660#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 416119#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 421657#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 421655#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 421653#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 421651#L1437-3 assume !(1 == ~E_9~0); 421649#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 421647#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 421645#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 421641#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 421636#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 421623#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 421621#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 421620#L1822 assume !(0 == start_simulation_~tmp~3#1); 421618#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 418418#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 418409#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 418407#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 418405#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 418403#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 418401#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 418396#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 418391#L1803-2 [2022-12-13 15:37:51,879 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:51,879 INFO L85 PathProgramCache]: Analyzing trace with hash 852319035, now seen corresponding path program 1 times [2022-12-13 15:37:51,879 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:51,879 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1353706273] [2022-12-13 15:37:51,879 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:51,879 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:51,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:51,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:51,927 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:51,928 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1353706273] [2022-12-13 15:37:51,928 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1353706273] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:51,928 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:51,928 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:51,928 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2081525475] [2022-12-13 15:37:51,928 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:51,928 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:37:51,929 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:51,929 INFO L85 PathProgramCache]: Analyzing trace with hash 1727493246, now seen corresponding path program 1 times [2022-12-13 15:37:51,929 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:51,929 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1779110281] [2022-12-13 15:37:51,929 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:51,929 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:51,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:51,960 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:51,960 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:51,960 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1779110281] [2022-12-13 15:37:51,960 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1779110281] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:51,960 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:51,960 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:51,961 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [469207316] [2022-12-13 15:37:51,961 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:51,961 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:37:51,961 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:37:51,961 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 15:37:51,961 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 15:37:51,962 INFO L87 Difference]: Start difference. First operand 83431 states and 119488 transitions. cyclomatic complexity: 36089 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:52,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:37:52,789 INFO L93 Difference]: Finished difference Result 202350 states and 288049 transitions. [2022-12-13 15:37:52,789 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 202350 states and 288049 transitions. [2022-12-13 15:37:53,595 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 198732 [2022-12-13 15:37:53,903 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 202350 states to 202350 states and 288049 transitions. [2022-12-13 15:37:53,904 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 202350 [2022-12-13 15:37:53,985 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 202350 [2022-12-13 15:37:53,985 INFO L73 IsDeterministic]: Start isDeterministic. Operand 202350 states and 288049 transitions. [2022-12-13 15:37:54,061 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:37:54,061 INFO L218 hiAutomatonCegarLoop]: Abstraction has 202350 states and 288049 transitions. [2022-12-13 15:37:54,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 202350 states and 288049 transitions. [2022-12-13 15:37:55,213 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 202350 to 159714. [2022-12-13 15:37:55,290 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 159714 states, 159714 states have (on average 1.4273075622675533) internal successors, (227961), 159713 states have internal predecessors, (227961), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:55,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159714 states to 159714 states and 227961 transitions. [2022-12-13 15:37:55,496 INFO L240 hiAutomatonCegarLoop]: Abstraction has 159714 states and 227961 transitions. [2022-12-13 15:37:55,496 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 15:37:55,496 INFO L428 stractBuchiCegarLoop]: Abstraction has 159714 states and 227961 transitions. [2022-12-13 15:37:55,497 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-12-13 15:37:55,497 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 159714 states and 227961 transitions. [2022-12-13 15:37:55,964 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 159296 [2022-12-13 15:37:55,964 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:37:55,964 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:37:55,966 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:55,966 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:37:55,967 INFO L748 eck$LassoCheckResult]: Stem: 690349#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 690350#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 691289#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 691290#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 690415#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 690416#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 690323#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 690324#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 691653#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 690956#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 690957#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 690855#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 690856#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 691375#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 691376#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 690609#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 690610#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 691045#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 691046#L1194 assume !(0 == ~M_E~0); 691202#L1194-2 assume !(0 == ~T1_E~0); 691203#L1199-1 assume !(0 == ~T2_E~0); 691512#L1204-1 assume !(0 == ~T3_E~0); 691426#L1209-1 assume !(0 == ~T4_E~0); 691427#L1214-1 assume !(0 == ~T5_E~0); 691915#L1219-1 assume !(0 == ~T6_E~0); 692042#L1224-1 assume !(0 == ~T7_E~0); 690688#L1229-1 assume !(0 == ~T8_E~0); 690253#L1234-1 assume !(0 == ~T9_E~0); 690254#L1239-1 assume !(0 == ~T10_E~0); 690291#L1244-1 assume !(0 == ~T11_E~0); 690292#L1249-1 assume !(0 == ~T12_E~0); 690988#L1254-1 assume !(0 == ~E_M~0); 690187#L1259-1 assume !(0 == ~E_1~0); 690153#L1264-1 assume !(0 == ~E_2~0); 690154#L1269-1 assume !(0 == ~E_3~0); 692054#L1274-1 assume !(0 == ~E_4~0); 691954#L1279-1 assume !(0 == ~E_5~0); 690358#L1284-1 assume !(0 == ~E_6~0); 690359#L1289-1 assume !(0 == ~E_7~0); 691055#L1294-1 assume !(0 == ~E_8~0); 691056#L1299-1 assume !(0 == ~E_9~0); 691067#L1304-1 assume !(0 == ~E_10~0); 692024#L1309-1 assume !(0 == ~E_11~0); 692037#L1314-1 assume !(0 == ~E_12~0); 690317#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 690243#L586 assume !(1 == ~m_pc~0); 690244#L586-2 is_master_triggered_~__retres1~0#1 := 0; 690308#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 691126#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 690516#L1485 assume !(0 != activate_threads_~tmp~1#1); 690517#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 691662#L605 assume !(1 == ~t1_pc~0); 691141#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 690882#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 690883#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 691557#L1493 assume !(0 != activate_threads_~tmp___0~0#1); 691484#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 690790#L624 assume !(1 == ~t2_pc~0); 690791#L624-2 is_transmit2_triggered_~__retres1~2#1 := 0; 690963#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 690539#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 690540#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 691708#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 691555#L643 assume !(1 == ~t3_pc~0); 691397#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 691088#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 691089#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 690616#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 690617#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 690379#L662 assume !(1 == ~t4_pc~0); 690380#L662-2 is_transmit4_triggered_~__retres1~4#1 := 0; 690338#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 690208#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 690209#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 690234#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 690235#L681 assume !(1 == ~t5_pc~0); 690103#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 690104#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 691169#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 691868#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 690629#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 690630#L700 assume !(1 == ~t6_pc~0); 690460#L700-2 is_transmit6_triggered_~__retres1~6#1 := 0; 690370#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 690371#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 690417#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 690418#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 691775#L719 assume 1 == ~t7_pc~0; 691883#L720 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 690585#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 692016#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 691937#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 690117#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 690118#L738 assume !(1 == ~t8_pc~0); 691520#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 691418#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 691419#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 691198#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 691199#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 691579#L757 assume 1 == ~t9_pc~0; 691580#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 690112#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 690113#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 690582#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 691161#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 691162#L776 assume !(1 == ~t10_pc~0); 690137#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 690136#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 690522#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 690360#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 690361#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 690318#L795 assume 1 == ~t11_pc~0; 690319#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 690651#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 691688#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 691902#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 691389#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 691378#L814 assume !(1 == ~t12_pc~0); 691228#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 691229#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 690168#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 690169#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 690567#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 690568#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 691721#L1332-2 assume !(1 == ~T1_E~0); 691979#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 691307#L1342-1 assume !(1 == ~T3_E~0); 691308#L1347-1 assume !(1 == ~T4_E~0); 691759#L1352-1 assume !(1 == ~T5_E~0); 691586#L1357-1 assume !(1 == ~T6_E~0); 690853#L1362-1 assume !(1 == ~T7_E~0); 690854#L1367-1 assume !(1 == ~T8_E~0); 690456#L1372-1 assume !(1 == ~T9_E~0); 690457#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 690765#L1382-1 assume !(1 == ~T11_E~0); 690766#L1387-1 assume !(1 == ~T12_E~0); 691480#L1392-1 assume !(1 == ~E_M~0); 690792#L1397-1 assume !(1 == ~E_1~0); 690793#L1402-1 assume !(1 == ~E_2~0); 690471#L1407-1 assume !(1 == ~E_3~0); 690472#L1412-1 assume !(1 == ~E_4~0); 691686#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 691687#L1422-1 assume !(1 == ~E_6~0); 691980#L1427-1 assume !(1 == ~E_7~0); 690652#L1432-1 assume !(1 == ~E_8~0); 690653#L1437-1 assume !(1 == ~E_9~0); 691619#L1442-1 assume !(1 == ~E_10~0); 691620#L1447-1 assume !(1 == ~E_11~0); 691470#L1452-1 assume !(1 == ~E_12~0); 691471#L1457-1 assume { :end_inline_reset_delta_events } true; 839418#L1803-2 [2022-12-13 15:37:55,967 INFO L750 eck$LassoCheckResult]: Loop: 839418#L1803-2 assume !false; 839416#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 839410#L1169 assume !false; 839408#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 839401#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 839389#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 839387#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 839384#L996 assume !(0 != eval_~tmp~0#1); 839385#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 848168#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 848167#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 848166#L1194-5 assume !(0 == ~T1_E~0); 848164#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 848163#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 848162#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 848161#L1214-3 assume !(0 == ~T5_E~0); 848160#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 848159#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 848158#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 848157#L1234-3 assume !(0 == ~T9_E~0); 848156#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 848155#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 848154#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 848153#L1254-3 assume !(0 == ~E_M~0); 848151#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 848148#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 848146#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 848143#L1274-3 assume !(0 == ~E_4~0); 848141#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 848136#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 691977#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 690861#L1294-3 assume !(0 == ~E_8~0); 690862#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 691259#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 691260#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 690767#L1314-3 assume !(0 == ~E_12~0); 690768#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 690772#L586-42 assume !(1 == ~m_pc~0); 690773#L586-44 is_master_triggered_~__retres1~0#1 := 0; 690366#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 690367#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 690836#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 690908#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 690909#L605-42 assume !(1 == ~t1_pc~0); 691528#L605-44 is_transmit1_triggered_~__retres1~1#1 := 0; 691221#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 691222#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 690910#L1493-42 assume !(0 != activate_threads_~tmp___0~0#1); 690911#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 690915#L624-42 assume !(1 == ~t2_pc~0); 690916#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 691061#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 691159#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 691160#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 690730#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 690731#L643-42 assume 1 == ~t3_pc~0; 691084#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 691040#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 691041#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 690876#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 690877#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 691631#L662-42 assume !(1 == ~t4_pc~0); 691890#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 847416#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 847414#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 847412#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 847410#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 847408#L681-42 assume 1 == ~t5_pc~0; 847405#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 847403#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 847401#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 847399#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 847397#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 847395#L700-42 assume !(1 == ~t6_pc~0); 760365#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 847392#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 847390#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 847388#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 847386#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 847384#L719-42 assume 1 == ~t7_pc~0; 847381#L720-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 847379#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 847377#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 847375#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 847373#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 847371#L738-42 assume 1 == ~t8_pc~0; 847368#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 847366#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 847365#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 690300#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 690301#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 690831#L757-42 assume 1 == ~t9_pc~0; 691171#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 690483#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 690484#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 692038#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 844091#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 844087#L776-42 assume 1 == ~t10_pc~0; 844084#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 843912#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 843677#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 843674#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 843672#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 843670#L795-42 assume 1 == ~t11_pc~0; 843668#L796-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 843666#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 843652#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 843650#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 843648#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 843646#L814-42 assume !(1 == ~t12_pc~0); 843644#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 843641#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 843639#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 843628#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 843618#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 843538#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 798489#L1332-5 assume !(1 == ~T1_E~0); 843533#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 843531#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 843530#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 843528#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 843526#L1357-3 assume !(1 == ~T6_E~0); 843524#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 843522#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 843520#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 843516#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 843515#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 843514#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 843512#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 843510#L1397-3 assume !(1 == ~E_1~0); 843508#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 843506#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 843504#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 843500#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 843498#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 843480#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 843475#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 843470#L1437-3 assume !(1 == ~E_9~0); 843463#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 843457#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 843456#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 805035#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 842408#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 842388#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 842381#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 842373#L1822 assume !(0 == start_simulation_~tmp~3#1); 842363#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 839439#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 839430#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 839428#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 839426#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 839424#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 839422#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 839420#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 839418#L1803-2 [2022-12-13 15:37:55,968 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:55,968 INFO L85 PathProgramCache]: Analyzing trace with hash 1989947900, now seen corresponding path program 1 times [2022-12-13 15:37:55,968 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:55,968 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [61627241] [2022-12-13 15:37:55,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:55,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:55,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:56,050 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:56,050 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:56,050 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [61627241] [2022-12-13 15:37:56,050 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [61627241] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:56,050 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:56,051 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:56,051 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [836357610] [2022-12-13 15:37:56,051 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:56,051 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:37:56,052 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:37:56,052 INFO L85 PathProgramCache]: Analyzing trace with hash 770456125, now seen corresponding path program 1 times [2022-12-13 15:37:56,052 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:37:56,052 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1363725048] [2022-12-13 15:37:56,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:37:56,052 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:37:56,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:37:56,106 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:37:56,106 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:37:56,106 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1363725048] [2022-12-13 15:37:56,106 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1363725048] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:37:56,106 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:37:56,106 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:37:56,107 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1956661501] [2022-12-13 15:37:56,107 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:37:56,107 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:37:56,107 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:37:56,108 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 15:37:56,108 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 15:37:56,108 INFO L87 Difference]: Start difference. First operand 159714 states and 227961 transitions. cyclomatic complexity: 68279 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:37:57,335 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:37:57,335 INFO L93 Difference]: Finished difference Result 386469 states and 548410 transitions. [2022-12-13 15:37:57,335 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 386469 states and 548410 transitions. [2022-12-13 15:37:58,674 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 379492 [2022-12-13 15:37:59,281 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 386469 states to 386469 states and 548410 transitions. [2022-12-13 15:37:59,281 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 386469 [2022-12-13 15:37:59,437 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 386469 [2022-12-13 15:37:59,437 INFO L73 IsDeterministic]: Start isDeterministic. Operand 386469 states and 548410 transitions. [2022-12-13 15:37:59,720 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:37:59,720 INFO L218 hiAutomatonCegarLoop]: Abstraction has 386469 states and 548410 transitions. [2022-12-13 15:37:59,895 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 386469 states and 548410 transitions. [2022-12-13 15:38:01,947 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 386469 to 305489. [2022-12-13 15:38:02,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 305489 states, 305489 states have (on average 1.4227877272176739) internal successors, (434646), 305488 states have internal predecessors, (434646), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:38:02,818 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 305489 states to 305489 states and 434646 transitions. [2022-12-13 15:38:02,818 INFO L240 hiAutomatonCegarLoop]: Abstraction has 305489 states and 434646 transitions. [2022-12-13 15:38:02,819 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 15:38:02,819 INFO L428 stractBuchiCegarLoop]: Abstraction has 305489 states and 434646 transitions. [2022-12-13 15:38:02,819 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-12-13 15:38:02,819 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 305489 states and 434646 transitions. [2022-12-13 15:38:03,590 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 304880 [2022-12-13 15:38:03,590 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:38:03,590 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:38:03,593 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:38:03,593 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:38:03,593 INFO L748 eck$LassoCheckResult]: Stem: 1236544#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1236545#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1237528#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1237529#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1236611#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 1236612#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1236518#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1236519#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1237911#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1237167#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1237168#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1237063#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1237064#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1237617#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1237618#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1236808#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1236809#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1237263#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1237264#L1194 assume !(0 == ~M_E~0); 1237438#L1194-2 assume !(0 == ~T1_E~0); 1237439#L1199-1 assume !(0 == ~T2_E~0); 1237758#L1204-1 assume !(0 == ~T3_E~0); 1237667#L1209-1 assume !(0 == ~T4_E~0); 1237668#L1214-1 assume !(0 == ~T5_E~0); 1238166#L1219-1 assume !(0 == ~T6_E~0); 1238312#L1224-1 assume !(0 == ~T7_E~0); 1236888#L1229-1 assume !(0 == ~T8_E~0); 1236447#L1234-1 assume !(0 == ~T9_E~0); 1236448#L1239-1 assume !(0 == ~T10_E~0); 1236486#L1244-1 assume !(0 == ~T11_E~0); 1236487#L1249-1 assume !(0 == ~T12_E~0); 1237202#L1254-1 assume !(0 == ~E_M~0); 1236380#L1259-1 assume !(0 == ~E_1~0); 1236346#L1264-1 assume !(0 == ~E_2~0); 1236347#L1269-1 assume !(0 == ~E_3~0); 1238330#L1274-1 assume !(0 == ~E_4~0); 1238219#L1279-1 assume !(0 == ~E_5~0); 1236553#L1284-1 assume !(0 == ~E_6~0); 1236554#L1289-1 assume !(0 == ~E_7~0); 1237274#L1294-1 assume !(0 == ~E_8~0); 1237275#L1299-1 assume !(0 == ~E_9~0); 1237287#L1304-1 assume !(0 == ~E_10~0); 1238297#L1309-1 assume !(0 == ~E_11~0); 1238308#L1314-1 assume !(0 == ~E_12~0); 1236512#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1236437#L586 assume !(1 == ~m_pc~0); 1236438#L586-2 is_master_triggered_~__retres1~0#1 := 0; 1236503#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1237356#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1236713#L1485 assume !(0 != activate_threads_~tmp~1#1); 1236714#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1237920#L605 assume !(1 == ~t1_pc~0); 1237373#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1237092#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1237093#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1237803#L1493 assume !(0 != activate_threads_~tmp___0~0#1); 1237730#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1236996#L624 assume !(1 == ~t2_pc~0); 1236997#L624-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1237174#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1236736#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1236737#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 1237961#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1237801#L643 assume !(1 == ~t3_pc~0); 1237640#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1237312#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1237313#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1236815#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 1236816#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1236575#L662 assume !(1 == ~t4_pc~0); 1236576#L662-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1236533#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1236402#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1236403#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 1236428#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1236429#L681 assume !(1 == ~t5_pc~0); 1236296#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1236297#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1237402#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1238119#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 1236828#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1236829#L700 assume !(1 == ~t6_pc~0); 1236657#L700-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1236566#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1236567#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1236613#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 1236614#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1238026#L719 assume !(1 == ~t7_pc~0); 1236781#L719-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1236782#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1238289#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1238195#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 1236310#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1236311#L738 assume !(1 == ~t8_pc~0); 1237766#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1237659#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1237660#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1237434#L1549 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1237435#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1237828#L757 assume 1 == ~t9_pc~0; 1237829#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1236305#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1236306#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1236779#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 1237394#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1237395#L776 assume !(1 == ~t10_pc~0); 1236330#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1236329#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1236719#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1236555#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 1236556#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1236513#L795 assume 1 == ~t11_pc~0; 1236514#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1236852#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1237938#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1238154#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 1237632#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1237620#L814 assume !(1 == ~t12_pc~0); 1237467#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1237468#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1236361#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1236362#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 1236764#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1236765#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 1237974#L1332-2 assume !(1 == ~T1_E~0); 1238248#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1237546#L1342-1 assume !(1 == ~T3_E~0); 1237547#L1347-1 assume !(1 == ~T4_E~0); 1238011#L1352-1 assume !(1 == ~T5_E~0); 1238012#L1357-1 assume !(1 == ~T6_E~0); 1237061#L1362-1 assume !(1 == ~T7_E~0); 1237062#L1367-1 assume !(1 == ~T8_E~0); 1236653#L1372-1 assume !(1 == ~T9_E~0); 1236654#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1236969#L1382-1 assume !(1 == ~T11_E~0); 1236970#L1387-1 assume !(1 == ~T12_E~0); 1238184#L1392-1 assume !(1 == ~E_M~0); 1238185#L1397-1 assume !(1 == ~E_1~0); 1238250#L1402-1 assume !(1 == ~E_2~0); 1238251#L1407-1 assume !(1 == ~E_3~0); 1238295#L1412-1 assume !(1 == ~E_4~0); 1238296#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1353381#L1422-1 assume !(1 == ~E_6~0); 1238249#L1427-1 assume !(1 == ~E_7~0); 1236853#L1432-1 assume !(1 == ~E_8~0); 1236854#L1437-1 assume !(1 == ~E_9~0); 1237876#L1442-1 assume !(1 == ~E_10~0); 1237877#L1447-1 assume !(1 == ~E_11~0); 1237713#L1452-1 assume !(1 == ~E_12~0); 1236456#L1457-1 assume { :end_inline_reset_delta_events } true; 1236457#L1803-2 [2022-12-13 15:38:03,594 INFO L750 eck$LassoCheckResult]: Loop: 1236457#L1803-2 assume !false; 1367859#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1367853#L1169 assume !false; 1367832#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1367751#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1367738#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1367737#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1367735#L996 assume !(0 != eval_~tmp~0#1); 1367736#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1382411#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1382408#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1382405#L1194-5 assume !(0 == ~T1_E~0); 1382402#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1382390#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1382385#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1382378#L1214-3 assume !(0 == ~T5_E~0); 1382373#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1382368#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1382363#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1382357#L1234-3 assume !(0 == ~T9_E~0); 1382354#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1382294#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1382289#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1382282#L1254-3 assume !(0 == ~E_M~0); 1382276#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1382259#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1382251#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1382246#L1274-3 assume !(0 == ~E_4~0); 1382241#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1382234#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1382228#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1381869#L1294-3 assume !(0 == ~E_8~0); 1381868#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1381867#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1381860#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1381822#L1314-3 assume !(0 == ~E_12~0); 1381815#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1380239#L586-42 assume !(1 == ~m_pc~0); 1380234#L586-44 is_master_triggered_~__retres1~0#1 := 0; 1380228#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1380221#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1380214#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 1379281#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1376761#L605-42 assume 1 == ~t1_pc~0; 1376759#L606-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1376760#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1376762#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1376751#L1493-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1376749#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1372136#L624-42 assume !(1 == ~t2_pc~0); 1372128#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1372121#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1372115#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1372109#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1372103#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1372098#L643-42 assume 1 == ~t3_pc~0; 1371962#L644-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1371960#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1371958#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1371956#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1371954#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1371952#L662-42 assume !(1 == ~t4_pc~0); 1371949#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1371947#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1371945#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1371943#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1371941#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1371939#L681-42 assume 1 == ~t5_pc~0; 1371937#L682-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1371935#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1371933#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1371931#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1371929#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1371927#L700-42 assume !(1 == ~t6_pc~0); 1330848#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 1371925#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1371923#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1371921#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1371919#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1371917#L719-42 assume !(1 == ~t7_pc~0); 1286407#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 1371914#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1371912#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1371910#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 1371908#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1371906#L738-42 assume !(1 == ~t8_pc~0); 1371904#L738-44 is_transmit8_triggered_~__retres1~8#1 := 0; 1371890#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1371884#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1371728#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1371725#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1371723#L757-42 assume 1 == ~t9_pc~0; 1371720#L758-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1371718#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1371716#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1371714#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1371711#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1371709#L776-42 assume 1 == ~t10_pc~0; 1371702#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1371699#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1371697#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1371695#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1371693#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1371691#L795-42 assume !(1 == ~t11_pc~0); 1371689#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 1371686#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1371684#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1371682#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1371680#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1371678#L814-42 assume !(1 == ~t12_pc~0); 1371676#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 1371674#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1371672#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1371670#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1371668#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1371666#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1315780#L1332-5 assume !(1 == ~T1_E~0); 1371664#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1371662#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1371660#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1371658#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1371656#L1357-3 assume !(1 == ~T6_E~0); 1371654#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1371651#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1371649#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1315760#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1371646#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1371644#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1371642#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1371641#L1397-3 assume !(1 == ~E_1~0); 1371638#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1371636#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1371634#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1350490#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1371631#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1371629#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1371626#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1371624#L1437-3 assume !(1 == ~E_9~0); 1371591#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1371581#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1371569#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1353957#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1370450#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1370434#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1370432#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1370430#L1822 assume !(0 == start_simulation_~tmp~3#1); 1370428#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1370065#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1370049#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1370043#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 1370034#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1370027#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1370022#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1369443#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 1236457#L1803-2 [2022-12-13 15:38:03,594 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:38:03,595 INFO L85 PathProgramCache]: Analyzing trace with hash -1728090755, now seen corresponding path program 1 times [2022-12-13 15:38:03,595 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:38:03,595 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [469480026] [2022-12-13 15:38:03,595 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:38:03,595 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:38:03,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:38:03,657 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:38:03,658 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:38:03,658 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [469480026] [2022-12-13 15:38:03,658 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [469480026] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:38:03,658 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:38:03,658 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 15:38:03,658 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [322604462] [2022-12-13 15:38:03,659 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:38:03,659 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:38:03,659 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:38:03,659 INFO L85 PathProgramCache]: Analyzing trace with hash 1365124349, now seen corresponding path program 1 times [2022-12-13 15:38:03,660 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:38:03,660 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [910518814] [2022-12-13 15:38:03,660 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:38:03,660 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:38:03,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:38:03,714 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:38:03,714 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:38:03,714 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [910518814] [2022-12-13 15:38:03,714 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [910518814] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:38:03,714 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:38:03,715 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:38:03,715 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [237768751] [2022-12-13 15:38:03,715 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:38:03,715 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:38:03,715 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:38:03,716 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 15:38:03,716 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 15:38:03,716 INFO L87 Difference]: Start difference. First operand 305489 states and 434646 transitions. cyclomatic complexity: 129189 Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:38:05,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:38:05,988 INFO L93 Difference]: Finished difference Result 737652 states and 1056403 transitions. [2022-12-13 15:38:05,988 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 737652 states and 1056403 transitions. [2022-12-13 15:38:08,408 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 736032 [2022-12-13 15:38:09,671 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 737652 states to 737652 states and 1056403 transitions. [2022-12-13 15:38:09,671 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 737652 [2022-12-13 15:38:10,017 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 737652 [2022-12-13 15:38:10,017 INFO L73 IsDeterministic]: Start isDeterministic. Operand 737652 states and 1056403 transitions. [2022-12-13 15:38:10,208 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:38:10,208 INFO L218 hiAutomatonCegarLoop]: Abstraction has 737652 states and 1056403 transitions. [2022-12-13 15:38:10,452 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 737652 states and 1056403 transitions. [2022-12-13 15:38:13,602 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 737652 to 313652. [2022-12-13 15:38:13,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 313652 states, 313652 states have (on average 1.4117843979952305) internal successors, (442809), 313651 states have internal predecessors, (442809), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:38:14,192 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 313652 states to 313652 states and 442809 transitions. [2022-12-13 15:38:14,193 INFO L240 hiAutomatonCegarLoop]: Abstraction has 313652 states and 442809 transitions. [2022-12-13 15:38:14,193 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 15:38:14,193 INFO L428 stractBuchiCegarLoop]: Abstraction has 313652 states and 442809 transitions. [2022-12-13 15:38:14,193 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-12-13 15:38:14,194 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 313652 states and 442809 transitions. [2022-12-13 15:38:15,069 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 313040 [2022-12-13 15:38:15,070 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:38:15,070 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:38:15,071 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:38:15,072 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:38:15,072 INFO L748 eck$LassoCheckResult]: Stem: 2279698#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 2279699#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 2280673#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2280674#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2279765#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 2279766#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2279672#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2279673#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2281085#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2280314#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2280315#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2280212#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2280213#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2280768#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2280769#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 2279961#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 2279962#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 2280413#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2280414#L1194 assume !(0 == ~M_E~0); 2280583#L1194-2 assume !(0 == ~T1_E~0); 2280584#L1199-1 assume !(0 == ~T2_E~0); 2280922#L1204-1 assume !(0 == ~T3_E~0); 2280827#L1209-1 assume !(0 == ~T4_E~0); 2280828#L1214-1 assume !(0 == ~T5_E~0); 2281367#L1219-1 assume !(0 == ~T6_E~0); 2281545#L1224-1 assume !(0 == ~T7_E~0); 2280039#L1229-1 assume !(0 == ~T8_E~0); 2279601#L1234-1 assume !(0 == ~T9_E~0); 2279602#L1239-1 assume !(0 == ~T10_E~0); 2279640#L1244-1 assume !(0 == ~T11_E~0); 2279641#L1249-1 assume !(0 == ~T12_E~0); 2280349#L1254-1 assume !(0 == ~E_M~0); 2279534#L1259-1 assume !(0 == ~E_1~0); 2279500#L1264-1 assume !(0 == ~E_2~0); 2279501#L1269-1 assume !(0 == ~E_3~0); 2281567#L1274-1 assume !(0 == ~E_4~0); 2281418#L1279-1 assume !(0 == ~E_5~0); 2279707#L1284-1 assume !(0 == ~E_6~0); 2279708#L1289-1 assume !(0 == ~E_7~0); 2280421#L1294-1 assume !(0 == ~E_8~0); 2280422#L1299-1 assume !(0 == ~E_9~0); 2280436#L1304-1 assume !(0 == ~E_10~0); 2281530#L1309-1 assume !(0 == ~E_11~0); 2281538#L1314-1 assume !(0 == ~E_12~0); 2279666#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2279591#L586 assume !(1 == ~m_pc~0); 2279592#L586-2 is_master_triggered_~__retres1~0#1 := 0; 2279657#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2280501#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2279867#L1485 assume !(0 != activate_threads_~tmp~1#1); 2279868#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2281095#L605 assume !(1 == ~t1_pc~0); 2280520#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2280239#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2280240#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2280973#L1493 assume !(0 != activate_threads_~tmp___0~0#1); 2280889#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2280144#L624 assume !(1 == ~t2_pc~0); 2280145#L624-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2280320#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2279890#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2279891#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 2281145#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2280970#L643 assume !(1 == ~t3_pc~0); 2280790#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2280459#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2280460#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2279968#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 2279969#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2279729#L662 assume !(1 == ~t4_pc~0); 2279730#L662-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2279687#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2279553#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2279554#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 2279582#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2279583#L681 assume !(1 == ~t5_pc~0); 2279450#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2279451#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2280548#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2281318#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 2279981#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2279982#L700 assume !(1 == ~t6_pc~0); 2279810#L700-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2279720#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2279721#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2279767#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 2279768#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2281214#L719 assume !(1 == ~t7_pc~0); 2279934#L719-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2279935#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2281520#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2281393#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 2279464#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2279465#L738 assume !(1 == ~t8_pc~0); 2280931#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2280819#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2280820#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2280579#L1549 assume !(0 != activate_threads_~tmp___7~0#1); 2280580#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2281001#L757 assume 1 == ~t9_pc~0; 2281002#L758 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2279459#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2279460#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2279933#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 2280539#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2280540#L776 assume !(1 == ~t10_pc~0); 2279484#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 2279483#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2279871#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 2279709#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 2279710#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2279667#L795 assume 1 == ~t11_pc~0; 2279668#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 2280002#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2281119#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 2281354#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 2280783#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 2280771#L814 assume !(1 == ~t12_pc~0); 2280611#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 2280612#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 2279513#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 2279514#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 2279918#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2279919#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 2281159#L1332-2 assume !(1 == ~T1_E~0); 2281462#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2280692#L1342-1 assume !(1 == ~T3_E~0); 2280693#L1347-1 assume !(1 == ~T4_E~0); 2281196#L1352-1 assume !(1 == ~T5_E~0); 2281197#L1357-1 assume !(1 == ~T6_E~0); 2311053#L1362-1 assume !(1 == ~T7_E~0); 2311051#L1367-1 assume !(1 == ~T8_E~0); 2279806#L1372-1 assume !(1 == ~T9_E~0); 2279807#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2280117#L1382-1 assume !(1 == ~T11_E~0); 2280118#L1387-1 assume !(1 == ~T12_E~0); 2280886#L1392-1 assume !(1 == ~E_M~0); 2280146#L1397-1 assume !(1 == ~E_1~0); 2280147#L1402-1 assume !(1 == ~E_2~0); 2279822#L1407-1 assume !(1 == ~E_3~0); 2279823#L1412-1 assume !(1 == ~E_4~0); 2281528#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 2344918#L1422-1 assume !(1 == ~E_6~0); 2344904#L1427-1 assume !(1 == ~E_7~0); 2344902#L1432-1 assume !(1 == ~E_8~0); 2344900#L1437-1 assume !(1 == ~E_9~0); 2344898#L1442-1 assume !(1 == ~E_10~0); 2344896#L1447-1 assume !(1 == ~E_11~0); 2344894#L1452-1 assume !(1 == ~E_12~0); 2280872#L1457-1 assume { :end_inline_reset_delta_events } true; 2344888#L1803-2 [2022-12-13 15:38:15,072 INFO L750 eck$LassoCheckResult]: Loop: 2344888#L1803-2 assume !false; 2344887#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2344882#L1169 assume !false; 2344881#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 2343469#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 2343457#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 2343456#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2343357#L996 assume !(0 != eval_~tmp~0#1); 2343358#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2346879#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2346830#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2346822#L1194-5 assume !(0 == ~T1_E~0); 2346817#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2346811#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2346807#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2346698#L1214-3 assume !(0 == ~T5_E~0); 2346692#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2346685#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2346678#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2346671#L1234-3 assume !(0 == ~T9_E~0); 2346665#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 2346659#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 2346654#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 2346649#L1254-3 assume !(0 == ~E_M~0); 2346644#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2346640#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2346637#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2346401#L1274-3 assume !(0 == ~E_4~0); 2346396#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2346389#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2346128#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2346127#L1294-3 assume !(0 == ~E_8~0); 2346126#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2346125#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 2346124#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 2346123#L1314-3 assume !(0 == ~E_12~0); 2346122#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2346121#L586-42 assume !(1 == ~m_pc~0); 2346120#L586-44 is_master_triggered_~__retres1~0#1 := 0; 2346119#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2346118#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2346117#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 2346116#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2346115#L605-42 assume !(1 == ~t1_pc~0); 2346114#L605-44 is_transmit1_triggered_~__retres1~1#1 := 0; 2346112#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2346110#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2346108#L1493-42 assume !(0 != activate_threads_~tmp___0~0#1); 2346106#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2346105#L624-42 assume !(1 == ~t2_pc~0); 2342578#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 2346104#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2346103#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2346102#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2346101#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2346100#L643-42 assume !(1 == ~t3_pc~0); 2346099#L643-44 is_transmit3_triggered_~__retres1~3#1 := 0; 2346097#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2346096#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2346095#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2346094#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2346093#L662-42 assume !(1 == ~t4_pc~0); 2346092#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 2346091#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2346090#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2346089#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2346088#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2346087#L681-42 assume !(1 == ~t5_pc~0); 2346086#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 2346084#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2346083#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2346082#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2346081#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2346080#L700-42 assume !(1 == ~t6_pc~0); 2344952#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 2346079#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2346078#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2346077#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2346076#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2346075#L719-42 assume !(1 == ~t7_pc~0); 2336362#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 2346074#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2346073#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2346072#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 2346071#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2346070#L738-42 assume !(1 == ~t8_pc~0); 2346069#L738-44 is_transmit8_triggered_~__retres1~8#1 := 0; 2346067#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2346065#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2346063#L1549-42 assume !(0 != activate_threads_~tmp___7~0#1); 2346060#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2346057#L757-42 assume !(1 == ~t9_pc~0); 2346055#L757-44 is_transmit9_triggered_~__retres1~9#1 := 0; 2346052#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2346050#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2346048#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2345763#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2345761#L776-42 assume !(1 == ~t10_pc~0); 2345759#L776-44 is_transmit10_triggered_~__retres1~10#1 := 0; 2345755#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2345753#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 2345751#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2345749#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2345747#L795-42 assume 1 == ~t11_pc~0; 2345745#L796-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 2345741#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2345739#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 2345737#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2345735#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 2345733#L814-42 assume !(1 == ~t12_pc~0); 2345731#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 2345727#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 2345725#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 2345723#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 2345721#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2345719#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2311159#L1332-5 assume !(1 == ~T1_E~0); 2345713#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2345711#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2345709#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2345707#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2345705#L1357-3 assume !(1 == ~T6_E~0); 2345703#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2345701#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2345699#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2345695#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2345693#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 2345691#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 2345689#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2345687#L1397-3 assume !(1 == ~E_1~0); 2345685#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2345683#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2345681#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2322487#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2345678#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2345676#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2345674#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2345672#L1437-3 assume !(1 == ~E_9~0); 2345670#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2345668#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 2345666#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 2345662#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 2345657#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 2345637#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 2345629#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 2345623#L1822 assume !(0 == start_simulation_~tmp~3#1); 2345578#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 2344912#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 2344903#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 2344901#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 2344899#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2344897#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2344895#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 2344893#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 2344888#L1803-2 [2022-12-13 15:38:15,072 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:38:15,072 INFO L85 PathProgramCache]: Analyzing trace with hash -1284190081, now seen corresponding path program 1 times [2022-12-13 15:38:15,073 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:38:15,073 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [983869632] [2022-12-13 15:38:15,073 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:38:15,073 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:38:15,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:38:15,116 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:38:15,117 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:38:15,117 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [983869632] [2022-12-13 15:38:15,117 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [983869632] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:38:15,117 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:38:15,117 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:38:15,117 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1729978934] [2022-12-13 15:38:15,117 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:38:15,117 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:38:15,118 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:38:15,118 INFO L85 PathProgramCache]: Analyzing trace with hash 1879361093, now seen corresponding path program 1 times [2022-12-13 15:38:15,118 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:38:15,118 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [643428686] [2022-12-13 15:38:15,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:38:15,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:38:15,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:38:15,148 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:38:15,148 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:38:15,148 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [643428686] [2022-12-13 15:38:15,148 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [643428686] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:38:15,148 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:38:15,148 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:38:15,149 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1933886943] [2022-12-13 15:38:15,149 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:38:15,149 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:38:15,149 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:38:15,149 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 15:38:15,149 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 15:38:15,150 INFO L87 Difference]: Start difference. First operand 313652 states and 442809 transitions. cyclomatic complexity: 129189 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:38:17,269 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:38:17,269 INFO L93 Difference]: Finished difference Result 754675 states and 1059654 transitions. [2022-12-13 15:38:17,269 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 754675 states and 1059654 transitions. [2022-12-13 15:38:20,053 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 740624 [2022-12-13 15:38:21,372 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 754675 states to 754675 states and 1059654 transitions. [2022-12-13 15:38:21,372 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 754675 [2022-12-13 15:38:21,618 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 754675 [2022-12-13 15:38:21,618 INFO L73 IsDeterministic]: Start isDeterministic. Operand 754675 states and 1059654 transitions. [2022-12-13 15:38:21,831 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:38:21,831 INFO L218 hiAutomatonCegarLoop]: Abstraction has 754675 states and 1059654 transitions. [2022-12-13 15:38:22,171 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 754675 states and 1059654 transitions. [2022-12-13 15:38:26,594 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 754675 to 599139. [2022-12-13 15:38:26,827 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 599139 states, 599139 states have (on average 1.4077367689300813) internal successors, (843430), 599138 states have internal predecessors, (843430), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:38:27,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 599139 states to 599139 states and 843430 transitions. [2022-12-13 15:38:27,845 INFO L240 hiAutomatonCegarLoop]: Abstraction has 599139 states and 843430 transitions. [2022-12-13 15:38:27,845 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 15:38:27,846 INFO L428 stractBuchiCegarLoop]: Abstraction has 599139 states and 843430 transitions. [2022-12-13 15:38:27,846 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-12-13 15:38:27,846 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 599139 states and 843430 transitions. [2022-12-13 15:38:29,186 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 598144 [2022-12-13 15:38:29,186 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:38:29,186 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:38:29,188 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:38:29,188 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:38:29,189 INFO L748 eck$LassoCheckResult]: Stem: 3348033#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 3348034#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 3349016#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret33#1, start_simulation_#t~ret34#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3349017#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3348100#L841 assume 1 == ~m_i~0;~m_st~0 := 0; 3348101#L841-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3348008#L846-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3348009#L851-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3349429#L856-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3348660#L861-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3348661#L866-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3348553#L871-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3348554#L876-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3349108#L881-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3349109#L886-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3348296#L891-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 3348297#L896-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 3348755#L901-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3348756#L1194 assume !(0 == ~M_E~0); 3348925#L1194-2 assume !(0 == ~T1_E~0); 3348926#L1199-1 assume !(0 == ~T2_E~0); 3349254#L1204-1 assume !(0 == ~T3_E~0); 3349161#L1209-1 assume !(0 == ~T4_E~0); 3349162#L1214-1 assume !(0 == ~T5_E~0); 3349726#L1219-1 assume !(0 == ~T6_E~0); 3349930#L1224-1 assume !(0 == ~T7_E~0); 3348372#L1229-1 assume !(0 == ~T8_E~0); 3347936#L1234-1 assume !(0 == ~T9_E~0); 3347937#L1239-1 assume !(0 == ~T10_E~0); 3347976#L1244-1 assume !(0 == ~T11_E~0); 3347977#L1249-1 assume !(0 == ~T12_E~0); 3348692#L1254-1 assume !(0 == ~E_M~0); 3347870#L1259-1 assume !(0 == ~E_1~0); 3347837#L1264-1 assume !(0 == ~E_2~0); 3347838#L1269-1 assume !(0 == ~E_3~0); 3349951#L1274-1 assume !(0 == ~E_4~0); 3349792#L1279-1 assume !(0 == ~E_5~0); 3348042#L1284-1 assume !(0 == ~E_6~0); 3348043#L1289-1 assume !(0 == ~E_7~0); 3348763#L1294-1 assume !(0 == ~E_8~0); 3348764#L1299-1 assume !(0 == ~E_9~0); 3348778#L1304-1 assume !(0 == ~E_10~0); 3349913#L1309-1 assume !(0 == ~E_11~0); 3349923#L1314-1 assume !(0 == ~E_12~0); 3348002#L1319-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3347926#L586 assume !(1 == ~m_pc~0); 3347927#L586-2 is_master_triggered_~__retres1~0#1 := 0; 3347993#L597 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3348843#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3348202#L1485 assume !(0 != activate_threads_~tmp~1#1); 3348203#L1485-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3349438#L605 assume !(1 == ~t1_pc~0); 3348862#L605-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3348583#L616 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3348584#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3349307#L1493 assume !(0 != activate_threads_~tmp___0~0#1); 3349219#L1493-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3348486#L624 assume !(1 == ~t2_pc~0); 3348487#L624-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3348667#L635 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3348225#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3348226#L1501 assume !(0 != activate_threads_~tmp___1~0#1); 3349492#L1501-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3349305#L643 assume !(1 == ~t3_pc~0); 3349130#L643-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3348802#L654 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3348803#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3348303#L1509 assume !(0 != activate_threads_~tmp___2~0#1); 3348304#L1509-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3348064#L662 assume !(1 == ~t4_pc~0); 3348065#L662-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3348022#L673 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3347892#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3347893#L1517 assume !(0 != activate_threads_~tmp___3~0#1); 3347918#L1517-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3347919#L681 assume !(1 == ~t5_pc~0); 3347787#L681-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3347788#L692 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3348892#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3349678#L1525 assume !(0 != activate_threads_~tmp___4~0#1); 3348315#L1525-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3348316#L700 assume !(1 == ~t6_pc~0); 3348145#L700-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3348055#L711 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3348056#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3348102#L1533 assume !(0 != activate_threads_~tmp___5~0#1); 3348103#L1533-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3349569#L719 assume !(1 == ~t7_pc~0); 3348269#L719-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3348270#L730 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3349898#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3349765#L1541 assume !(0 != activate_threads_~tmp___6~0#1); 3347801#L1541-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3347802#L738 assume !(1 == ~t8_pc~0); 3349262#L738-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3349152#L749 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3349153#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3348921#L1549 assume !(0 != activate_threads_~tmp___7~0#1); 3348922#L1549-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3349332#L757 assume !(1 == ~t9_pc~0); 3349333#L757-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3347796#L768 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3347797#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3348268#L1557 assume !(0 != activate_threads_~tmp___8~0#1); 3348884#L1557-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3348885#L776 assume !(1 == ~t10_pc~0); 3347821#L776-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3347820#L787 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3348206#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3348044#L1565 assume !(0 != activate_threads_~tmp___9~0#1); 3348045#L1565-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3348003#L795 assume 1 == ~t11_pc~0; 3348004#L796 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3348335#L806 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3349464#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3349714#L1573 assume !(0 != activate_threads_~tmp___10~0#1); 3349124#L1573-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 3349111#L814 assume !(1 == ~t12_pc~0); 3348953#L814-2 is_transmit12_triggered_~__retres1~12#1 := 0; 3348954#L825 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3347850#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3347851#L1581 assume !(0 != activate_threads_~tmp___11~0#1); 3348253#L1581-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3348254#L1332 assume 1 == ~M_E~0;~M_E~0 := 2; 3349506#L1332-2 assume !(1 == ~T1_E~0); 3349825#L1337-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3349035#L1342-1 assume !(1 == ~T3_E~0); 3349036#L1347-1 assume !(1 == ~T4_E~0); 3349551#L1352-1 assume !(1 == ~T5_E~0); 3349552#L1357-1 assume !(1 == ~T6_E~0); 3348551#L1362-1 assume !(1 == ~T7_E~0); 3348552#L1367-1 assume !(1 == ~T8_E~0); 3348141#L1372-1 assume !(1 == ~T9_E~0); 3348142#L1377-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3348456#L1382-1 assume !(1 == ~T11_E~0); 3348457#L1387-1 assume !(1 == ~T12_E~0); 3349755#L1392-1 assume !(1 == ~E_M~0); 3349756#L1397-1 assume !(1 == ~E_1~0); 3349829#L1402-1 assume !(1 == ~E_2~0); 3349830#L1407-1 assume !(1 == ~E_3~0); 3349908#L1412-1 assume !(1 == ~E_4~0); 3349462#L1417-1 assume 1 == ~E_5~0;~E_5~0 := 2; 3349463#L1422-1 assume !(1 == ~E_6~0); 3349828#L1427-1 assume !(1 == ~E_7~0); 3348336#L1432-1 assume !(1 == ~E_8~0); 3348337#L1437-1 assume !(1 == ~E_9~0); 3349383#L1442-1 assume !(1 == ~E_10~0); 3349384#L1447-1 assume !(1 == ~E_11~0); 3349205#L1452-1 assume !(1 == ~E_12~0); 3349206#L1457-1 assume { :end_inline_reset_delta_events } true; 3565556#L1803-2 [2022-12-13 15:38:29,189 INFO L750 eck$LassoCheckResult]: Loop: 3565556#L1803-2 assume !false; 3565544#L1804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3565512#L1169 assume !false; 3565508#L992 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 3565435#L914 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3565421#L981 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3565419#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3565417#L996 assume !(0 != eval_~tmp~0#1); 3565418#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3635183#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3635182#L1194-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3635181#L1194-5 assume !(0 == ~T1_E~0); 3635180#L1199-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3635179#L1204-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3635177#L1209-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3635175#L1214-3 assume !(0 == ~T5_E~0); 3635173#L1219-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3635171#L1224-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3635169#L1229-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3634641#L1234-3 assume !(0 == ~T9_E~0); 3634636#L1239-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3634632#L1244-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 3634627#L1249-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 3634623#L1254-3 assume !(0 == ~E_M~0); 3634616#L1259-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3634611#L1264-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3634606#L1269-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3634601#L1274-3 assume !(0 == ~E_4~0); 3634596#L1279-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3634591#L1284-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3634586#L1289-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3634582#L1294-3 assume !(0 == ~E_8~0); 3634578#L1299-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3634573#L1304-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3634569#L1309-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3634566#L1314-3 assume !(0 == ~E_12~0); 3634563#L1319-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3634559#L586-42 assume !(1 == ~m_pc~0); 3634555#L586-44 is_master_triggered_~__retres1~0#1 := 0; 3634551#L597-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3634546#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3634540#L1485-42 assume !(0 != activate_threads_~tmp~1#1); 3634535#L1485-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3634530#L605-42 assume !(1 == ~t1_pc~0); 3634526#L605-44 is_transmit1_triggered_~__retres1~1#1 := 0; 3634520#L616-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3634514#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3634506#L1493-42 assume !(0 != activate_threads_~tmp___0~0#1); 3634499#L1493-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3634494#L624-42 assume !(1 == ~t2_pc~0); 3633719#L624-44 is_transmit2_triggered_~__retres1~2#1 := 0; 3634487#L635-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3634483#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3634480#L1501-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3634477#L1501-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3634473#L643-42 assume !(1 == ~t3_pc~0); 3634469#L643-44 is_transmit3_triggered_~__retres1~3#1 := 0; 3634463#L654-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3634459#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3634453#L1509-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3634449#L1509-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3634445#L662-42 assume !(1 == ~t4_pc~0); 3634440#L662-44 is_transmit4_triggered_~__retres1~4#1 := 0; 3634435#L673-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3634430#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3634423#L1517-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3634418#L1517-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3633394#L681-42 assume !(1 == ~t5_pc~0); 3633391#L681-44 is_transmit5_triggered_~__retres1~5#1 := 0; 3633388#L692-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3633386#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3633384#L1525-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3633382#L1525-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3566677#L700-42 assume !(1 == ~t6_pc~0); 3566674#L700-44 is_transmit6_triggered_~__retres1~6#1 := 0; 3566672#L711-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3566670#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3566669#L1533-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3566667#L1533-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3566665#L719-42 assume !(1 == ~t7_pc~0); 3510094#L719-44 is_transmit7_triggered_~__retres1~7#1 := 0; 3566662#L730-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3566660#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3566659#L1541-42 assume !(0 != activate_threads_~tmp___6~0#1); 3566656#L1541-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3566654#L738-42 assume 1 == ~t8_pc~0; 3566652#L739-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3566653#L749-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3566688#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3566643#L1549-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3566642#L1549-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3566605#L757-42 assume !(1 == ~t9_pc~0); 3468754#L757-44 is_transmit9_triggered_~__retres1~9#1 := 0; 3566591#L768-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3566584#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3566575#L1557-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3566567#L1557-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3566560#L776-42 assume 1 == ~t10_pc~0; 3566554#L777-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3566545#L787-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3566538#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3566529#L1565-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3566523#L1565-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3566516#L795-42 assume !(1 == ~t11_pc~0); 3566508#L795-44 is_transmit11_triggered_~__retres1~11#1 := 0; 3566500#L806-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3566491#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3566484#L1573-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3566477#L1573-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 3566469#L814-42 assume !(1 == ~t12_pc~0); 3566462#L814-44 is_transmit12_triggered_~__retres1~12#1 := 0; 3566454#L825-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3566446#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3566438#L1581-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 3566431#L1581-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3566424#L1332-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3502912#L1332-5 assume !(1 == ~T1_E~0); 3566411#L1337-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3566404#L1342-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3566397#L1347-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3566390#L1352-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3566384#L1357-3 assume !(1 == ~T6_E~0); 3566376#L1362-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3566368#L1367-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3566362#L1372-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3566354#L1377-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3566348#L1382-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3566341#L1387-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 3566334#L1392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3566327#L1397-3 assume !(1 == ~E_1~0); 3566319#L1402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3566313#L1407-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3566206#L1412-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3566202#L1417-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3566200#L1422-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3566198#L1427-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3566178#L1432-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3566170#L1437-3 assume !(1 == ~E_9~0); 3566163#L1442-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3566157#L1447-3 assume 1 == ~E_11~0;~E_11~0 := 2; 3566151#L1452-3 assume 1 == ~E_12~0;~E_12~0 := 2; 3533569#L1457-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 3565979#L914-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3565962#L981-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3565956#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 3565951#L1822 assume !(0 == start_simulation_~tmp~3#1); 3565947#L1822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret32#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 3565754#L914-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3565739#L981-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3565731#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret32#1;havoc stop_simulation_#t~ret32#1; 3565725#L1777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3565579#L1784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3565574#stop_simulation_returnLabel#1 start_simulation_#t~ret34#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 3565571#L1835 assume !(0 != start_simulation_~tmp___0~1#1); 3565556#L1803-2 [2022-12-13 15:38:29,189 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:38:29,189 INFO L85 PathProgramCache]: Analyzing trace with hash 909936000, now seen corresponding path program 1 times [2022-12-13 15:38:29,189 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:38:29,189 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [553673523] [2022-12-13 15:38:29,189 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:38:29,190 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:38:29,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:38:29,446 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:38:29,447 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:38:29,447 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [553673523] [2022-12-13 15:38:29,447 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [553673523] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:38:29,447 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:38:29,447 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:38:29,447 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [940452223] [2022-12-13 15:38:29,448 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:38:29,448 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:38:29,448 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:38:29,448 INFO L85 PathProgramCache]: Analyzing trace with hash 86803522, now seen corresponding path program 1 times [2022-12-13 15:38:29,449 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:38:29,449 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2061738530] [2022-12-13 15:38:29,449 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:38:29,449 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:38:29,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:38:29,486 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:38:29,486 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:38:29,487 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2061738530] [2022-12-13 15:38:29,487 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2061738530] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:38:29,487 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:38:29,487 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:38:29,487 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1802680589] [2022-12-13 15:38:29,487 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:38:29,488 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:38:29,488 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:38:29,488 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 15:38:29,488 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 15:38:29,489 INFO L87 Difference]: Start difference. First operand 599139 states and 843430 transitions. cyclomatic complexity: 244323 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:38:34,225 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:38:34,225 INFO L93 Difference]: Finished difference Result 1465458 states and 2049779 transitions. [2022-12-13 15:38:34,225 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1465458 states and 2049779 transitions. [2022-12-13 15:38:39,363 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 1437712 [2022-12-13 15:38:42,333 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1465458 states to 1465458 states and 2049779 transitions. [2022-12-13 15:38:42,333 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1465458 [2022-12-13 15:38:42,820 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1465458 [2022-12-13 15:38:42,820 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1465458 states and 2049779 transitions. [2022-12-13 15:38:43,400 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:38:43,400 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1465458 states and 2049779 transitions. [2022-12-13 15:38:44,063 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1465458 states and 2049779 transitions. [2022-12-13 15:38:52,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1465458 to 1167010. [2022-12-13 15:38:52,635 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1167010 states, 1167010 states have (on average 1.4024241437519815) internal successors, (1636643), 1167009 states have internal predecessors, (1636643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)