./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.13.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05334efe-f067-46a5-a63a-2683bf946a78/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05334efe-f067-46a5-a63a-2683bf946a78/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05334efe-f067-46a5-a63a-2683bf946a78/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05334efe-f067-46a5-a63a-2683bf946a78/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.13.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05334efe-f067-46a5-a63a-2683bf946a78/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05334efe-f067-46a5-a63a-2683bf946a78/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 1b2c6a3c4af8091017033117c21d8fbc40cee2009788b890a114045d77587077 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 18:37:18,846 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 18:37:18,847 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 18:37:18,865 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 18:37:18,865 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 18:37:18,866 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 18:37:18,868 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 18:37:18,869 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 18:37:18,871 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 18:37:18,872 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 18:37:18,872 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 18:37:18,873 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 18:37:18,874 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 18:37:18,875 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 18:37:18,876 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 18:37:18,877 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 18:37:18,878 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 18:37:18,879 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 18:37:18,880 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 18:37:18,882 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 18:37:18,884 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 18:37:18,885 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 18:37:18,886 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 18:37:18,887 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 18:37:18,890 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 18:37:18,891 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 18:37:18,891 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 18:37:18,892 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 18:37:18,892 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 18:37:18,893 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 18:37:18,893 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 18:37:18,894 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 18:37:18,895 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 18:37:18,896 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 18:37:18,897 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 18:37:18,897 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 18:37:18,898 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 18:37:18,898 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 18:37:18,898 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 18:37:18,899 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 18:37:18,900 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 18:37:18,900 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05334efe-f067-46a5-a63a-2683bf946a78/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 18:37:18,922 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 18:37:18,922 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 18:37:18,923 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 18:37:18,923 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 18:37:18,924 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 18:37:18,924 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 18:37:18,924 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 18:37:18,924 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 18:37:18,925 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 18:37:18,925 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 18:37:18,925 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 18:37:18,925 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 18:37:18,925 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 18:37:18,926 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 18:37:18,926 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 18:37:18,926 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 18:37:18,926 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 18:37:18,926 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 18:37:18,927 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 18:37:18,927 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 18:37:18,927 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 18:37:18,927 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 18:37:18,927 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 18:37:18,927 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 18:37:18,928 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 18:37:18,928 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 18:37:18,928 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 18:37:18,928 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 18:37:18,928 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 18:37:18,929 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 18:37:18,929 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 18:37:18,930 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 18:37:18,930 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05334efe-f067-46a5-a63a-2683bf946a78/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05334efe-f067-46a5-a63a-2683bf946a78/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1b2c6a3c4af8091017033117c21d8fbc40cee2009788b890a114045d77587077 [2022-12-13 18:37:19,144 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 18:37:19,160 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 18:37:19,161 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 18:37:19,162 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 18:37:19,162 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 18:37:19,163 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05334efe-f067-46a5-a63a-2683bf946a78/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/token_ring.13.cil-1.c [2022-12-13 18:37:21,844 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 18:37:22,028 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 18:37:22,029 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05334efe-f067-46a5-a63a-2683bf946a78/sv-benchmarks/c/systemc/token_ring.13.cil-1.c [2022-12-13 18:37:22,040 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05334efe-f067-46a5-a63a-2683bf946a78/bin/uautomizer-uyxdKDjOR8/data/d84a948e4/a438c20e7daa432fb89259c2e14bcc63/FLAGcb765cdff [2022-12-13 18:37:22,052 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05334efe-f067-46a5-a63a-2683bf946a78/bin/uautomizer-uyxdKDjOR8/data/d84a948e4/a438c20e7daa432fb89259c2e14bcc63 [2022-12-13 18:37:22,054 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 18:37:22,055 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 18:37:22,056 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 18:37:22,056 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 18:37:22,059 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 18:37:22,059 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 06:37:22" (1/1) ... [2022-12-13 18:37:22,060 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@294efa89 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 06:37:22, skipping insertion in model container [2022-12-13 18:37:22,060 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 06:37:22" (1/1) ... [2022-12-13 18:37:22,067 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 18:37:22,104 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 18:37:22,222 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05334efe-f067-46a5-a63a-2683bf946a78/sv-benchmarks/c/systemc/token_ring.13.cil-1.c[671,684] [2022-12-13 18:37:22,307 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 18:37:22,318 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 18:37:22,326 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05334efe-f067-46a5-a63a-2683bf946a78/sv-benchmarks/c/systemc/token_ring.13.cil-1.c[671,684] [2022-12-13 18:37:22,389 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 18:37:22,408 INFO L208 MainTranslator]: Completed translation [2022-12-13 18:37:22,409 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 06:37:22 WrapperNode [2022-12-13 18:37:22,409 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 18:37:22,410 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 18:37:22,410 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 18:37:22,410 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 18:37:22,417 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 06:37:22" (1/1) ... [2022-12-13 18:37:22,431 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 06:37:22" (1/1) ... [2022-12-13 18:37:22,521 INFO L138 Inliner]: procedures = 54, calls = 71, calls flagged for inlining = 66, calls inlined = 303, statements flattened = 4665 [2022-12-13 18:37:22,521 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 18:37:22,522 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 18:37:22,522 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 18:37:22,522 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 18:37:22,531 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 06:37:22" (1/1) ... [2022-12-13 18:37:22,532 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 06:37:22" (1/1) ... [2022-12-13 18:37:22,544 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 06:37:22" (1/1) ... [2022-12-13 18:37:22,544 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 06:37:22" (1/1) ... [2022-12-13 18:37:22,575 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 06:37:22" (1/1) ... [2022-12-13 18:37:22,595 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 06:37:22" (1/1) ... [2022-12-13 18:37:22,600 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 06:37:22" (1/1) ... [2022-12-13 18:37:22,607 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 06:37:22" (1/1) ... [2022-12-13 18:37:22,621 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 18:37:22,622 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 18:37:22,623 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 18:37:22,623 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 18:37:22,623 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 06:37:22" (1/1) ... [2022-12-13 18:37:22,629 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 18:37:22,640 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05334efe-f067-46a5-a63a-2683bf946a78/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 18:37:22,651 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05334efe-f067-46a5-a63a-2683bf946a78/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 18:37:22,653 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_05334efe-f067-46a5-a63a-2683bf946a78/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 18:37:22,682 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 18:37:22,683 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 18:37:22,683 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 18:37:22,683 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 18:37:22,775 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 18:37:22,776 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 18:37:24,438 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 18:37:24,453 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 18:37:24,453 INFO L300 CfgBuilder]: Removed 16 assume(true) statements. [2022-12-13 18:37:24,456 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 06:37:24 BoogieIcfgContainer [2022-12-13 18:37:24,456 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 18:37:24,457 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 18:37:24,457 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 18:37:24,460 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 18:37:24,460 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 18:37:24,460 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 06:37:22" (1/3) ... [2022-12-13 18:37:24,461 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@79409ccb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 06:37:24, skipping insertion in model container [2022-12-13 18:37:24,461 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 18:37:24,461 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 06:37:22" (2/3) ... [2022-12-13 18:37:24,461 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@79409ccb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 06:37:24, skipping insertion in model container [2022-12-13 18:37:24,461 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 18:37:24,462 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 06:37:24" (3/3) ... [2022-12-13 18:37:24,463 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.13.cil-1.c [2022-12-13 18:37:24,520 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 18:37:24,521 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 18:37:24,521 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 18:37:24,521 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 18:37:24,521 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 18:37:24,521 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 18:37:24,521 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 18:37:24,521 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 18:37:24,541 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2031 states, 2030 states have (on average 1.4965517241379311) internal successors, (3038), 2030 states have internal predecessors, (3038), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:24,590 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1852 [2022-12-13 18:37:24,591 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:37:24,591 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:37:24,601 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:24,602 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:24,602 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 18:37:24,604 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2031 states, 2030 states have (on average 1.4965517241379311) internal successors, (3038), 2030 states have internal predecessors, (3038), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:24,617 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1852 [2022-12-13 18:37:24,617 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:37:24,617 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:37:24,620 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:24,620 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:24,627 INFO L748 eck$LassoCheckResult]: Stem: 137#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1952#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 732#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1944#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1850#L914true assume !(1 == ~m_i~0);~m_st~0 := 2; 838#L914-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 447#L919-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1228#L924-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1113#L929-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1856#L934-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1269#L939-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1644#L944-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 308#L949-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 1319#L954-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 1961#L959-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 643#L964-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 1177#L969-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 1765#L974-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 585#L979-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1888#L1291true assume 0 == ~M_E~0;~M_E~0 := 1; 1852#L1291-2true assume !(0 == ~T1_E~0); 1844#L1296-1true assume !(0 == ~T2_E~0); 692#L1301-1true assume !(0 == ~T3_E~0); 1223#L1306-1true assume !(0 == ~T4_E~0); 1196#L1311-1true assume !(0 == ~T5_E~0); 226#L1316-1true assume !(0 == ~T6_E~0); 1648#L1321-1true assume !(0 == ~T7_E~0); 703#L1326-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 135#L1331-1true assume !(0 == ~T9_E~0); 3#L1336-1true assume !(0 == ~T10_E~0); 1077#L1341-1true assume !(0 == ~T11_E~0); 34#L1346-1true assume !(0 == ~T12_E~0); 1448#L1351-1true assume !(0 == ~T13_E~0); 194#L1356-1true assume !(0 == ~E_M~0); 1969#L1361-1true assume !(0 == ~E_1~0); 1621#L1366-1true assume 0 == ~E_2~0;~E_2~0 := 1; 217#L1371-1true assume !(0 == ~E_3~0); 1427#L1376-1true assume !(0 == ~E_4~0); 756#L1381-1true assume !(0 == ~E_5~0); 1723#L1386-1true assume !(0 == ~E_6~0); 1881#L1391-1true assume !(0 == ~E_7~0); 1797#L1396-1true assume !(0 == ~E_8~0); 663#L1401-1true assume !(0 == ~E_9~0); 1285#L1406-1true assume 0 == ~E_10~0;~E_10~0 := 1; 909#L1411-1true assume !(0 == ~E_11~0); 1682#L1416-1true assume !(0 == ~E_12~0); 611#L1421-1true assume !(0 == ~E_13~0); 318#L1426-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 761#L640true assume !(1 == ~m_pc~0); 1801#L640-2true is_master_triggered_~__retres1~0#1 := 0; 719#L651true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 615#is_master_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 635#L1603true assume !(0 != activate_threads_~tmp~1#1); 1270#L1603-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 403#L659true assume 1 == ~t1_pc~0; 465#L660true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1409#L670true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1039#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 477#L1611true assume !(0 != activate_threads_~tmp___0~0#1); 486#L1611-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1589#L678true assume 1 == ~t2_pc~0; 1449#L679true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1701#L689true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 238#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 547#L1619true assume !(0 != activate_threads_~tmp___1~0#1); 688#L1619-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 632#L697true assume !(1 == ~t3_pc~0); 739#L697-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1495#L708true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1019#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 572#L1627true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1913#L1627-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1531#L716true assume 1 == ~t4_pc~0; 1504#L717true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 391#L727true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 65#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 118#L1635true assume !(0 != activate_threads_~tmp___3~0#1); 984#L1635-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1473#L735true assume !(1 == ~t5_pc~0); 104#L735-2true is_transmit5_triggered_~__retres1~5#1 := 0; 334#L746true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1636#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1008#L1643true assume !(0 != activate_threads_~tmp___4~0#1); 685#L1643-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 876#L754true assume 1 == ~t6_pc~0; 521#L755true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 456#L765true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 228#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 439#L1651true assume !(0 != activate_threads_~tmp___5~0#1); 1103#L1651-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1959#L773true assume !(1 == ~t7_pc~0); 896#L773-2true is_transmit7_triggered_~__retres1~7#1 := 0; 721#L784true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1971#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 694#L1659true assume !(0 != activate_threads_~tmp___6~0#1); 749#L1659-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 884#L792true assume 1 == ~t8_pc~0; 1954#L793true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1271#L803true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1559#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 686#L1667true assume !(0 != activate_threads_~tmp___7~0#1); 633#L1667-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 805#L811true assume 1 == ~t9_pc~0; 1332#L812true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1696#L822true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 266#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 801#L1675true assume !(0 != activate_threads_~tmp___8~0#1); 640#L1675-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1726#L830true assume !(1 == ~t10_pc~0); 2018#L830-2true is_transmit10_triggered_~__retres1~10#1 := 0; 184#L841true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1345#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 172#L1683true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1792#L1683-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1124#L849true assume 1 == ~t11_pc~0; 1617#L850true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 92#L860true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1450#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1143#L1691true assume !(0 != activate_threads_~tmp___10~0#1); 1014#L1691-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1799#L868true assume !(1 == ~t12_pc~0); 1381#L868-2true is_transmit12_triggered_~__retres1~12#1 := 0; 568#L879true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 41#is_transmit12_triggered_returnLabel#1true activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1716#L1699true assume !(0 != activate_threads_~tmp___11~0#1); 202#L1699-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1619#L887true assume 1 == ~t13_pc~0; 1024#L888true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 569#L898true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1386#is_transmit13_triggered_returnLabel#1true activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1092#L1707true assume !(0 != activate_threads_~tmp___12~0#1); 58#L1707-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1674#L1439true assume !(1 == ~M_E~0); 681#L1439-2true assume !(1 == ~T1_E~0); 142#L1444-1true assume !(1 == ~T2_E~0); 914#L1449-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 405#L1454-1true assume !(1 == ~T4_E~0); 1447#L1459-1true assume !(1 == ~T5_E~0); 798#L1464-1true assume !(1 == ~T6_E~0); 860#L1469-1true assume !(1 == ~T7_E~0); 1704#L1474-1true assume !(1 == ~T8_E~0); 612#L1479-1true assume !(1 == ~T9_E~0); 802#L1484-1true assume !(1 == ~T10_E~0); 1242#L1489-1true assume 1 == ~T11_E~0;~T11_E~0 := 2; 533#L1494-1true assume !(1 == ~T12_E~0); 1834#L1499-1true assume !(1 == ~T13_E~0); 653#L1504-1true assume !(1 == ~E_M~0); 1503#L1509-1true assume !(1 == ~E_1~0); 1240#L1514-1true assume !(1 == ~E_2~0); 885#L1519-1true assume !(1 == ~E_3~0); 1953#L1524-1true assume !(1 == ~E_4~0); 1663#L1529-1true assume 1 == ~E_5~0;~E_5~0 := 2; 1766#L1534-1true assume !(1 == ~E_6~0); 55#L1539-1true assume !(1 == ~E_7~0); 264#L1544-1true assume !(1 == ~E_8~0); 1581#L1549-1true assume !(1 == ~E_9~0); 1605#L1554-1true assume !(1 == ~E_10~0); 1577#L1559-1true assume !(1 == ~E_11~0); 1309#L1564-1true assume !(1 == ~E_12~0); 1645#L1569-1true assume 1 == ~E_13~0;~E_13~0 := 2; 1742#L1574-1true assume { :end_inline_reset_delta_events } true; 141#L1940-2true [2022-12-13 18:37:24,629 INFO L750 eck$LassoCheckResult]: Loop: 141#L1940-2true assume !false; 1548#L1941true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1029#L1266true assume false; 562#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 355#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 967#L1291-3true assume 0 == ~M_E~0;~M_E~0 := 1; 861#L1291-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1861#L1296-3true assume !(0 == ~T2_E~0); 1769#L1301-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1603#L1306-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 588#L1311-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 160#L1316-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 212#L1321-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 676#L1326-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1566#L1331-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 889#L1336-3true assume !(0 == ~T10_E~0); 1489#L1341-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 401#L1346-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 387#L1351-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 354#L1356-3true assume 0 == ~E_M~0;~E_M~0 := 1; 740#L1361-3true assume 0 == ~E_1~0;~E_1~0 := 1; 769#L1366-3true assume 0 == ~E_2~0;~E_2~0 := 1; 24#L1371-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1279#L1376-3true assume !(0 == ~E_4~0); 1540#L1381-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1079#L1386-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1672#L1391-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1323#L1396-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1974#L1401-3true assume 0 == ~E_9~0;~E_9~0 := 1; 191#L1406-3true assume 0 == ~E_10~0;~E_10~0 := 1; 122#L1411-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1768#L1416-3true assume !(0 == ~E_12~0); 493#L1421-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1112#L1426-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 566#L640-45true assume 1 == ~m_pc~0; 1138#L641-15true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 244#L651-15true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 932#is_master_triggered_returnLabel#16true activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22#L1603-45true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1855#L1603-47true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61#L659-45true assume !(1 == ~t1_pc~0); 286#L659-47true is_transmit1_triggered_~__retres1~1#1 := 0; 1782#L670-15true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1858#is_transmit1_triggered_returnLabel#16true activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1545#L1611-45true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 992#L1611-47true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1514#L678-45true assume !(1 == ~t2_pc~0); 971#L678-47true is_transmit2_triggered_~__retres1~2#1 := 0; 570#L689-15true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 928#is_transmit2_triggered_returnLabel#16true activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1353#L1619-45true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1659#L1619-47true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1597#L697-45true assume !(1 == ~t3_pc~0); 1235#L697-47true is_transmit3_triggered_~__retres1~3#1 := 0; 1849#L708-15true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1990#is_transmit3_triggered_returnLabel#16true activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 897#L1627-45true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 934#L1627-47true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2014#L716-45true assume 1 == ~t4_pc~0; 619#L717-15true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2009#L727-15true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1288#is_transmit4_triggered_returnLabel#16true activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 623#L1635-45true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1498#L1635-47true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 411#L735-45true assume 1 == ~t5_pc~0; 795#L736-15true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1651#L746-15true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1985#is_transmit5_triggered_returnLabel#16true activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1829#L1643-45true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1657#L1643-47true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1641#L754-45true assume !(1 == ~t6_pc~0); 1484#L754-47true is_transmit6_triggered_~__retres1~6#1 := 0; 1991#L765-15true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 660#is_transmit6_triggered_returnLabel#16true activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1964#L1651-45true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 762#L1651-47true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 551#L773-45true assume !(1 == ~t7_pc~0); 283#L773-47true is_transmit7_triggered_~__retres1~7#1 := 0; 941#L784-15true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 730#is_transmit7_triggered_returnLabel#16true activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1385#L1659-45true assume !(0 != activate_threads_~tmp___6~0#1); 559#L1659-47true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 351#L792-45true assume !(1 == ~t8_pc~0); 1491#L792-47true is_transmit8_triggered_~__retres1~8#1 := 0; 1187#L803-15true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1711#is_transmit8_triggered_returnLabel#16true activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 71#L1667-45true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 720#L1667-47true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 323#L811-45true assume !(1 == ~t9_pc~0); 279#L811-47true is_transmit9_triggered_~__retres1~9#1 := 0; 1093#L822-15true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1074#is_transmit9_triggered_returnLabel#16true activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 924#L1675-45true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 606#L1675-47true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 469#L830-45true assume !(1 == ~t10_pc~0); 39#L830-47true is_transmit10_triggered_~__retres1~10#1 := 0; 680#L841-15true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1186#is_transmit10_triggered_returnLabel#16true activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 147#L1683-45true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1361#L1683-47true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 31#L849-45true assume !(1 == ~t11_pc~0); 1517#L849-47true is_transmit11_triggered_~__retres1~11#1 := 0; 252#L860-15true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 176#is_transmit11_triggered_returnLabel#16true activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25#L1691-45true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 174#L1691-47true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 145#L868-45true assume 1 == ~t12_pc~0; 398#L869-15true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 115#L879-15true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1117#is_transmit12_triggered_returnLabel#16true activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1915#L1699-45true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1375#L1699-47true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1934#L887-45true assume !(1 == ~t13_pc~0); 148#L887-47true is_transmit13_triggered_~__retres1~13#1 := 0; 1027#L898-15true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1051#is_transmit13_triggered_returnLabel#16true activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1942#L1707-45true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 132#L1707-47true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1045#L1439-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1018#L1439-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 140#L1444-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 219#L1449-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1602#L1454-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 849#L1459-3true assume !(1 == ~T5_E~0); 2012#L1464-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1383#L1469-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1284#L1474-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1611#L1479-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1387#L1484-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 592#L1489-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1170#L1494-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1793#L1499-3true assume !(1 == ~T13_E~0); 811#L1504-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1304#L1509-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1354#L1514-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1892#L1519-3true assume 1 == ~E_3~0;~E_3~0 := 2; 538#L1524-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1432#L1529-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1662#L1534-3true assume 1 == ~E_6~0;~E_6~0 := 2; 746#L1539-3true assume !(1 == ~E_7~0); 380#L1544-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1397#L1549-3true assume 1 == ~E_9~0;~E_9~0 := 2; 706#L1554-3true assume 1 == ~E_10~0;~E_10~0 := 2; 163#L1559-3true assume 1 == ~E_11~0;~E_11~0 := 2; 1198#L1564-3true assume 1 == ~E_12~0;~E_12~0 := 2; 935#L1569-3true assume 1 == ~E_13~0;~E_13~0 := 2; 1162#L1574-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 110#L992-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 159#L1064-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 204#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 113#L1959true assume !(0 == start_simulation_~tmp~3#1); 128#L1959-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 892#L992-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 974#L1064-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 29#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 1419#L1914true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1588#L1921true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1364#stop_simulation_returnLabel#1true start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1604#L1972true assume !(0 != start_simulation_~tmp___0~1#1); 141#L1940-2true [2022-12-13 18:37:24,634 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:24,635 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 1 times [2022-12-13 18:37:24,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:24,643 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [446616796] [2022-12-13 18:37:24,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:24,644 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:24,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:24,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:24,921 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:24,921 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [446616796] [2022-12-13 18:37:24,922 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [446616796] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:24,922 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:24,922 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:24,924 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1938087543] [2022-12-13 18:37:24,924 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:24,929 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 18:37:24,930 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:24,930 INFO L85 PathProgramCache]: Analyzing trace with hash 1154234999, now seen corresponding path program 1 times [2022-12-13 18:37:24,930 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:24,930 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1070225515] [2022-12-13 18:37:24,930 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:24,931 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:24,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:24,990 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:24,990 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:24,990 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1070225515] [2022-12-13 18:37:24,990 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1070225515] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:24,991 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:24,991 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 18:37:24,991 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [288506806] [2022-12-13 18:37:24,991 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:24,992 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:37:24,993 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:37:25,024 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-12-13 18:37:25,025 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-12-13 18:37:25,030 INFO L87 Difference]: Start difference. First operand has 2031 states, 2030 states have (on average 1.4965517241379311) internal successors, (3038), 2030 states have internal predecessors, (3038), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 79.5) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:25,099 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:37:25,100 INFO L93 Difference]: Finished difference Result 2029 states and 3002 transitions. [2022-12-13 18:37:25,101 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2029 states and 3002 transitions. [2022-12-13 18:37:25,116 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-12-13 18:37:25,132 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2029 states to 2023 states and 2996 transitions. [2022-12-13 18:37:25,133 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2022-12-13 18:37:25,135 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2022-12-13 18:37:25,136 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2996 transitions. [2022-12-13 18:37:25,141 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:37:25,142 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2023 states and 2996 transitions. [2022-12-13 18:37:25,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2996 transitions. [2022-12-13 18:37:25,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2022-12-13 18:37:25,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.480968858131488) internal successors, (2996), 2022 states have internal predecessors, (2996), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:25,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2996 transitions. [2022-12-13 18:37:25,218 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2023 states and 2996 transitions. [2022-12-13 18:37:25,219 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-12-13 18:37:25,223 INFO L428 stractBuchiCegarLoop]: Abstraction has 2023 states and 2996 transitions. [2022-12-13 18:37:25,223 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 18:37:25,223 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2996 transitions. [2022-12-13 18:37:25,233 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-12-13 18:37:25,233 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:37:25,233 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:37:25,236 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:25,237 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:25,237 INFO L748 eck$LassoCheckResult]: Stem: 4359#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 4360#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 5347#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5348#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6077#L914 assume !(1 == ~m_i~0);~m_st~0 := 2; 5475#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4938#L919-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4939#L924-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5744#L929-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5745#L934-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5851#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5852#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4693#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4694#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5886#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5245#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5246#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5790#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 5157#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5158#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 6078#L1291-2 assume !(0 == ~T1_E~0); 6075#L1296-1 assume !(0 == ~T2_E~0); 5309#L1301-1 assume !(0 == ~T3_E~0); 5310#L1306-1 assume !(0 == ~T4_E~0); 5801#L1311-1 assume !(0 == ~T5_E~0); 4533#L1316-1 assume !(0 == ~T6_E~0); 4534#L1321-1 assume !(0 == ~T7_E~0); 5323#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4356#L1331-1 assume !(0 == ~T9_E~0); 4071#L1336-1 assume !(0 == ~T10_E~0); 4072#L1341-1 assume !(0 == ~T11_E~0); 4148#L1346-1 assume !(0 == ~T12_E~0); 4149#L1351-1 assume !(0 == ~T13_E~0); 4473#L1356-1 assume !(0 == ~E_M~0); 4474#L1361-1 assume !(0 == ~E_1~0); 6015#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 4517#L1371-1 assume !(0 == ~E_3~0); 4518#L1376-1 assume !(0 == ~E_4~0); 5375#L1381-1 assume !(0 == ~E_5~0); 5376#L1386-1 assume !(0 == ~E_6~0); 6046#L1391-1 assume !(0 == ~E_7~0); 6066#L1396-1 assume !(0 == ~E_8~0); 5277#L1401-1 assume !(0 == ~E_9~0); 5278#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 5565#L1411-1 assume !(0 == ~E_11~0); 5566#L1416-1 assume !(0 == ~E_12~0); 5195#L1421-1 assume !(0 == ~E_13~0); 4714#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4715#L640 assume !(1 == ~m_pc~0); 5244#L640-2 is_master_triggered_~__retres1~0#1 := 0; 5243#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5203#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5204#L1603 assume !(0 != activate_threads_~tmp~1#1); 5232#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4860#L659 assume 1 == ~t1_pc~0; 4861#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4968#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5681#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4989#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 4990#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5006#L678 assume 1 == ~t2_pc~0; 5953#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5954#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4558#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4559#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 5102#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5225#L697 assume !(1 == ~t3_pc~0); 5226#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5356#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5671#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5137#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5138#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5986#L716 assume 1 == ~t4_pc~0; 5974#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4842#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4221#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4222#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 4326#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5637#L735 assume !(1 == ~t5_pc~0); 4293#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4294#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4741#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5661#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 5303#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5304#L754 assume 1 == ~t6_pc~0; 5054#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4951#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4537#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4538#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 4925#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5735#L773 assume !(1 == ~t7_pc~0); 4477#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4476#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5338#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5313#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 5314#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5367#L792 assume 1 == ~t8_pc~0; 5535#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5853#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5854#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5305#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 5228#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5229#L811 assume 1 == ~t9_pc~0; 5438#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5898#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4614#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4615#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 5240#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5241#L830 assume !(1 == ~t10_pc~0); 4960#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4453#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4454#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4431#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4432#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5753#L849 assume 1 == ~t11_pc~0; 5754#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4272#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4273#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 5764#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 5665#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5666#L868 assume !(1 == ~t12_pc~0); 5086#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 5085#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4163#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4164#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 4488#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4489#L887 assume 1 == ~t13_pc~0; 5673#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 5131#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5132#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 5729#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 4203#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4204#L1439 assume !(1 == ~M_E~0); 5297#L1439-2 assume !(1 == ~T1_E~0); 4369#L1444-1 assume !(1 == ~T2_E~0); 4370#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4865#L1454-1 assume !(1 == ~T4_E~0); 4866#L1459-1 assume !(1 == ~T5_E~0); 5430#L1464-1 assume !(1 == ~T6_E~0); 5431#L1469-1 assume !(1 == ~T7_E~0); 5504#L1474-1 assume !(1 == ~T8_E~0); 5196#L1479-1 assume !(1 == ~T9_E~0); 5197#L1484-1 assume !(1 == ~T10_E~0); 5434#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5075#L1494-1 assume !(1 == ~T12_E~0); 5076#L1499-1 assume !(1 == ~T13_E~0); 5262#L1504-1 assume !(1 == ~E_M~0); 5263#L1509-1 assume !(1 == ~E_1~0); 5838#L1514-1 assume !(1 == ~E_2~0); 5537#L1519-1 assume !(1 == ~E_3~0); 5538#L1524-1 assume !(1 == ~E_4~0); 6030#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 6031#L1534-1 assume !(1 == ~E_6~0); 4197#L1539-1 assume !(1 == ~E_7~0); 4198#L1544-1 assume !(1 == ~E_8~0); 4611#L1549-1 assume !(1 == ~E_9~0); 6003#L1554-1 assume !(1 == ~E_10~0); 6000#L1559-1 assume !(1 == ~E_11~0); 5878#L1564-1 assume !(1 == ~E_12~0); 5879#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 6025#L1574-1 assume { :end_inline_reset_delta_events } true; 4367#L1940-2 [2022-12-13 18:37:25,238 INFO L750 eck$LassoCheckResult]: Loop: 4367#L1940-2 assume !false; 4368#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4963#L1266 assume !false; 5677#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4920#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4639#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5837#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5846#L1079 assume !(0 != eval_~tmp~0#1); 5119#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4778#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4779#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5505#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5506#L1296-3 assume !(0 == ~T2_E~0); 6056#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6011#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5161#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4405#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4406#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4507#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5292#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5543#L1336-3 assume !(0 == ~T10_E~0); 5544#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4857#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4836#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4776#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4777#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5357#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4123#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4124#L1376-3 assume !(0 == ~E_4~0); 5858#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5715#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5716#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5890#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5891#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4468#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4334#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4335#L1416-3 assume !(0 == ~E_12~0); 5014#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5015#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5126#L640-45 assume !(1 == ~m_pc~0); 5127#L640-47 is_master_triggered_~__retres1~0#1 := 0; 4571#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4572#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4119#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4120#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4211#L659-45 assume 1 == ~t1_pc~0; 4212#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4654#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6060#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5991#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5646#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5647#L678-45 assume 1 == ~t2_pc~0; 5601#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5133#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5134#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5583#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5907#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6009#L697-45 assume 1 == ~t3_pc~0; 5396#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5397#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6076#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5549#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5550#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5584#L716-45 assume 1 == ~t4_pc~0; 5208#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5209#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5864#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5215#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5216#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4875#L735-45 assume 1 == ~t5_pc~0; 4876#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5428#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6027#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6073#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6029#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6023#L754-45 assume 1 == ~t6_pc~0; 5379#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5380#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5273#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5274#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5384#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5107#L773-45 assume 1 == ~t7_pc~0; 5108#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4650#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5345#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5346#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 5115#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4770#L792-45 assume 1 == ~t8_pc~0; 4771#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5793#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5794#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4232#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4233#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4720#L811-45 assume 1 == ~t9_pc~0; 4500#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4502#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5712#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5580#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5187#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4973#L830-45 assume 1 == ~t10_pc~0; 4974#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4159#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5296#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4378#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4379#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4139#L849-45 assume !(1 == ~t11_pc~0); 4140#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 4589#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4435#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4125#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4126#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4373#L868-45 assume 1 == ~t12_pc~0; 4374#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4319#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4320#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 5747#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 5920#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5921#L887-45 assume 1 == ~t13_pc~0; 5748#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4381#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5675#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 5694#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4349#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4350#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5670#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4365#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4366#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4521#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5486#L1459-3 assume !(1 == ~T5_E~0); 5487#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5922#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5861#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5862#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5924#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5169#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5170#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5787#L1499-3 assume !(1 == ~T13_E~0); 5445#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5446#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5874#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5908#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5082#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5083#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5946#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5364#L1539-3 assume !(1 == ~E_7~0); 4821#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4822#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5327#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4412#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4413#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 5585#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 5586#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4306#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4080#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4404#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 4313#L1959 assume !(0 == start_simulation_~tmp~3#1); 4315#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4345#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4299#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4134#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 4135#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5940#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5915#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 5916#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 4367#L1940-2 [2022-12-13 18:37:25,239 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:25,239 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 2 times [2022-12-13 18:37:25,239 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:25,239 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2013243411] [2022-12-13 18:37:25,240 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:25,240 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:25,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:25,324 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:25,324 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:25,324 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2013243411] [2022-12-13 18:37:25,325 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2013243411] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:25,325 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:25,325 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:25,325 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1027264858] [2022-12-13 18:37:25,325 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:25,326 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 18:37:25,326 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:25,326 INFO L85 PathProgramCache]: Analyzing trace with hash -1148495268, now seen corresponding path program 1 times [2022-12-13 18:37:25,327 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:25,327 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1548790925] [2022-12-13 18:37:25,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:25,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:25,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:25,444 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:25,444 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:25,445 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1548790925] [2022-12-13 18:37:25,445 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1548790925] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:25,445 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:25,445 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:25,445 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1569341722] [2022-12-13 18:37:25,445 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:25,446 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:37:25,446 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:37:25,447 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 18:37:25,447 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 18:37:25,447 INFO L87 Difference]: Start difference. First operand 2023 states and 2996 transitions. cyclomatic complexity: 974 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:25,501 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:37:25,501 INFO L93 Difference]: Finished difference Result 2023 states and 2995 transitions. [2022-12-13 18:37:25,501 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2995 transitions. [2022-12-13 18:37:25,511 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-12-13 18:37:25,516 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2995 transitions. [2022-12-13 18:37:25,516 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2022-12-13 18:37:25,517 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2022-12-13 18:37:25,517 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2995 transitions. [2022-12-13 18:37:25,519 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:37:25,519 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2023 states and 2995 transitions. [2022-12-13 18:37:25,522 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2995 transitions. [2022-12-13 18:37:25,536 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2022-12-13 18:37:25,538 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4804745427582797) internal successors, (2995), 2022 states have internal predecessors, (2995), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:25,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2995 transitions. [2022-12-13 18:37:25,541 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2023 states and 2995 transitions. [2022-12-13 18:37:25,542 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 18:37:25,542 INFO L428 stractBuchiCegarLoop]: Abstraction has 2023 states and 2995 transitions. [2022-12-13 18:37:25,542 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 18:37:25,542 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2995 transitions. [2022-12-13 18:37:25,547 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-12-13 18:37:25,548 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:37:25,548 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:37:25,550 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:25,550 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:25,550 INFO L748 eck$LassoCheckResult]: Stem: 8412#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 8413#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 9400#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9401#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10130#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 9528#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8991#L919-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8992#L924-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 9797#L929-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 9798#L934-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9904#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9905#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8746#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8747#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9939#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9298#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9299#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9843#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 9210#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9211#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 10131#L1291-2 assume !(0 == ~T1_E~0); 10128#L1296-1 assume !(0 == ~T2_E~0); 9362#L1301-1 assume !(0 == ~T3_E~0); 9363#L1306-1 assume !(0 == ~T4_E~0); 9854#L1311-1 assume !(0 == ~T5_E~0); 8586#L1316-1 assume !(0 == ~T6_E~0); 8587#L1321-1 assume !(0 == ~T7_E~0); 9376#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8409#L1331-1 assume !(0 == ~T9_E~0); 8124#L1336-1 assume !(0 == ~T10_E~0); 8125#L1341-1 assume !(0 == ~T11_E~0); 8201#L1346-1 assume !(0 == ~T12_E~0); 8202#L1351-1 assume !(0 == ~T13_E~0); 8526#L1356-1 assume !(0 == ~E_M~0); 8527#L1361-1 assume !(0 == ~E_1~0); 10068#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 8570#L1371-1 assume !(0 == ~E_3~0); 8571#L1376-1 assume !(0 == ~E_4~0); 9428#L1381-1 assume !(0 == ~E_5~0); 9429#L1386-1 assume !(0 == ~E_6~0); 10099#L1391-1 assume !(0 == ~E_7~0); 10119#L1396-1 assume !(0 == ~E_8~0); 9330#L1401-1 assume !(0 == ~E_9~0); 9331#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 9618#L1411-1 assume !(0 == ~E_11~0); 9619#L1416-1 assume !(0 == ~E_12~0); 9248#L1421-1 assume !(0 == ~E_13~0); 8767#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8768#L640 assume !(1 == ~m_pc~0); 9297#L640-2 is_master_triggered_~__retres1~0#1 := 0; 9296#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9256#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9257#L1603 assume !(0 != activate_threads_~tmp~1#1); 9285#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8913#L659 assume 1 == ~t1_pc~0; 8914#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9021#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9734#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9042#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 9043#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9059#L678 assume 1 == ~t2_pc~0; 10006#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10007#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8611#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8612#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 9155#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9278#L697 assume !(1 == ~t3_pc~0); 9279#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9409#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9724#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9190#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9191#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10039#L716 assume 1 == ~t4_pc~0; 10027#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8895#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8274#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8275#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 8379#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9690#L735 assume !(1 == ~t5_pc~0); 8346#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8347#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8794#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9714#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 9356#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9357#L754 assume 1 == ~t6_pc~0; 9107#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9004#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8590#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8591#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 8978#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9788#L773 assume !(1 == ~t7_pc~0); 8530#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8529#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9391#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9366#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 9367#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9420#L792 assume 1 == ~t8_pc~0; 9588#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9906#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9907#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9358#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 9281#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9282#L811 assume 1 == ~t9_pc~0; 9491#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9951#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8667#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8668#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 9293#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9294#L830 assume !(1 == ~t10_pc~0); 9013#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8506#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8507#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8484#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8485#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9806#L849 assume 1 == ~t11_pc~0; 9807#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 8325#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8326#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 9817#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 9718#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9719#L868 assume !(1 == ~t12_pc~0); 9139#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 9138#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8216#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 8217#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 8541#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8542#L887 assume 1 == ~t13_pc~0; 9726#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 9184#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 9185#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 9782#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 8256#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8257#L1439 assume !(1 == ~M_E~0); 9350#L1439-2 assume !(1 == ~T1_E~0); 8422#L1444-1 assume !(1 == ~T2_E~0); 8423#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8918#L1454-1 assume !(1 == ~T4_E~0); 8919#L1459-1 assume !(1 == ~T5_E~0); 9483#L1464-1 assume !(1 == ~T6_E~0); 9484#L1469-1 assume !(1 == ~T7_E~0); 9557#L1474-1 assume !(1 == ~T8_E~0); 9249#L1479-1 assume !(1 == ~T9_E~0); 9250#L1484-1 assume !(1 == ~T10_E~0); 9487#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9128#L1494-1 assume !(1 == ~T12_E~0); 9129#L1499-1 assume !(1 == ~T13_E~0); 9315#L1504-1 assume !(1 == ~E_M~0); 9316#L1509-1 assume !(1 == ~E_1~0); 9891#L1514-1 assume !(1 == ~E_2~0); 9590#L1519-1 assume !(1 == ~E_3~0); 9591#L1524-1 assume !(1 == ~E_4~0); 10083#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 10084#L1534-1 assume !(1 == ~E_6~0); 8250#L1539-1 assume !(1 == ~E_7~0); 8251#L1544-1 assume !(1 == ~E_8~0); 8664#L1549-1 assume !(1 == ~E_9~0); 10056#L1554-1 assume !(1 == ~E_10~0); 10053#L1559-1 assume !(1 == ~E_11~0); 9931#L1564-1 assume !(1 == ~E_12~0); 9932#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 10078#L1574-1 assume { :end_inline_reset_delta_events } true; 8420#L1940-2 [2022-12-13 18:37:25,551 INFO L750 eck$LassoCheckResult]: Loop: 8420#L1940-2 assume !false; 8421#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9016#L1266 assume !false; 9730#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8973#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8692#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 9890#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 9899#L1079 assume !(0 != eval_~tmp~0#1); 9172#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8831#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8832#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9558#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9559#L1296-3 assume !(0 == ~T2_E~0); 10109#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10064#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9214#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8458#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8459#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8560#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9345#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9596#L1336-3 assume !(0 == ~T10_E~0); 9597#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 8910#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8889#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 8829#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8830#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9410#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8176#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8177#L1376-3 assume !(0 == ~E_4~0); 9911#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9768#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9769#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9943#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9944#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8521#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8387#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 8388#L1416-3 assume !(0 == ~E_12~0); 9067#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 9068#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9179#L640-45 assume !(1 == ~m_pc~0); 9180#L640-47 is_master_triggered_~__retres1~0#1 := 0; 8624#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8625#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8172#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8173#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8264#L659-45 assume 1 == ~t1_pc~0; 8265#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8707#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10113#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10044#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9699#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9700#L678-45 assume 1 == ~t2_pc~0; 9654#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9186#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9187#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9636#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9960#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10062#L697-45 assume 1 == ~t3_pc~0; 9449#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9450#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10129#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9602#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9603#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9637#L716-45 assume 1 == ~t4_pc~0; 9261#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9262#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9917#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9268#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9269#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8928#L735-45 assume 1 == ~t5_pc~0; 8929#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9481#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10080#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10126#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10082#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10076#L754-45 assume 1 == ~t6_pc~0; 9432#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9433#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9326#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9327#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9437#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9160#L773-45 assume 1 == ~t7_pc~0; 9161#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8703#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9398#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9399#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 9168#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8823#L792-45 assume 1 == ~t8_pc~0; 8824#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9846#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9847#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8285#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8286#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8773#L811-45 assume 1 == ~t9_pc~0; 8553#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8555#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9765#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9633#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9240#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9026#L830-45 assume 1 == ~t10_pc~0; 9027#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8212#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9349#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8431#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8432#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8192#L849-45 assume !(1 == ~t11_pc~0); 8193#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 8642#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8488#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8178#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8179#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8426#L868-45 assume 1 == ~t12_pc~0; 8427#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 8372#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8373#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 9800#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 9973#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9974#L887-45 assume !(1 == ~t13_pc~0); 8433#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 8434#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 9728#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 9747#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 8402#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8403#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9723#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8418#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8419#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8574#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9539#L1459-3 assume !(1 == ~T5_E~0); 9540#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9975#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9914#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9915#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9977#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9222#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9223#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 9840#L1499-3 assume !(1 == ~T13_E~0); 9498#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9499#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9927#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9961#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9135#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9136#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9999#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9417#L1539-3 assume !(1 == ~E_7~0); 8874#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8875#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9380#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 8465#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 8466#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 9638#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 9639#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8359#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8133#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8457#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 8366#L1959 assume !(0 == start_simulation_~tmp~3#1); 8368#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8398#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8352#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8187#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 8188#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9993#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9968#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 9969#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 8420#L1940-2 [2022-12-13 18:37:25,552 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:25,552 INFO L85 PathProgramCache]: Analyzing trace with hash 1533490443, now seen corresponding path program 1 times [2022-12-13 18:37:25,552 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:25,552 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1483557679] [2022-12-13 18:37:25,552 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:25,553 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:25,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:25,603 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:25,603 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:25,603 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1483557679] [2022-12-13 18:37:25,603 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1483557679] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:25,603 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:25,604 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:25,604 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [643149104] [2022-12-13 18:37:25,604 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:25,604 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 18:37:25,604 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:25,605 INFO L85 PathProgramCache]: Analyzing trace with hash 1253029853, now seen corresponding path program 1 times [2022-12-13 18:37:25,605 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:25,612 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [210691252] [2022-12-13 18:37:25,613 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:25,613 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:25,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:25,663 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:25,664 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:25,664 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [210691252] [2022-12-13 18:37:25,664 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [210691252] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:25,664 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:25,664 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:25,664 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2038894372] [2022-12-13 18:37:25,665 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:25,665 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:37:25,665 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:37:25,666 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 18:37:25,666 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 18:37:25,666 INFO L87 Difference]: Start difference. First operand 2023 states and 2995 transitions. cyclomatic complexity: 973 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:25,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:37:25,711 INFO L93 Difference]: Finished difference Result 2023 states and 2994 transitions. [2022-12-13 18:37:25,711 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2994 transitions. [2022-12-13 18:37:25,721 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-12-13 18:37:25,727 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2994 transitions. [2022-12-13 18:37:25,727 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2022-12-13 18:37:25,728 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2022-12-13 18:37:25,728 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2994 transitions. [2022-12-13 18:37:25,730 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:37:25,730 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2023 states and 2994 transitions. [2022-12-13 18:37:25,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2994 transitions. [2022-12-13 18:37:25,748 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2022-12-13 18:37:25,750 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4799802273850717) internal successors, (2994), 2022 states have internal predecessors, (2994), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:25,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2994 transitions. [2022-12-13 18:37:25,754 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2023 states and 2994 transitions. [2022-12-13 18:37:25,754 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 18:37:25,755 INFO L428 stractBuchiCegarLoop]: Abstraction has 2023 states and 2994 transitions. [2022-12-13 18:37:25,755 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 18:37:25,755 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2994 transitions. [2022-12-13 18:37:25,761 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-12-13 18:37:25,761 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:37:25,761 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:37:25,763 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:25,763 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:25,764 INFO L748 eck$LassoCheckResult]: Stem: 12465#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 12466#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 13453#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13454#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14183#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 13581#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13044#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13045#L924-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 13850#L929-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13851#L934-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13957#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13958#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12799#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12800#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13992#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13351#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 13352#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 13896#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 13263#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13264#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 14184#L1291-2 assume !(0 == ~T1_E~0); 14181#L1296-1 assume !(0 == ~T2_E~0); 13415#L1301-1 assume !(0 == ~T3_E~0); 13416#L1306-1 assume !(0 == ~T4_E~0); 13907#L1311-1 assume !(0 == ~T5_E~0); 12639#L1316-1 assume !(0 == ~T6_E~0); 12640#L1321-1 assume !(0 == ~T7_E~0); 13429#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12462#L1331-1 assume !(0 == ~T9_E~0); 12177#L1336-1 assume !(0 == ~T10_E~0); 12178#L1341-1 assume !(0 == ~T11_E~0); 12254#L1346-1 assume !(0 == ~T12_E~0); 12255#L1351-1 assume !(0 == ~T13_E~0); 12579#L1356-1 assume !(0 == ~E_M~0); 12580#L1361-1 assume !(0 == ~E_1~0); 14121#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 12623#L1371-1 assume !(0 == ~E_3~0); 12624#L1376-1 assume !(0 == ~E_4~0); 13481#L1381-1 assume !(0 == ~E_5~0); 13482#L1386-1 assume !(0 == ~E_6~0); 14152#L1391-1 assume !(0 == ~E_7~0); 14172#L1396-1 assume !(0 == ~E_8~0); 13383#L1401-1 assume !(0 == ~E_9~0); 13384#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 13671#L1411-1 assume !(0 == ~E_11~0); 13672#L1416-1 assume !(0 == ~E_12~0); 13301#L1421-1 assume !(0 == ~E_13~0); 12820#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12821#L640 assume !(1 == ~m_pc~0); 13350#L640-2 is_master_triggered_~__retres1~0#1 := 0; 13349#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13309#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13310#L1603 assume !(0 != activate_threads_~tmp~1#1); 13338#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12966#L659 assume 1 == ~t1_pc~0; 12967#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13074#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13787#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13095#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 13096#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13112#L678 assume 1 == ~t2_pc~0; 14059#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14060#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12664#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12665#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 13208#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13331#L697 assume !(1 == ~t3_pc~0); 13332#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13462#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13777#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13243#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13244#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14092#L716 assume 1 == ~t4_pc~0; 14080#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12948#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12327#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12328#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 12432#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13743#L735 assume !(1 == ~t5_pc~0); 12399#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 12400#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12847#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13767#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 13409#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13410#L754 assume 1 == ~t6_pc~0; 13160#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13057#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12643#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12644#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 13031#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13841#L773 assume !(1 == ~t7_pc~0); 12583#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 12582#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13444#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13419#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 13420#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13473#L792 assume 1 == ~t8_pc~0; 13641#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13959#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13960#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13411#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 13334#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13335#L811 assume 1 == ~t9_pc~0; 13544#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14004#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12720#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12721#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 13346#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13347#L830 assume !(1 == ~t10_pc~0); 13066#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12559#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12560#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12537#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12538#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13859#L849 assume 1 == ~t11_pc~0; 13860#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 12378#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12379#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13870#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 13771#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13772#L868 assume !(1 == ~t12_pc~0); 13192#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 13191#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12269#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 12270#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 12594#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12595#L887 assume 1 == ~t13_pc~0; 13779#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 13237#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13238#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 13835#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 12309#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12310#L1439 assume !(1 == ~M_E~0); 13403#L1439-2 assume !(1 == ~T1_E~0); 12475#L1444-1 assume !(1 == ~T2_E~0); 12476#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12971#L1454-1 assume !(1 == ~T4_E~0); 12972#L1459-1 assume !(1 == ~T5_E~0); 13536#L1464-1 assume !(1 == ~T6_E~0); 13537#L1469-1 assume !(1 == ~T7_E~0); 13610#L1474-1 assume !(1 == ~T8_E~0); 13302#L1479-1 assume !(1 == ~T9_E~0); 13303#L1484-1 assume !(1 == ~T10_E~0); 13540#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13181#L1494-1 assume !(1 == ~T12_E~0); 13182#L1499-1 assume !(1 == ~T13_E~0); 13368#L1504-1 assume !(1 == ~E_M~0); 13369#L1509-1 assume !(1 == ~E_1~0); 13944#L1514-1 assume !(1 == ~E_2~0); 13643#L1519-1 assume !(1 == ~E_3~0); 13644#L1524-1 assume !(1 == ~E_4~0); 14136#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 14137#L1534-1 assume !(1 == ~E_6~0); 12303#L1539-1 assume !(1 == ~E_7~0); 12304#L1544-1 assume !(1 == ~E_8~0); 12717#L1549-1 assume !(1 == ~E_9~0); 14109#L1554-1 assume !(1 == ~E_10~0); 14106#L1559-1 assume !(1 == ~E_11~0); 13984#L1564-1 assume !(1 == ~E_12~0); 13985#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 14131#L1574-1 assume { :end_inline_reset_delta_events } true; 12473#L1940-2 [2022-12-13 18:37:25,764 INFO L750 eck$LassoCheckResult]: Loop: 12473#L1940-2 assume !false; 12474#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13069#L1266 assume !false; 13783#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13026#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12745#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 13943#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 13952#L1079 assume !(0 != eval_~tmp~0#1); 13225#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12884#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12885#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13611#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13612#L1296-3 assume !(0 == ~T2_E~0); 14162#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14117#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13267#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12511#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12512#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12613#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13398#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13649#L1336-3 assume !(0 == ~T10_E~0); 13650#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 12963#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 12942#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 12882#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12883#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13463#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12229#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12230#L1376-3 assume !(0 == ~E_4~0); 13964#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13821#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13822#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13996#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13997#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12574#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12440#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 12441#L1416-3 assume !(0 == ~E_12~0); 13120#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13121#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13232#L640-45 assume !(1 == ~m_pc~0); 13233#L640-47 is_master_triggered_~__retres1~0#1 := 0; 12677#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12678#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12225#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12226#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12317#L659-45 assume 1 == ~t1_pc~0; 12318#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12760#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14166#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14097#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13752#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13753#L678-45 assume 1 == ~t2_pc~0; 13707#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13239#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13240#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13689#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14013#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14115#L697-45 assume !(1 == ~t3_pc~0); 13504#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 13503#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14182#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13655#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13656#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13690#L716-45 assume 1 == ~t4_pc~0; 13314#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13315#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13970#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13321#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13322#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12981#L735-45 assume 1 == ~t5_pc~0; 12982#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13534#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14133#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14179#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14135#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14129#L754-45 assume 1 == ~t6_pc~0; 13485#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13486#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13379#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13380#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13490#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13213#L773-45 assume !(1 == ~t7_pc~0); 12755#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 12756#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13451#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13452#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 13221#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12876#L792-45 assume 1 == ~t8_pc~0; 12877#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13899#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13900#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12338#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12339#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12826#L811-45 assume 1 == ~t9_pc~0; 12606#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12608#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13818#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13686#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13293#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13079#L830-45 assume 1 == ~t10_pc~0; 13080#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12265#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13402#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12484#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12485#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12245#L849-45 assume !(1 == ~t11_pc~0); 12246#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 12695#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12541#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12231#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 12232#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12479#L868-45 assume 1 == ~t12_pc~0; 12480#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 12425#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12426#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 13853#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 14026#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 14027#L887-45 assume !(1 == ~t13_pc~0); 12486#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 12487#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13781#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 13800#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 12455#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12456#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13776#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12471#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12472#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12627#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13592#L1459-3 assume !(1 == ~T5_E~0); 13593#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14028#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13967#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13968#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14030#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13275#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13276#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 13893#L1499-3 assume !(1 == ~T13_E~0); 13551#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13552#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13980#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14014#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13188#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13189#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14052#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13470#L1539-3 assume !(1 == ~E_7~0); 12927#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12928#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13433#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12518#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12519#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 13691#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 13692#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12412#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12186#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12510#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 12419#L1959 assume !(0 == start_simulation_~tmp~3#1); 12421#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12451#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12405#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12240#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 12241#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14046#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14021#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 14022#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 12473#L1940-2 [2022-12-13 18:37:25,765 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:25,765 INFO L85 PathProgramCache]: Analyzing trace with hash -992005239, now seen corresponding path program 1 times [2022-12-13 18:37:25,765 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:25,765 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1944675408] [2022-12-13 18:37:25,765 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:25,765 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:25,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:25,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:25,822 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:25,823 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1944675408] [2022-12-13 18:37:25,823 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1944675408] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:25,823 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:25,823 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:25,823 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [410417755] [2022-12-13 18:37:25,824 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:25,824 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 18:37:25,824 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:25,825 INFO L85 PathProgramCache]: Analyzing trace with hash 1223943903, now seen corresponding path program 1 times [2022-12-13 18:37:25,825 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:25,825 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1043206720] [2022-12-13 18:37:25,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:25,826 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:25,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:25,895 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:25,895 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:25,895 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1043206720] [2022-12-13 18:37:25,895 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1043206720] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:25,895 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:25,896 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:25,896 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [667320224] [2022-12-13 18:37:25,896 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:25,896 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:37:25,896 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:37:25,897 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 18:37:25,897 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 18:37:25,897 INFO L87 Difference]: Start difference. First operand 2023 states and 2994 transitions. cyclomatic complexity: 972 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:25,929 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:37:25,929 INFO L93 Difference]: Finished difference Result 2023 states and 2993 transitions. [2022-12-13 18:37:25,929 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2993 transitions. [2022-12-13 18:37:25,936 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-12-13 18:37:25,941 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2993 transitions. [2022-12-13 18:37:25,941 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2022-12-13 18:37:25,942 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2022-12-13 18:37:25,942 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2993 transitions. [2022-12-13 18:37:25,944 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:37:25,944 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2023 states and 2993 transitions. [2022-12-13 18:37:25,947 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2993 transitions. [2022-12-13 18:37:25,963 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2022-12-13 18:37:25,966 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4794859120118635) internal successors, (2993), 2022 states have internal predecessors, (2993), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:25,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2993 transitions. [2022-12-13 18:37:25,969 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2023 states and 2993 transitions. [2022-12-13 18:37:25,969 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 18:37:25,970 INFO L428 stractBuchiCegarLoop]: Abstraction has 2023 states and 2993 transitions. [2022-12-13 18:37:25,970 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 18:37:25,971 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2993 transitions. [2022-12-13 18:37:25,979 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-12-13 18:37:25,979 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:37:25,979 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:37:25,981 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:25,981 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:25,981 INFO L748 eck$LassoCheckResult]: Stem: 16518#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 16519#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 17506#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17507#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18236#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 17634#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17097#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17098#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17903#L929-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 17904#L934-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 18010#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 18011#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16852#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16853#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18045#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17404#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17405#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 17949#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 17316#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17317#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 18237#L1291-2 assume !(0 == ~T1_E~0); 18234#L1296-1 assume !(0 == ~T2_E~0); 17468#L1301-1 assume !(0 == ~T3_E~0); 17469#L1306-1 assume !(0 == ~T4_E~0); 17960#L1311-1 assume !(0 == ~T5_E~0); 16692#L1316-1 assume !(0 == ~T6_E~0); 16693#L1321-1 assume !(0 == ~T7_E~0); 17482#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16515#L1331-1 assume !(0 == ~T9_E~0); 16230#L1336-1 assume !(0 == ~T10_E~0); 16231#L1341-1 assume !(0 == ~T11_E~0); 16307#L1346-1 assume !(0 == ~T12_E~0); 16308#L1351-1 assume !(0 == ~T13_E~0); 16632#L1356-1 assume !(0 == ~E_M~0); 16633#L1361-1 assume !(0 == ~E_1~0); 18174#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 16676#L1371-1 assume !(0 == ~E_3~0); 16677#L1376-1 assume !(0 == ~E_4~0); 17534#L1381-1 assume !(0 == ~E_5~0); 17535#L1386-1 assume !(0 == ~E_6~0); 18205#L1391-1 assume !(0 == ~E_7~0); 18225#L1396-1 assume !(0 == ~E_8~0); 17436#L1401-1 assume !(0 == ~E_9~0); 17437#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 17724#L1411-1 assume !(0 == ~E_11~0); 17725#L1416-1 assume !(0 == ~E_12~0); 17354#L1421-1 assume !(0 == ~E_13~0); 16873#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16874#L640 assume !(1 == ~m_pc~0); 17403#L640-2 is_master_triggered_~__retres1~0#1 := 0; 17402#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17362#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17363#L1603 assume !(0 != activate_threads_~tmp~1#1); 17391#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17019#L659 assume 1 == ~t1_pc~0; 17020#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17127#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17840#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17148#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 17149#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17165#L678 assume 1 == ~t2_pc~0; 18112#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18113#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16717#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16718#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 17261#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17384#L697 assume !(1 == ~t3_pc~0); 17385#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17515#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17830#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17296#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17297#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18145#L716 assume 1 == ~t4_pc~0; 18133#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17001#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16380#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16381#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 16485#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17796#L735 assume !(1 == ~t5_pc~0); 16452#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 16453#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16900#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17820#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 17462#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17463#L754 assume 1 == ~t6_pc~0; 17213#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17110#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16696#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16697#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 17084#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17894#L773 assume !(1 == ~t7_pc~0); 16636#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 16635#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17497#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17472#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 17473#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17526#L792 assume 1 == ~t8_pc~0; 17694#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18012#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18013#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17464#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 17387#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17388#L811 assume 1 == ~t9_pc~0; 17597#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18057#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16773#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16774#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 17399#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17400#L830 assume !(1 == ~t10_pc~0); 17119#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 16612#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16613#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16590#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16591#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17912#L849 assume 1 == ~t11_pc~0; 17913#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 16431#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16432#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 17923#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 17824#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17825#L868 assume !(1 == ~t12_pc~0); 17245#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 17244#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16322#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 16323#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 16647#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16648#L887 assume 1 == ~t13_pc~0; 17832#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 17290#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17291#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 17888#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 16362#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16363#L1439 assume !(1 == ~M_E~0); 17456#L1439-2 assume !(1 == ~T1_E~0); 16528#L1444-1 assume !(1 == ~T2_E~0); 16529#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17024#L1454-1 assume !(1 == ~T4_E~0); 17025#L1459-1 assume !(1 == ~T5_E~0); 17589#L1464-1 assume !(1 == ~T6_E~0); 17590#L1469-1 assume !(1 == ~T7_E~0); 17663#L1474-1 assume !(1 == ~T8_E~0); 17355#L1479-1 assume !(1 == ~T9_E~0); 17356#L1484-1 assume !(1 == ~T10_E~0); 17593#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17234#L1494-1 assume !(1 == ~T12_E~0); 17235#L1499-1 assume !(1 == ~T13_E~0); 17421#L1504-1 assume !(1 == ~E_M~0); 17422#L1509-1 assume !(1 == ~E_1~0); 17997#L1514-1 assume !(1 == ~E_2~0); 17696#L1519-1 assume !(1 == ~E_3~0); 17697#L1524-1 assume !(1 == ~E_4~0); 18189#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 18190#L1534-1 assume !(1 == ~E_6~0); 16356#L1539-1 assume !(1 == ~E_7~0); 16357#L1544-1 assume !(1 == ~E_8~0); 16770#L1549-1 assume !(1 == ~E_9~0); 18162#L1554-1 assume !(1 == ~E_10~0); 18159#L1559-1 assume !(1 == ~E_11~0); 18037#L1564-1 assume !(1 == ~E_12~0); 18038#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 18184#L1574-1 assume { :end_inline_reset_delta_events } true; 16526#L1940-2 [2022-12-13 18:37:25,982 INFO L750 eck$LassoCheckResult]: Loop: 16526#L1940-2 assume !false; 16527#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17122#L1266 assume !false; 17836#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 17079#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16798#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 17996#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 18005#L1079 assume !(0 != eval_~tmp~0#1); 17278#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16937#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16938#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17664#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17665#L1296-3 assume !(0 == ~T2_E~0); 18215#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18170#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17320#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16564#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16565#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16666#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17451#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17702#L1336-3 assume !(0 == ~T10_E~0); 17703#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 17016#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 16995#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 16935#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16936#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17516#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16282#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16283#L1376-3 assume !(0 == ~E_4~0); 18017#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17874#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17875#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18049#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18050#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 16627#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16493#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16494#L1416-3 assume !(0 == ~E_12~0); 17173#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 17174#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17285#L640-45 assume !(1 == ~m_pc~0); 17286#L640-47 is_master_triggered_~__retres1~0#1 := 0; 16730#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16731#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16278#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16279#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16370#L659-45 assume 1 == ~t1_pc~0; 16371#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16813#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18219#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18150#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17805#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17806#L678-45 assume 1 == ~t2_pc~0; 17760#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17292#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17293#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17742#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18066#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18168#L697-45 assume 1 == ~t3_pc~0; 17555#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17556#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18235#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17708#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17709#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17743#L716-45 assume 1 == ~t4_pc~0; 17367#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17368#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18023#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17374#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17375#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17034#L735-45 assume 1 == ~t5_pc~0; 17035#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17587#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18186#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18232#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18188#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18182#L754-45 assume 1 == ~t6_pc~0; 17538#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17539#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17432#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17433#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17543#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17266#L773-45 assume 1 == ~t7_pc~0; 17267#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16809#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17504#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17505#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 17274#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16929#L792-45 assume 1 == ~t8_pc~0; 16930#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17952#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17953#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16391#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16392#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16879#L811-45 assume 1 == ~t9_pc~0; 16659#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16661#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17871#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17739#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17346#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17132#L830-45 assume 1 == ~t10_pc~0; 17133#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16318#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17455#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16537#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16538#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16298#L849-45 assume !(1 == ~t11_pc~0); 16299#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 16748#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16594#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16284#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 16285#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16532#L868-45 assume 1 == ~t12_pc~0; 16533#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 16478#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16479#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 17906#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 18079#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 18080#L887-45 assume 1 == ~t13_pc~0; 17907#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 16540#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17834#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 17853#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 16508#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16509#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17829#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16524#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16525#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16680#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17645#L1459-3 assume !(1 == ~T5_E~0); 17646#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18081#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18020#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18021#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18083#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17328#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17329#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 17946#L1499-3 assume !(1 == ~T13_E~0); 17604#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17605#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18033#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18067#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17241#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17242#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18105#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 17523#L1539-3 assume !(1 == ~E_7~0); 16980#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16981#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17486#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16571#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 16572#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 17744#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 17745#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16465#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16239#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16563#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 16472#L1959 assume !(0 == start_simulation_~tmp~3#1); 16474#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16504#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16458#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16293#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 16294#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18099#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18074#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 18075#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 16526#L1940-2 [2022-12-13 18:37:25,982 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:25,982 INFO L85 PathProgramCache]: Analyzing trace with hash -380736181, now seen corresponding path program 1 times [2022-12-13 18:37:25,982 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:25,983 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [670576471] [2022-12-13 18:37:25,983 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:25,983 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:25,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:26,021 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:26,021 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:26,022 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [670576471] [2022-12-13 18:37:26,022 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [670576471] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:26,022 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:26,022 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:26,022 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1413951716] [2022-12-13 18:37:26,022 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:26,023 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 18:37:26,023 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:26,023 INFO L85 PathProgramCache]: Analyzing trace with hash -1148495268, now seen corresponding path program 2 times [2022-12-13 18:37:26,023 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:26,023 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [920477235] [2022-12-13 18:37:26,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:26,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:26,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:26,099 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:26,100 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:26,100 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [920477235] [2022-12-13 18:37:26,100 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [920477235] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:26,100 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:26,100 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:26,100 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1293356115] [2022-12-13 18:37:26,100 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:26,101 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:37:26,101 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:37:26,101 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 18:37:26,101 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 18:37:26,102 INFO L87 Difference]: Start difference. First operand 2023 states and 2993 transitions. cyclomatic complexity: 971 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:26,133 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:37:26,133 INFO L93 Difference]: Finished difference Result 2023 states and 2992 transitions. [2022-12-13 18:37:26,133 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2992 transitions. [2022-12-13 18:37:26,139 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-12-13 18:37:26,144 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2992 transitions. [2022-12-13 18:37:26,144 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2022-12-13 18:37:26,145 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2022-12-13 18:37:26,145 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2992 transitions. [2022-12-13 18:37:26,147 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:37:26,147 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2023 states and 2992 transitions. [2022-12-13 18:37:26,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2992 transitions. [2022-12-13 18:37:26,169 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2022-12-13 18:37:26,174 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4789915966386555) internal successors, (2992), 2022 states have internal predecessors, (2992), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:26,180 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2992 transitions. [2022-12-13 18:37:26,180 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2023 states and 2992 transitions. [2022-12-13 18:37:26,181 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 18:37:26,181 INFO L428 stractBuchiCegarLoop]: Abstraction has 2023 states and 2992 transitions. [2022-12-13 18:37:26,181 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 18:37:26,182 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2992 transitions. [2022-12-13 18:37:26,189 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-12-13 18:37:26,189 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:37:26,189 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:37:26,192 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:26,192 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:26,193 INFO L748 eck$LassoCheckResult]: Stem: 20571#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 20572#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 21559#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21560#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22289#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 21687#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21150#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21151#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21956#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21957#L934-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 22063#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 22064#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20905#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 20906#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22098#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21457#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21458#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 22002#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 21369#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21370#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 22290#L1291-2 assume !(0 == ~T1_E~0); 22287#L1296-1 assume !(0 == ~T2_E~0); 21521#L1301-1 assume !(0 == ~T3_E~0); 21522#L1306-1 assume !(0 == ~T4_E~0); 22013#L1311-1 assume !(0 == ~T5_E~0); 20745#L1316-1 assume !(0 == ~T6_E~0); 20746#L1321-1 assume !(0 == ~T7_E~0); 21535#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20568#L1331-1 assume !(0 == ~T9_E~0); 20283#L1336-1 assume !(0 == ~T10_E~0); 20284#L1341-1 assume !(0 == ~T11_E~0); 20360#L1346-1 assume !(0 == ~T12_E~0); 20361#L1351-1 assume !(0 == ~T13_E~0); 20685#L1356-1 assume !(0 == ~E_M~0); 20686#L1361-1 assume !(0 == ~E_1~0); 22227#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 20729#L1371-1 assume !(0 == ~E_3~0); 20730#L1376-1 assume !(0 == ~E_4~0); 21587#L1381-1 assume !(0 == ~E_5~0); 21588#L1386-1 assume !(0 == ~E_6~0); 22258#L1391-1 assume !(0 == ~E_7~0); 22278#L1396-1 assume !(0 == ~E_8~0); 21489#L1401-1 assume !(0 == ~E_9~0); 21490#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 21777#L1411-1 assume !(0 == ~E_11~0); 21778#L1416-1 assume !(0 == ~E_12~0); 21407#L1421-1 assume !(0 == ~E_13~0); 20926#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20927#L640 assume !(1 == ~m_pc~0); 21456#L640-2 is_master_triggered_~__retres1~0#1 := 0; 21455#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21415#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21416#L1603 assume !(0 != activate_threads_~tmp~1#1); 21444#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21072#L659 assume 1 == ~t1_pc~0; 21073#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21180#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21893#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21201#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 21202#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21218#L678 assume 1 == ~t2_pc~0; 22165#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22166#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20770#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20771#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 21314#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21437#L697 assume !(1 == ~t3_pc~0); 21438#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21568#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21883#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21349#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21350#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22198#L716 assume 1 == ~t4_pc~0; 22186#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21054#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20433#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20434#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 20538#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21849#L735 assume !(1 == ~t5_pc~0); 20505#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 20506#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20953#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21873#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 21515#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21516#L754 assume 1 == ~t6_pc~0; 21266#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21163#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20749#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20750#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 21137#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21947#L773 assume !(1 == ~t7_pc~0); 20689#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20688#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21550#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21525#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 21526#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21579#L792 assume 1 == ~t8_pc~0; 21747#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22065#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22066#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21517#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 21440#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21441#L811 assume 1 == ~t9_pc~0; 21650#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22110#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20826#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20827#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 21452#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21453#L830 assume !(1 == ~t10_pc~0); 21172#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 20665#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20666#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20643#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20644#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21965#L849 assume 1 == ~t11_pc~0; 21966#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 20484#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20485#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21976#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 21877#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21878#L868 assume !(1 == ~t12_pc~0); 21298#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 21297#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20375#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 20376#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 20700#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20701#L887 assume 1 == ~t13_pc~0; 21885#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 21343#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21344#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 21941#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 20415#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20416#L1439 assume !(1 == ~M_E~0); 21509#L1439-2 assume !(1 == ~T1_E~0); 20581#L1444-1 assume !(1 == ~T2_E~0); 20582#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21077#L1454-1 assume !(1 == ~T4_E~0); 21078#L1459-1 assume !(1 == ~T5_E~0); 21642#L1464-1 assume !(1 == ~T6_E~0); 21643#L1469-1 assume !(1 == ~T7_E~0); 21716#L1474-1 assume !(1 == ~T8_E~0); 21408#L1479-1 assume !(1 == ~T9_E~0); 21409#L1484-1 assume !(1 == ~T10_E~0); 21646#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21287#L1494-1 assume !(1 == ~T12_E~0); 21288#L1499-1 assume !(1 == ~T13_E~0); 21474#L1504-1 assume !(1 == ~E_M~0); 21475#L1509-1 assume !(1 == ~E_1~0); 22050#L1514-1 assume !(1 == ~E_2~0); 21749#L1519-1 assume !(1 == ~E_3~0); 21750#L1524-1 assume !(1 == ~E_4~0); 22242#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 22243#L1534-1 assume !(1 == ~E_6~0); 20409#L1539-1 assume !(1 == ~E_7~0); 20410#L1544-1 assume !(1 == ~E_8~0); 20823#L1549-1 assume !(1 == ~E_9~0); 22215#L1554-1 assume !(1 == ~E_10~0); 22212#L1559-1 assume !(1 == ~E_11~0); 22090#L1564-1 assume !(1 == ~E_12~0); 22091#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 22237#L1574-1 assume { :end_inline_reset_delta_events } true; 20579#L1940-2 [2022-12-13 18:37:26,193 INFO L750 eck$LassoCheckResult]: Loop: 20579#L1940-2 assume !false; 20580#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21175#L1266 assume !false; 21889#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 21132#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20851#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 22049#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22058#L1079 assume !(0 != eval_~tmp~0#1); 21331#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20990#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20991#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21717#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21718#L1296-3 assume !(0 == ~T2_E~0); 22268#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22223#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21373#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20617#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20618#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20719#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21504#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21755#L1336-3 assume !(0 == ~T10_E~0); 21756#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 21069#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21048#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 20988#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20989#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21569#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20335#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20336#L1376-3 assume !(0 == ~E_4~0); 22070#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21927#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21928#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22102#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22103#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 20680#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 20546#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 20547#L1416-3 assume !(0 == ~E_12~0); 21226#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 21227#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21338#L640-45 assume !(1 == ~m_pc~0); 21339#L640-47 is_master_triggered_~__retres1~0#1 := 0; 20783#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20784#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20331#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20332#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20423#L659-45 assume 1 == ~t1_pc~0; 20424#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20866#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22272#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22203#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21858#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21859#L678-45 assume 1 == ~t2_pc~0; 21813#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21345#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21346#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21795#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22119#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22221#L697-45 assume 1 == ~t3_pc~0; 21608#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21609#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22288#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21761#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21762#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21796#L716-45 assume 1 == ~t4_pc~0; 21420#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21421#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22076#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21427#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21428#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21087#L735-45 assume 1 == ~t5_pc~0; 21088#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21640#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22239#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22285#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22241#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22235#L754-45 assume 1 == ~t6_pc~0; 21591#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21592#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21485#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21486#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21596#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21319#L773-45 assume 1 == ~t7_pc~0; 21320#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20862#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21557#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21558#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 21327#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20982#L792-45 assume 1 == ~t8_pc~0; 20983#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22005#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22006#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20444#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20445#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20932#L811-45 assume 1 == ~t9_pc~0; 20712#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20714#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21924#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21792#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21399#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21185#L830-45 assume 1 == ~t10_pc~0; 21186#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 20371#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21508#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20590#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20591#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20351#L849-45 assume !(1 == ~t11_pc~0); 20352#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 20801#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20647#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 20337#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20338#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20585#L868-45 assume 1 == ~t12_pc~0; 20586#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20531#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20532#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 21959#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 22132#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 22133#L887-45 assume !(1 == ~t13_pc~0); 20592#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 20593#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21887#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 21906#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 20561#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20562#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21882#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20577#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20578#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20733#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21698#L1459-3 assume !(1 == ~T5_E~0); 21699#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 22134#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22073#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22074#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22136#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21381#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21382#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 21999#L1499-3 assume !(1 == ~T13_E~0); 21657#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21658#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22086#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22120#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21294#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21295#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22158#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21576#L1539-3 assume !(1 == ~E_7~0); 21033#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21034#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21539#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20624#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 20625#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 21797#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 21798#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20518#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20292#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20616#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 20525#L1959 assume !(0 == start_simulation_~tmp~3#1); 20527#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20557#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20511#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20346#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 20347#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22152#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22127#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 22128#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 20579#L1940-2 [2022-12-13 18:37:26,194 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:26,194 INFO L85 PathProgramCache]: Analyzing trace with hash 1024455497, now seen corresponding path program 1 times [2022-12-13 18:37:26,195 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:26,195 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1233664167] [2022-12-13 18:37:26,195 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:26,195 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:26,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:26,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:26,245 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:26,246 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1233664167] [2022-12-13 18:37:26,246 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1233664167] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:26,246 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:26,246 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:26,246 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [245335740] [2022-12-13 18:37:26,246 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:26,247 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 18:37:26,247 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:26,247 INFO L85 PathProgramCache]: Analyzing trace with hash 1253029853, now seen corresponding path program 2 times [2022-12-13 18:37:26,247 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:26,248 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [873211996] [2022-12-13 18:37:26,248 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:26,248 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:26,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:26,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:26,306 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:26,306 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [873211996] [2022-12-13 18:37:26,306 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [873211996] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:26,306 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:26,306 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:26,307 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1941292666] [2022-12-13 18:37:26,307 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:26,307 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:37:26,307 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:37:26,308 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 18:37:26,308 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 18:37:26,308 INFO L87 Difference]: Start difference. First operand 2023 states and 2992 transitions. cyclomatic complexity: 970 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:26,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:37:26,344 INFO L93 Difference]: Finished difference Result 2023 states and 2991 transitions. [2022-12-13 18:37:26,344 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2991 transitions. [2022-12-13 18:37:26,349 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-12-13 18:37:26,353 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2991 transitions. [2022-12-13 18:37:26,353 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2022-12-13 18:37:26,354 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2022-12-13 18:37:26,354 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2991 transitions. [2022-12-13 18:37:26,356 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:37:26,356 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2023 states and 2991 transitions. [2022-12-13 18:37:26,358 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2991 transitions. [2022-12-13 18:37:26,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2022-12-13 18:37:26,374 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4784972812654473) internal successors, (2991), 2022 states have internal predecessors, (2991), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:26,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2991 transitions. [2022-12-13 18:37:26,378 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2023 states and 2991 transitions. [2022-12-13 18:37:26,378 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 18:37:26,378 INFO L428 stractBuchiCegarLoop]: Abstraction has 2023 states and 2991 transitions. [2022-12-13 18:37:26,378 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 18:37:26,379 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2991 transitions. [2022-12-13 18:37:26,383 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-12-13 18:37:26,383 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:37:26,383 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:37:26,385 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:26,385 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:26,385 INFO L748 eck$LassoCheckResult]: Stem: 24624#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 24625#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 25612#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25613#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26342#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 25740#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25203#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25204#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26009#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26010#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26116#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 26117#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 24958#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24959#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 26151#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25510#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25511#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 26055#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 25422#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25423#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 26343#L1291-2 assume !(0 == ~T1_E~0); 26340#L1296-1 assume !(0 == ~T2_E~0); 25574#L1301-1 assume !(0 == ~T3_E~0); 25575#L1306-1 assume !(0 == ~T4_E~0); 26066#L1311-1 assume !(0 == ~T5_E~0); 24798#L1316-1 assume !(0 == ~T6_E~0); 24799#L1321-1 assume !(0 == ~T7_E~0); 25588#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24621#L1331-1 assume !(0 == ~T9_E~0); 24336#L1336-1 assume !(0 == ~T10_E~0); 24337#L1341-1 assume !(0 == ~T11_E~0); 24413#L1346-1 assume !(0 == ~T12_E~0); 24414#L1351-1 assume !(0 == ~T13_E~0); 24738#L1356-1 assume !(0 == ~E_M~0); 24739#L1361-1 assume !(0 == ~E_1~0); 26280#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 24782#L1371-1 assume !(0 == ~E_3~0); 24783#L1376-1 assume !(0 == ~E_4~0); 25640#L1381-1 assume !(0 == ~E_5~0); 25641#L1386-1 assume !(0 == ~E_6~0); 26311#L1391-1 assume !(0 == ~E_7~0); 26331#L1396-1 assume !(0 == ~E_8~0); 25542#L1401-1 assume !(0 == ~E_9~0); 25543#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 25830#L1411-1 assume !(0 == ~E_11~0); 25831#L1416-1 assume !(0 == ~E_12~0); 25460#L1421-1 assume !(0 == ~E_13~0); 24979#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24980#L640 assume !(1 == ~m_pc~0); 25509#L640-2 is_master_triggered_~__retres1~0#1 := 0; 25508#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25468#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25469#L1603 assume !(0 != activate_threads_~tmp~1#1); 25497#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25125#L659 assume 1 == ~t1_pc~0; 25126#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25233#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25946#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25254#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 25255#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25271#L678 assume 1 == ~t2_pc~0; 26218#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26219#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24823#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24824#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 25367#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25490#L697 assume !(1 == ~t3_pc~0); 25491#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25621#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25936#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25402#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25403#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26251#L716 assume 1 == ~t4_pc~0; 26239#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25107#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24486#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24487#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 24591#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25902#L735 assume !(1 == ~t5_pc~0); 24558#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 24559#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25006#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25926#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 25568#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25569#L754 assume 1 == ~t6_pc~0; 25319#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25216#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24802#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24803#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 25190#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26000#L773 assume !(1 == ~t7_pc~0); 24742#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 24741#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25603#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25578#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 25579#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25632#L792 assume 1 == ~t8_pc~0; 25800#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26118#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26119#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25570#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 25493#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25494#L811 assume 1 == ~t9_pc~0; 25703#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26163#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24879#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 24880#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 25505#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25506#L830 assume !(1 == ~t10_pc~0); 25225#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 24718#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24719#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 24696#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24697#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26018#L849 assume 1 == ~t11_pc~0; 26019#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 24537#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24538#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 26029#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 25930#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25931#L868 assume !(1 == ~t12_pc~0); 25351#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 25350#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24428#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 24429#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 24753#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 24754#L887 assume 1 == ~t13_pc~0; 25938#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25396#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 25397#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 25994#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 24468#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24469#L1439 assume !(1 == ~M_E~0); 25562#L1439-2 assume !(1 == ~T1_E~0); 24634#L1444-1 assume !(1 == ~T2_E~0); 24635#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25130#L1454-1 assume !(1 == ~T4_E~0); 25131#L1459-1 assume !(1 == ~T5_E~0); 25695#L1464-1 assume !(1 == ~T6_E~0); 25696#L1469-1 assume !(1 == ~T7_E~0); 25769#L1474-1 assume !(1 == ~T8_E~0); 25461#L1479-1 assume !(1 == ~T9_E~0); 25462#L1484-1 assume !(1 == ~T10_E~0); 25699#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25340#L1494-1 assume !(1 == ~T12_E~0); 25341#L1499-1 assume !(1 == ~T13_E~0); 25527#L1504-1 assume !(1 == ~E_M~0); 25528#L1509-1 assume !(1 == ~E_1~0); 26103#L1514-1 assume !(1 == ~E_2~0); 25802#L1519-1 assume !(1 == ~E_3~0); 25803#L1524-1 assume !(1 == ~E_4~0); 26295#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 26296#L1534-1 assume !(1 == ~E_6~0); 24462#L1539-1 assume !(1 == ~E_7~0); 24463#L1544-1 assume !(1 == ~E_8~0); 24876#L1549-1 assume !(1 == ~E_9~0); 26268#L1554-1 assume !(1 == ~E_10~0); 26265#L1559-1 assume !(1 == ~E_11~0); 26143#L1564-1 assume !(1 == ~E_12~0); 26144#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 26290#L1574-1 assume { :end_inline_reset_delta_events } true; 24632#L1940-2 [2022-12-13 18:37:26,385 INFO L750 eck$LassoCheckResult]: Loop: 24632#L1940-2 assume !false; 24633#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25228#L1266 assume !false; 25942#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 25185#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24904#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 26102#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 26111#L1079 assume !(0 != eval_~tmp~0#1); 25384#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25043#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25044#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25770#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25771#L1296-3 assume !(0 == ~T2_E~0); 26321#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26276#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25426#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24670#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24671#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24772#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25557#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25808#L1336-3 assume !(0 == ~T10_E~0); 25809#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 25122#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 25101#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 25041#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25042#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25622#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24388#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24389#L1376-3 assume !(0 == ~E_4~0); 26123#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25980#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25981#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26155#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26156#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 24733#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 24599#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24600#L1416-3 assume !(0 == ~E_12~0); 25279#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 25280#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25391#L640-45 assume !(1 == ~m_pc~0); 25392#L640-47 is_master_triggered_~__retres1~0#1 := 0; 24836#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24837#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24384#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24385#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24476#L659-45 assume 1 == ~t1_pc~0; 24477#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24919#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26325#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26256#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25911#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25912#L678-45 assume 1 == ~t2_pc~0; 25866#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25398#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25399#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25848#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26172#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26274#L697-45 assume 1 == ~t3_pc~0; 25661#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25662#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26341#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25814#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25815#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25849#L716-45 assume 1 == ~t4_pc~0; 25473#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25474#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26129#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25480#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25481#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25140#L735-45 assume 1 == ~t5_pc~0; 25141#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25693#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26292#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26338#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26294#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26288#L754-45 assume 1 == ~t6_pc~0; 25644#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25645#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25538#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25539#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25649#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25372#L773-45 assume !(1 == ~t7_pc~0); 24914#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 24915#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25610#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25611#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 25380#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25035#L792-45 assume 1 == ~t8_pc~0; 25036#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26058#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26059#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24497#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24498#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24985#L811-45 assume 1 == ~t9_pc~0; 24765#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24767#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25977#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25845#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25452#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25238#L830-45 assume 1 == ~t10_pc~0; 25239#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24424#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25561#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 24643#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24644#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24404#L849-45 assume !(1 == ~t11_pc~0); 24405#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 24854#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24700#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 24390#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 24391#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24638#L868-45 assume !(1 == ~t12_pc~0); 24640#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 24584#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24585#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 26012#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 26185#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 26186#L887-45 assume !(1 == ~t13_pc~0); 24645#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 24646#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 25940#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 25959#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 24614#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24615#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25935#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24630#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24631#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24786#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25751#L1459-3 assume !(1 == ~T5_E~0); 25752#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26187#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26126#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26127#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 26189#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25434#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25435#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 26052#L1499-3 assume !(1 == ~T13_E~0); 25710#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25711#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26139#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26173#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25347#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25348#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26211#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25629#L1539-3 assume !(1 == ~E_7~0); 25086#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25087#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25592#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24677#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24678#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 25850#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 25851#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24571#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24345#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24669#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 24578#L1959 assume !(0 == start_simulation_~tmp~3#1); 24580#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24610#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24564#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24399#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 24400#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26205#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26180#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 26181#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 24632#L1940-2 [2022-12-13 18:37:26,385 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:26,386 INFO L85 PathProgramCache]: Analyzing trace with hash -869878389, now seen corresponding path program 1 times [2022-12-13 18:37:26,386 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:26,386 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1482124049] [2022-12-13 18:37:26,386 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:26,386 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:26,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:26,418 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:26,418 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:26,419 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1482124049] [2022-12-13 18:37:26,419 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1482124049] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:26,419 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:26,419 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:26,419 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1872323484] [2022-12-13 18:37:26,419 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:26,420 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 18:37:26,420 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:26,420 INFO L85 PathProgramCache]: Analyzing trace with hash -420896353, now seen corresponding path program 1 times [2022-12-13 18:37:26,420 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:26,420 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1572826084] [2022-12-13 18:37:26,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:26,421 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:26,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:26,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:26,474 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:26,474 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1572826084] [2022-12-13 18:37:26,474 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1572826084] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:26,474 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:26,474 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:26,474 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1452283446] [2022-12-13 18:37:26,474 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:26,475 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:37:26,475 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:37:26,475 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 18:37:26,475 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 18:37:26,476 INFO L87 Difference]: Start difference. First operand 2023 states and 2991 transitions. cyclomatic complexity: 969 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:26,501 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:37:26,501 INFO L93 Difference]: Finished difference Result 2023 states and 2990 transitions. [2022-12-13 18:37:26,501 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2990 transitions. [2022-12-13 18:37:26,506 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-12-13 18:37:26,510 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2990 transitions. [2022-12-13 18:37:26,511 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2022-12-13 18:37:26,511 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2022-12-13 18:37:26,512 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2990 transitions. [2022-12-13 18:37:26,513 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:37:26,513 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2023 states and 2990 transitions. [2022-12-13 18:37:26,515 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2990 transitions. [2022-12-13 18:37:26,538 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2022-12-13 18:37:26,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4780029658922393) internal successors, (2990), 2022 states have internal predecessors, (2990), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:26,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2990 transitions. [2022-12-13 18:37:26,544 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2023 states and 2990 transitions. [2022-12-13 18:37:26,544 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 18:37:26,544 INFO L428 stractBuchiCegarLoop]: Abstraction has 2023 states and 2990 transitions. [2022-12-13 18:37:26,545 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 18:37:26,545 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2990 transitions. [2022-12-13 18:37:26,551 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-12-13 18:37:26,551 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:37:26,551 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:37:26,554 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:26,554 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:26,554 INFO L748 eck$LassoCheckResult]: Stem: 28677#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 28678#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 29665#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29666#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30395#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 29793#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29256#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29257#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30062#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30063#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30169#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30170#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 29011#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 29012#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 30204#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29563#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29564#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 30108#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 29475#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29476#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 30396#L1291-2 assume !(0 == ~T1_E~0); 30393#L1296-1 assume !(0 == ~T2_E~0); 29627#L1301-1 assume !(0 == ~T3_E~0); 29628#L1306-1 assume !(0 == ~T4_E~0); 30119#L1311-1 assume !(0 == ~T5_E~0); 28851#L1316-1 assume !(0 == ~T6_E~0); 28852#L1321-1 assume !(0 == ~T7_E~0); 29641#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28674#L1331-1 assume !(0 == ~T9_E~0); 28389#L1336-1 assume !(0 == ~T10_E~0); 28390#L1341-1 assume !(0 == ~T11_E~0); 28466#L1346-1 assume !(0 == ~T12_E~0); 28467#L1351-1 assume !(0 == ~T13_E~0); 28791#L1356-1 assume !(0 == ~E_M~0); 28792#L1361-1 assume !(0 == ~E_1~0); 30333#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 28835#L1371-1 assume !(0 == ~E_3~0); 28836#L1376-1 assume !(0 == ~E_4~0); 29693#L1381-1 assume !(0 == ~E_5~0); 29694#L1386-1 assume !(0 == ~E_6~0); 30364#L1391-1 assume !(0 == ~E_7~0); 30384#L1396-1 assume !(0 == ~E_8~0); 29595#L1401-1 assume !(0 == ~E_9~0); 29596#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 29883#L1411-1 assume !(0 == ~E_11~0); 29884#L1416-1 assume !(0 == ~E_12~0); 29513#L1421-1 assume !(0 == ~E_13~0); 29032#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29033#L640 assume !(1 == ~m_pc~0); 29562#L640-2 is_master_triggered_~__retres1~0#1 := 0; 29561#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29521#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29522#L1603 assume !(0 != activate_threads_~tmp~1#1); 29550#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29178#L659 assume 1 == ~t1_pc~0; 29179#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29286#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29999#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29307#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 29308#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29324#L678 assume 1 == ~t2_pc~0; 30271#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30272#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28876#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28877#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 29420#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29543#L697 assume !(1 == ~t3_pc~0); 29544#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29674#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29989#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29455#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29456#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30304#L716 assume 1 == ~t4_pc~0; 30292#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29160#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28539#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28540#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 28644#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29955#L735 assume !(1 == ~t5_pc~0); 28611#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 28612#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29059#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29979#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 29621#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29622#L754 assume 1 == ~t6_pc~0; 29372#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29269#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28855#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28856#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 29243#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30053#L773 assume !(1 == ~t7_pc~0); 28795#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 28794#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29656#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29631#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 29632#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29685#L792 assume 1 == ~t8_pc~0; 29853#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30171#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30172#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29623#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 29546#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29547#L811 assume 1 == ~t9_pc~0; 29756#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30216#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28932#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 28933#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 29558#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29559#L830 assume !(1 == ~t10_pc~0); 29278#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 28771#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28772#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28749#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28750#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30071#L849 assume 1 == ~t11_pc~0; 30072#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28590#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28591#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 30082#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 29983#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29984#L868 assume !(1 == ~t12_pc~0); 29404#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 29403#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28481#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 28482#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 28806#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 28807#L887 assume 1 == ~t13_pc~0; 29991#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29449#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29450#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 30047#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 28521#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28522#L1439 assume !(1 == ~M_E~0); 29615#L1439-2 assume !(1 == ~T1_E~0); 28687#L1444-1 assume !(1 == ~T2_E~0); 28688#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29183#L1454-1 assume !(1 == ~T4_E~0); 29184#L1459-1 assume !(1 == ~T5_E~0); 29748#L1464-1 assume !(1 == ~T6_E~0); 29749#L1469-1 assume !(1 == ~T7_E~0); 29822#L1474-1 assume !(1 == ~T8_E~0); 29514#L1479-1 assume !(1 == ~T9_E~0); 29515#L1484-1 assume !(1 == ~T10_E~0); 29752#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29393#L1494-1 assume !(1 == ~T12_E~0); 29394#L1499-1 assume !(1 == ~T13_E~0); 29580#L1504-1 assume !(1 == ~E_M~0); 29581#L1509-1 assume !(1 == ~E_1~0); 30156#L1514-1 assume !(1 == ~E_2~0); 29855#L1519-1 assume !(1 == ~E_3~0); 29856#L1524-1 assume !(1 == ~E_4~0); 30348#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 30349#L1534-1 assume !(1 == ~E_6~0); 28515#L1539-1 assume !(1 == ~E_7~0); 28516#L1544-1 assume !(1 == ~E_8~0); 28929#L1549-1 assume !(1 == ~E_9~0); 30321#L1554-1 assume !(1 == ~E_10~0); 30318#L1559-1 assume !(1 == ~E_11~0); 30196#L1564-1 assume !(1 == ~E_12~0); 30197#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 30343#L1574-1 assume { :end_inline_reset_delta_events } true; 28685#L1940-2 [2022-12-13 18:37:26,555 INFO L750 eck$LassoCheckResult]: Loop: 28685#L1940-2 assume !false; 28686#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29281#L1266 assume !false; 29995#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 29238#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28957#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 30155#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 30164#L1079 assume !(0 != eval_~tmp~0#1); 29437#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29096#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29097#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29823#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29824#L1296-3 assume !(0 == ~T2_E~0); 30374#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30329#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29479#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28723#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28724#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28825#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29610#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29861#L1336-3 assume !(0 == ~T10_E~0); 29862#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29175#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 29154#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 29094#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29095#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29675#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28441#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28442#L1376-3 assume !(0 == ~E_4~0); 30176#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30033#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30034#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30208#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30209#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28786#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28652#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28653#L1416-3 assume !(0 == ~E_12~0); 29332#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 29333#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29444#L640-45 assume !(1 == ~m_pc~0); 29445#L640-47 is_master_triggered_~__retres1~0#1 := 0; 28889#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28890#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28437#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28438#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28529#L659-45 assume 1 == ~t1_pc~0; 28530#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28972#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30378#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30309#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29964#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29965#L678-45 assume !(1 == ~t2_pc~0); 29920#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 29451#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29452#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29901#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30225#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30327#L697-45 assume 1 == ~t3_pc~0; 29714#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29715#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30394#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29867#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29868#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29902#L716-45 assume 1 == ~t4_pc~0; 29526#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29527#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30182#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29533#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29534#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29193#L735-45 assume 1 == ~t5_pc~0; 29194#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29746#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30345#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30391#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30347#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30341#L754-45 assume 1 == ~t6_pc~0; 29697#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29698#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29591#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29592#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29702#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29425#L773-45 assume 1 == ~t7_pc~0; 29426#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28968#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29663#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29664#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 29433#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29088#L792-45 assume 1 == ~t8_pc~0; 29089#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30111#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30112#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28550#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28551#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29038#L811-45 assume 1 == ~t9_pc~0; 28818#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28820#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30030#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29898#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29505#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29291#L830-45 assume 1 == ~t10_pc~0; 29292#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28477#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29614#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28696#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28697#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28457#L849-45 assume !(1 == ~t11_pc~0); 28458#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 28907#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28753#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28443#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28444#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28691#L868-45 assume 1 == ~t12_pc~0; 28692#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 28637#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28638#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 30065#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 30238#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 30239#L887-45 assume 1 == ~t13_pc~0; 30066#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 28699#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29993#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 30012#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 28667#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28668#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29988#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28683#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28684#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28839#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29804#L1459-3 assume !(1 == ~T5_E~0); 29805#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30240#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30179#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30180#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30242#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29487#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29488#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 30105#L1499-3 assume !(1 == ~T13_E~0); 29763#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29764#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30192#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30226#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29400#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29401#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30264#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29682#L1539-3 assume !(1 == ~E_7~0); 29139#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 29140#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 29645#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 28730#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28731#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 29903#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 29904#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28624#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28398#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28722#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 28631#L1959 assume !(0 == start_simulation_~tmp~3#1); 28633#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28663#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28617#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28452#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 28453#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30258#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30233#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 30234#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 28685#L1940-2 [2022-12-13 18:37:26,555 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:26,555 INFO L85 PathProgramCache]: Analyzing trace with hash 1978508041, now seen corresponding path program 1 times [2022-12-13 18:37:26,555 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:26,555 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [941213083] [2022-12-13 18:37:26,555 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:26,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:26,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:26,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:26,590 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:26,590 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [941213083] [2022-12-13 18:37:26,590 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [941213083] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:26,590 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:26,590 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:26,590 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [94593567] [2022-12-13 18:37:26,590 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:26,591 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 18:37:26,591 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:26,591 INFO L85 PathProgramCache]: Analyzing trace with hash -131869795, now seen corresponding path program 1 times [2022-12-13 18:37:26,591 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:26,591 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [380906669] [2022-12-13 18:37:26,592 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:26,592 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:26,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:26,647 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:26,647 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:26,647 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [380906669] [2022-12-13 18:37:26,647 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [380906669] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:26,647 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:26,647 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:26,648 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1047479748] [2022-12-13 18:37:26,648 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:26,648 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:37:26,648 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:37:26,648 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 18:37:26,649 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 18:37:26,649 INFO L87 Difference]: Start difference. First operand 2023 states and 2990 transitions. cyclomatic complexity: 968 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:26,673 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:37:26,673 INFO L93 Difference]: Finished difference Result 2023 states and 2989 transitions. [2022-12-13 18:37:26,673 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2989 transitions. [2022-12-13 18:37:26,679 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-12-13 18:37:26,684 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2989 transitions. [2022-12-13 18:37:26,684 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2022-12-13 18:37:26,687 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2022-12-13 18:37:26,687 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2989 transitions. [2022-12-13 18:37:26,690 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:37:26,690 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2023 states and 2989 transitions. [2022-12-13 18:37:26,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2989 transitions. [2022-12-13 18:37:26,722 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2022-12-13 18:37:26,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4775086505190311) internal successors, (2989), 2022 states have internal predecessors, (2989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:26,744 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2989 transitions. [2022-12-13 18:37:26,744 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2023 states and 2989 transitions. [2022-12-13 18:37:26,744 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 18:37:26,745 INFO L428 stractBuchiCegarLoop]: Abstraction has 2023 states and 2989 transitions. [2022-12-13 18:37:26,745 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 18:37:26,745 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2989 transitions. [2022-12-13 18:37:26,749 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-12-13 18:37:26,750 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:37:26,750 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:37:26,752 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:26,752 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:26,753 INFO L748 eck$LassoCheckResult]: Stem: 32730#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 32731#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 33718#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33719#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34448#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 33846#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33309#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33310#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34115#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34116#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34222#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34223#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33064#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 33065#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 34257#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 33616#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33617#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 34161#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 33528#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33529#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 34449#L1291-2 assume !(0 == ~T1_E~0); 34446#L1296-1 assume !(0 == ~T2_E~0); 33680#L1301-1 assume !(0 == ~T3_E~0); 33681#L1306-1 assume !(0 == ~T4_E~0); 34172#L1311-1 assume !(0 == ~T5_E~0); 32904#L1316-1 assume !(0 == ~T6_E~0); 32905#L1321-1 assume !(0 == ~T7_E~0); 33694#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32727#L1331-1 assume !(0 == ~T9_E~0); 32442#L1336-1 assume !(0 == ~T10_E~0); 32443#L1341-1 assume !(0 == ~T11_E~0); 32519#L1346-1 assume !(0 == ~T12_E~0); 32520#L1351-1 assume !(0 == ~T13_E~0); 32844#L1356-1 assume !(0 == ~E_M~0); 32845#L1361-1 assume !(0 == ~E_1~0); 34386#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 32888#L1371-1 assume !(0 == ~E_3~0); 32889#L1376-1 assume !(0 == ~E_4~0); 33746#L1381-1 assume !(0 == ~E_5~0); 33747#L1386-1 assume !(0 == ~E_6~0); 34417#L1391-1 assume !(0 == ~E_7~0); 34437#L1396-1 assume !(0 == ~E_8~0); 33648#L1401-1 assume !(0 == ~E_9~0); 33649#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 33936#L1411-1 assume !(0 == ~E_11~0); 33937#L1416-1 assume !(0 == ~E_12~0); 33566#L1421-1 assume !(0 == ~E_13~0); 33085#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33086#L640 assume !(1 == ~m_pc~0); 33615#L640-2 is_master_triggered_~__retres1~0#1 := 0; 33614#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33574#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33575#L1603 assume !(0 != activate_threads_~tmp~1#1); 33603#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33231#L659 assume 1 == ~t1_pc~0; 33232#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33339#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34052#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33360#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 33361#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33377#L678 assume 1 == ~t2_pc~0; 34324#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34325#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32929#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32930#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 33473#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33596#L697 assume !(1 == ~t3_pc~0); 33597#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33727#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34042#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33508#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33509#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34357#L716 assume 1 == ~t4_pc~0; 34345#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33213#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32592#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32593#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 32697#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34008#L735 assume !(1 == ~t5_pc~0); 32664#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 32665#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33112#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34032#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 33674#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33675#L754 assume 1 == ~t6_pc~0; 33425#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33322#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32908#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32909#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 33296#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34106#L773 assume !(1 == ~t7_pc~0); 32848#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 32847#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33709#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33684#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 33685#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33738#L792 assume 1 == ~t8_pc~0; 33906#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34224#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34225#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33676#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 33599#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33600#L811 assume 1 == ~t9_pc~0; 33809#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34269#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32985#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 32986#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 33611#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33612#L830 assume !(1 == ~t10_pc~0); 33331#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 32824#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32825#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32802#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32803#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34124#L849 assume 1 == ~t11_pc~0; 34125#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32643#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32644#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34135#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 34036#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 34037#L868 assume !(1 == ~t12_pc~0); 33457#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 33456#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32534#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 32535#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 32859#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 32860#L887 assume 1 == ~t13_pc~0; 34044#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 33502#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 33503#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 34100#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 32574#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32575#L1439 assume !(1 == ~M_E~0); 33668#L1439-2 assume !(1 == ~T1_E~0); 32740#L1444-1 assume !(1 == ~T2_E~0); 32741#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33236#L1454-1 assume !(1 == ~T4_E~0); 33237#L1459-1 assume !(1 == ~T5_E~0); 33801#L1464-1 assume !(1 == ~T6_E~0); 33802#L1469-1 assume !(1 == ~T7_E~0); 33875#L1474-1 assume !(1 == ~T8_E~0); 33567#L1479-1 assume !(1 == ~T9_E~0); 33568#L1484-1 assume !(1 == ~T10_E~0); 33805#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33446#L1494-1 assume !(1 == ~T12_E~0); 33447#L1499-1 assume !(1 == ~T13_E~0); 33633#L1504-1 assume !(1 == ~E_M~0); 33634#L1509-1 assume !(1 == ~E_1~0); 34209#L1514-1 assume !(1 == ~E_2~0); 33908#L1519-1 assume !(1 == ~E_3~0); 33909#L1524-1 assume !(1 == ~E_4~0); 34401#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 34402#L1534-1 assume !(1 == ~E_6~0); 32568#L1539-1 assume !(1 == ~E_7~0); 32569#L1544-1 assume !(1 == ~E_8~0); 32982#L1549-1 assume !(1 == ~E_9~0); 34374#L1554-1 assume !(1 == ~E_10~0); 34371#L1559-1 assume !(1 == ~E_11~0); 34249#L1564-1 assume !(1 == ~E_12~0); 34250#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 34396#L1574-1 assume { :end_inline_reset_delta_events } true; 32738#L1940-2 [2022-12-13 18:37:26,753 INFO L750 eck$LassoCheckResult]: Loop: 32738#L1940-2 assume !false; 32739#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33334#L1266 assume !false; 34048#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 33291#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 33010#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 34208#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 34217#L1079 assume !(0 != eval_~tmp~0#1); 33490#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33149#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33150#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33876#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33877#L1296-3 assume !(0 == ~T2_E~0); 34427#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34382#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33532#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32776#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32777#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32878#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33663#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33914#L1336-3 assume !(0 == ~T10_E~0); 33915#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 33228#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 33207#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 33147#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 33148#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33728#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32494#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32495#L1376-3 assume !(0 == ~E_4~0); 34229#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 34086#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 34087#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34261#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 34262#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32839#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 32705#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32706#L1416-3 assume !(0 == ~E_12~0); 33385#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 33386#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33497#L640-45 assume !(1 == ~m_pc~0); 33498#L640-47 is_master_triggered_~__retres1~0#1 := 0; 32942#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32943#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32490#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32491#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32582#L659-45 assume 1 == ~t1_pc~0; 32583#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33025#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34431#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34362#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34017#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34018#L678-45 assume 1 == ~t2_pc~0; 33972#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 33504#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33505#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33954#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34278#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34380#L697-45 assume 1 == ~t3_pc~0; 33767#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33768#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34447#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33920#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33921#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33955#L716-45 assume 1 == ~t4_pc~0; 33579#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33580#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34235#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33586#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33587#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33246#L735-45 assume !(1 == ~t5_pc~0); 33248#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 33799#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34398#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34444#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 34400#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34394#L754-45 assume 1 == ~t6_pc~0; 33750#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33751#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33644#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33645#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33755#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33478#L773-45 assume 1 == ~t7_pc~0; 33479#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33021#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33716#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33717#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 33486#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33141#L792-45 assume 1 == ~t8_pc~0; 33142#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34164#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34165#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32603#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32604#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33091#L811-45 assume 1 == ~t9_pc~0; 32871#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32873#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34083#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33951#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33558#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33344#L830-45 assume 1 == ~t10_pc~0; 33345#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 32530#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33667#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32749#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32750#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32510#L849-45 assume 1 == ~t11_pc~0; 32512#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32960#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32806#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32496#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32497#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32744#L868-45 assume 1 == ~t12_pc~0; 32745#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 32690#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32691#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 34118#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 34291#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 34292#L887-45 assume 1 == ~t13_pc~0; 34119#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 32752#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 34046#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 34065#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 32720#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32721#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 34041#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32736#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32737#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32892#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33857#L1459-3 assume !(1 == ~T5_E~0); 33858#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34293#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34232#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 34233#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34295#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33540#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33541#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 34158#L1499-3 assume !(1 == ~T13_E~0); 33816#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33817#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34245#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34279#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33453#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33454#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 34317#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33735#L1539-3 assume !(1 == ~E_7~0); 33192#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33193#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 33698#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32783#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 32784#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 33956#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 33957#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32677#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32451#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 32775#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 32684#L1959 assume !(0 == start_simulation_~tmp~3#1); 32686#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32716#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32670#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 32505#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 32506#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34311#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34286#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 34287#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 32738#L1940-2 [2022-12-13 18:37:26,753 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:26,753 INFO L85 PathProgramCache]: Analyzing trace with hash -1393291829, now seen corresponding path program 1 times [2022-12-13 18:37:26,754 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:26,754 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [996102947] [2022-12-13 18:37:26,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:26,754 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:26,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:26,807 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:26,808 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:26,808 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [996102947] [2022-12-13 18:37:26,808 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [996102947] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:26,808 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:26,808 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:26,809 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1285086443] [2022-12-13 18:37:26,809 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:26,809 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 18:37:26,809 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:26,810 INFO L85 PathProgramCache]: Analyzing trace with hash -244240932, now seen corresponding path program 1 times [2022-12-13 18:37:26,810 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:26,810 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [525399977] [2022-12-13 18:37:26,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:26,810 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:26,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:26,891 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:26,891 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:26,892 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [525399977] [2022-12-13 18:37:26,892 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [525399977] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:26,892 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:26,892 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:26,892 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1444275102] [2022-12-13 18:37:26,892 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:26,893 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:37:26,893 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:37:26,893 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 18:37:26,893 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 18:37:26,894 INFO L87 Difference]: Start difference. First operand 2023 states and 2989 transitions. cyclomatic complexity: 967 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:26,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:37:26,915 INFO L93 Difference]: Finished difference Result 2023 states and 2988 transitions. [2022-12-13 18:37:26,915 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2988 transitions. [2022-12-13 18:37:26,920 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-12-13 18:37:26,924 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2988 transitions. [2022-12-13 18:37:26,924 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2022-12-13 18:37:26,925 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2022-12-13 18:37:26,925 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2988 transitions. [2022-12-13 18:37:26,927 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:37:26,927 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2023 states and 2988 transitions. [2022-12-13 18:37:26,929 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2988 transitions. [2022-12-13 18:37:26,943 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2022-12-13 18:37:26,945 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4770143351458231) internal successors, (2988), 2022 states have internal predecessors, (2988), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:26,948 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2988 transitions. [2022-12-13 18:37:26,948 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2023 states and 2988 transitions. [2022-12-13 18:37:26,948 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 18:37:26,949 INFO L428 stractBuchiCegarLoop]: Abstraction has 2023 states and 2988 transitions. [2022-12-13 18:37:26,949 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 18:37:26,949 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2988 transitions. [2022-12-13 18:37:26,955 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-12-13 18:37:26,956 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:37:26,956 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:37:26,958 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:26,958 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:26,958 INFO L748 eck$LassoCheckResult]: Stem: 36783#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 36784#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 37771#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37772#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38501#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 37899#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37362#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37363#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38168#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38169#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38275#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 38276#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37117#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37118#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 38310#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 37669#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37670#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 38214#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 37581#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37582#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 38502#L1291-2 assume !(0 == ~T1_E~0); 38499#L1296-1 assume !(0 == ~T2_E~0); 37733#L1301-1 assume !(0 == ~T3_E~0); 37734#L1306-1 assume !(0 == ~T4_E~0); 38225#L1311-1 assume !(0 == ~T5_E~0); 36957#L1316-1 assume !(0 == ~T6_E~0); 36958#L1321-1 assume !(0 == ~T7_E~0); 37747#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36780#L1331-1 assume !(0 == ~T9_E~0); 36495#L1336-1 assume !(0 == ~T10_E~0); 36496#L1341-1 assume !(0 == ~T11_E~0); 36572#L1346-1 assume !(0 == ~T12_E~0); 36573#L1351-1 assume !(0 == ~T13_E~0); 36897#L1356-1 assume !(0 == ~E_M~0); 36898#L1361-1 assume !(0 == ~E_1~0); 38439#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 36941#L1371-1 assume !(0 == ~E_3~0); 36942#L1376-1 assume !(0 == ~E_4~0); 37799#L1381-1 assume !(0 == ~E_5~0); 37800#L1386-1 assume !(0 == ~E_6~0); 38470#L1391-1 assume !(0 == ~E_7~0); 38490#L1396-1 assume !(0 == ~E_8~0); 37701#L1401-1 assume !(0 == ~E_9~0); 37702#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 37989#L1411-1 assume !(0 == ~E_11~0); 37990#L1416-1 assume !(0 == ~E_12~0); 37619#L1421-1 assume !(0 == ~E_13~0); 37138#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37139#L640 assume !(1 == ~m_pc~0); 37668#L640-2 is_master_triggered_~__retres1~0#1 := 0; 37667#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37627#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37628#L1603 assume !(0 != activate_threads_~tmp~1#1); 37656#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37284#L659 assume 1 == ~t1_pc~0; 37285#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37392#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38105#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37413#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 37414#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37430#L678 assume 1 == ~t2_pc~0; 38377#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38378#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36982#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36983#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 37526#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37649#L697 assume !(1 == ~t3_pc~0); 37650#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37780#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38095#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37561#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37562#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38410#L716 assume 1 == ~t4_pc~0; 38398#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37266#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36645#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36646#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 36750#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38061#L735 assume !(1 == ~t5_pc~0); 36717#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 36718#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37165#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38085#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 37727#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37728#L754 assume 1 == ~t6_pc~0; 37478#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37375#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36961#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36962#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 37349#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38159#L773 assume !(1 == ~t7_pc~0); 36901#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 36900#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37762#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37737#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 37738#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37791#L792 assume 1 == ~t8_pc~0; 37959#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38277#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38278#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37729#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 37652#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37653#L811 assume 1 == ~t9_pc~0; 37862#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38322#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37038#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37039#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 37664#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37665#L830 assume !(1 == ~t10_pc~0); 37384#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36877#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36878#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36855#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 36856#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38177#L849 assume 1 == ~t11_pc~0; 38178#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 36696#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36697#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38188#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 38089#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 38090#L868 assume !(1 == ~t12_pc~0); 37510#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 37509#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36587#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 36588#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 36912#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 36913#L887 assume 1 == ~t13_pc~0; 38097#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37555#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 37556#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 38153#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 36627#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36628#L1439 assume !(1 == ~M_E~0); 37721#L1439-2 assume !(1 == ~T1_E~0); 36793#L1444-1 assume !(1 == ~T2_E~0); 36794#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37289#L1454-1 assume !(1 == ~T4_E~0); 37290#L1459-1 assume !(1 == ~T5_E~0); 37854#L1464-1 assume !(1 == ~T6_E~0); 37855#L1469-1 assume !(1 == ~T7_E~0); 37928#L1474-1 assume !(1 == ~T8_E~0); 37620#L1479-1 assume !(1 == ~T9_E~0); 37621#L1484-1 assume !(1 == ~T10_E~0); 37858#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37499#L1494-1 assume !(1 == ~T12_E~0); 37500#L1499-1 assume !(1 == ~T13_E~0); 37686#L1504-1 assume !(1 == ~E_M~0); 37687#L1509-1 assume !(1 == ~E_1~0); 38262#L1514-1 assume !(1 == ~E_2~0); 37961#L1519-1 assume !(1 == ~E_3~0); 37962#L1524-1 assume !(1 == ~E_4~0); 38454#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 38455#L1534-1 assume !(1 == ~E_6~0); 36621#L1539-1 assume !(1 == ~E_7~0); 36622#L1544-1 assume !(1 == ~E_8~0); 37035#L1549-1 assume !(1 == ~E_9~0); 38427#L1554-1 assume !(1 == ~E_10~0); 38424#L1559-1 assume !(1 == ~E_11~0); 38302#L1564-1 assume !(1 == ~E_12~0); 38303#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 38449#L1574-1 assume { :end_inline_reset_delta_events } true; 36791#L1940-2 [2022-12-13 18:37:26,959 INFO L750 eck$LassoCheckResult]: Loop: 36791#L1940-2 assume !false; 36792#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37387#L1266 assume !false; 38101#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 37344#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 37063#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 38261#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 38270#L1079 assume !(0 != eval_~tmp~0#1); 37543#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37202#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37203#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37929#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37930#L1296-3 assume !(0 == ~T2_E~0); 38480#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38435#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37585#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36829#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36830#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36931#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37716#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37967#L1336-3 assume !(0 == ~T10_E~0); 37968#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 37281#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 37260#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 37200#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 37201#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37781#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36547#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36548#L1376-3 assume !(0 == ~E_4~0); 38282#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38139#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38140#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 38314#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 38315#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 36892#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 36758#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36759#L1416-3 assume !(0 == ~E_12~0); 37438#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 37439#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37550#L640-45 assume 1 == ~m_pc~0; 37552#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36995#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36996#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36543#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36544#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36635#L659-45 assume 1 == ~t1_pc~0; 36636#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37078#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38484#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38415#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38070#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38071#L678-45 assume 1 == ~t2_pc~0; 38025#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 37557#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37558#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38007#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38331#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38433#L697-45 assume 1 == ~t3_pc~0; 37820#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37821#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38500#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37973#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37974#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38008#L716-45 assume 1 == ~t4_pc~0; 37632#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37633#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38288#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37639#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37640#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37299#L735-45 assume 1 == ~t5_pc~0; 37300#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37852#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38451#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38497#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38453#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38447#L754-45 assume 1 == ~t6_pc~0; 37803#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37804#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37697#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37698#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37808#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37531#L773-45 assume !(1 == ~t7_pc~0); 37073#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 37074#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37769#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37770#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 37539#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37194#L792-45 assume 1 == ~t8_pc~0; 37195#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38217#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38218#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36656#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36657#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37144#L811-45 assume 1 == ~t9_pc~0; 36924#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36926#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38136#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38004#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 37611#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37397#L830-45 assume 1 == ~t10_pc~0; 37398#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 36583#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37720#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36802#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 36803#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36563#L849-45 assume !(1 == ~t11_pc~0); 36564#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 37013#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36859#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 36549#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 36550#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36797#L868-45 assume 1 == ~t12_pc~0; 36798#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 36743#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36744#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 38171#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 38344#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 38345#L887-45 assume !(1 == ~t13_pc~0); 36804#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 36805#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 38099#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 38118#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 36773#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36774#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 38094#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36789#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36790#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36945#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37910#L1459-3 assume !(1 == ~T5_E~0); 37911#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38346#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38285#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38286#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38348#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37593#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37594#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 38211#L1499-3 assume !(1 == ~T13_E~0); 37869#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37870#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38298#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38332#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37506#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37507#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38370#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37788#L1539-3 assume !(1 == ~E_7~0); 37245#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37246#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 37751#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 36836#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 36837#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 38009#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 38010#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36730#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36504#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 36828#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 36737#L1959 assume !(0 == start_simulation_~tmp~3#1); 36739#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36769#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36723#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 36558#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 36559#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38364#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38339#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 38340#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 36791#L1940-2 [2022-12-13 18:37:26,959 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:26,959 INFO L85 PathProgramCache]: Analyzing trace with hash -1779154231, now seen corresponding path program 1 times [2022-12-13 18:37:26,959 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:26,960 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1169889063] [2022-12-13 18:37:26,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:26,960 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:26,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:27,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:27,003 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:27,004 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1169889063] [2022-12-13 18:37:27,004 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1169889063] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:27,004 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:27,004 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:27,004 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [834330909] [2022-12-13 18:37:27,004 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:27,005 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 18:37:27,005 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:27,005 INFO L85 PathProgramCache]: Analyzing trace with hash 1632340253, now seen corresponding path program 1 times [2022-12-13 18:37:27,005 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:27,005 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1209383904] [2022-12-13 18:37:27,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:27,006 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:27,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:27,075 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:27,075 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:27,075 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1209383904] [2022-12-13 18:37:27,075 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1209383904] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:27,075 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:27,076 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:27,076 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1762071054] [2022-12-13 18:37:27,076 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:27,076 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:37:27,076 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:37:27,077 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 18:37:27,077 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 18:37:27,077 INFO L87 Difference]: Start difference. First operand 2023 states and 2988 transitions. cyclomatic complexity: 966 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:27,112 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:37:27,112 INFO L93 Difference]: Finished difference Result 2023 states and 2987 transitions. [2022-12-13 18:37:27,112 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2987 transitions. [2022-12-13 18:37:27,119 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-12-13 18:37:27,127 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2987 transitions. [2022-12-13 18:37:27,127 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2022-12-13 18:37:27,129 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2022-12-13 18:37:27,129 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2987 transitions. [2022-12-13 18:37:27,132 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:37:27,132 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2023 states and 2987 transitions. [2022-12-13 18:37:27,135 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2987 transitions. [2022-12-13 18:37:27,157 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2022-12-13 18:37:27,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.476520019772615) internal successors, (2987), 2022 states have internal predecessors, (2987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:27,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2987 transitions. [2022-12-13 18:37:27,165 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2023 states and 2987 transitions. [2022-12-13 18:37:27,166 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 18:37:27,166 INFO L428 stractBuchiCegarLoop]: Abstraction has 2023 states and 2987 transitions. [2022-12-13 18:37:27,166 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 18:37:27,167 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2987 transitions. [2022-12-13 18:37:27,173 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-12-13 18:37:27,173 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:37:27,173 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:37:27,175 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:27,175 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:27,175 INFO L748 eck$LassoCheckResult]: Stem: 40836#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 40837#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 41824#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41825#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42554#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 41952#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41415#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41416#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42221#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42222#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42328#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 42329#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41170#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41171#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 42363#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41722#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 41723#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 42267#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 41634#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41635#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 42555#L1291-2 assume !(0 == ~T1_E~0); 42552#L1296-1 assume !(0 == ~T2_E~0); 41786#L1301-1 assume !(0 == ~T3_E~0); 41787#L1306-1 assume !(0 == ~T4_E~0); 42278#L1311-1 assume !(0 == ~T5_E~0); 41010#L1316-1 assume !(0 == ~T6_E~0); 41011#L1321-1 assume !(0 == ~T7_E~0); 41800#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40833#L1331-1 assume !(0 == ~T9_E~0); 40548#L1336-1 assume !(0 == ~T10_E~0); 40549#L1341-1 assume !(0 == ~T11_E~0); 40625#L1346-1 assume !(0 == ~T12_E~0); 40626#L1351-1 assume !(0 == ~T13_E~0); 40950#L1356-1 assume !(0 == ~E_M~0); 40951#L1361-1 assume !(0 == ~E_1~0); 42492#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 40994#L1371-1 assume !(0 == ~E_3~0); 40995#L1376-1 assume !(0 == ~E_4~0); 41852#L1381-1 assume !(0 == ~E_5~0); 41853#L1386-1 assume !(0 == ~E_6~0); 42523#L1391-1 assume !(0 == ~E_7~0); 42543#L1396-1 assume !(0 == ~E_8~0); 41754#L1401-1 assume !(0 == ~E_9~0); 41755#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 42042#L1411-1 assume !(0 == ~E_11~0); 42043#L1416-1 assume !(0 == ~E_12~0); 41672#L1421-1 assume !(0 == ~E_13~0); 41191#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41192#L640 assume !(1 == ~m_pc~0); 41721#L640-2 is_master_triggered_~__retres1~0#1 := 0; 41720#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41680#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41681#L1603 assume !(0 != activate_threads_~tmp~1#1); 41709#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41337#L659 assume 1 == ~t1_pc~0; 41338#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41445#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42158#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41466#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 41467#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41483#L678 assume 1 == ~t2_pc~0; 42430#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42431#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41035#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41036#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 41579#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41702#L697 assume !(1 == ~t3_pc~0); 41703#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41833#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42148#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41614#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41615#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42463#L716 assume 1 == ~t4_pc~0; 42451#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41319#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40698#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40699#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 40803#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42114#L735 assume !(1 == ~t5_pc~0); 40770#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 40771#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41218#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42138#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 41780#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41781#L754 assume 1 == ~t6_pc~0; 41531#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41428#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41014#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41015#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 41402#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42212#L773 assume !(1 == ~t7_pc~0); 40954#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 40953#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41815#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41790#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 41791#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41844#L792 assume 1 == ~t8_pc~0; 42012#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 42330#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42331#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41782#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 41705#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41706#L811 assume 1 == ~t9_pc~0; 41915#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 42375#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41091#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41092#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 41717#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41718#L830 assume !(1 == ~t10_pc~0); 41437#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 40930#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40931#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 40908#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 40909#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 42230#L849 assume 1 == ~t11_pc~0; 42231#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 40749#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40750#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42241#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 42142#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 42143#L868 assume !(1 == ~t12_pc~0); 41563#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 41562#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40640#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 40641#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 40965#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 40966#L887 assume 1 == ~t13_pc~0; 42150#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 41608#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 41609#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 42206#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 40680#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40681#L1439 assume !(1 == ~M_E~0); 41774#L1439-2 assume !(1 == ~T1_E~0); 40846#L1444-1 assume !(1 == ~T2_E~0); 40847#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41342#L1454-1 assume !(1 == ~T4_E~0); 41343#L1459-1 assume !(1 == ~T5_E~0); 41907#L1464-1 assume !(1 == ~T6_E~0); 41908#L1469-1 assume !(1 == ~T7_E~0); 41981#L1474-1 assume !(1 == ~T8_E~0); 41673#L1479-1 assume !(1 == ~T9_E~0); 41674#L1484-1 assume !(1 == ~T10_E~0); 41911#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41552#L1494-1 assume !(1 == ~T12_E~0); 41553#L1499-1 assume !(1 == ~T13_E~0); 41739#L1504-1 assume !(1 == ~E_M~0); 41740#L1509-1 assume !(1 == ~E_1~0); 42315#L1514-1 assume !(1 == ~E_2~0); 42014#L1519-1 assume !(1 == ~E_3~0); 42015#L1524-1 assume !(1 == ~E_4~0); 42507#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 42508#L1534-1 assume !(1 == ~E_6~0); 40674#L1539-1 assume !(1 == ~E_7~0); 40675#L1544-1 assume !(1 == ~E_8~0); 41088#L1549-1 assume !(1 == ~E_9~0); 42480#L1554-1 assume !(1 == ~E_10~0); 42477#L1559-1 assume !(1 == ~E_11~0); 42355#L1564-1 assume !(1 == ~E_12~0); 42356#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 42502#L1574-1 assume { :end_inline_reset_delta_events } true; 40844#L1940-2 [2022-12-13 18:37:27,175 INFO L750 eck$LassoCheckResult]: Loop: 40844#L1940-2 assume !false; 40845#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41440#L1266 assume !false; 42154#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 41397#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 41116#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 42314#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 42323#L1079 assume !(0 != eval_~tmp~0#1); 41596#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41255#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41256#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 41982#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41983#L1296-3 assume !(0 == ~T2_E~0); 42533#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42488#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41638#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40882#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40883#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40984#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41769#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 42020#L1336-3 assume !(0 == ~T10_E~0); 42021#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 41334#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 41313#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 41253#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 41254#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 41834#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40600#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40601#L1376-3 assume !(0 == ~E_4~0); 42335#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42192#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 42193#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 42367#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 42368#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 40945#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 40811#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 40812#L1416-3 assume !(0 == ~E_12~0); 41491#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 41492#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41603#L640-45 assume !(1 == ~m_pc~0); 41604#L640-47 is_master_triggered_~__retres1~0#1 := 0; 41048#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41049#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40596#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40597#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40688#L659-45 assume 1 == ~t1_pc~0; 40689#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41131#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42537#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42468#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42123#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42124#L678-45 assume 1 == ~t2_pc~0; 42078#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41610#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41611#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42060#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42384#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42486#L697-45 assume 1 == ~t3_pc~0; 41873#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 41874#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42553#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 42026#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42027#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42061#L716-45 assume 1 == ~t4_pc~0; 41685#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41686#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42341#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41692#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41693#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41352#L735-45 assume 1 == ~t5_pc~0; 41353#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41905#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42504#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42550#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42506#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42500#L754-45 assume 1 == ~t6_pc~0; 41856#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41857#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41750#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41751#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 41861#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41584#L773-45 assume 1 == ~t7_pc~0; 41585#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41127#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41822#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41823#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 41592#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41247#L792-45 assume 1 == ~t8_pc~0; 41248#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 42270#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42271#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40709#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40710#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41197#L811-45 assume 1 == ~t9_pc~0; 40977#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40979#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42189#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42057#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 41664#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41450#L830-45 assume 1 == ~t10_pc~0; 41451#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 40636#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41773#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 40855#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 40856#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40616#L849-45 assume !(1 == ~t11_pc~0); 40617#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 41066#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40912#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 40602#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 40603#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40850#L868-45 assume 1 == ~t12_pc~0; 40851#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 40796#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40797#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 42224#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 42397#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 42398#L887-45 assume 1 == ~t13_pc~0; 42225#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 40858#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42152#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 42171#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 40826#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40827#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 42147#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40842#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40843#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40998#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41963#L1459-3 assume !(1 == ~T5_E~0); 41964#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42399#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42338#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 42339#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42401#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 41646#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41647#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 42264#L1499-3 assume !(1 == ~T13_E~0); 41922#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41923#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 42351#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42385#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41559#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41560#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42423#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 41841#L1539-3 assume !(1 == ~E_7~0); 41298#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41299#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 41804#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 40889#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 40890#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 42062#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 42063#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 40783#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 40557#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 40881#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 40790#L1959 assume !(0 == start_simulation_~tmp~3#1); 40792#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 40822#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 40776#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 40611#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 40612#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42417#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42392#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 42393#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 40844#L1940-2 [2022-12-13 18:37:27,176 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:27,176 INFO L85 PathProgramCache]: Analyzing trace with hash 584687431, now seen corresponding path program 1 times [2022-12-13 18:37:27,176 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:27,176 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1215015710] [2022-12-13 18:37:27,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:27,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:27,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:27,219 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:27,220 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:27,220 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1215015710] [2022-12-13 18:37:27,220 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1215015710] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:27,220 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:27,220 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:27,220 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1104220390] [2022-12-13 18:37:27,220 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:27,221 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 18:37:27,221 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:27,221 INFO L85 PathProgramCache]: Analyzing trace with hash -1148495268, now seen corresponding path program 3 times [2022-12-13 18:37:27,221 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:27,221 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [546732029] [2022-12-13 18:37:27,221 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:27,222 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:27,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:27,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:27,278 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:27,278 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [546732029] [2022-12-13 18:37:27,278 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [546732029] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:27,278 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:27,278 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:27,278 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1188670151] [2022-12-13 18:37:27,278 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:27,279 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:37:27,279 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:37:27,279 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 18:37:27,279 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 18:37:27,279 INFO L87 Difference]: Start difference. First operand 2023 states and 2987 transitions. cyclomatic complexity: 965 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:27,313 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:37:27,313 INFO L93 Difference]: Finished difference Result 2023 states and 2986 transitions. [2022-12-13 18:37:27,313 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2986 transitions. [2022-12-13 18:37:27,320 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-12-13 18:37:27,327 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2986 transitions. [2022-12-13 18:37:27,327 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2022-12-13 18:37:27,328 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2022-12-13 18:37:27,328 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2986 transitions. [2022-12-13 18:37:27,331 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:37:27,331 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2023 states and 2986 transitions. [2022-12-13 18:37:27,334 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2986 transitions. [2022-12-13 18:37:27,354 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2022-12-13 18:37:27,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4760257043994067) internal successors, (2986), 2022 states have internal predecessors, (2986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:27,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2986 transitions. [2022-12-13 18:37:27,374 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2023 states and 2986 transitions. [2022-12-13 18:37:27,374 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 18:37:27,375 INFO L428 stractBuchiCegarLoop]: Abstraction has 2023 states and 2986 transitions. [2022-12-13 18:37:27,375 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 18:37:27,375 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2986 transitions. [2022-12-13 18:37:27,378 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-12-13 18:37:27,378 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:37:27,378 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:37:27,379 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:27,379 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:27,379 INFO L748 eck$LassoCheckResult]: Stem: 44889#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 44890#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 45877#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45878#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46607#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 46005#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45468#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45469#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46274#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46275#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46381#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46382#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45223#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45224#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 46416#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 45775#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 45776#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 46320#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 45687#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45688#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 46608#L1291-2 assume !(0 == ~T1_E~0); 46605#L1296-1 assume !(0 == ~T2_E~0); 45839#L1301-1 assume !(0 == ~T3_E~0); 45840#L1306-1 assume !(0 == ~T4_E~0); 46331#L1311-1 assume !(0 == ~T5_E~0); 45063#L1316-1 assume !(0 == ~T6_E~0); 45064#L1321-1 assume !(0 == ~T7_E~0); 45853#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44886#L1331-1 assume !(0 == ~T9_E~0); 44601#L1336-1 assume !(0 == ~T10_E~0); 44602#L1341-1 assume !(0 == ~T11_E~0); 44678#L1346-1 assume !(0 == ~T12_E~0); 44679#L1351-1 assume !(0 == ~T13_E~0); 45003#L1356-1 assume !(0 == ~E_M~0); 45004#L1361-1 assume !(0 == ~E_1~0); 46545#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 45047#L1371-1 assume !(0 == ~E_3~0); 45048#L1376-1 assume !(0 == ~E_4~0); 45905#L1381-1 assume !(0 == ~E_5~0); 45906#L1386-1 assume !(0 == ~E_6~0); 46576#L1391-1 assume !(0 == ~E_7~0); 46596#L1396-1 assume !(0 == ~E_8~0); 45807#L1401-1 assume !(0 == ~E_9~0); 45808#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 46095#L1411-1 assume !(0 == ~E_11~0); 46096#L1416-1 assume !(0 == ~E_12~0); 45725#L1421-1 assume !(0 == ~E_13~0); 45244#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45245#L640 assume !(1 == ~m_pc~0); 45774#L640-2 is_master_triggered_~__retres1~0#1 := 0; 45773#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45733#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45734#L1603 assume !(0 != activate_threads_~tmp~1#1); 45762#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45390#L659 assume 1 == ~t1_pc~0; 45391#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 45498#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46211#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45519#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 45520#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45536#L678 assume 1 == ~t2_pc~0; 46483#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46484#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45088#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45089#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 45632#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45755#L697 assume !(1 == ~t3_pc~0); 45756#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 45886#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46201#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45667#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45668#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46516#L716 assume 1 == ~t4_pc~0; 46504#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45372#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44751#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44752#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 44856#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46167#L735 assume !(1 == ~t5_pc~0); 44823#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 44824#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45271#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46191#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 45833#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45834#L754 assume 1 == ~t6_pc~0; 45584#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45481#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45067#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45068#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 45455#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46265#L773 assume !(1 == ~t7_pc~0); 45007#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 45006#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45868#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 45843#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 45844#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45897#L792 assume 1 == ~t8_pc~0; 46065#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46383#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46384#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45835#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 45758#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45759#L811 assume 1 == ~t9_pc~0; 45968#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46428#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45144#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45145#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 45770#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45771#L830 assume !(1 == ~t10_pc~0); 45490#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 44983#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44984#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 44961#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 44962#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46283#L849 assume 1 == ~t11_pc~0; 46284#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 44802#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44803#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46294#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 46195#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 46196#L868 assume !(1 == ~t12_pc~0); 45616#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 45615#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44693#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 44694#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 45018#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45019#L887 assume 1 == ~t13_pc~0; 46203#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 45661#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 45662#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 46259#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 44733#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44734#L1439 assume !(1 == ~M_E~0); 45827#L1439-2 assume !(1 == ~T1_E~0); 44899#L1444-1 assume !(1 == ~T2_E~0); 44900#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45395#L1454-1 assume !(1 == ~T4_E~0); 45396#L1459-1 assume !(1 == ~T5_E~0); 45960#L1464-1 assume !(1 == ~T6_E~0); 45961#L1469-1 assume !(1 == ~T7_E~0); 46034#L1474-1 assume !(1 == ~T8_E~0); 45726#L1479-1 assume !(1 == ~T9_E~0); 45727#L1484-1 assume !(1 == ~T10_E~0); 45964#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45605#L1494-1 assume !(1 == ~T12_E~0); 45606#L1499-1 assume !(1 == ~T13_E~0); 45792#L1504-1 assume !(1 == ~E_M~0); 45793#L1509-1 assume !(1 == ~E_1~0); 46368#L1514-1 assume !(1 == ~E_2~0); 46067#L1519-1 assume !(1 == ~E_3~0); 46068#L1524-1 assume !(1 == ~E_4~0); 46560#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 46561#L1534-1 assume !(1 == ~E_6~0); 44727#L1539-1 assume !(1 == ~E_7~0); 44728#L1544-1 assume !(1 == ~E_8~0); 45141#L1549-1 assume !(1 == ~E_9~0); 46533#L1554-1 assume !(1 == ~E_10~0); 46530#L1559-1 assume !(1 == ~E_11~0); 46408#L1564-1 assume !(1 == ~E_12~0); 46409#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 46555#L1574-1 assume { :end_inline_reset_delta_events } true; 44897#L1940-2 [2022-12-13 18:37:27,379 INFO L750 eck$LassoCheckResult]: Loop: 44897#L1940-2 assume !false; 44898#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45493#L1266 assume !false; 46207#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 45450#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 45169#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 46367#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 46376#L1079 assume !(0 != eval_~tmp~0#1); 45649#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45308#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 45309#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 46035#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 46036#L1296-3 assume !(0 == ~T2_E~0); 46586#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46541#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45691#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44935#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 44936#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 45037#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45822#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 46073#L1336-3 assume !(0 == ~T10_E~0); 46074#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 45387#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 45366#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 45306#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 45307#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45887#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 44653#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44654#L1376-3 assume !(0 == ~E_4~0); 46388#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46245#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 46246#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 46420#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 46421#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 44998#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 44864#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 44865#L1416-3 assume !(0 == ~E_12~0); 45544#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 45545#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45656#L640-45 assume !(1 == ~m_pc~0); 45657#L640-47 is_master_triggered_~__retres1~0#1 := 0; 45101#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45102#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44649#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 44650#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44741#L659-45 assume 1 == ~t1_pc~0; 44742#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 45184#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46590#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46521#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46176#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46177#L678-45 assume 1 == ~t2_pc~0; 46131#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 45663#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45664#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46113#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46437#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46539#L697-45 assume 1 == ~t3_pc~0; 45926#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 45927#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46606#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46079#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46080#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46114#L716-45 assume 1 == ~t4_pc~0; 45738#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45739#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46394#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45745#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45746#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45405#L735-45 assume 1 == ~t5_pc~0; 45406#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 45958#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46557#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46603#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46559#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46553#L754-45 assume 1 == ~t6_pc~0; 45909#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45910#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45803#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45804#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 45914#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45637#L773-45 assume 1 == ~t7_pc~0; 45638#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45180#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45875#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 45876#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 45645#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45300#L792-45 assume 1 == ~t8_pc~0; 45301#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46323#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46324#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 44762#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 44763#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45250#L811-45 assume 1 == ~t9_pc~0; 45030#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 45032#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46242#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46110#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 45717#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45503#L830-45 assume 1 == ~t10_pc~0; 45504#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 44689#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45826#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 44908#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 44909#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44669#L849-45 assume !(1 == ~t11_pc~0); 44670#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 45119#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44965#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 44655#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 44656#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44903#L868-45 assume 1 == ~t12_pc~0; 44904#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 44849#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44850#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 46277#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 46450#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 46451#L887-45 assume 1 == ~t13_pc~0; 46278#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 44911#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46205#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 46224#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 44879#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44880#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 46200#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44895#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44896#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45051#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46016#L1459-3 assume !(1 == ~T5_E~0); 46017#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46452#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46391#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 46392#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46454#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 45699#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45700#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 46317#L1499-3 assume !(1 == ~T13_E~0); 45975#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45976#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46404#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46438#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 45612#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 45613#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46476#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 45894#L1539-3 assume !(1 == ~E_7~0); 45351#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 45352#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 45857#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 44942#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 44943#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 46115#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 46116#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 44836#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 44610#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 44934#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 44843#L1959 assume !(0 == start_simulation_~tmp~3#1); 44845#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 44875#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 44829#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 44664#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 44665#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46470#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46445#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 46446#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 44897#L1940-2 [2022-12-13 18:37:27,380 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:27,380 INFO L85 PathProgramCache]: Analyzing trace with hash 1907866377, now seen corresponding path program 1 times [2022-12-13 18:37:27,380 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:27,380 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [806545844] [2022-12-13 18:37:27,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:27,380 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:27,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:27,408 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:27,408 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:27,408 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [806545844] [2022-12-13 18:37:27,409 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [806545844] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:27,409 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:27,409 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:27,409 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1605497759] [2022-12-13 18:37:27,409 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:27,409 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 18:37:27,410 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:27,410 INFO L85 PathProgramCache]: Analyzing trace with hash -1148495268, now seen corresponding path program 4 times [2022-12-13 18:37:27,410 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:27,410 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1573781330] [2022-12-13 18:37:27,410 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:27,410 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:27,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:27,451 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:27,451 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:27,451 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1573781330] [2022-12-13 18:37:27,451 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1573781330] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:27,451 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:27,451 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:27,452 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1588988117] [2022-12-13 18:37:27,452 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:27,452 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:37:27,452 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:37:27,452 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 18:37:27,452 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 18:37:27,453 INFO L87 Difference]: Start difference. First operand 2023 states and 2986 transitions. cyclomatic complexity: 964 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:27,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:37:27,478 INFO L93 Difference]: Finished difference Result 2023 states and 2985 transitions. [2022-12-13 18:37:27,478 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2985 transitions. [2022-12-13 18:37:27,482 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-12-13 18:37:27,486 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2985 transitions. [2022-12-13 18:37:27,486 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2022-12-13 18:37:27,487 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2022-12-13 18:37:27,487 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2985 transitions. [2022-12-13 18:37:27,489 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:37:27,489 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2023 states and 2985 transitions. [2022-12-13 18:37:27,491 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2985 transitions. [2022-12-13 18:37:27,506 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2022-12-13 18:37:27,509 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4755313890261987) internal successors, (2985), 2022 states have internal predecessors, (2985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:27,511 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2985 transitions. [2022-12-13 18:37:27,511 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2023 states and 2985 transitions. [2022-12-13 18:37:27,512 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 18:37:27,512 INFO L428 stractBuchiCegarLoop]: Abstraction has 2023 states and 2985 transitions. [2022-12-13 18:37:27,512 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-12-13 18:37:27,512 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2985 transitions. [2022-12-13 18:37:27,516 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-12-13 18:37:27,516 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:37:27,516 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:37:27,517 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:27,517 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:27,518 INFO L748 eck$LassoCheckResult]: Stem: 48942#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 48943#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 49930#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 49931#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50660#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 50058#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49521#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49522#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50327#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50328#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50434#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50435#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49276#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49277#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50469#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49828#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 49829#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 50373#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 49740#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49741#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 50661#L1291-2 assume !(0 == ~T1_E~0); 50658#L1296-1 assume !(0 == ~T2_E~0); 49892#L1301-1 assume !(0 == ~T3_E~0); 49893#L1306-1 assume !(0 == ~T4_E~0); 50384#L1311-1 assume !(0 == ~T5_E~0); 49116#L1316-1 assume !(0 == ~T6_E~0); 49117#L1321-1 assume !(0 == ~T7_E~0); 49906#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 48939#L1331-1 assume !(0 == ~T9_E~0); 48654#L1336-1 assume !(0 == ~T10_E~0); 48655#L1341-1 assume !(0 == ~T11_E~0); 48731#L1346-1 assume !(0 == ~T12_E~0); 48732#L1351-1 assume !(0 == ~T13_E~0); 49056#L1356-1 assume !(0 == ~E_M~0); 49057#L1361-1 assume !(0 == ~E_1~0); 50598#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 49100#L1371-1 assume !(0 == ~E_3~0); 49101#L1376-1 assume !(0 == ~E_4~0); 49958#L1381-1 assume !(0 == ~E_5~0); 49959#L1386-1 assume !(0 == ~E_6~0); 50629#L1391-1 assume !(0 == ~E_7~0); 50649#L1396-1 assume !(0 == ~E_8~0); 49860#L1401-1 assume !(0 == ~E_9~0); 49861#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 50148#L1411-1 assume !(0 == ~E_11~0); 50149#L1416-1 assume !(0 == ~E_12~0); 49778#L1421-1 assume !(0 == ~E_13~0); 49297#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49298#L640 assume !(1 == ~m_pc~0); 49827#L640-2 is_master_triggered_~__retres1~0#1 := 0; 49826#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49786#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49787#L1603 assume !(0 != activate_threads_~tmp~1#1); 49815#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49443#L659 assume 1 == ~t1_pc~0; 49444#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49551#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50264#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49572#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 49573#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49589#L678 assume 1 == ~t2_pc~0; 50536#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50537#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49141#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49142#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 49685#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49808#L697 assume !(1 == ~t3_pc~0); 49809#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 49939#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50254#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49720#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49721#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50569#L716 assume 1 == ~t4_pc~0; 50557#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49425#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48804#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48805#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 48909#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50220#L735 assume !(1 == ~t5_pc~0); 48876#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 48877#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49324#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50244#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 49886#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49887#L754 assume 1 == ~t6_pc~0; 49637#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49534#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49120#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49121#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 49508#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50318#L773 assume !(1 == ~t7_pc~0); 49060#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 49059#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49921#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49896#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 49897#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49950#L792 assume 1 == ~t8_pc~0; 50118#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50436#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50437#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49888#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 49811#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49812#L811 assume 1 == ~t9_pc~0; 50021#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50481#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49197#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49198#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 49823#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49824#L830 assume !(1 == ~t10_pc~0); 49543#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 49036#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49037#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 49014#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49015#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 50336#L849 assume 1 == ~t11_pc~0; 50337#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 48855#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48856#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50347#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 50248#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50249#L868 assume !(1 == ~t12_pc~0); 49669#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 49668#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 48746#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 48747#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 49071#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 49072#L887 assume 1 == ~t13_pc~0; 50256#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 49714#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 49715#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 50312#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 48786#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48787#L1439 assume !(1 == ~M_E~0); 49880#L1439-2 assume !(1 == ~T1_E~0); 48952#L1444-1 assume !(1 == ~T2_E~0); 48953#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49448#L1454-1 assume !(1 == ~T4_E~0); 49449#L1459-1 assume !(1 == ~T5_E~0); 50013#L1464-1 assume !(1 == ~T6_E~0); 50014#L1469-1 assume !(1 == ~T7_E~0); 50087#L1474-1 assume !(1 == ~T8_E~0); 49779#L1479-1 assume !(1 == ~T9_E~0); 49780#L1484-1 assume !(1 == ~T10_E~0); 50017#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 49658#L1494-1 assume !(1 == ~T12_E~0); 49659#L1499-1 assume !(1 == ~T13_E~0); 49845#L1504-1 assume !(1 == ~E_M~0); 49846#L1509-1 assume !(1 == ~E_1~0); 50421#L1514-1 assume !(1 == ~E_2~0); 50120#L1519-1 assume !(1 == ~E_3~0); 50121#L1524-1 assume !(1 == ~E_4~0); 50613#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 50614#L1534-1 assume !(1 == ~E_6~0); 48780#L1539-1 assume !(1 == ~E_7~0); 48781#L1544-1 assume !(1 == ~E_8~0); 49194#L1549-1 assume !(1 == ~E_9~0); 50586#L1554-1 assume !(1 == ~E_10~0); 50583#L1559-1 assume !(1 == ~E_11~0); 50461#L1564-1 assume !(1 == ~E_12~0); 50462#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 50608#L1574-1 assume { :end_inline_reset_delta_events } true; 48950#L1940-2 [2022-12-13 18:37:27,518 INFO L750 eck$LassoCheckResult]: Loop: 48950#L1940-2 assume !false; 48951#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49546#L1266 assume !false; 50260#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 49503#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 49222#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 50420#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 50429#L1079 assume !(0 != eval_~tmp~0#1); 49702#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49361#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49362#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50088#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 50089#L1296-3 assume !(0 == ~T2_E~0); 50639#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50594#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49744#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 48988#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 48989#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49090#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49875#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 50126#L1336-3 assume !(0 == ~T10_E~0); 50127#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 49440#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 49419#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 49359#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 49360#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 49940#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 48706#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 48707#L1376-3 assume !(0 == ~E_4~0); 50441#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50298#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50299#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50473#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50474#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 49051#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 48917#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 48918#L1416-3 assume !(0 == ~E_12~0); 49597#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 49598#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49709#L640-45 assume !(1 == ~m_pc~0); 49710#L640-47 is_master_triggered_~__retres1~0#1 := 0; 49154#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49155#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48702#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 48703#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48794#L659-45 assume 1 == ~t1_pc~0; 48795#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49237#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50643#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50574#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50229#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50230#L678-45 assume 1 == ~t2_pc~0; 50184#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 49716#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49717#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50166#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50490#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50592#L697-45 assume 1 == ~t3_pc~0; 49979#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49980#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50659#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50132#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50133#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50167#L716-45 assume !(1 == ~t4_pc~0); 49793#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 49792#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50447#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49798#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49799#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49458#L735-45 assume 1 == ~t5_pc~0; 49459#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50011#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50610#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50656#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 50612#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50606#L754-45 assume 1 == ~t6_pc~0; 49962#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49963#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49856#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49857#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 49967#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49690#L773-45 assume !(1 == ~t7_pc~0); 49232#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 49233#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49928#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49929#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 49698#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49353#L792-45 assume 1 == ~t8_pc~0; 49354#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50376#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50377#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 48815#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 48816#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49303#L811-45 assume 1 == ~t9_pc~0; 49083#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49085#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50295#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50163#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 49770#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49556#L830-45 assume 1 == ~t10_pc~0; 49557#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 48742#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49879#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 48961#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 48962#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48722#L849-45 assume !(1 == ~t11_pc~0); 48723#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 49172#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49018#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 48708#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 48709#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 48956#L868-45 assume 1 == ~t12_pc~0; 48957#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 48902#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 48903#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 50330#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 50503#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 50504#L887-45 assume !(1 == ~t13_pc~0); 48963#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 48964#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50258#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 50277#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 48932#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48933#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 50253#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 48948#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48949#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49104#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50069#L1459-3 assume !(1 == ~T5_E~0); 50070#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50505#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50444#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50445#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50507#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 49752#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 49753#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 50370#L1499-3 assume !(1 == ~T13_E~0); 50028#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 50029#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50457#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50491#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 49665#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49666#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50529#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 49947#L1539-3 assume !(1 == ~E_7~0); 49404#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49405#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 49910#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 48995#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 48996#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 50168#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 50169#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 48889#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 48663#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 48987#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 48896#L1959 assume !(0 == start_simulation_~tmp~3#1); 48898#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 48928#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 48882#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 48717#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 48718#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50523#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50498#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 50499#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 48950#L1940-2 [2022-12-13 18:37:27,518 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:27,518 INFO L85 PathProgramCache]: Analyzing trace with hash 10886919, now seen corresponding path program 1 times [2022-12-13 18:37:27,518 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:27,518 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1070263756] [2022-12-13 18:37:27,519 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:27,519 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:27,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:27,548 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:27,549 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:27,549 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1070263756] [2022-12-13 18:37:27,549 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1070263756] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:27,549 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:27,549 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:27,549 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [934917360] [2022-12-13 18:37:27,549 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:27,550 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 18:37:27,550 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:27,550 INFO L85 PathProgramCache]: Analyzing trace with hash -1177109601, now seen corresponding path program 1 times [2022-12-13 18:37:27,550 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:27,550 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1173978850] [2022-12-13 18:37:27,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:27,551 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:27,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:27,605 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:27,605 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:27,605 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1173978850] [2022-12-13 18:37:27,606 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1173978850] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:27,606 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:27,606 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:27,606 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [134738626] [2022-12-13 18:37:27,606 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:27,606 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:37:27,606 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:37:27,607 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 18:37:27,607 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 18:37:27,607 INFO L87 Difference]: Start difference. First operand 2023 states and 2985 transitions. cyclomatic complexity: 963 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:27,638 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:37:27,638 INFO L93 Difference]: Finished difference Result 2023 states and 2984 transitions. [2022-12-13 18:37:27,638 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2984 transitions. [2022-12-13 18:37:27,645 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-12-13 18:37:27,649 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2984 transitions. [2022-12-13 18:37:27,649 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2022-12-13 18:37:27,650 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2022-12-13 18:37:27,650 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2984 transitions. [2022-12-13 18:37:27,652 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:37:27,652 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2023 states and 2984 transitions. [2022-12-13 18:37:27,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2984 transitions. [2022-12-13 18:37:27,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2022-12-13 18:37:27,669 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4750370736529905) internal successors, (2984), 2022 states have internal predecessors, (2984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:27,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2984 transitions. [2022-12-13 18:37:27,672 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2023 states and 2984 transitions. [2022-12-13 18:37:27,672 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 18:37:27,672 INFO L428 stractBuchiCegarLoop]: Abstraction has 2023 states and 2984 transitions. [2022-12-13 18:37:27,672 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-12-13 18:37:27,672 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2984 transitions. [2022-12-13 18:37:27,676 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2022-12-13 18:37:27,676 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:37:27,676 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:37:27,677 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:27,677 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:27,677 INFO L748 eck$LassoCheckResult]: Stem: 52995#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 52996#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 53983#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53984#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54713#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 54111#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53574#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53575#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 54380#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 54381#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54487#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54488#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 53329#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 53330#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 54522#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 53881#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 53882#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 54426#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 53793#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53794#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 54714#L1291-2 assume !(0 == ~T1_E~0); 54711#L1296-1 assume !(0 == ~T2_E~0); 53945#L1301-1 assume !(0 == ~T3_E~0); 53946#L1306-1 assume !(0 == ~T4_E~0); 54437#L1311-1 assume !(0 == ~T5_E~0); 53169#L1316-1 assume !(0 == ~T6_E~0); 53170#L1321-1 assume !(0 == ~T7_E~0); 53959#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 52992#L1331-1 assume !(0 == ~T9_E~0); 52707#L1336-1 assume !(0 == ~T10_E~0); 52708#L1341-1 assume !(0 == ~T11_E~0); 52784#L1346-1 assume !(0 == ~T12_E~0); 52785#L1351-1 assume !(0 == ~T13_E~0); 53109#L1356-1 assume !(0 == ~E_M~0); 53110#L1361-1 assume !(0 == ~E_1~0); 54651#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 53153#L1371-1 assume !(0 == ~E_3~0); 53154#L1376-1 assume !(0 == ~E_4~0); 54011#L1381-1 assume !(0 == ~E_5~0); 54012#L1386-1 assume !(0 == ~E_6~0); 54682#L1391-1 assume !(0 == ~E_7~0); 54702#L1396-1 assume !(0 == ~E_8~0); 53913#L1401-1 assume !(0 == ~E_9~0); 53914#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 54201#L1411-1 assume !(0 == ~E_11~0); 54202#L1416-1 assume !(0 == ~E_12~0); 53831#L1421-1 assume !(0 == ~E_13~0); 53350#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53351#L640 assume !(1 == ~m_pc~0); 53880#L640-2 is_master_triggered_~__retres1~0#1 := 0; 53879#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53839#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53840#L1603 assume !(0 != activate_threads_~tmp~1#1); 53868#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53496#L659 assume 1 == ~t1_pc~0; 53497#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53604#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54317#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53625#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 53626#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53642#L678 assume 1 == ~t2_pc~0; 54589#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54590#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53194#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53195#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 53738#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53861#L697 assume !(1 == ~t3_pc~0); 53862#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53992#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54307#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53773#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53774#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54622#L716 assume 1 == ~t4_pc~0; 54610#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53478#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52857#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 52858#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 52962#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54273#L735 assume !(1 == ~t5_pc~0); 52929#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 52930#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53377#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54297#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 53939#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53940#L754 assume 1 == ~t6_pc~0; 53690#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53587#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53173#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53174#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 53561#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54371#L773 assume !(1 == ~t7_pc~0); 53113#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 53112#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53974#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 53949#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 53950#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54003#L792 assume 1 == ~t8_pc~0; 54171#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 54489#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54490#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 53941#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 53864#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53865#L811 assume 1 == ~t9_pc~0; 54074#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54534#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53250#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53251#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 53876#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53877#L830 assume !(1 == ~t10_pc~0); 53596#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 53089#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53090#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 53067#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53068#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54389#L849 assume 1 == ~t11_pc~0; 54390#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 52908#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 52909#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 54400#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 54301#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54302#L868 assume !(1 == ~t12_pc~0); 53722#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 53721#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 52799#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 52800#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 53124#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 53125#L887 assume 1 == ~t13_pc~0; 54309#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 53767#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 53768#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 54365#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 52839#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52840#L1439 assume !(1 == ~M_E~0); 53933#L1439-2 assume !(1 == ~T1_E~0); 53005#L1444-1 assume !(1 == ~T2_E~0); 53006#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53501#L1454-1 assume !(1 == ~T4_E~0); 53502#L1459-1 assume !(1 == ~T5_E~0); 54066#L1464-1 assume !(1 == ~T6_E~0); 54067#L1469-1 assume !(1 == ~T7_E~0); 54140#L1474-1 assume !(1 == ~T8_E~0); 53832#L1479-1 assume !(1 == ~T9_E~0); 53833#L1484-1 assume !(1 == ~T10_E~0); 54070#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 53711#L1494-1 assume !(1 == ~T12_E~0); 53712#L1499-1 assume !(1 == ~T13_E~0); 53898#L1504-1 assume !(1 == ~E_M~0); 53899#L1509-1 assume !(1 == ~E_1~0); 54474#L1514-1 assume !(1 == ~E_2~0); 54173#L1519-1 assume !(1 == ~E_3~0); 54174#L1524-1 assume !(1 == ~E_4~0); 54666#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 54667#L1534-1 assume !(1 == ~E_6~0); 52833#L1539-1 assume !(1 == ~E_7~0); 52834#L1544-1 assume !(1 == ~E_8~0); 53247#L1549-1 assume !(1 == ~E_9~0); 54639#L1554-1 assume !(1 == ~E_10~0); 54636#L1559-1 assume !(1 == ~E_11~0); 54514#L1564-1 assume !(1 == ~E_12~0); 54515#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 54661#L1574-1 assume { :end_inline_reset_delta_events } true; 53003#L1940-2 [2022-12-13 18:37:27,677 INFO L750 eck$LassoCheckResult]: Loop: 53003#L1940-2 assume !false; 53004#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53599#L1266 assume !false; 54313#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 53556#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 53275#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 54473#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 54482#L1079 assume !(0 != eval_~tmp~0#1); 53755#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 53414#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 53415#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 54141#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 54142#L1296-3 assume !(0 == ~T2_E~0); 54692#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54647#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 53797#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53041#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 53042#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53143#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53928#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 54179#L1336-3 assume !(0 == ~T10_E~0); 54180#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 53493#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 53472#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 53412#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 53413#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 53993#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 52759#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 52760#L1376-3 assume !(0 == ~E_4~0); 54494#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54351#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 54352#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 54526#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 54527#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 53104#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 52970#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 52971#L1416-3 assume !(0 == ~E_12~0); 53650#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 53651#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53762#L640-45 assume !(1 == ~m_pc~0); 53763#L640-47 is_master_triggered_~__retres1~0#1 := 0; 53207#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53208#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 52755#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 52756#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52847#L659-45 assume 1 == ~t1_pc~0; 52848#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53290#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54696#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54627#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 54282#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54283#L678-45 assume 1 == ~t2_pc~0; 54237#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 53769#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53770#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54219#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54543#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54645#L697-45 assume 1 == ~t3_pc~0; 54032#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 54033#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54712#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54185#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54186#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54220#L716-45 assume 1 == ~t4_pc~0; 53844#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53845#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54500#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53851#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 53852#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53511#L735-45 assume 1 == ~t5_pc~0; 53512#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 54064#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54663#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54709#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 54665#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54659#L754-45 assume !(1 == ~t6_pc~0); 54017#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 54016#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53909#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53910#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54020#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53743#L773-45 assume 1 == ~t7_pc~0; 53744#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 53286#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53981#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 53982#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 53751#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53406#L792-45 assume !(1 == ~t8_pc~0); 53408#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 54429#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54430#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 52868#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 52869#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53356#L811-45 assume 1 == ~t9_pc~0; 53136#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 53138#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54348#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54216#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 53823#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53609#L830-45 assume 1 == ~t10_pc~0; 53610#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 52795#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53932#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 53014#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53015#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 52775#L849-45 assume !(1 == ~t11_pc~0); 52776#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 53225#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53071#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 52761#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 52762#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53009#L868-45 assume 1 == ~t12_pc~0; 53010#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 52955#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 52956#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 54383#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 54556#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 54557#L887-45 assume 1 == ~t13_pc~0; 54384#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 53017#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 54311#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 54330#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 52985#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52986#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 54306#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 53001#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 53002#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53157#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54122#L1459-3 assume !(1 == ~T5_E~0); 54123#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 54558#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54497#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 54498#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 54560#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 53805#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 53806#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 54423#L1499-3 assume !(1 == ~T13_E~0); 54081#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 54082#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 54510#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 54544#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 53718#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53719#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 54582#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 54000#L1539-3 assume !(1 == ~E_7~0); 53457#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 53458#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 53963#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 53048#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 53049#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 54221#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 54222#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 52942#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 52716#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53040#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 52949#L1959 assume !(0 == start_simulation_~tmp~3#1); 52951#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 52981#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 52935#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 52770#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 52771#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54576#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54551#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 54552#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 53003#L1940-2 [2022-12-13 18:37:27,677 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:27,678 INFO L85 PathProgramCache]: Analyzing trace with hash -327400631, now seen corresponding path program 1 times [2022-12-13 18:37:27,678 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:27,678 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1677340020] [2022-12-13 18:37:27,678 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:27,678 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:27,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:27,723 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:27,723 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:27,724 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1677340020] [2022-12-13 18:37:27,724 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1677340020] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:27,724 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:27,724 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 18:37:27,724 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1594586643] [2022-12-13 18:37:27,724 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:27,724 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 18:37:27,725 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:27,725 INFO L85 PathProgramCache]: Analyzing trace with hash -82523042, now seen corresponding path program 1 times [2022-12-13 18:37:27,725 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:27,725 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1251114857] [2022-12-13 18:37:27,725 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:27,725 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:27,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:27,763 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:27,763 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:27,763 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1251114857] [2022-12-13 18:37:27,764 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1251114857] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:27,764 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:27,764 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:27,764 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1394132916] [2022-12-13 18:37:27,764 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:27,765 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:37:27,765 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:37:27,765 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 18:37:27,765 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 18:37:27,765 INFO L87 Difference]: Start difference. First operand 2023 states and 2984 transitions. cyclomatic complexity: 962 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:27,870 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:37:27,870 INFO L93 Difference]: Finished difference Result 3771 states and 5546 transitions. [2022-12-13 18:37:27,870 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3771 states and 5546 transitions. [2022-12-13 18:37:27,887 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3596 [2022-12-13 18:37:27,900 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3771 states to 3771 states and 5546 transitions. [2022-12-13 18:37:27,900 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3771 [2022-12-13 18:37:27,903 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3771 [2022-12-13 18:37:27,903 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3771 states and 5546 transitions. [2022-12-13 18:37:27,909 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:37:27,909 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3771 states and 5546 transitions. [2022-12-13 18:37:27,915 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3771 states and 5546 transitions. [2022-12-13 18:37:27,982 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3771 to 3771. [2022-12-13 18:37:27,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3771 states, 3771 states have (on average 1.4706974277380005) internal successors, (5546), 3770 states have internal predecessors, (5546), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:27,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3771 states to 3771 states and 5546 transitions. [2022-12-13 18:37:27,997 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3771 states and 5546 transitions. [2022-12-13 18:37:27,998 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 18:37:27,998 INFO L428 stractBuchiCegarLoop]: Abstraction has 3771 states and 5546 transitions. [2022-12-13 18:37:27,998 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-12-13 18:37:27,999 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3771 states and 5546 transitions. [2022-12-13 18:37:28,012 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3596 [2022-12-13 18:37:28,013 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:37:28,013 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:37:28,015 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:28,015 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:28,016 INFO L748 eck$LassoCheckResult]: Stem: 58797#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 58798#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 59796#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 59797#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60607#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 59925#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59378#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59379#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60208#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60209#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 60329#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 60330#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 59131#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 59132#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 60367#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 59692#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 59693#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 60257#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 59603#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 59604#L1291 assume !(0 == ~M_E~0); 60608#L1291-2 assume !(0 == ~T1_E~0); 60603#L1296-1 assume !(0 == ~T2_E~0); 59756#L1301-1 assume !(0 == ~T3_E~0); 59757#L1306-1 assume !(0 == ~T4_E~0); 60269#L1311-1 assume !(0 == ~T5_E~0); 58971#L1316-1 assume !(0 == ~T6_E~0); 58972#L1321-1 assume !(0 == ~T7_E~0); 59770#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 58794#L1331-1 assume !(0 == ~T9_E~0); 58508#L1336-1 assume !(0 == ~T10_E~0); 58509#L1341-1 assume !(0 == ~T11_E~0); 58585#L1346-1 assume !(0 == ~T12_E~0); 58586#L1351-1 assume !(0 == ~T13_E~0); 58911#L1356-1 assume !(0 == ~E_M~0); 58912#L1361-1 assume !(0 == ~E_1~0); 60528#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 58955#L1371-1 assume !(0 == ~E_3~0); 58956#L1376-1 assume !(0 == ~E_4~0); 59824#L1381-1 assume !(0 == ~E_5~0); 59825#L1386-1 assume !(0 == ~E_6~0); 60571#L1391-1 assume !(0 == ~E_7~0); 60593#L1396-1 assume !(0 == ~E_8~0); 59724#L1401-1 assume !(0 == ~E_9~0); 59725#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 60016#L1411-1 assume !(0 == ~E_11~0); 60017#L1416-1 assume !(0 == ~E_12~0); 59642#L1421-1 assume !(0 == ~E_13~0); 59154#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59155#L640 assume !(1 == ~m_pc~0); 59691#L640-2 is_master_triggered_~__retres1~0#1 := 0; 59690#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59650#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59651#L1603 assume !(0 != activate_threads_~tmp~1#1); 59679#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59300#L659 assume 1 == ~t1_pc~0; 59301#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59411#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60137#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59433#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 59434#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59450#L678 assume 1 == ~t2_pc~0; 60441#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 60442#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58996#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 58997#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 59546#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59672#L697 assume !(1 == ~t3_pc~0); 59673#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 59805#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60124#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59583#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59584#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60489#L716 assume 1 == ~t4_pc~0; 60469#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 59284#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58660#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 58661#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 58763#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60090#L735 assume !(1 == ~t5_pc~0); 58730#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 58731#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 59179#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 60114#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 59750#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59751#L754 assume 1 == ~t6_pc~0; 59498#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 59392#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58975#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 58976#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 59365#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60197#L773 assume !(1 == ~t7_pc~0); 58915#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 58914#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 59785#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 59760#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 59761#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 59816#L792 assume 1 == ~t8_pc~0; 59986#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 60331#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 60332#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 59752#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 59675#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59676#L811 assume 1 == ~t9_pc~0; 59889#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 60379#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 59052#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 59053#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 59687#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 59688#L830 assume !(1 == ~t10_pc~0); 59403#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 58891#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 58892#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 58869#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 58870#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 60217#L849 assume 1 == ~t11_pc~0; 60218#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 58709#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 58710#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 60230#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 60120#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 60121#L868 assume !(1 == ~t12_pc~0); 59530#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 59529#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58600#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 58601#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 58926#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 58927#L887 assume 1 == ~t13_pc~0; 60127#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 59577#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 59578#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 60190#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 58640#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58641#L1439 assume !(1 == ~M_E~0); 59746#L1439-2 assume !(1 == ~T1_E~0); 58807#L1444-1 assume !(1 == ~T2_E~0); 58808#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 59306#L1454-1 assume !(1 == ~T4_E~0); 59307#L1459-1 assume !(1 == ~T5_E~0); 59881#L1464-1 assume !(1 == ~T6_E~0); 59882#L1469-1 assume !(1 == ~T7_E~0); 59954#L1474-1 assume !(1 == ~T8_E~0); 59643#L1479-1 assume !(1 == ~T9_E~0); 59644#L1484-1 assume !(1 == ~T10_E~0); 59884#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59519#L1494-1 assume !(1 == ~T12_E~0); 59520#L1499-1 assume !(1 == ~T13_E~0); 59709#L1504-1 assume !(1 == ~E_M~0); 59710#L1509-1 assume !(1 == ~E_1~0); 60311#L1514-1 assume !(1 == ~E_2~0); 59988#L1519-1 assume !(1 == ~E_3~0); 59989#L1524-1 assume !(1 == ~E_4~0); 60551#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 60552#L1534-1 assume !(1 == ~E_6~0); 58634#L1539-1 assume !(1 == ~E_7~0); 58635#L1544-1 assume !(1 == ~E_8~0); 59049#L1549-1 assume !(1 == ~E_9~0); 60515#L1554-1 assume !(1 == ~E_10~0); 60509#L1559-1 assume !(1 == ~E_11~0); 60358#L1564-1 assume !(1 == ~E_12~0); 60359#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 60541#L1574-1 assume { :end_inline_reset_delta_events } true; 60578#L1940-2 [2022-12-13 18:37:28,016 INFO L750 eck$LassoCheckResult]: Loop: 60578#L1940-2 assume !false; 60499#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 59406#L1266 assume !false; 60612#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 59360#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 59078#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 60323#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 60324#L1079 assume !(0 != eval_~tmp~0#1); 59564#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59216#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 59217#L1291-3 assume !(0 == ~M_E~0); 59955#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 59956#L1296-3 assume !(0 == ~T2_E~0); 60582#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 60583#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 59607#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 59608#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 60711#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 60710#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 60505#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 59993#L1336-3 assume !(0 == ~T10_E~0); 59994#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 60708#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 60707#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 60706#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 60705#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 60704#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 60703#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 60336#L1376-3 assume !(0 == ~E_4~0); 60337#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 60174#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 60175#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 60371#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 60372#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 58908#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 58771#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 58772#L1416-3 assume !(0 == ~E_12~0); 59458#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 59459#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60697#L640-45 assume 1 == ~m_pc~0; 60227#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 59009#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59010#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 58556#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 58557#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 58645#L659-45 assume 1 == ~t1_pc~0; 58646#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59090#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60587#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 60609#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 60687#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60480#L678-45 assume 1 == ~t2_pc~0; 60053#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 59579#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59580#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60034#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 60549#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60550#L697-45 assume 1 == ~t3_pc~0; 60681#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 60680#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60679#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 60678#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 60677#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60676#L716-45 assume 1 == ~t4_pc~0; 59655#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 59656#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 60631#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 60674#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 60464#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59315#L735-45 assume 1 == ~t5_pc~0; 59316#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 59878#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60670#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 60669#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 60547#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 60548#L754-45 assume 1 == ~t6_pc~0; 59828#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 59829#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59720#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59721#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 59833#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 59551#L773-45 assume !(1 == ~t7_pc~0); 59552#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 60663#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 60662#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 60408#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 59560#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 59208#L792-45 assume 1 == ~t8_pc~0; 59209#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 60261#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 60262#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 60659#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 60658#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 60657#L811-45 assume 1 == ~t9_pc~0; 60656#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 60188#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 60189#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 60654#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 60653#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 60652#L830-45 assume !(1 == ~t10_pc~0); 58595#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 58596#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 59743#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 60650#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 60396#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 58576#L849-45 assume !(1 == ~t11_pc~0); 58577#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 60648#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 60647#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 60646#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 60645#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 60644#L868-45 assume 1 == ~t12_pc~0; 60642#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 60641#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 60210#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 60211#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 60618#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 60639#L887-45 assume !(1 == ~t13_pc~0); 60637#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 60129#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 60130#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 60636#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 60635#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60142#L1439-3 assume !(1 == ~M_E~0); 60143#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 62171#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 62170#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 62169#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 62168#L1459-3 assume !(1 == ~T5_E~0); 62167#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 62166#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 62165#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 62164#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 62163#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 62162#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 62161#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 62160#L1499-3 assume !(1 == ~T13_E~0); 62159#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 62158#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 62157#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 62156#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 62155#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 62154#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 62153#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 62152#L1539-3 assume !(1 == ~E_7~0); 62151#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 62150#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 62149#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 62148#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 62147#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 62146#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 62145#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 62143#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 62130#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 62129#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 62128#L1959 assume !(0 == start_simulation_~tmp~3#1); 58782#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 58783#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 60873#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 60872#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 60871#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 60870#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 60869#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 60868#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 60578#L1940-2 [2022-12-13 18:37:28,017 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:28,017 INFO L85 PathProgramCache]: Analyzing trace with hash -867830137, now seen corresponding path program 1 times [2022-12-13 18:37:28,017 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:28,017 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [507818488] [2022-12-13 18:37:28,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:28,018 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:28,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:28,107 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:28,107 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:28,107 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [507818488] [2022-12-13 18:37:28,107 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [507818488] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:28,107 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:28,107 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:28,107 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [15360402] [2022-12-13 18:37:28,108 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:28,108 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 18:37:28,108 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:28,109 INFO L85 PathProgramCache]: Analyzing trace with hash 1822360734, now seen corresponding path program 1 times [2022-12-13 18:37:28,109 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:28,109 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1414326645] [2022-12-13 18:37:28,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:28,109 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:28,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:28,170 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:28,170 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:28,170 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1414326645] [2022-12-13 18:37:28,170 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1414326645] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:28,170 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:28,170 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:28,170 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [774275066] [2022-12-13 18:37:28,170 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:28,171 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:37:28,171 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:37:28,171 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 18:37:28,171 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 18:37:28,171 INFO L87 Difference]: Start difference. First operand 3771 states and 5546 transitions. cyclomatic complexity: 1776 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:28,303 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:37:28,303 INFO L93 Difference]: Finished difference Result 5511 states and 8090 transitions. [2022-12-13 18:37:28,303 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5511 states and 8090 transitions. [2022-12-13 18:37:28,337 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5316 [2022-12-13 18:37:28,350 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5511 states to 5511 states and 8090 transitions. [2022-12-13 18:37:28,351 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5511 [2022-12-13 18:37:28,354 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5511 [2022-12-13 18:37:28,354 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5511 states and 8090 transitions. [2022-12-13 18:37:28,360 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:37:28,360 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5511 states and 8090 transitions. [2022-12-13 18:37:28,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5511 states and 8090 transitions. [2022-12-13 18:37:28,415 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5511 to 3771. [2022-12-13 18:37:28,419 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3771 states, 3771 states have (on average 1.469901882789711) internal successors, (5543), 3770 states have internal predecessors, (5543), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:28,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3771 states to 3771 states and 5543 transitions. [2022-12-13 18:37:28,424 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3771 states and 5543 transitions. [2022-12-13 18:37:28,424 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 18:37:28,425 INFO L428 stractBuchiCegarLoop]: Abstraction has 3771 states and 5543 transitions. [2022-12-13 18:37:28,425 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-12-13 18:37:28,425 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3771 states and 5543 transitions. [2022-12-13 18:37:28,433 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3596 [2022-12-13 18:37:28,433 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:37:28,433 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:37:28,434 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:28,434 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:28,434 INFO L748 eck$LassoCheckResult]: Stem: 68088#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 68089#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 69078#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 69079#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 69807#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 69205#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68667#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68668#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 69475#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 69476#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 69581#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 69582#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 68425#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 68426#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 69616#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 68975#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 68976#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 69520#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 68888#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68889#L1291 assume !(0 == ~M_E~0); 69808#L1291-2 assume !(0 == ~T1_E~0); 69805#L1296-1 assume !(0 == ~T2_E~0); 69039#L1301-1 assume !(0 == ~T3_E~0); 69040#L1306-1 assume !(0 == ~T4_E~0); 69531#L1311-1 assume !(0 == ~T5_E~0); 68262#L1316-1 assume !(0 == ~T6_E~0); 68263#L1321-1 assume !(0 == ~T7_E~0); 69053#L1326-1 assume !(0 == ~T8_E~0); 68085#L1331-1 assume !(0 == ~T9_E~0); 67800#L1336-1 assume !(0 == ~T10_E~0); 67801#L1341-1 assume !(0 == ~T11_E~0); 67877#L1346-1 assume !(0 == ~T12_E~0); 67878#L1351-1 assume !(0 == ~T13_E~0); 68202#L1356-1 assume !(0 == ~E_M~0); 68203#L1361-1 assume !(0 == ~E_1~0); 69745#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 68246#L1371-1 assume !(0 == ~E_3~0); 68247#L1376-1 assume !(0 == ~E_4~0); 69105#L1381-1 assume !(0 == ~E_5~0); 69106#L1386-1 assume !(0 == ~E_6~0); 69776#L1391-1 assume !(0 == ~E_7~0); 69796#L1396-1 assume !(0 == ~E_8~0); 69007#L1401-1 assume !(0 == ~E_9~0); 69008#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 69295#L1411-1 assume !(0 == ~E_11~0); 69296#L1416-1 assume !(0 == ~E_12~0); 68925#L1421-1 assume !(0 == ~E_13~0); 68447#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68448#L640 assume !(1 == ~m_pc~0); 68974#L640-2 is_master_triggered_~__retres1~0#1 := 0; 68973#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68933#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 68934#L1603 assume !(0 != activate_threads_~tmp~1#1); 68962#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68589#L659 assume 1 == ~t1_pc~0; 68590#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 68698#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69411#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 68719#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 68720#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68736#L678 assume 1 == ~t2_pc~0; 69683#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 69684#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68287#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 68288#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 68832#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68957#L697 assume !(1 == ~t3_pc~0); 68958#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 69086#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69401#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 68867#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 68868#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69716#L716 assume 1 == ~t4_pc~0; 69704#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 68573#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 67952#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 67953#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 68055#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69368#L735 assume !(1 == ~t5_pc~0); 68022#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 68023#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68470#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 69391#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 69033#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69034#L754 assume 1 == ~t6_pc~0; 68786#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 68681#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 68266#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 68267#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 68654#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 69466#L773 assume !(1 == ~t7_pc~0); 68206#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 68205#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 69068#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 69043#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 69044#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 69097#L792 assume 1 == ~t8_pc~0; 69266#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 69583#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 69584#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 69037#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 68960#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 68961#L811 assume 1 == ~t9_pc~0; 69169#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 69628#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 68343#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 68344#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 68970#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 68971#L830 assume !(1 == ~t10_pc~0); 68693#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 68182#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 68183#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 68160#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 68161#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69483#L849 assume 1 == ~t11_pc~0; 69484#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 68001#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 68002#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 69494#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 69397#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 69398#L868 assume !(1 == ~t12_pc~0); 68816#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 68815#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 67892#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 67893#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 68217#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 68218#L887 assume 1 == ~t13_pc~0; 69403#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 68861#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 68862#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 69459#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 67932#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 67933#L1439 assume !(1 == ~M_E~0); 69029#L1439-2 assume !(1 == ~T1_E~0); 68098#L1444-1 assume !(1 == ~T2_E~0); 68099#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 68595#L1454-1 assume !(1 == ~T4_E~0); 68596#L1459-1 assume !(1 == ~T5_E~0); 69161#L1464-1 assume !(1 == ~T6_E~0); 69162#L1469-1 assume !(1 == ~T7_E~0); 69237#L1474-1 assume !(1 == ~T8_E~0); 68926#L1479-1 assume !(1 == ~T9_E~0); 68927#L1484-1 assume !(1 == ~T10_E~0); 69164#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 68807#L1494-1 assume !(1 == ~T12_E~0); 68808#L1499-1 assume !(1 == ~T13_E~0); 68992#L1504-1 assume !(1 == ~E_M~0); 68993#L1509-1 assume !(1 == ~E_1~0); 69568#L1514-1 assume !(1 == ~E_2~0); 69268#L1519-1 assume !(1 == ~E_3~0); 69269#L1524-1 assume !(1 == ~E_4~0); 69760#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 69761#L1534-1 assume !(1 == ~E_6~0); 67926#L1539-1 assume !(1 == ~E_7~0); 67927#L1544-1 assume !(1 == ~E_8~0); 68342#L1549-1 assume !(1 == ~E_9~0); 69737#L1554-1 assume !(1 == ~E_10~0); 69731#L1559-1 assume !(1 == ~E_11~0); 69608#L1564-1 assume !(1 == ~E_12~0); 69609#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 69755#L1574-1 assume { :end_inline_reset_delta_events } true; 68096#L1940-2 [2022-12-13 18:37:28,434 INFO L750 eck$LassoCheckResult]: Loop: 68096#L1940-2 assume !false; 68097#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 68691#L1266 assume !false; 69407#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68649#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68369#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 69567#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 69576#L1079 assume !(0 != eval_~tmp~0#1); 68849#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 68507#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 68508#L1291-3 assume !(0 == ~M_E~0); 69234#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 69235#L1296-3 assume !(0 == ~T2_E~0); 69786#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 69741#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 68891#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 68134#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 68135#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 68236#L1326-3 assume !(0 == ~T8_E~0); 69022#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 69273#L1336-3 assume !(0 == ~T10_E~0); 69274#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 68586#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 68565#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 68505#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 68506#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 69087#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 67852#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 67853#L1376-3 assume !(0 == ~E_4~0); 69588#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 69445#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 69446#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 69620#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 69621#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 68197#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 68063#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 68064#L1416-3 assume !(0 == ~E_12~0); 68744#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 68745#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68856#L640-45 assume !(1 == ~m_pc~0); 68857#L640-47 is_master_triggered_~__retres1~0#1 := 0; 68300#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68301#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 67848#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 67849#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67940#L659-45 assume 1 == ~t1_pc~0; 67941#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 68386#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69790#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 69721#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 69376#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69377#L678-45 assume 1 == ~t2_pc~0; 69331#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 68863#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68864#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 69313#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 69637#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69739#L697-45 assume 1 == ~t3_pc~0; 69126#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 69127#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69806#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 69279#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 69280#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69314#L716-45 assume 1 == ~t4_pc~0; 68938#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 68939#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69594#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 68945#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 68946#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 68604#L735-45 assume 1 == ~t5_pc~0; 68605#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 69158#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 69757#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 69803#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 69759#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69753#L754-45 assume 1 == ~t6_pc~0; 69109#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 69110#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 69003#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 69004#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 69114#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 68838#L773-45 assume 1 == ~t7_pc~0; 68839#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 68380#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 69075#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 69076#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 68845#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 68499#L792-45 assume !(1 == ~t8_pc~0); 68501#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 69523#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 69524#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 67961#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 67962#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 68449#L811-45 assume 1 == ~t9_pc~0; 68231#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 68233#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 69442#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 69310#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 68917#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 68702#L830-45 assume 1 == ~t10_pc~0; 68703#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 67888#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 69026#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 68107#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 68108#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 67865#L849-45 assume 1 == ~t11_pc~0; 67867#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 68318#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 68162#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 67854#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 67855#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 68102#L868-45 assume 1 == ~t12_pc~0; 68103#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 68048#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 68049#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 69477#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 69650#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 69651#L887-45 assume 1 == ~t13_pc~0; 69478#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 68110#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 69405#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 69424#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 68078#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68079#L1439-3 assume !(1 == ~M_E~0); 69400#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 68094#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 68095#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 68250#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69216#L1459-3 assume !(1 == ~T5_E~0); 69217#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 69652#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 69591#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 69592#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 69654#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 68896#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 68897#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 69515#L1499-3 assume !(1 == ~T13_E~0); 69175#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 69176#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 69604#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 69638#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 68812#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 68813#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 69676#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 69094#L1539-3 assume !(1 == ~E_7~0); 68550#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 68551#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 69056#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 68141#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 68142#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 69315#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 69316#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68035#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 67809#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68130#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 68042#L1959 assume !(0 == start_simulation_~tmp~3#1); 68044#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68072#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68028#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 67863#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 67864#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 69669#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 69644#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 69645#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 68096#L1940-2 [2022-12-13 18:37:28,435 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:28,435 INFO L85 PathProgramCache]: Analyzing trace with hash 1809696709, now seen corresponding path program 1 times [2022-12-13 18:37:28,435 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:28,435 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1820739600] [2022-12-13 18:37:28,435 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:28,435 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:28,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:28,486 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:28,486 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:28,486 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1820739600] [2022-12-13 18:37:28,486 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1820739600] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:28,486 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:28,486 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 18:37:28,486 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [101518976] [2022-12-13 18:37:28,486 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:28,486 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 18:37:28,487 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:28,487 INFO L85 PathProgramCache]: Analyzing trace with hash 824687770, now seen corresponding path program 1 times [2022-12-13 18:37:28,487 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:28,487 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [754083728] [2022-12-13 18:37:28,487 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:28,487 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:28,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:28,528 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:28,528 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:28,528 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [754083728] [2022-12-13 18:37:28,528 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [754083728] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:28,528 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:28,528 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:28,528 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1560410744] [2022-12-13 18:37:28,528 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:28,529 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:37:28,529 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:37:28,529 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 18:37:28,529 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 18:37:28,529 INFO L87 Difference]: Start difference. First operand 3771 states and 5543 transitions. cyclomatic complexity: 1773 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:28,584 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:37:28,584 INFO L93 Difference]: Finished difference Result 3771 states and 5505 transitions. [2022-12-13 18:37:28,585 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3771 states and 5505 transitions. [2022-12-13 18:37:28,594 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3596 [2022-12-13 18:37:28,602 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3771 states to 3771 states and 5505 transitions. [2022-12-13 18:37:28,602 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3771 [2022-12-13 18:37:28,604 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3771 [2022-12-13 18:37:28,605 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3771 states and 5505 transitions. [2022-12-13 18:37:28,607 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:37:28,608 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3771 states and 5505 transitions. [2022-12-13 18:37:28,611 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3771 states and 5505 transitions. [2022-12-13 18:37:28,639 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3771 to 3771. [2022-12-13 18:37:28,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3771 states, 3771 states have (on average 1.4598249801113763) internal successors, (5505), 3770 states have internal predecessors, (5505), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:28,648 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3771 states to 3771 states and 5505 transitions. [2022-12-13 18:37:28,648 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3771 states and 5505 transitions. [2022-12-13 18:37:28,649 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 18:37:28,649 INFO L428 stractBuchiCegarLoop]: Abstraction has 3771 states and 5505 transitions. [2022-12-13 18:37:28,649 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-12-13 18:37:28,649 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3771 states and 5505 transitions. [2022-12-13 18:37:28,660 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3596 [2022-12-13 18:37:28,660 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:37:28,660 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:37:28,662 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:28,662 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:28,663 INFO L748 eck$LassoCheckResult]: Stem: 75635#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 75636#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 76630#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 76631#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77391#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 76758#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76215#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76216#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 77031#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 77032#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 77141#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 77142#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 75972#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 75973#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 77180#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 76523#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 76524#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 77078#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 76437#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76438#L1291 assume !(0 == ~M_E~0); 77392#L1291-2 assume !(0 == ~T1_E~0); 77389#L1296-1 assume !(0 == ~T2_E~0); 76588#L1301-1 assume !(0 == ~T3_E~0); 76589#L1306-1 assume !(0 == ~T4_E~0); 77089#L1311-1 assume !(0 == ~T5_E~0); 75809#L1316-1 assume !(0 == ~T6_E~0); 75810#L1321-1 assume !(0 == ~T7_E~0); 76602#L1326-1 assume !(0 == ~T8_E~0); 75632#L1331-1 assume !(0 == ~T9_E~0); 75349#L1336-1 assume !(0 == ~T10_E~0); 75350#L1341-1 assume !(0 == ~T11_E~0); 75425#L1346-1 assume !(0 == ~T12_E~0); 75426#L1351-1 assume !(0 == ~T13_E~0); 75749#L1356-1 assume !(0 == ~E_M~0); 75750#L1361-1 assume !(0 == ~E_1~0); 77317#L1366-1 assume !(0 == ~E_2~0); 75793#L1371-1 assume !(0 == ~E_3~0); 75794#L1376-1 assume !(0 == ~E_4~0); 76657#L1381-1 assume !(0 == ~E_5~0); 76658#L1386-1 assume !(0 == ~E_6~0); 77354#L1391-1 assume !(0 == ~E_7~0); 77376#L1396-1 assume !(0 == ~E_8~0); 76555#L1401-1 assume !(0 == ~E_9~0); 76556#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 76849#L1411-1 assume !(0 == ~E_11~0); 76850#L1416-1 assume !(0 == ~E_12~0); 76474#L1421-1 assume !(0 == ~E_13~0); 75992#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75993#L640 assume !(1 == ~m_pc~0); 76522#L640-2 is_master_triggered_~__retres1~0#1 := 0; 76521#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76482#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 76483#L1603 assume !(0 != activate_threads_~tmp~1#1); 76510#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76137#L659 assume 1 == ~t1_pc~0; 76138#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 76246#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76966#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 76267#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 76268#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76284#L678 assume !(1 == ~t2_pc~0); 77253#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 77351#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75834#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 75835#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 76381#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76505#L697 assume !(1 == ~t3_pc~0); 76506#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 76638#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76956#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 76416#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 76417#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77285#L716 assume 1 == ~t4_pc~0; 77273#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 76121#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75500#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 75501#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 75602#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76923#L735 assume !(1 == ~t5_pc~0); 75570#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 75571#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76017#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 76946#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 76581#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76582#L754 assume 1 == ~t6_pc~0; 76334#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 76229#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 75813#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 75814#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 76202#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 77022#L773 assume !(1 == ~t7_pc~0); 75753#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 75752#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 76620#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 76592#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 76593#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 76649#L792 assume 1 == ~t8_pc~0; 76820#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 77143#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 77144#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 76585#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 76508#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 76509#L811 assume 1 == ~t9_pc~0; 76721#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 77192#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 75890#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 75891#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 76518#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 76519#L830 assume !(1 == ~t10_pc~0); 76241#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 75729#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 75730#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 75707#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 75708#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77039#L849 assume 1 == ~t11_pc~0; 77040#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 75549#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 75550#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 77051#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 76952#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 76953#L868 assume !(1 == ~t12_pc~0); 76365#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 76364#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 75440#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 75441#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 75764#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 75765#L887 assume 1 == ~t13_pc~0; 76958#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 76410#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 76411#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 77015#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 75480#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 75481#L1439 assume !(1 == ~M_E~0); 76577#L1439-2 assume !(1 == ~T1_E~0); 75645#L1444-1 assume !(1 == ~T2_E~0); 75646#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 76143#L1454-1 assume !(1 == ~T4_E~0); 76144#L1459-1 assume !(1 == ~T5_E~0); 76713#L1464-1 assume !(1 == ~T6_E~0); 76714#L1469-1 assume !(1 == ~T7_E~0); 76788#L1474-1 assume !(1 == ~T8_E~0); 76475#L1479-1 assume !(1 == ~T9_E~0); 76476#L1484-1 assume !(1 == ~T10_E~0); 76716#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 76356#L1494-1 assume !(1 == ~T12_E~0); 76357#L1499-1 assume !(1 == ~T13_E~0); 76540#L1504-1 assume !(1 == ~E_M~0); 76541#L1509-1 assume !(1 == ~E_1~0); 77127#L1514-1 assume !(1 == ~E_2~0); 76822#L1519-1 assume !(1 == ~E_3~0); 76823#L1524-1 assume !(1 == ~E_4~0); 77336#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 77337#L1534-1 assume !(1 == ~E_6~0); 75474#L1539-1 assume !(1 == ~E_7~0); 75475#L1544-1 assume !(1 == ~E_8~0); 75889#L1549-1 assume !(1 == ~E_9~0); 77307#L1554-1 assume !(1 == ~E_10~0); 77300#L1559-1 assume !(1 == ~E_11~0); 77171#L1564-1 assume !(1 == ~E_12~0); 77172#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 77329#L1574-1 assume { :end_inline_reset_delta_events } true; 77362#L1940-2 [2022-12-13 18:37:28,663 INFO L750 eck$LassoCheckResult]: Loop: 77362#L1940-2 assume !false; 77440#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 77436#L1266 assume !false; 77397#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 76197#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 75915#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 77126#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 77136#L1079 assume !(0 != eval_~tmp~0#1); 76398#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 76054#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 76055#L1291-3 assume !(0 == ~M_E~0); 76905#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 78903#L1296-3 assume !(0 == ~T2_E~0); 78901#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 78899#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 78896#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 78894#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 78892#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 78891#L1326-3 assume !(0 == ~T8_E~0); 78890#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 78889#L1336-3 assume !(0 == ~T10_E~0); 78888#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 78886#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 78884#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 78881#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 78879#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 78877#L1366-3 assume !(0 == ~E_2~0); 78875#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 78873#L1376-3 assume !(0 == ~E_4~0); 78871#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 78868#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 78866#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 78864#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 78862#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 78860#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 78858#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 78855#L1416-3 assume !(0 == ~E_12~0); 78853#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 78851#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 78849#L640-45 assume !(1 == ~m_pc~0); 78847#L640-47 is_master_triggered_~__retres1~0#1 := 0; 78844#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 78841#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 78840#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 78839#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 78838#L659-45 assume !(1 == ~t1_pc~0); 78837#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 78835#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 78834#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 78833#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 78832#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 78831#L678-45 assume !(1 == ~t2_pc~0); 78829#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 78828#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 78827#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 78826#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 78825#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 78824#L697-45 assume !(1 == ~t3_pc~0); 78823#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 78821#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78820#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 78819#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 78818#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 78817#L716-45 assume 1 == ~t4_pc~0; 78816#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 78814#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78813#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 78812#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 78811#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 78810#L735-45 assume !(1 == ~t5_pc~0); 78809#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 78807#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 78806#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 78805#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 78804#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 78803#L754-45 assume !(1 == ~t6_pc~0); 78801#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 78800#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 78799#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 78798#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 78797#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 78796#L773-45 assume !(1 == ~t7_pc~0); 78795#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 78793#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 78792#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 78791#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 78790#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 78789#L792-45 assume 1 == ~t8_pc~0; 78787#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 78786#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 78785#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 78784#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 78783#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 78782#L811-45 assume 1 == ~t9_pc~0; 78781#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 78779#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 78778#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 78777#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 78776#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 78775#L830-45 assume 1 == ~t10_pc~0; 78773#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 78772#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 78771#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 78770#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 78769#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 78768#L849-45 assume 1 == ~t11_pc~0; 78767#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 78765#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 78764#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 78763#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 75706#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 75649#L868-45 assume !(1 == ~t12_pc~0); 75651#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 75595#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 75596#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 77033#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 77214#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 77215#L887-45 assume !(1 == ~t13_pc~0); 75656#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 75657#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 76960#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 76980#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 75625#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 75626#L1439-3 assume !(1 == ~M_E~0); 76971#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 78545#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 78543#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 78541#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 78539#L1459-3 assume !(1 == ~T5_E~0); 78358#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 78357#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 78356#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 78355#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 78354#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 78353#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 78352#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 78351#L1499-3 assume !(1 == ~T13_E~0); 78350#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 78349#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 78348#L1514-3 assume !(1 == ~E_2~0); 78347#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 78346#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 78345#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 78344#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 78343#L1539-3 assume !(1 == ~E_7~0); 78342#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 78341#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 78340#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 78339#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 78338#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 78337#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 78336#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 78334#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 78320#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 78317#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 78315#L1959 assume !(0 == start_simulation_~tmp~3#1); 77766#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 77519#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 77505#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 77503#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 77501#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 77473#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 77461#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 77451#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 77362#L1940-2 [2022-12-13 18:37:28,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:28,663 INFO L85 PathProgramCache]: Analyzing trace with hash 350046660, now seen corresponding path program 1 times [2022-12-13 18:37:28,664 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:28,664 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [974386332] [2022-12-13 18:37:28,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:28,664 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:28,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:28,733 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:28,733 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:28,733 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [974386332] [2022-12-13 18:37:28,733 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [974386332] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:28,733 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:28,733 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:28,733 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [711139103] [2022-12-13 18:37:28,733 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:28,734 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 18:37:28,734 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:28,734 INFO L85 PathProgramCache]: Analyzing trace with hash 848099809, now seen corresponding path program 1 times [2022-12-13 18:37:28,734 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:28,735 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1320106611] [2022-12-13 18:37:28,735 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:28,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:28,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:28,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:28,774 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:28,775 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1320106611] [2022-12-13 18:37:28,775 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1320106611] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:28,775 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:28,775 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:28,775 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1117871877] [2022-12-13 18:37:28,775 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:28,775 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:37:28,775 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:37:28,776 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 18:37:28,776 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 18:37:28,776 INFO L87 Difference]: Start difference. First operand 3771 states and 5505 transitions. cyclomatic complexity: 1735 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:28,909 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:37:28,909 INFO L93 Difference]: Finished difference Result 5396 states and 7860 transitions. [2022-12-13 18:37:28,909 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5396 states and 7860 transitions. [2022-12-13 18:37:28,923 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5216 [2022-12-13 18:37:28,933 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5396 states to 5396 states and 7860 transitions. [2022-12-13 18:37:28,933 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5396 [2022-12-13 18:37:28,937 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5396 [2022-12-13 18:37:28,937 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5396 states and 7860 transitions. [2022-12-13 18:37:28,941 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:37:28,941 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5396 states and 7860 transitions. [2022-12-13 18:37:28,946 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5396 states and 7860 transitions. [2022-12-13 18:37:28,980 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5396 to 3771. [2022-12-13 18:37:28,984 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3771 states, 3771 states have (on average 1.4590294351630868) internal successors, (5502), 3770 states have internal predecessors, (5502), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:28,989 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3771 states to 3771 states and 5502 transitions. [2022-12-13 18:37:28,989 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3771 states and 5502 transitions. [2022-12-13 18:37:28,990 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 18:37:28,990 INFO L428 stractBuchiCegarLoop]: Abstraction has 3771 states and 5502 transitions. [2022-12-13 18:37:28,990 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-12-13 18:37:28,990 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3771 states and 5502 transitions. [2022-12-13 18:37:28,999 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3596 [2022-12-13 18:37:28,999 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:37:28,999 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:37:29,000 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:29,001 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:29,001 INFO L748 eck$LassoCheckResult]: Stem: 84812#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 84813#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 85804#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 85805#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 86545#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 85931#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 85392#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 85393#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 86203#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 86204#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 86315#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 86316#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 85148#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 85149#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 86350#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 85700#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 85701#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 86249#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 85614#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 85615#L1291 assume !(0 == ~M_E~0); 86546#L1291-2 assume !(0 == ~T1_E~0); 86543#L1296-1 assume !(0 == ~T2_E~0); 85765#L1301-1 assume !(0 == ~T3_E~0); 85766#L1306-1 assume !(0 == ~T4_E~0); 86260#L1311-1 assume !(0 == ~T5_E~0); 84985#L1316-1 assume !(0 == ~T6_E~0); 84986#L1321-1 assume !(0 == ~T7_E~0); 85779#L1326-1 assume !(0 == ~T8_E~0); 84809#L1331-1 assume !(0 == ~T9_E~0); 84526#L1336-1 assume !(0 == ~T10_E~0); 84527#L1341-1 assume !(0 == ~T11_E~0); 84602#L1346-1 assume !(0 == ~T12_E~0); 84603#L1351-1 assume !(0 == ~T13_E~0); 84925#L1356-1 assume !(0 == ~E_M~0); 84926#L1361-1 assume !(0 == ~E_1~0); 86482#L1366-1 assume !(0 == ~E_2~0); 84969#L1371-1 assume !(0 == ~E_3~0); 84970#L1376-1 assume !(0 == ~E_4~0); 85831#L1381-1 assume !(0 == ~E_5~0); 85832#L1386-1 assume !(0 == ~E_6~0); 86514#L1391-1 assume !(0 == ~E_7~0); 86534#L1396-1 assume !(0 == ~E_8~0); 85732#L1401-1 assume !(0 == ~E_9~0); 85733#L1406-1 assume !(0 == ~E_10~0); 86023#L1411-1 assume !(0 == ~E_11~0); 86024#L1416-1 assume !(0 == ~E_12~0); 85651#L1421-1 assume !(0 == ~E_13~0); 85171#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 85172#L640 assume !(1 == ~m_pc~0); 85699#L640-2 is_master_triggered_~__retres1~0#1 := 0; 85698#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 85659#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 85660#L1603 assume !(0 != activate_threads_~tmp~1#1); 85687#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 85314#L659 assume 1 == ~t1_pc~0; 85315#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 85424#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86139#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 85445#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 85446#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 85462#L678 assume !(1 == ~t2_pc~0); 86422#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 86511#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 85010#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 85011#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 85558#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 85682#L697 assume !(1 == ~t3_pc~0); 85683#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 85812#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86129#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 85593#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 85594#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 86453#L716 assume 1 == ~t4_pc~0; 86441#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 85298#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 84677#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 84678#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 84779#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 86096#L735 assume !(1 == ~t5_pc~0); 84747#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 84748#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 85194#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 86119#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 85758#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 85759#L754 assume 1 == ~t6_pc~0; 85512#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 85407#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 84989#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 84990#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 85379#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 86194#L773 assume !(1 == ~t7_pc~0); 84929#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 84928#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 85794#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 85769#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 85770#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 85823#L792 assume 1 == ~t8_pc~0; 85994#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 86317#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 86318#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 85762#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 85685#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 85686#L811 assume 1 == ~t9_pc~0; 85895#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 86362#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 85066#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 85067#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 85695#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 85696#L830 assume !(1 == ~t10_pc~0); 85419#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 84905#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 84906#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 84883#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 84884#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 86211#L849 assume 1 == ~t11_pc~0; 86212#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 84726#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 84727#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 86223#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 86125#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 86126#L868 assume !(1 == ~t12_pc~0); 85542#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 85541#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 84617#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 84618#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 84940#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 84941#L887 assume 1 == ~t13_pc~0; 86131#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 85587#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 85588#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 86187#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 84657#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 84658#L1439 assume !(1 == ~M_E~0); 85754#L1439-2 assume !(1 == ~T1_E~0); 84822#L1444-1 assume !(1 == ~T2_E~0); 84823#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 85320#L1454-1 assume !(1 == ~T4_E~0); 85321#L1459-1 assume !(1 == ~T5_E~0); 85887#L1464-1 assume !(1 == ~T6_E~0); 85888#L1469-1 assume !(1 == ~T7_E~0); 85965#L1474-1 assume !(1 == ~T8_E~0); 85652#L1479-1 assume !(1 == ~T9_E~0); 85653#L1484-1 assume !(1 == ~T10_E~0); 85890#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 85533#L1494-1 assume !(1 == ~T12_E~0); 85534#L1499-1 assume !(1 == ~T13_E~0); 85717#L1504-1 assume !(1 == ~E_M~0); 85718#L1509-1 assume !(1 == ~E_1~0); 86299#L1514-1 assume !(1 == ~E_2~0); 85996#L1519-1 assume !(1 == ~E_3~0); 85997#L1524-1 assume !(1 == ~E_4~0); 86497#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 86498#L1534-1 assume !(1 == ~E_6~0); 84651#L1539-1 assume !(1 == ~E_7~0); 84652#L1544-1 assume !(1 == ~E_8~0); 85065#L1549-1 assume !(1 == ~E_9~0); 86474#L1554-1 assume !(1 == ~E_10~0); 86468#L1559-1 assume !(1 == ~E_11~0); 86342#L1564-1 assume !(1 == ~E_12~0); 86343#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 86492#L1574-1 assume { :end_inline_reset_delta_events } true; 84820#L1940-2 [2022-12-13 18:37:29,001 INFO L750 eck$LassoCheckResult]: Loop: 84820#L1940-2 assume !false; 84821#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 85417#L1266 assume !false; 86135#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 85374#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 85092#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 86298#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 86309#L1079 assume !(0 != eval_~tmp~0#1); 85575#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 85231#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 85232#L1291-3 assume !(0 == ~M_E~0); 85962#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 85963#L1296-3 assume !(0 == ~T2_E~0); 86524#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 86478#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 85617#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 84857#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 84858#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 84959#L1326-3 assume !(0 == ~T8_E~0); 85747#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 86001#L1336-3 assume !(0 == ~T10_E~0); 86002#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 85311#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 85290#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 85229#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 85230#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 85813#L1366-3 assume !(0 == ~E_2~0); 84577#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 84578#L1376-3 assume !(0 == ~E_4~0); 86322#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 86173#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 86174#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 86354#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 86355#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 84922#L1406-3 assume !(0 == ~E_10~0); 84787#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 84788#L1416-3 assume !(0 == ~E_12~0); 85470#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 85471#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 85582#L640-45 assume 1 == ~m_pc~0; 85584#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 85023#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 85024#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 84573#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 84574#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 84665#L659-45 assume !(1 == ~t1_pc~0); 84667#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 85109#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86528#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 86458#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 86104#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86105#L678-45 assume !(1 == ~t2_pc~0); 86061#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 85589#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 85590#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 86041#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 86371#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 86476#L697-45 assume 1 == ~t3_pc~0; 85852#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 85853#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86544#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 86007#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 86008#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 86042#L716-45 assume 1 == ~t4_pc~0; 85664#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 85665#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86328#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 85670#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 85671#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 85329#L735-45 assume !(1 == ~t5_pc~0); 85331#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 85884#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 86494#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 86541#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 86496#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 86490#L754-45 assume 1 == ~t6_pc~0; 85835#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 85836#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85728#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 85729#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 85840#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 85564#L773-45 assume 1 == ~t7_pc~0; 85565#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 85103#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 85801#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 85802#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 85571#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 85222#L792-45 assume 1 == ~t8_pc~0; 85223#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 86252#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 86253#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 84686#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 84687#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 85173#L811-45 assume !(1 == ~t9_pc~0); 84953#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 84954#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 86170#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 86038#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 85643#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 85428#L830-45 assume 1 == ~t10_pc~0; 85429#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 84613#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 85751#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 84831#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 84832#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 84593#L849-45 assume 1 == ~t11_pc~0; 84595#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 85041#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 84885#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 84579#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 84580#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 84826#L868-45 assume 1 == ~t12_pc~0; 84827#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 84772#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 84773#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 86205#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 86384#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 86385#L887-45 assume !(1 == ~t13_pc~0); 84833#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 84834#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86133#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 86152#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 84802#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 84803#L1439-3 assume !(1 == ~M_E~0); 86128#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 84818#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 84819#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 84973#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 85942#L1459-3 assume !(1 == ~T5_E~0); 85943#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 86386#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 86325#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 86326#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 86389#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 85622#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 85623#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 86246#L1499-3 assume !(1 == ~T13_E~0); 85901#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 85902#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 86338#L1514-3 assume !(1 == ~E_2~0); 86372#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 85538#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 85539#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 86414#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 85820#L1539-3 assume !(1 == ~E_7~0); 85275#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 85276#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 85782#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 84864#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 84865#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 86043#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 86044#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 84760#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 84535#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 84853#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 84766#L1959 assume !(0 == start_simulation_~tmp~3#1); 84768#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 84796#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 84753#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 84588#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 84589#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 86407#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 86378#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 86379#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 84820#L1940-2 [2022-12-13 18:37:29,001 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:29,002 INFO L85 PathProgramCache]: Analyzing trace with hash -1492429054, now seen corresponding path program 1 times [2022-12-13 18:37:29,002 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:29,002 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1191331704] [2022-12-13 18:37:29,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:29,002 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:29,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:29,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:29,056 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:29,056 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1191331704] [2022-12-13 18:37:29,056 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1191331704] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:29,056 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:29,056 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:29,056 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1416130777] [2022-12-13 18:37:29,056 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:29,056 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 18:37:29,056 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:29,057 INFO L85 PathProgramCache]: Analyzing trace with hash -1258024741, now seen corresponding path program 1 times [2022-12-13 18:37:29,057 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:29,057 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2064683592] [2022-12-13 18:37:29,057 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:29,057 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:29,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:29,092 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:29,092 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:29,092 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2064683592] [2022-12-13 18:37:29,093 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2064683592] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:29,093 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:29,093 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:29,093 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [883789817] [2022-12-13 18:37:29,093 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:29,093 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:37:29,093 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:37:29,093 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 18:37:29,093 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 18:37:29,094 INFO L87 Difference]: Start difference. First operand 3771 states and 5502 transitions. cyclomatic complexity: 1732 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:29,377 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:37:29,377 INFO L93 Difference]: Finished difference Result 10636 states and 15357 transitions. [2022-12-13 18:37:29,377 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10636 states and 15357 transitions. [2022-12-13 18:37:29,415 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10253 [2022-12-13 18:37:29,444 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10636 states to 10636 states and 15357 transitions. [2022-12-13 18:37:29,444 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10636 [2022-12-13 18:37:29,450 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10636 [2022-12-13 18:37:29,450 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10636 states and 15357 transitions. [2022-12-13 18:37:29,456 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:37:29,456 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10636 states and 15357 transitions. [2022-12-13 18:37:29,464 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10636 states and 15357 transitions. [2022-12-13 18:37:29,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10636 to 10252. [2022-12-13 18:37:29,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10252 states, 10252 states have (on average 1.4458642216152946) internal successors, (14823), 10251 states have internal predecessors, (14823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:29,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10252 states to 10252 states and 14823 transitions. [2022-12-13 18:37:29,567 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10252 states and 14823 transitions. [2022-12-13 18:37:29,567 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 18:37:29,568 INFO L428 stractBuchiCegarLoop]: Abstraction has 10252 states and 14823 transitions. [2022-12-13 18:37:29,568 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-12-13 18:37:29,568 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10252 states and 14823 transitions. [2022-12-13 18:37:29,591 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10069 [2022-12-13 18:37:29,591 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:37:29,591 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:37:29,593 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:29,593 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:29,593 INFO L748 eck$LassoCheckResult]: Stem: 99232#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 99233#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 100265#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 100266#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 101258#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 100412#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 99832#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 99833#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 100728#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 100729#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 100867#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 100868#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 99577#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 99578#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 100914#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 100149#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 100150#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 100784#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 100062#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 100063#L1291 assume !(0 == ~M_E~0); 101259#L1291-2 assume !(0 == ~T1_E~0); 101255#L1296-1 assume !(0 == ~T2_E~0); 100223#L1301-1 assume !(0 == ~T3_E~0); 100224#L1306-1 assume !(0 == ~T4_E~0); 100797#L1311-1 assume !(0 == ~T5_E~0); 99412#L1316-1 assume !(0 == ~T6_E~0); 99413#L1321-1 assume !(0 == ~T7_E~0); 100238#L1326-1 assume !(0 == ~T8_E~0); 99229#L1331-1 assume !(0 == ~T9_E~0); 98943#L1336-1 assume !(0 == ~T10_E~0); 98944#L1341-1 assume !(0 == ~T11_E~0); 99018#L1346-1 assume !(0 == ~T12_E~0); 99019#L1351-1 assume !(0 == ~T13_E~0); 99349#L1356-1 assume !(0 == ~E_M~0); 99350#L1361-1 assume !(0 == ~E_1~0); 101129#L1366-1 assume !(0 == ~E_2~0); 99395#L1371-1 assume !(0 == ~E_3~0); 99396#L1376-1 assume !(0 == ~E_4~0); 100296#L1381-1 assume !(0 == ~E_5~0); 100297#L1386-1 assume !(0 == ~E_6~0); 101178#L1391-1 assume !(0 == ~E_7~0); 101221#L1396-1 assume !(0 == ~E_8~0); 100186#L1401-1 assume !(0 == ~E_9~0); 100187#L1406-1 assume !(0 == ~E_10~0); 100510#L1411-1 assume !(0 == ~E_11~0); 100511#L1416-1 assume !(0 == ~E_12~0); 100102#L1421-1 assume !(0 == ~E_13~0); 99600#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 99601#L640 assume !(1 == ~m_pc~0); 100307#L640-2 is_master_triggered_~__retres1~0#1 := 0; 100255#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 100109#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 100110#L1603 assume !(0 != activate_threads_~tmp~1#1); 100139#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 99753#L659 assume !(1 == ~t1_pc~0); 99754#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 100990#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 100641#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 99885#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 99886#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 99902#L678 assume !(1 == ~t2_pc~0); 101026#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 101172#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 99438#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 99439#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 100006#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 100132#L697 assume !(1 == ~t3_pc~0); 100133#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 100276#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 100623#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 100041#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 100042#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 101082#L716 assume 1 == ~t4_pc~0; 101063#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 99732#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 99090#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 99091#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 99196#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 100587#L735 assume !(1 == ~t5_pc~0); 99164#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 99165#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 99629#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 100612#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 100216#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 100217#L754 assume 1 == ~t6_pc~0; 99955#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 99846#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 99416#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 99417#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 99818#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 100716#L773 assume !(1 == ~t7_pc~0); 99353#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 99352#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 100256#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 100227#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 100228#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 100287#L792 assume 1 == ~t8_pc~0; 100480#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 100869#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 100870#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 100218#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 100135#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 100136#L811 assume 1 == ~t9_pc~0; 100367#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 100929#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 99496#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 99497#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 100147#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 100148#L830 assume !(1 == ~t10_pc~0); 99857#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 99328#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 99329#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 99307#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 99308#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 100737#L849 assume 1 == ~t11_pc~0; 100738#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 99142#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 99143#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 100750#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 100619#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 100620#L868 assume !(1 == ~t12_pc~0); 99990#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 99989#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 99033#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 99034#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 99364#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 99365#L887 assume 1 == ~t13_pc~0; 100628#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 100035#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 100036#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 100709#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 99073#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 99074#L1439 assume !(1 == ~M_E~0); 100210#L1439-2 assume !(1 == ~T1_E~0); 99242#L1444-1 assume !(1 == ~T2_E~0); 99243#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 99757#L1454-1 assume !(1 == ~T4_E~0); 99758#L1459-1 assume !(1 == ~T5_E~0); 100359#L1464-1 assume !(1 == ~T6_E~0); 100360#L1469-1 assume !(1 == ~T7_E~0); 100445#L1474-1 assume !(1 == ~T8_E~0); 100103#L1479-1 assume !(1 == ~T9_E~0); 100104#L1484-1 assume !(1 == ~T10_E~0); 100363#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 99978#L1494-1 assume !(1 == ~T12_E~0); 99979#L1499-1 assume !(1 == ~T13_E~0); 100169#L1504-1 assume !(1 == ~E_M~0); 100170#L1509-1 assume !(1 == ~E_1~0); 100849#L1514-1 assume !(1 == ~E_2~0); 100482#L1519-1 assume !(1 == ~E_3~0); 100483#L1524-1 assume !(1 == ~E_4~0); 101153#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 101154#L1534-1 assume !(1 == ~E_6~0); 99067#L1539-1 assume !(1 == ~E_7~0); 99068#L1544-1 assume !(1 == ~E_8~0); 99493#L1549-1 assume !(1 == ~E_9~0); 101111#L1554-1 assume !(1 == ~E_10~0); 101109#L1559-1 assume !(1 == ~E_11~0); 100902#L1564-1 assume !(1 == ~E_12~0); 100903#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 101144#L1574-1 assume { :end_inline_reset_delta_events } true; 101189#L1940-2 [2022-12-13 18:37:29,593 INFO L750 eck$LassoCheckResult]: Loop: 101189#L1940-2 assume !false; 103722#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 103716#L1266 assume !false; 103714#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 103565#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 103543#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 103541#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 103538#L1079 assume !(0 != eval_~tmp~0#1); 103535#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 103533#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 103531#L1291-3 assume !(0 == ~M_E~0); 103529#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 103527#L1296-3 assume !(0 == ~T2_E~0); 103525#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 103523#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 103521#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 103519#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 103517#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 103515#L1326-3 assume !(0 == ~T8_E~0); 103513#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 103511#L1336-3 assume !(0 == ~T10_E~0); 103509#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 103507#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 103505#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 103503#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 103501#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 103499#L1366-3 assume !(0 == ~E_2~0); 103497#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 103495#L1376-3 assume !(0 == ~E_4~0); 103493#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 103491#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 103489#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 103487#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 103485#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 103483#L1406-3 assume !(0 == ~E_10~0); 103481#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 103479#L1416-3 assume !(0 == ~E_12~0); 103477#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 103475#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 103473#L640-45 assume !(1 == ~m_pc~0); 103471#L640-47 is_master_triggered_~__retres1~0#1 := 0; 103469#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 103467#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 103465#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 103463#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 103461#L659-45 assume !(1 == ~t1_pc~0); 103459#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 103457#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 103455#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 103453#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 103451#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 103449#L678-45 assume !(1 == ~t2_pc~0); 103445#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 103443#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 103441#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 103439#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 103437#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 103435#L697-45 assume !(1 == ~t3_pc~0); 103433#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 103429#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 103427#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 103425#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 103423#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 103421#L716-45 assume 1 == ~t4_pc~0; 103419#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 103415#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 103413#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 103411#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 103409#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 103407#L735-45 assume !(1 == ~t5_pc~0); 103405#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 103401#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 103399#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 103397#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 103395#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 103393#L754-45 assume 1 == ~t6_pc~0; 103391#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 103387#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 103385#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 103383#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 103381#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 103379#L773-45 assume !(1 == ~t7_pc~0); 103377#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 103373#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 103371#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 103369#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 103367#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 103365#L792-45 assume !(1 == ~t8_pc~0); 103363#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 103359#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 103357#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 103355#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 103353#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 103351#L811-45 assume 1 == ~t9_pc~0; 103349#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 103345#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 103343#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 103341#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 103339#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 103337#L830-45 assume !(1 == ~t10_pc~0); 103335#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 103331#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 103329#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 103327#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 103325#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 103323#L849-45 assume 1 == ~t11_pc~0; 103321#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 103317#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 103315#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 103313#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 103311#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 103309#L868-45 assume !(1 == ~t12_pc~0); 103307#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 103303#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 103301#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 103299#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 103297#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 103295#L887-45 assume 1 == ~t13_pc~0; 103293#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 103289#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 103287#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 103285#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 103283#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 103281#L1439-3 assume !(1 == ~M_E~0); 103103#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 103100#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 103098#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 103096#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 103094#L1459-3 assume !(1 == ~T5_E~0); 103092#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 103090#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 103087#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 103085#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 103083#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 103081#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 103078#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 103076#L1499-3 assume !(1 == ~T13_E~0); 103074#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 103072#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 103070#L1514-3 assume !(1 == ~E_2~0); 103068#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 103065#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 103063#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 103061#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 103045#L1539-3 assume !(1 == ~E_7~0); 103033#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 103024#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 103017#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 103012#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 103013#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 105017#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 102994#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 102995#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 101451#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 101452#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 104812#L1959 assume !(0 == start_simulation_~tmp~3#1); 104804#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 103751#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 103736#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 103734#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 103732#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 103730#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 103728#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 103726#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 101189#L1940-2 [2022-12-13 18:37:29,594 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:29,594 INFO L85 PathProgramCache]: Analyzing trace with hash -121367293, now seen corresponding path program 1 times [2022-12-13 18:37:29,594 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:29,594 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1021086158] [2022-12-13 18:37:29,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:29,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:29,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:29,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:29,670 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:29,670 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1021086158] [2022-12-13 18:37:29,670 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1021086158] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:29,670 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:29,671 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 18:37:29,671 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1643438437] [2022-12-13 18:37:29,671 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:29,671 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 18:37:29,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:29,672 INFO L85 PathProgramCache]: Analyzing trace with hash -956254881, now seen corresponding path program 1 times [2022-12-13 18:37:29,672 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:29,672 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [729513028] [2022-12-13 18:37:29,672 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:29,672 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:29,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:29,720 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:29,720 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:29,720 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [729513028] [2022-12-13 18:37:29,720 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [729513028] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:29,720 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:29,721 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:29,721 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2026738283] [2022-12-13 18:37:29,721 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:29,721 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:37:29,722 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:37:29,722 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 18:37:29,722 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 18:37:29,722 INFO L87 Difference]: Start difference. First operand 10252 states and 14823 transitions. cyclomatic complexity: 4573 Second operand has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:30,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:37:30,181 INFO L93 Difference]: Finished difference Result 28084 states and 40677 transitions. [2022-12-13 18:37:30,181 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28084 states and 40677 transitions. [2022-12-13 18:37:30,281 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 27680 [2022-12-13 18:37:30,364 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28084 states to 28084 states and 40677 transitions. [2022-12-13 18:37:30,364 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28084 [2022-12-13 18:37:30,381 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28084 [2022-12-13 18:37:30,382 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28084 states and 40677 transitions. [2022-12-13 18:37:30,409 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:37:30,409 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28084 states and 40677 transitions. [2022-12-13 18:37:30,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28084 states and 40677 transitions. [2022-12-13 18:37:30,561 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28084 to 10516. [2022-12-13 18:37:30,571 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10516 states, 10516 states have (on average 1.4346709775580069) internal successors, (15087), 10515 states have internal predecessors, (15087), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:30,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10516 states to 10516 states and 15087 transitions. [2022-12-13 18:37:30,586 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10516 states and 15087 transitions. [2022-12-13 18:37:30,586 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 18:37:30,586 INFO L428 stractBuchiCegarLoop]: Abstraction has 10516 states and 15087 transitions. [2022-12-13 18:37:30,586 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-12-13 18:37:30,587 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10516 states and 15087 transitions. [2022-12-13 18:37:30,606 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10330 [2022-12-13 18:37:30,606 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:37:30,606 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:37:30,607 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:30,607 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:30,608 INFO L748 eck$LassoCheckResult]: Stem: 137581#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 137582#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 138595#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 138596#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 139540#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 138741#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 138172#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 138173#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 139050#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 139051#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 139191#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 139192#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 137919#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 137920#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 139231#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 138485#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 138486#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 139110#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 138399#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 138400#L1291 assume !(0 == ~M_E~0); 139541#L1291-2 assume !(0 == ~T1_E~0); 139538#L1296-1 assume !(0 == ~T2_E~0); 138555#L1301-1 assume !(0 == ~T3_E~0); 138556#L1306-1 assume !(0 == ~T4_E~0); 139127#L1311-1 assume !(0 == ~T5_E~0); 137759#L1316-1 assume !(0 == ~T6_E~0); 137760#L1321-1 assume !(0 == ~T7_E~0); 138569#L1326-1 assume !(0 == ~T8_E~0); 137578#L1331-1 assume !(0 == ~T9_E~0); 137292#L1336-1 assume !(0 == ~T10_E~0); 137293#L1341-1 assume !(0 == ~T11_E~0); 137367#L1346-1 assume !(0 == ~T12_E~0); 137368#L1351-1 assume !(0 == ~T13_E~0); 137697#L1356-1 assume !(0 == ~E_M~0); 137698#L1361-1 assume !(0 == ~E_1~0); 139433#L1366-1 assume !(0 == ~E_2~0); 137743#L1371-1 assume !(0 == ~E_3~0); 137744#L1376-1 assume !(0 == ~E_4~0); 138626#L1381-1 assume !(0 == ~E_5~0); 138627#L1386-1 assume !(0 == ~E_6~0); 139483#L1391-1 assume !(0 == ~E_7~0); 139514#L1396-1 assume !(0 == ~E_8~0); 138520#L1401-1 assume !(0 == ~E_9~0); 138521#L1406-1 assume !(0 == ~E_10~0); 138834#L1411-1 assume !(0 == ~E_11~0); 138835#L1416-1 assume !(0 == ~E_12~0); 138439#L1421-1 assume !(0 == ~E_13~0); 137944#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 137945#L640 assume !(1 == ~m_pc~0); 138637#L640-2 is_master_triggered_~__retres1~0#1 := 0; 138585#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 138446#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 138447#L1603 assume !(0 != activate_threads_~tmp~1#1); 138475#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 138093#L659 assume !(1 == ~t1_pc~0); 138094#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 139300#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 138968#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 138224#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 138225#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 138241#L678 assume !(1 == ~t2_pc~0); 139330#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 139478#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 137785#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 137786#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 138343#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 138468#L697 assume !(1 == ~t3_pc~0); 138469#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 138606#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 139357#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 138377#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 138378#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 139378#L716 assume 1 == ~t4_pc~0; 139362#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 138075#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 137439#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 137440#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 137547#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 138916#L735 assume !(1 == ~t5_pc~0); 137513#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 137514#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 137972#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 138940#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 138548#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 138549#L754 assume 1 == ~t6_pc~0; 138294#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 138186#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 137763#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 137764#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 138158#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 139040#L773 assume !(1 == ~t7_pc~0); 137701#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 137700#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 138586#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 138559#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 138560#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 138618#L792 assume 1 == ~t8_pc~0; 138805#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 139193#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 139194#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 138550#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 138471#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 138472#L811 assume 1 == ~t9_pc~0; 138697#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 139246#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 137841#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 137842#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 138483#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 138484#L830 assume !(1 == ~t10_pc~0); 138195#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 137677#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 137678#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 137656#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 137657#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 139060#L849 assume 1 == ~t11_pc~0; 139061#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 137492#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 137493#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 139078#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 138947#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 138948#L868 assume !(1 == ~t12_pc~0); 138327#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 138326#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 137383#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 137384#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 137712#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 137713#L887 assume 1 == ~t13_pc~0; 138954#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 138371#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 138372#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 139033#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 137422#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 137423#L1439 assume !(1 == ~M_E~0); 138542#L1439-2 assume !(1 == ~T1_E~0); 137591#L1444-1 assume !(1 == ~T2_E~0); 137592#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 138098#L1454-1 assume !(1 == ~T4_E~0); 138099#L1459-1 assume !(1 == ~T5_E~0); 138689#L1464-1 assume !(1 == ~T6_E~0); 138690#L1469-1 assume !(1 == ~T7_E~0); 138772#L1474-1 assume !(1 == ~T8_E~0); 138440#L1479-1 assume !(1 == ~T9_E~0); 138441#L1484-1 assume !(1 == ~T10_E~0); 138692#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 138316#L1494-1 assume !(1 == ~T12_E~0); 138317#L1499-1 assume !(1 == ~T13_E~0); 138503#L1504-1 assume !(1 == ~E_M~0); 138504#L1509-1 assume !(1 == ~E_1~0); 139172#L1514-1 assume !(1 == ~E_2~0); 138807#L1519-1 assume !(1 == ~E_3~0); 138808#L1524-1 assume !(1 == ~E_4~0); 139460#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 139461#L1534-1 assume !(1 == ~E_6~0); 137416#L1539-1 assume !(1 == ~E_7~0); 137417#L1544-1 assume !(1 == ~E_8~0); 137838#L1549-1 assume !(1 == ~E_9~0); 139412#L1554-1 assume !(1 == ~E_10~0); 139407#L1559-1 assume !(1 == ~E_11~0); 139221#L1564-1 assume !(1 == ~E_12~0); 139222#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 139453#L1574-1 assume { :end_inline_reset_delta_events } true; 139490#L1940-2 [2022-12-13 18:37:30,608 INFO L750 eck$LassoCheckResult]: Loop: 139490#L1940-2 assume !false; 145489#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 145483#L1266 assume !false; 145479#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 145468#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 145459#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 145456#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 145453#L1079 assume !(0 != eval_~tmp~0#1); 145454#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 147478#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 147475#L1291-3 assume !(0 == ~M_E~0); 147473#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 147471#L1296-3 assume !(0 == ~T2_E~0); 147469#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 147467#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 147465#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 147462#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 147460#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 147458#L1326-3 assume !(0 == ~T8_E~0); 147456#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 147454#L1336-3 assume !(0 == ~T10_E~0); 147452#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 147449#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 147447#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 147445#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 147443#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 147441#L1366-3 assume !(0 == ~E_2~0); 147439#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 147436#L1376-3 assume !(0 == ~E_4~0); 147434#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 147432#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 147430#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 147428#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 147426#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 147418#L1406-3 assume !(0 == ~E_10~0); 147416#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 147415#L1416-3 assume !(0 == ~E_12~0); 147414#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 147413#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 147412#L640-45 assume !(1 == ~m_pc~0); 147411#L640-47 is_master_triggered_~__retres1~0#1 := 0; 147410#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 147409#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 147408#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 147407#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 147406#L659-45 assume !(1 == ~t1_pc~0); 147405#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 147404#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 147403#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 147402#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 147401#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 147400#L678-45 assume !(1 == ~t2_pc~0); 147398#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 147397#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 147396#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 147395#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 147388#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 139420#L697-45 assume !(1 == ~t3_pc~0); 139422#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 147387#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 147385#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 147383#L1627-45 assume !(0 != activate_threads_~tmp___2~0#1); 147381#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 147380#L716-45 assume !(1 == ~t4_pc~0); 147378#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 147377#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 147376#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 147375#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 147374#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 147373#L735-45 assume 1 == ~t5_pc~0; 147371#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 147370#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 139588#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 139531#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 139458#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 139448#L754-45 assume 1 == ~t6_pc~0; 138631#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 138632#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 138516#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 138517#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 138636#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 138348#L773-45 assume !(1 == ~t7_pc~0); 137876#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 137877#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 138593#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 138594#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 138356#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 138001#L792-45 assume 1 == ~t8_pc~0; 138002#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 139119#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 139120#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 137451#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 137452#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 137949#L811-45 assume 1 == ~t9_pc~0; 137726#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 137728#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 139012#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 138856#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 138431#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 138208#L830-45 assume !(1 == ~t10_pc~0); 137378#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 137379#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 138541#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 137600#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 137601#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 137358#L849-45 assume 1 == ~t11_pc~0; 137360#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 137816#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 137658#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 137344#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 137345#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 137595#L868-45 assume 1 == ~t12_pc~0; 137596#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 137540#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 137541#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 139054#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 139276#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 139277#L887-45 assume !(1 == ~t13_pc~0); 137602#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 137603#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 138959#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 138982#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 137571#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 137572#L1439-3 assume !(1 == ~M_E~0); 138973#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 146972#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 146970#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 146968#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 146966#L1459-3 assume !(1 == ~T5_E~0); 146964#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 146963#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 146960#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 146958#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 146956#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 146954#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 146952#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 146950#L1499-3 assume !(1 == ~T13_E~0); 146947#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 146945#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 146943#L1514-3 assume !(1 == ~E_2~0); 146941#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 146939#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 146937#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 146935#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 146895#L1539-3 assume !(1 == ~E_7~0); 146887#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 146880#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 146874#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 146869#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 146824#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 146819#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 146809#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 146654#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 146497#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 146496#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 146495#L1959 assume !(0 == start_simulation_~tmp~3#1); 146489#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 145791#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 145777#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 145721#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 145709#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 145697#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 145669#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 145661#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 139490#L1940-2 [2022-12-13 18:37:30,608 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:30,608 INFO L85 PathProgramCache]: Analyzing trace with hash -2061949307, now seen corresponding path program 1 times [2022-12-13 18:37:30,609 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:30,609 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2115295512] [2022-12-13 18:37:30,609 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:30,609 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:30,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:30,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:30,671 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:30,671 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2115295512] [2022-12-13 18:37:30,671 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2115295512] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:30,671 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:30,671 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 18:37:30,671 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [780105330] [2022-12-13 18:37:30,671 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:30,672 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 18:37:30,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:30,672 INFO L85 PathProgramCache]: Analyzing trace with hash 625053216, now seen corresponding path program 1 times [2022-12-13 18:37:30,672 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:30,672 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1516579526] [2022-12-13 18:37:30,672 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:30,672 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:30,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:30,714 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:30,714 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:30,715 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1516579526] [2022-12-13 18:37:30,715 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1516579526] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:30,715 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:30,715 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:30,715 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [368453453] [2022-12-13 18:37:30,715 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:30,715 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:37:30,716 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:37:30,716 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 18:37:30,716 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 18:37:30,716 INFO L87 Difference]: Start difference. First operand 10516 states and 15087 transitions. cyclomatic complexity: 4573 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:30,840 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:37:30,840 INFO L93 Difference]: Finished difference Result 20156 states and 28805 transitions. [2022-12-13 18:37:30,840 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20156 states and 28805 transitions. [2022-12-13 18:37:30,897 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 19949 [2022-12-13 18:37:30,948 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20156 states to 20156 states and 28805 transitions. [2022-12-13 18:37:30,948 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20156 [2022-12-13 18:37:30,959 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20156 [2022-12-13 18:37:30,959 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20156 states and 28805 transitions. [2022-12-13 18:37:31,019 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:37:31,020 INFO L218 hiAutomatonCegarLoop]: Abstraction has 20156 states and 28805 transitions. [2022-12-13 18:37:31,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20156 states and 28805 transitions. [2022-12-13 18:37:31,177 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20156 to 20144. [2022-12-13 18:37:31,197 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20144 states, 20144 states have (on average 1.4293586179507545) internal successors, (28793), 20143 states have internal predecessors, (28793), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:31,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20144 states to 20144 states and 28793 transitions. [2022-12-13 18:37:31,230 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20144 states and 28793 transitions. [2022-12-13 18:37:31,230 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 18:37:31,230 INFO L428 stractBuchiCegarLoop]: Abstraction has 20144 states and 28793 transitions. [2022-12-13 18:37:31,230 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-12-13 18:37:31,231 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20144 states and 28793 transitions. [2022-12-13 18:37:31,281 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 19937 [2022-12-13 18:37:31,281 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:37:31,281 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:37:31,283 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:31,283 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:31,283 INFO L748 eck$LassoCheckResult]: Stem: 168254#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 168255#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 169267#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 169268#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 170169#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 169411#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 168839#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 168840#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 169725#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 169726#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 169858#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 169859#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 168590#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 168591#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 169898#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 169155#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 169156#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 169785#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 169068#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 169069#L1291 assume !(0 == ~M_E~0); 170170#L1291-2 assume !(0 == ~T1_E~0); 170166#L1296-1 assume !(0 == ~T2_E~0); 169224#L1301-1 assume !(0 == ~T3_E~0); 169225#L1306-1 assume !(0 == ~T4_E~0); 169798#L1311-1 assume !(0 == ~T5_E~0); 168430#L1316-1 assume !(0 == ~T6_E~0); 168431#L1321-1 assume !(0 == ~T7_E~0); 169240#L1326-1 assume !(0 == ~T8_E~0); 168251#L1331-1 assume !(0 == ~T9_E~0); 167971#L1336-1 assume !(0 == ~T10_E~0); 167972#L1341-1 assume !(0 == ~T11_E~0); 168045#L1346-1 assume !(0 == ~T12_E~0); 168046#L1351-1 assume !(0 == ~T13_E~0); 168368#L1356-1 assume !(0 == ~E_M~0); 168369#L1361-1 assume !(0 == ~E_1~0); 170068#L1366-1 assume !(0 == ~E_2~0); 168414#L1371-1 assume !(0 == ~E_3~0); 168415#L1376-1 assume !(0 == ~E_4~0); 169301#L1381-1 assume !(0 == ~E_5~0); 169302#L1386-1 assume !(0 == ~E_6~0); 170106#L1391-1 assume !(0 == ~E_7~0); 170144#L1396-1 assume !(0 == ~E_8~0); 169189#L1401-1 assume !(0 == ~E_9~0); 169190#L1406-1 assume !(0 == ~E_10~0); 169506#L1411-1 assume !(0 == ~E_11~0); 169507#L1416-1 assume !(0 == ~E_12~0); 169108#L1421-1 assume !(0 == ~E_13~0); 168613#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 168614#L640 assume !(1 == ~m_pc~0); 169312#L640-2 is_master_triggered_~__retres1~0#1 := 0; 169256#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 169116#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 169117#L1603 assume !(0 != activate_threads_~tmp~1#1); 169145#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 168763#L659 assume !(1 == ~t1_pc~0); 168764#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 169959#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 169643#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 168892#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 168893#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 168909#L678 assume !(1 == ~t2_pc~0); 169985#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 170100#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 168456#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 168457#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 169011#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 169138#L697 assume !(1 == ~t3_pc~0); 169139#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 169281#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 169629#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 169046#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 169047#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 170021#L716 assume !(1 == ~t4_pc~0); 169580#L716-2 is_transmit4_triggered_~__retres1~4#1 := 0; 168743#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 168116#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 168117#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 168220#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 169592#L735 assume !(1 == ~t5_pc~0); 168188#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 168189#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 168640#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 169618#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 169217#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 169218#L754 assume 1 == ~t6_pc~0; 168962#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 168854#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 168434#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 168435#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 168826#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 169713#L773 assume !(1 == ~t7_pc~0); 168372#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 168371#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 169257#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 169228#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 169229#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 169292#L792 assume 1 == ~t8_pc~0; 169476#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 169860#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 169861#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 169219#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 169141#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 169142#L811 assume 1 == ~t9_pc~0; 169369#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 169911#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 168512#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 168513#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 169153#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 169154#L830 assume !(1 == ~t10_pc~0); 168863#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 168348#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 168349#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 168327#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 168328#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 169734#L849 assume 1 == ~t11_pc~0; 169735#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 168167#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 168168#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 169752#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 169625#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 169626#L868 assume !(1 == ~t12_pc~0); 168995#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 168994#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 168060#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 168061#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 168384#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 168385#L887 assume 1 == ~t13_pc~0; 169632#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 169040#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 169041#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 169704#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 168099#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 168100#L1439 assume !(1 == ~M_E~0); 169211#L1439-2 assume !(1 == ~T1_E~0); 168264#L1444-1 assume !(1 == ~T2_E~0); 168265#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 168768#L1454-1 assume !(1 == ~T4_E~0); 168769#L1459-1 assume !(1 == ~T5_E~0); 169362#L1464-1 assume !(1 == ~T6_E~0); 169363#L1469-1 assume !(1 == ~T7_E~0); 169443#L1474-1 assume !(1 == ~T8_E~0); 169109#L1479-1 assume !(1 == ~T9_E~0); 169110#L1484-1 assume !(1 == ~T10_E~0); 169365#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 168984#L1494-1 assume !(1 == ~T12_E~0); 168985#L1499-1 assume !(1 == ~T13_E~0); 169174#L1504-1 assume !(1 == ~E_M~0); 169175#L1509-1 assume !(1 == ~E_1~0); 169839#L1514-1 assume !(1 == ~E_2~0); 169478#L1519-1 assume !(1 == ~E_3~0); 169479#L1524-1 assume !(1 == ~E_4~0); 170084#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 170085#L1534-1 assume !(1 == ~E_6~0); 168093#L1539-1 assume !(1 == ~E_7~0); 168094#L1544-1 assume !(1 == ~E_8~0); 168509#L1549-1 assume !(1 == ~E_9~0); 170052#L1554-1 assume !(1 == ~E_10~0); 170050#L1559-1 assume !(1 == ~E_11~0); 169888#L1564-1 assume !(1 == ~E_12~0); 169889#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 170078#L1574-1 assume { :end_inline_reset_delta_events } true; 170113#L1940-2 [2022-12-13 18:37:31,284 INFO L750 eck$LassoCheckResult]: Loop: 170113#L1940-2 assume !false; 183339#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 183333#L1266 assume !false; 183332#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 183322#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 183312#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 183309#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 183306#L1079 assume !(0 != eval_~tmp~0#1); 169028#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 169029#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 169573#L1291-3 assume !(0 == ~M_E~0); 169444#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 169445#L1296-3 assume !(0 == ~T2_E~0); 170125#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 170063#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 169072#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 168301#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 168302#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 168404#L1326-3 assume !(0 == ~T8_E~0); 169206#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 169483#L1336-3 assume !(0 == ~T10_E~0); 169484#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 168759#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 168737#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 168675#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 168676#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 169282#L1366-3 assume !(0 == ~E_2~0); 168020#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 168021#L1376-3 assume !(0 == ~E_4~0); 169866#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 169687#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 169688#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 169900#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 169901#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 168365#L1406-3 assume !(0 == ~E_10~0); 168228#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 168229#L1416-3 assume !(0 == ~E_12~0); 168918#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 168919#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 169036#L640-45 assume !(1 == ~m_pc~0); 169037#L640-47 is_master_triggered_~__retres1~0#1 := 0; 187818#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 187817#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 187816#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 187815#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 187814#L659-45 assume !(1 == ~t1_pc~0); 187813#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 187812#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 187811#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 187810#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 187809#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 187808#L678-45 assume !(1 == ~t2_pc~0); 187806#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 187805#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 187804#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 187803#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 187802#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 187801#L697-45 assume !(1 == ~t3_pc~0); 187799#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 187797#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 187795#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 187794#L1627-45 assume !(0 != activate_threads_~tmp___2~0#1); 187792#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 187791#L716-45 assume !(1 == ~t4_pc~0); 187790#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 187789#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 187788#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 187787#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 187786#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 187785#L735-45 assume 1 == ~t5_pc~0; 187783#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 187782#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 170213#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 170157#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 170082#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 170076#L754-45 assume 1 == ~t6_pc~0; 169306#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 169307#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 169185#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 169186#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 169311#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 169016#L773-45 assume !(1 == ~t7_pc~0); 168547#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 168548#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 169265#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 169266#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 169024#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 168669#L792-45 assume 1 == ~t8_pc~0; 168670#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 169790#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 169791#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 168127#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 168128#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 168617#L811-45 assume !(1 == ~t9_pc~0); 168398#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 168399#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 169684#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 169527#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 169100#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 168876#L830-45 assume !(1 == ~t10_pc~0); 168055#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 168056#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 169210#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 168273#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 168274#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 168036#L849-45 assume 1 == ~t11_pc~0; 168038#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 168487#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 168329#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 168022#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 168023#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 168268#L868-45 assume !(1 == ~t12_pc~0); 168270#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 168213#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 168214#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 169728#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 169936#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 169937#L887-45 assume !(1 == ~t13_pc~0); 168275#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 168276#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 169635#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 169656#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 168244#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 168245#L1439-3 assume !(1 == ~M_E~0); 169628#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 168260#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 168261#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 168418#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 169424#L1459-3 assume !(1 == ~T5_E~0); 169425#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 169940#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 169870#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 169871#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 169942#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 169077#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 169078#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 169781#L1499-3 assume !(1 == ~T13_E~0); 169377#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 169378#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 169884#L1514-3 assume !(1 == ~E_2~0); 169923#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 168991#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 168992#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 169972#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 169289#L1539-3 assume !(1 == ~E_7~0); 168722#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 168723#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 169243#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 168308#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 168309#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 169536#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 169537#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 183161#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 183149#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 179912#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 179913#L1959 assume !(0 == start_simulation_~tmp~3#1); 183431#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 183410#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 183394#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 183391#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 183388#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 183385#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 183381#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 183353#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 170113#L1940-2 [2022-12-13 18:37:31,284 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:31,284 INFO L85 PathProgramCache]: Analyzing trace with hash 846336710, now seen corresponding path program 1 times [2022-12-13 18:37:31,284 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:31,284 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1022913312] [2022-12-13 18:37:31,285 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:31,285 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:31,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:31,391 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:31,391 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:31,391 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1022913312] [2022-12-13 18:37:31,391 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1022913312] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:31,391 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:31,391 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:31,392 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [186028321] [2022-12-13 18:37:31,392 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:31,392 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 18:37:31,392 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:31,392 INFO L85 PathProgramCache]: Analyzing trace with hash -1604046494, now seen corresponding path program 1 times [2022-12-13 18:37:31,392 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:31,392 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [403621815] [2022-12-13 18:37:31,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:31,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:31,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:31,427 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:31,427 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:31,428 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [403621815] [2022-12-13 18:37:31,428 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [403621815] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:31,428 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:31,428 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:31,428 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1652618237] [2022-12-13 18:37:31,428 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:31,428 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:37:31,428 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:37:31,428 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 18:37:31,428 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 18:37:31,429 INFO L87 Difference]: Start difference. First operand 20144 states and 28793 transitions. cyclomatic complexity: 8653 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:31,929 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:37:31,929 INFO L93 Difference]: Finished difference Result 57805 states and 82024 transitions. [2022-12-13 18:37:31,929 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57805 states and 82024 transitions. [2022-12-13 18:37:32,147 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 56663 [2022-12-13 18:37:32,277 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57805 states to 57805 states and 82024 transitions. [2022-12-13 18:37:32,277 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 57805 [2022-12-13 18:37:32,312 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 57805 [2022-12-13 18:37:32,312 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57805 states and 82024 transitions. [2022-12-13 18:37:32,344 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:37:32,344 INFO L218 hiAutomatonCegarLoop]: Abstraction has 57805 states and 82024 transitions. [2022-12-13 18:37:32,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57805 states and 82024 transitions. [2022-12-13 18:37:32,788 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57805 to 56249. [2022-12-13 18:37:32,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 56249 states, 56249 states have (on average 1.4205408096143932) internal successors, (79904), 56248 states have internal predecessors, (79904), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:32,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56249 states to 56249 states and 79904 transitions. [2022-12-13 18:37:32,932 INFO L240 hiAutomatonCegarLoop]: Abstraction has 56249 states and 79904 transitions. [2022-12-13 18:37:32,933 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 18:37:32,934 INFO L428 stractBuchiCegarLoop]: Abstraction has 56249 states and 79904 transitions. [2022-12-13 18:37:32,934 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-12-13 18:37:32,934 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 56249 states and 79904 transitions. [2022-12-13 18:37:33,030 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 55979 [2022-12-13 18:37:33,030 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:37:33,030 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:37:33,031 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:33,031 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:33,032 INFO L748 eck$LassoCheckResult]: Stem: 246213#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 246214#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 247231#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 247232#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 248168#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 247373#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 246802#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 246803#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 247681#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 247682#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 247824#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 247825#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 246547#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 246548#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 247864#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 247117#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 247118#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 247746#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 247029#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 247030#L1291 assume !(0 == ~M_E~0); 248169#L1291-2 assume !(0 == ~T1_E~0); 248166#L1296-1 assume !(0 == ~T2_E~0); 247187#L1301-1 assume !(0 == ~T3_E~0); 247188#L1306-1 assume !(0 == ~T4_E~0); 247762#L1311-1 assume !(0 == ~T5_E~0); 246387#L1316-1 assume !(0 == ~T6_E~0); 246388#L1321-1 assume !(0 == ~T7_E~0); 247203#L1326-1 assume !(0 == ~T8_E~0); 246210#L1331-1 assume !(0 == ~T9_E~0); 245930#L1336-1 assume !(0 == ~T10_E~0); 245931#L1341-1 assume !(0 == ~T11_E~0); 246004#L1346-1 assume !(0 == ~T12_E~0); 246005#L1351-1 assume !(0 == ~T13_E~0); 246326#L1356-1 assume !(0 == ~E_M~0); 246327#L1361-1 assume !(0 == ~E_1~0); 248052#L1366-1 assume !(0 == ~E_2~0); 246371#L1371-1 assume !(0 == ~E_3~0); 246372#L1376-1 assume !(0 == ~E_4~0); 247263#L1381-1 assume !(0 == ~E_5~0); 247264#L1386-1 assume !(0 == ~E_6~0); 248112#L1391-1 assume !(0 == ~E_7~0); 248151#L1396-1 assume !(0 == ~E_8~0); 247149#L1401-1 assume !(0 == ~E_9~0); 247150#L1406-1 assume !(0 == ~E_10~0); 247466#L1411-1 assume !(0 == ~E_11~0); 247467#L1416-1 assume !(0 == ~E_12~0); 247068#L1421-1 assume !(0 == ~E_13~0); 246570#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 246571#L640 assume !(1 == ~m_pc~0); 247273#L640-2 is_master_triggered_~__retres1~0#1 := 0; 247219#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 247076#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 247077#L1603 assume !(0 != activate_threads_~tmp~1#1); 247106#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 246723#L659 assume !(1 == ~t1_pc~0); 246724#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 247920#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 247602#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 246853#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 246854#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 246871#L678 assume !(1 == ~t2_pc~0); 247956#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 248101#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 246412#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 246413#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 246974#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 247099#L697 assume !(1 == ~t3_pc~0); 247100#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 247242#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 248230#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 247009#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 247010#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 248005#L716 assume !(1 == ~t4_pc~0); 247536#L716-2 is_transmit4_triggered_~__retres1~4#1 := 0; 246704#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 246075#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 246076#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 246179#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 247548#L735 assume !(1 == ~t5_pc~0); 246147#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 246148#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 246597#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 247572#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 247179#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 247180#L754 assume !(1 == ~t6_pc~0); 247426#L754-2 is_transmit6_triggered_~__retres1~6#1 := 0; 246815#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 246391#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 246392#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 246787#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 247670#L773 assume !(1 == ~t7_pc~0); 246330#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 246329#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 247220#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 247191#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 247192#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 247254#L792 assume 1 == ~t8_pc~0; 247436#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 247826#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 247827#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 247181#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 247102#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 247103#L811 assume 1 == ~t9_pc~0; 247333#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 247876#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 246468#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 246469#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 247114#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 247115#L830 assume !(1 == ~t10_pc~0); 246824#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 246307#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 246308#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 246286#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 246287#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 247691#L849 assume 1 == ~t11_pc~0; 247692#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 246126#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 246127#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 247711#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 247577#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 247578#L868 assume !(1 == ~t12_pc~0); 246958#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 246957#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 246019#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 246020#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 246341#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 246342#L887 assume 1 == ~t13_pc~0; 247587#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 247003#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 247004#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 247662#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 246058#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 246059#L1439 assume !(1 == ~M_E~0); 247173#L1439-2 assume !(1 == ~T1_E~0); 246223#L1444-1 assume !(1 == ~T2_E~0); 246224#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 246727#L1454-1 assume !(1 == ~T4_E~0); 246728#L1459-1 assume !(1 == ~T5_E~0); 247325#L1464-1 assume !(1 == ~T6_E~0); 247326#L1469-1 assume !(1 == ~T7_E~0); 247404#L1474-1 assume !(1 == ~T8_E~0); 247069#L1479-1 assume !(1 == ~T9_E~0); 247070#L1484-1 assume !(1 == ~T10_E~0); 247329#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 246946#L1494-1 assume !(1 == ~T12_E~0); 246947#L1499-1 assume !(1 == ~T13_E~0); 247134#L1504-1 assume !(1 == ~E_M~0); 247135#L1509-1 assume !(1 == ~E_1~0); 247805#L1514-1 assume !(1 == ~E_2~0); 247438#L1519-1 assume !(1 == ~E_3~0); 247439#L1524-1 assume !(1 == ~E_4~0); 248079#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 248080#L1534-1 assume !(1 == ~E_6~0); 246052#L1539-1 assume !(1 == ~E_7~0); 246053#L1544-1 assume !(1 == ~E_8~0); 246465#L1549-1 assume !(1 == ~E_9~0); 248032#L1554-1 assume !(1 == ~E_10~0); 248030#L1559-1 assume !(1 == ~E_11~0); 247856#L1564-1 assume !(1 == ~E_12~0); 247857#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 248069#L1574-1 assume { :end_inline_reset_delta_events } true; 248121#L1940-2 [2022-12-13 18:37:33,032 INFO L750 eck$LassoCheckResult]: Loop: 248121#L1940-2 assume !false; 279699#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 279695#L1266 assume !false; 279677#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 279678#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 279631#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 279632#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 279598#L1079 assume !(0 != eval_~tmp~0#1); 279600#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 281523#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 281524#L1291-3 assume !(0 == ~M_E~0); 281513#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 281514#L1296-3 assume !(0 == ~T2_E~0); 281503#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 281504#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 281491#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 281492#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 281477#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 281478#L1326-3 assume !(0 == ~T8_E~0); 281464#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 281465#L1336-3 assume !(0 == ~T10_E~0); 281449#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 281450#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 281436#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 281437#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 281421#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 281422#L1366-3 assume !(0 == ~E_2~0); 281406#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 281407#L1376-3 assume !(0 == ~E_4~0); 281393#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 281394#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 281385#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 281386#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 281377#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 281378#L1406-3 assume !(0 == ~E_10~0); 281368#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 281369#L1416-3 assume !(0 == ~E_12~0); 281357#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 281358#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 281347#L640-45 assume !(1 == ~m_pc~0); 281348#L640-47 is_master_triggered_~__retres1~0#1 := 0; 281335#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 281336#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 281323#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 281324#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 281309#L659-45 assume !(1 == ~t1_pc~0); 281310#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 281295#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 281296#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 281280#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 281281#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 281264#L678-45 assume !(1 == ~t2_pc~0); 281263#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 281244#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 281245#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 281227#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 281228#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 281207#L697-45 assume 1 == ~t3_pc~0; 281208#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 281187#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 281188#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 281170#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 281171#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 281154#L716-45 assume !(1 == ~t4_pc~0); 281155#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 281137#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 281138#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 281121#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 281122#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 281105#L735-45 assume 1 == ~t5_pc~0; 281106#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 281090#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 281091#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 281076#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 281077#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 281060#L754-45 assume !(1 == ~t6_pc~0); 281061#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 281044#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 281045#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 281030#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 281031#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 281012#L773-45 assume !(1 == ~t7_pc~0); 281013#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 280996#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 280997#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 280983#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 280984#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 280964#L792-45 assume 1 == ~t8_pc~0; 280965#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 280945#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 280946#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 280929#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 280930#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 280911#L811-45 assume !(1 == ~t9_pc~0); 280912#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 280892#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 280893#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 280876#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 280877#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 280858#L830-45 assume !(1 == ~t10_pc~0); 280860#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 280841#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 280842#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 280827#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 280828#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 280807#L849-45 assume !(1 == ~t11_pc~0); 280808#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 280786#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 280787#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 280771#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 280772#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 280754#L868-45 assume !(1 == ~t12_pc~0); 280756#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 280737#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 280738#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 280721#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 280722#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 280700#L887-45 assume 1 == ~t13_pc~0; 280701#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 280678#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 280679#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 280609#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 280610#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 280590#L1439-3 assume !(1 == ~M_E~0); 279638#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 280574#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 280575#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 280560#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 280561#L1459-3 assume !(1 == ~T5_E~0); 280545#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 280546#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 280529#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 280530#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 280516#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 280517#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 280499#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 280500#L1499-3 assume !(1 == ~T13_E~0); 280482#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 280483#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 280468#L1514-3 assume !(1 == ~E_2~0); 280469#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 280452#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 280453#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 280438#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 280439#L1539-3 assume !(1 == ~E_7~0); 280421#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 280422#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 280404#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 280405#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 280391#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 280392#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 280381#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 280382#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 283118#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 283117#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 283116#L1959 assume !(0 == start_simulation_~tmp~3#1); 280299#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 280000#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 279986#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 279984#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 279982#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 279980#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 279755#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 279726#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 248121#L1940-2 [2022-12-13 18:37:33,032 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:33,032 INFO L85 PathProgramCache]: Analyzing trace with hash -995977081, now seen corresponding path program 1 times [2022-12-13 18:37:33,033 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:33,033 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1709626738] [2022-12-13 18:37:33,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:33,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:33,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:33,094 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:33,095 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:33,095 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1709626738] [2022-12-13 18:37:33,095 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1709626738] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:33,095 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:33,095 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 18:37:33,095 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [866815633] [2022-12-13 18:37:33,095 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:33,096 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 18:37:33,096 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:33,096 INFO L85 PathProgramCache]: Analyzing trace with hash -1466284128, now seen corresponding path program 1 times [2022-12-13 18:37:33,096 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:33,096 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1876383476] [2022-12-13 18:37:33,096 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:33,097 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:33,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:33,145 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:33,145 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:33,145 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1876383476] [2022-12-13 18:37:33,145 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1876383476] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:33,145 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:33,145 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:33,145 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [729478219] [2022-12-13 18:37:33,146 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:33,146 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:37:33,146 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:37:33,146 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 18:37:33,146 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 18:37:33,147 INFO L87 Difference]: Start difference. First operand 56249 states and 79904 transitions. cyclomatic complexity: 23663 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:33,573 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:37:33,573 INFO L93 Difference]: Finished difference Result 108229 states and 153240 transitions. [2022-12-13 18:37:33,573 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 108229 states and 153240 transitions. [2022-12-13 18:37:34,003 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 107792 [2022-12-13 18:37:34,248 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 108229 states to 108229 states and 153240 transitions. [2022-12-13 18:37:34,248 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 108229 [2022-12-13 18:37:34,300 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 108229 [2022-12-13 18:37:34,300 INFO L73 IsDeterministic]: Start isDeterministic. Operand 108229 states and 153240 transitions. [2022-12-13 18:37:34,358 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:37:34,359 INFO L218 hiAutomatonCegarLoop]: Abstraction has 108229 states and 153240 transitions. [2022-12-13 18:37:34,415 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108229 states and 153240 transitions. [2022-12-13 18:37:35,193 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108229 to 108157. [2022-12-13 18:37:35,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108157 states, 108157 states have (on average 1.4161635400390173) internal successors, (153168), 108156 states have internal predecessors, (153168), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:35,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108157 states to 108157 states and 153168 transitions. [2022-12-13 18:37:35,406 INFO L240 hiAutomatonCegarLoop]: Abstraction has 108157 states and 153168 transitions. [2022-12-13 18:37:35,406 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 18:37:35,407 INFO L428 stractBuchiCegarLoop]: Abstraction has 108157 states and 153168 transitions. [2022-12-13 18:37:35,407 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-12-13 18:37:35,407 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108157 states and 153168 transitions. [2022-12-13 18:37:35,674 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 107720 [2022-12-13 18:37:35,674 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:37:35,674 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:37:35,676 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:35,676 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:35,676 INFO L748 eck$LassoCheckResult]: Stem: 410698#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 410699#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 411719#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 411720#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 412680#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 411869#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 411283#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 411284#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 412186#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 412187#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 412319#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 412320#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 411031#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 411032#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 412358#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 411603#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 411604#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 412242#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 411512#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 411513#L1291 assume !(0 == ~M_E~0); 412683#L1291-2 assume !(0 == ~T1_E~0); 412678#L1296-1 assume !(0 == ~T2_E~0); 411676#L1301-1 assume !(0 == ~T3_E~0); 411677#L1306-1 assume !(0 == ~T4_E~0); 412258#L1311-1 assume !(0 == ~T5_E~0); 410872#L1316-1 assume !(0 == ~T6_E~0); 410873#L1321-1 assume !(0 == ~T7_E~0); 411692#L1326-1 assume !(0 == ~T8_E~0); 410695#L1331-1 assume !(0 == ~T9_E~0); 410415#L1336-1 assume !(0 == ~T10_E~0); 410416#L1341-1 assume !(0 == ~T11_E~0); 410488#L1346-1 assume !(0 == ~T12_E~0); 410489#L1351-1 assume !(0 == ~T13_E~0); 410810#L1356-1 assume !(0 == ~E_M~0); 410811#L1361-1 assume !(0 == ~E_1~0); 412569#L1366-1 assume !(0 == ~E_2~0); 410856#L1371-1 assume !(0 == ~E_3~0); 410857#L1376-1 assume !(0 == ~E_4~0); 411750#L1381-1 assume !(0 == ~E_5~0); 411751#L1386-1 assume !(0 == ~E_6~0); 412627#L1391-1 assume !(0 == ~E_7~0); 412658#L1396-1 assume !(0 == ~E_8~0); 411638#L1401-1 assume !(0 == ~E_9~0); 411639#L1406-1 assume !(0 == ~E_10~0); 411964#L1411-1 assume !(0 == ~E_11~0); 411965#L1416-1 assume !(0 == ~E_12~0); 411555#L1421-1 assume !(0 == ~E_13~0); 411055#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 411056#L640 assume !(1 == ~m_pc~0); 411760#L640-2 is_master_triggered_~__retres1~0#1 := 0; 411708#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 411562#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 411563#L1603 assume !(0 != activate_threads_~tmp~1#1); 411592#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 411208#L659 assume !(1 == ~t1_pc~0); 411209#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 412423#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 412105#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 411335#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 411336#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 411354#L678 assume !(1 == ~t2_pc~0); 412462#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 412617#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 410897#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 410898#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 411453#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 411585#L697 assume !(1 == ~t3_pc~0); 411586#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 411731#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 412747#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 411491#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 411492#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 412520#L716 assume !(1 == ~t4_pc~0); 412038#L716-2 is_transmit4_triggered_~__retres1~4#1 := 0; 411188#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 410560#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 410561#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 410664#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 412050#L735 assume !(1 == ~t5_pc~0); 410632#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 410633#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 411084#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 412078#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 411669#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 411670#L754 assume !(1 == ~t6_pc~0); 411924#L754-2 is_transmit6_triggered_~__retres1~6#1 := 0; 411297#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 410876#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 410877#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 411270#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 412176#L773 assume !(1 == ~t7_pc~0); 410814#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 410813#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 411710#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 411680#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 411681#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 411742#L792 assume !(1 == ~t8_pc~0); 411934#L792-2 is_transmit8_triggered_~__retres1~8#1 := 0; 412321#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 412322#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 411671#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 411588#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 411589#L811 assume 1 == ~t9_pc~0; 411822#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 412371#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 410953#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 410954#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 411600#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 411601#L830 assume !(1 == ~t10_pc~0); 411306#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 410791#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 410792#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 410770#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 410771#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 412195#L849 assume 1 == ~t11_pc~0; 412196#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 410611#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 410612#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 412211#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 412082#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 412083#L868 assume !(1 == ~t12_pc~0); 411437#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 411436#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 410503#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 410504#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 410825#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 410826#L887 assume 1 == ~t13_pc~0; 412091#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 411485#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 411486#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 412167#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 410543#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 410544#L1439 assume !(1 == ~M_E~0); 411663#L1439-2 assume !(1 == ~T1_E~0); 410708#L1444-1 assume !(1 == ~T2_E~0); 410709#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 411212#L1454-1 assume !(1 == ~T4_E~0); 411213#L1459-1 assume !(1 == ~T5_E~0); 411814#L1464-1 assume !(1 == ~T6_E~0); 411815#L1469-1 assume !(1 == ~T7_E~0); 411902#L1474-1 assume !(1 == ~T8_E~0); 411556#L1479-1 assume !(1 == ~T9_E~0); 411557#L1484-1 assume !(1 == ~T10_E~0); 411818#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 411425#L1494-1 assume !(1 == ~T12_E~0); 411426#L1499-1 assume !(1 == ~T13_E~0); 411623#L1504-1 assume !(1 == ~E_M~0); 411624#L1509-1 assume !(1 == ~E_1~0); 412301#L1514-1 assume !(1 == ~E_2~0); 411935#L1519-1 assume !(1 == ~E_3~0); 411936#L1524-1 assume !(1 == ~E_4~0); 412592#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 412593#L1534-1 assume !(1 == ~E_6~0); 410537#L1539-1 assume !(1 == ~E_7~0); 410538#L1544-1 assume !(1 == ~E_8~0); 410950#L1549-1 assume !(1 == ~E_9~0); 412550#L1554-1 assume !(1 == ~E_10~0); 412546#L1559-1 assume !(1 == ~E_11~0); 412350#L1564-1 assume !(1 == ~E_12~0); 412351#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 412585#L1574-1 assume { :end_inline_reset_delta_events } true; 412637#L1940-2 [2022-12-13 18:37:35,677 INFO L750 eck$LassoCheckResult]: Loop: 412637#L1940-2 assume !false; 438545#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 438539#L1266 assume !false; 438536#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 438537#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 438502#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 438499#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 438496#L1079 assume !(0 != eval_~tmp~0#1); 438498#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 447219#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 447204#L1291-3 assume !(0 == ~M_E~0); 447202#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 447200#L1296-3 assume !(0 == ~T2_E~0); 447197#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 447196#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 447194#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 447192#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 447190#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 447188#L1326-3 assume !(0 == ~T8_E~0); 447186#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 447184#L1336-3 assume !(0 == ~T10_E~0); 447182#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 447180#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 447178#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 447176#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 447174#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 447172#L1366-3 assume !(0 == ~E_2~0); 447169#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 447167#L1376-3 assume !(0 == ~E_4~0); 447165#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 447163#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 447161#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 447159#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 447157#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 447154#L1406-3 assume !(0 == ~E_10~0); 447152#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 447150#L1416-3 assume !(0 == ~E_12~0); 447147#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 447145#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 447143#L640-45 assume !(1 == ~m_pc~0); 447141#L640-47 is_master_triggered_~__retres1~0#1 := 0; 447139#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 447137#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 447135#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 447133#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 447131#L659-45 assume !(1 == ~t1_pc~0); 447130#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 447129#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 447127#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 447126#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 447125#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 447124#L678-45 assume !(1 == ~t2_pc~0); 447122#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 447120#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 447118#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 447116#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 447114#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 447112#L697-45 assume 1 == ~t3_pc~0; 447110#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 447111#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 447128#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 447101#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 447098#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 447096#L716-45 assume !(1 == ~t4_pc~0); 447094#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 447092#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 447090#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 447088#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 447086#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 447084#L735-45 assume !(1 == ~t5_pc~0); 447082#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 447079#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 447077#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 447075#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 447072#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 447070#L754-45 assume !(1 == ~t6_pc~0); 447068#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 447066#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 447064#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 447062#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 447060#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 447058#L773-45 assume 1 == ~t7_pc~0; 447054#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 447052#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 447050#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 447047#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 447045#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 447043#L792-45 assume !(1 == ~t8_pc~0); 447041#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 447039#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 447037#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 447034#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 447032#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 447030#L811-45 assume 1 == ~t9_pc~0; 447028#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 447025#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 447023#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 447020#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 447018#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 447016#L830-45 assume !(1 == ~t10_pc~0); 447014#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 447011#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 447009#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 447006#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 447004#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 447002#L849-45 assume !(1 == ~t11_pc~0); 446999#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 446997#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 446995#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 446992#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 446990#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 446988#L868-45 assume !(1 == ~t12_pc~0); 446986#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 446983#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 446980#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 446978#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 446976#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 446974#L887-45 assume 1 == ~t13_pc~0; 446972#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 446969#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 446967#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 446965#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 446963#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 446961#L1439-3 assume !(1 == ~M_E~0); 446957#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 446955#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 446953#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 446951#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 446949#L1459-3 assume !(1 == ~T5_E~0); 446947#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 446945#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 446943#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 446941#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 446939#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 446937#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 446935#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 446933#L1499-3 assume !(1 == ~T13_E~0); 446931#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 446929#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 446927#L1514-3 assume !(1 == ~E_2~0); 446925#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 446923#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 446922#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 446921#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 446920#L1539-3 assume !(1 == ~E_7~0); 446919#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 446918#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 446917#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 446916#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 446915#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 446914#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 446913#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 446911#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 446898#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 446897#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 446895#L1959 assume !(0 == start_simulation_~tmp~3#1); 446893#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 446891#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 446878#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 446877#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 446876#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 446875#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 446874#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 446873#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 412637#L1940-2 [2022-12-13 18:37:35,677 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:35,677 INFO L85 PathProgramCache]: Analyzing trace with hash -618334264, now seen corresponding path program 1 times [2022-12-13 18:37:35,677 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:35,677 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1972830123] [2022-12-13 18:37:35,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:35,678 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:35,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:35,837 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:35,837 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:35,837 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1972830123] [2022-12-13 18:37:35,837 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1972830123] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:35,838 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:35,838 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:35,838 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [744080449] [2022-12-13 18:37:35,838 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:35,838 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 18:37:35,839 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:35,839 INFO L85 PathProgramCache]: Analyzing trace with hash -80205472, now seen corresponding path program 1 times [2022-12-13 18:37:35,839 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:35,839 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [249838387] [2022-12-13 18:37:35,839 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:35,840 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:35,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:35,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:35,885 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:35,885 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [249838387] [2022-12-13 18:37:35,885 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [249838387] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:35,886 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:35,886 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:35,886 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1940245205] [2022-12-13 18:37:35,886 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:35,886 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:37:35,886 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:37:35,887 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 18:37:35,887 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 18:37:35,887 INFO L87 Difference]: Start difference. First operand 108157 states and 153168 transitions. cyclomatic complexity: 45027 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:36,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:37:36,968 INFO L93 Difference]: Finished difference Result 309716 states and 435997 transitions. [2022-12-13 18:37:36,968 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 309716 states and 435997 transitions. [2022-12-13 18:37:38,251 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 305200 [2022-12-13 18:37:38,769 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 309716 states to 309716 states and 435997 transitions. [2022-12-13 18:37:38,769 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 309716 [2022-12-13 18:37:38,857 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 309716 [2022-12-13 18:37:38,857 INFO L73 IsDeterministic]: Start isDeterministic. Operand 309716 states and 435997 transitions. [2022-12-13 18:37:38,952 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:37:38,952 INFO L218 hiAutomatonCegarLoop]: Abstraction has 309716 states and 435997 transitions. [2022-12-13 18:37:39,059 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 309716 states and 435997 transitions. [2022-12-13 18:37:41,252 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 309716 to 303492. [2022-12-13 18:37:41,370 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 303492 states, 303492 states have (on average 1.4091343429151344) internal successors, (427661), 303491 states have internal predecessors, (427661), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:41,962 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 303492 states to 303492 states and 427661 transitions. [2022-12-13 18:37:41,962 INFO L240 hiAutomatonCegarLoop]: Abstraction has 303492 states and 427661 transitions. [2022-12-13 18:37:41,963 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 18:37:41,963 INFO L428 stractBuchiCegarLoop]: Abstraction has 303492 states and 427661 transitions. [2022-12-13 18:37:41,963 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-12-13 18:37:41,963 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 303492 states and 427661 transitions. [2022-12-13 18:37:42,562 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 302608 [2022-12-13 18:37:42,562 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:37:42,562 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:37:42,563 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:42,563 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:42,564 INFO L748 eck$LassoCheckResult]: Stem: 828585#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 828586#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 829627#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 829628#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 830621#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 829774#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 829178#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 829179#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 830092#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 830093#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 830233#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 830234#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 828927#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 828928#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 830273#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 829507#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 829508#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 830160#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 829421#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 829422#L1291 assume !(0 == ~M_E~0); 830622#L1291-2 assume !(0 == ~T1_E~0); 830617#L1296-1 assume !(0 == ~T2_E~0); 829575#L1301-1 assume !(0 == ~T3_E~0); 829576#L1306-1 assume !(0 == ~T4_E~0); 830173#L1311-1 assume !(0 == ~T5_E~0); 828759#L1316-1 assume !(0 == ~T6_E~0); 828760#L1321-1 assume !(0 == ~T7_E~0); 829591#L1326-1 assume !(0 == ~T8_E~0); 828582#L1331-1 assume !(0 == ~T9_E~0); 828298#L1336-1 assume !(0 == ~T10_E~0); 828299#L1341-1 assume !(0 == ~T11_E~0); 828372#L1346-1 assume !(0 == ~T12_E~0); 828373#L1351-1 assume !(0 == ~T13_E~0); 828700#L1356-1 assume !(0 == ~E_M~0); 828701#L1361-1 assume !(0 == ~E_1~0); 830480#L1366-1 assume !(0 == ~E_2~0); 828742#L1371-1 assume !(0 == ~E_3~0); 828743#L1376-1 assume !(0 == ~E_4~0); 829657#L1381-1 assume !(0 == ~E_5~0); 829658#L1386-1 assume !(0 == ~E_6~0); 830544#L1391-1 assume !(0 == ~E_7~0); 830593#L1396-1 assume !(0 == ~E_8~0); 829538#L1401-1 assume !(0 == ~E_9~0); 829539#L1406-1 assume !(0 == ~E_10~0); 829878#L1411-1 assume !(0 == ~E_11~0); 829879#L1416-1 assume !(0 == ~E_12~0); 829460#L1421-1 assume !(0 == ~E_13~0); 828951#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 828952#L640 assume !(1 == ~m_pc~0); 829668#L640-2 is_master_triggered_~__retres1~0#1 := 0; 829614#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 829467#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 829468#L1603 assume !(0 != activate_threads_~tmp~1#1); 829496#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 829103#L659 assume !(1 == ~t1_pc~0); 829104#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 830335#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 830015#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 829237#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 829238#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 829255#L678 assume !(1 == ~t2_pc~0); 830364#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 830529#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 828785#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 828786#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 829360#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 829491#L697 assume !(1 == ~t3_pc~0); 829492#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 829637#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 830694#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 829399#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 829400#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 830424#L716 assume !(1 == ~t4_pc~0); 829951#L716-2 is_transmit4_triggered_~__retres1~4#1 := 0; 829086#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 828447#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 828448#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 828549#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 829963#L735 assume !(1 == ~t5_pc~0); 828517#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 828518#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 828979#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 829989#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 829568#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 829569#L754 assume !(1 == ~t6_pc~0); 829835#L754-2 is_transmit6_triggered_~__retres1~6#1 := 0; 829193#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 828763#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 828764#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 829165#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 830082#L773 assume !(1 == ~t7_pc~0); 828704#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 828703#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 829615#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 829579#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 829580#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 829649#L792 assume !(1 == ~t8_pc~0); 829847#L792-2 is_transmit8_triggered_~__retres1~8#1 := 0; 830235#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 830236#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 829572#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 829494#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 829495#L811 assume !(1 == ~t9_pc~0); 829730#L811-2 is_transmit9_triggered_~__retres1~9#1 := 0; 830315#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 828842#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 828843#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 829504#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 829505#L830 assume !(1 == ~t10_pc~0); 829206#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 828679#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 828680#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 828658#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 828659#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 830102#L849 assume 1 == ~t11_pc~0; 830103#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 828496#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 828497#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 830121#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 829995#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 829996#L868 assume !(1 == ~t12_pc~0); 829344#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 829343#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 828388#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 828389#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 828715#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 828716#L887 assume 1 == ~t13_pc~0; 830004#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 829393#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 829394#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 830075#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 828428#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 828429#L1439 assume !(1 == ~M_E~0); 829564#L1439-2 assume !(1 == ~T1_E~0); 828595#L1444-1 assume !(1 == ~T2_E~0); 828596#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 829108#L1454-1 assume !(1 == ~T4_E~0); 829109#L1459-1 assume !(1 == ~T5_E~0); 829722#L1464-1 assume !(1 == ~T6_E~0); 829723#L1469-1 assume !(1 == ~T7_E~0); 829814#L1474-1 assume !(1 == ~T8_E~0); 829461#L1479-1 assume !(1 == ~T9_E~0); 829462#L1484-1 assume !(1 == ~T10_E~0); 829725#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 829335#L1494-1 assume !(1 == ~T12_E~0); 829336#L1499-1 assume !(1 == ~T13_E~0); 829523#L1504-1 assume !(1 == ~E_M~0); 829524#L1509-1 assume !(1 == ~E_1~0); 830216#L1514-1 assume !(1 == ~E_2~0); 829848#L1519-1 assume !(1 == ~E_3~0); 829849#L1524-1 assume !(1 == ~E_4~0); 830508#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 830509#L1534-1 assume !(1 == ~E_6~0); 828423#L1539-1 assume !(1 == ~E_7~0); 828424#L1544-1 assume !(1 == ~E_8~0); 828841#L1549-1 assume !(1 == ~E_9~0); 830461#L1554-1 assume !(1 == ~E_10~0); 830453#L1559-1 assume !(1 == ~E_11~0); 830264#L1564-1 assume !(1 == ~E_12~0); 830265#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 830500#L1574-1 assume { :end_inline_reset_delta_events } true; 830554#L1940-2 [2022-12-13 18:37:42,564 INFO L750 eck$LassoCheckResult]: Loop: 830554#L1940-2 assume !false; 975943#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 975941#L1266 assume !false; 975940#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 975930#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 975922#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 975921#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 975919#L1079 assume !(0 != eval_~tmp~0#1); 975920#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 979423#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 979419#L1291-3 assume !(0 == ~M_E~0); 979415#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 979410#L1296-3 assume !(0 == ~T2_E~0); 979406#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 979400#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 979394#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 979388#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 979382#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 979376#L1326-3 assume !(0 == ~T8_E~0); 979371#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 979365#L1336-3 assume !(0 == ~T10_E~0); 979360#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 979355#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 979350#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 979347#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 979343#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 979339#L1366-3 assume !(0 == ~E_2~0); 978624#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 978622#L1376-3 assume !(0 == ~E_4~0); 978620#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 978619#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 978618#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 978615#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 978613#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 978611#L1406-3 assume !(0 == ~E_10~0); 978609#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 978607#L1416-3 assume !(0 == ~E_12~0); 978605#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 978603#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 978601#L640-45 assume !(1 == ~m_pc~0); 978599#L640-47 is_master_triggered_~__retres1~0#1 := 0; 978597#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 978595#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 978593#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 978033#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 975229#L659-45 assume !(1 == ~t1_pc~0); 975230#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 975216#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 975217#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 975204#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 975205#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 975192#L678-45 assume !(1 == ~t2_pc~0); 975191#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 975180#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 975181#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 975168#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 975169#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 971544#L697-45 assume !(1 == ~t3_pc~0); 971546#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 971536#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 971537#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 971531#L1627-45 assume !(0 != activate_threads_~tmp___2~0#1); 971530#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 971523#L716-45 assume !(1 == ~t4_pc~0); 971524#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 971517#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 971518#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 971511#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 971512#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 971503#L735-45 assume 1 == ~t5_pc~0; 971504#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 971495#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 971496#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 971489#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 971490#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 971482#L754-45 assume !(1 == ~t6_pc~0); 971483#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 971476#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 971477#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 971470#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 971471#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 971462#L773-45 assume 1 == ~t7_pc~0; 971464#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 971453#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 971454#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 971447#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 971448#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 971441#L792-45 assume !(1 == ~t8_pc~0); 971442#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 971434#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 971435#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 971428#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 971429#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 970130#L811-45 assume !(1 == ~t9_pc~0); 970131#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 970124#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 970125#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 970118#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 970119#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 970110#L830-45 assume 1 == ~t10_pc~0; 970111#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 970103#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 970104#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 970097#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 970098#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 970088#L849-45 assume 1 == ~t11_pc~0; 970090#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 970081#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 970082#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 970074#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 970075#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 970067#L868-45 assume 1 == ~t12_pc~0; 970068#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 970060#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 970061#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 970054#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 970055#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 970047#L887-45 assume 1 == ~t13_pc~0; 970048#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 970039#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 970040#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 970033#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 970034#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 970027#L1439-3 assume !(1 == ~M_E~0); 970028#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 970021#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 970022#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 970015#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 970016#L1459-3 assume !(1 == ~T5_E~0); 970009#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 970010#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 970002#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 970003#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 969996#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 969997#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 969990#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 969991#L1499-3 assume !(1 == ~T13_E~0); 969984#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 969985#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 969978#L1514-3 assume !(1 == ~E_2~0); 969979#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 969972#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 969973#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 969966#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 969967#L1539-3 assume !(1 == ~E_7~0); 969960#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 969961#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 969954#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 969955#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 969947#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 969948#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 969941#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 969942#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 975969#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 975968#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 975966#L1959 assume !(0 == start_simulation_~tmp~3#1); 975964#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 975962#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 975949#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 975948#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 975947#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 975946#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 975945#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 975944#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 830554#L1940-2 [2022-12-13 18:37:42,564 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:42,564 INFO L85 PathProgramCache]: Analyzing trace with hash -1649665079, now seen corresponding path program 1 times [2022-12-13 18:37:42,564 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:42,564 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2042788173] [2022-12-13 18:37:42,564 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:42,565 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:42,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:42,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:42,614 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:42,614 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2042788173] [2022-12-13 18:37:42,614 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2042788173] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:42,614 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:42,615 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 18:37:42,615 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1760793465] [2022-12-13 18:37:42,615 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:42,615 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 18:37:42,615 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:42,615 INFO L85 PathProgramCache]: Analyzing trace with hash -1643316000, now seen corresponding path program 1 times [2022-12-13 18:37:42,616 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:42,616 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [905691647] [2022-12-13 18:37:42,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:42,616 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:42,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:42,647 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:42,648 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:42,648 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [905691647] [2022-12-13 18:37:42,648 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [905691647] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:42,648 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:42,648 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:42,648 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1674966302] [2022-12-13 18:37:42,648 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:42,649 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:37:42,649 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:37:42,649 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 18:37:42,649 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 18:37:42,649 INFO L87 Difference]: Start difference. First operand 303492 states and 427661 transitions. cyclomatic complexity: 124201 Second operand has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:44,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:37:44,542 INFO L93 Difference]: Finished difference Result 710321 states and 1011636 transitions. [2022-12-13 18:37:44,542 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 710321 states and 1011636 transitions. [2022-12-13 18:37:46,956 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 707964 [2022-12-13 18:37:48,242 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 710321 states to 710321 states and 1011636 transitions. [2022-12-13 18:37:48,243 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 710321 [2022-12-13 18:37:48,390 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 710321 [2022-12-13 18:37:48,390 INFO L73 IsDeterministic]: Start isDeterministic. Operand 710321 states and 1011636 transitions. [2022-12-13 18:37:48,587 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:37:48,587 INFO L218 hiAutomatonCegarLoop]: Abstraction has 710321 states and 1011636 transitions. [2022-12-13 18:37:48,837 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 710321 states and 1011636 transitions. [2022-12-13 18:37:51,939 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 710321 to 311139. [2022-12-13 18:37:52,126 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 311139 states, 311139 states have (on average 1.3990788682871642) internal successors, (435308), 311138 states have internal predecessors, (435308), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:52,770 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 311139 states to 311139 states and 435308 transitions. [2022-12-13 18:37:52,770 INFO L240 hiAutomatonCegarLoop]: Abstraction has 311139 states and 435308 transitions. [2022-12-13 18:37:52,771 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 18:37:52,771 INFO L428 stractBuchiCegarLoop]: Abstraction has 311139 states and 435308 transitions. [2022-12-13 18:37:52,771 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-12-13 18:37:52,772 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 311139 states and 435308 transitions. [2022-12-13 18:37:53,603 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 310252 [2022-12-13 18:37:53,603 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:37:53,603 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:37:53,604 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:53,604 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:37:53,605 INFO L748 eck$LassoCheckResult]: Stem: 1842407#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1842408#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1843433#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1843434#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1844402#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 1843574#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1842994#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1842995#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1843900#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1843901#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1844048#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1844049#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1842740#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1842741#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1844091#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1843317#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1843318#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1843965#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1843228#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1843229#L1291 assume !(0 == ~M_E~0); 1844403#L1291-2 assume !(0 == ~T1_E~0); 1844400#L1296-1 assume !(0 == ~T2_E~0); 1843385#L1301-1 assume !(0 == ~T3_E~0); 1843386#L1306-1 assume !(0 == ~T4_E~0); 1843984#L1311-1 assume !(0 == ~T5_E~0); 1842578#L1316-1 assume !(0 == ~T6_E~0); 1842579#L1321-1 assume !(0 == ~T7_E~0); 1843401#L1326-1 assume !(0 == ~T8_E~0); 1842404#L1331-1 assume !(0 == ~T9_E~0); 1842124#L1336-1 assume !(0 == ~T10_E~0); 1842125#L1341-1 assume !(0 == ~T11_E~0); 1842198#L1346-1 assume !(0 == ~T12_E~0); 1842199#L1351-1 assume !(0 == ~T13_E~0); 1842518#L1356-1 assume !(0 == ~E_M~0); 1842519#L1361-1 assume !(0 == ~E_1~0); 1844282#L1366-1 assume !(0 == ~E_2~0); 1842561#L1371-1 assume !(0 == ~E_3~0); 1842562#L1376-1 assume !(0 == ~E_4~0); 1843461#L1381-1 assume !(0 == ~E_5~0); 1843462#L1386-1 assume !(0 == ~E_6~0); 1844342#L1391-1 assume !(0 == ~E_7~0); 1844383#L1396-1 assume !(0 == ~E_8~0); 1843351#L1401-1 assume !(0 == ~E_9~0); 1843352#L1406-1 assume !(0 == ~E_10~0); 1843673#L1411-1 assume !(0 == ~E_11~0); 1843674#L1416-1 assume !(0 == ~E_12~0); 1843269#L1421-1 assume !(0 == ~E_13~0); 1842763#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1842764#L640 assume !(1 == ~m_pc~0); 1843471#L640-2 is_master_triggered_~__retres1~0#1 := 0; 1843421#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1843276#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1843277#L1603 assume !(0 != activate_threads_~tmp~1#1); 1843306#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1842918#L659 assume !(1 == ~t1_pc~0); 1842919#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1844155#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1843824#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1843051#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 1843052#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1843069#L678 assume !(1 == ~t2_pc~0); 1844188#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1844332#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1842603#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1842604#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 1843171#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1843299#L697 assume !(1 == ~t3_pc~0); 1843300#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1843442#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1844469#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1843207#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 1843208#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1844238#L716 assume !(1 == ~t4_pc~0); 1843752#L716-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1842899#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1842268#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1842269#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 1842373#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1843763#L735 assume !(1 == ~t5_pc~0); 1842341#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1842342#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1842794#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1843793#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 1843378#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1843379#L754 assume !(1 == ~t6_pc~0); 1843631#L754-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1843008#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1842582#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1842583#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 1842980#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1843891#L773 assume !(1 == ~t7_pc~0); 1842522#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1842521#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1843422#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1843389#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 1843390#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1843453#L792 assume !(1 == ~t8_pc~0); 1843642#L792-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1844050#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1844051#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1843380#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 1843302#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1843303#L811 assume !(1 == ~t9_pc~0); 1843533#L811-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1844135#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1842659#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1842660#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 1843314#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1843315#L830 assume !(1 == ~t10_pc~0); 1843019#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1842499#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1842500#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1842478#L1683 assume !(0 != activate_threads_~tmp___9~0#1); 1842479#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1843911#L849 assume 1 == ~t11_pc~0; 1843912#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1842320#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1842321#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1843930#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 1843800#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1843801#L868 assume !(1 == ~t12_pc~0); 1843155#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1843154#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1842213#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1842214#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 1842533#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1842534#L887 assume 1 == ~t13_pc~0; 1843810#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1843201#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1843202#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1843885#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 1842251#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1842252#L1439 assume !(1 == ~M_E~0); 1843372#L1439-2 assume !(1 == ~T1_E~0); 1842417#L1444-1 assume !(1 == ~T2_E~0); 1842418#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1842922#L1454-1 assume !(1 == ~T4_E~0); 1842923#L1459-1 assume !(1 == ~T5_E~0); 1843524#L1464-1 assume !(1 == ~T6_E~0); 1843525#L1469-1 assume !(1 == ~T7_E~0); 1843606#L1474-1 assume !(1 == ~T8_E~0); 1843270#L1479-1 assume !(1 == ~T9_E~0); 1843271#L1484-1 assume !(1 == ~T10_E~0); 1843529#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1843142#L1494-1 assume !(1 == ~T12_E~0); 1843143#L1499-1 assume !(1 == ~T13_E~0); 1843334#L1504-1 assume !(1 == ~E_M~0); 1843335#L1509-1 assume !(1 == ~E_1~0); 1844027#L1514-1 assume !(1 == ~E_2~0); 1843643#L1519-1 assume !(1 == ~E_3~0); 1843644#L1524-1 assume !(1 == ~E_4~0); 1844309#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1844310#L1534-1 assume !(1 == ~E_6~0); 1842246#L1539-1 assume !(1 == ~E_7~0); 1842247#L1544-1 assume !(1 == ~E_8~0); 1842656#L1549-1 assume !(1 == ~E_9~0); 1844266#L1554-1 assume !(1 == ~E_10~0); 1844261#L1559-1 assume !(1 == ~E_11~0); 1844082#L1564-1 assume !(1 == ~E_12~0); 1844083#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 1844300#L1574-1 assume { :end_inline_reset_delta_events } true; 1844351#L1940-2 [2022-12-13 18:37:53,605 INFO L750 eck$LassoCheckResult]: Loop: 1844351#L1940-2 assume !false; 1924129#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1924121#L1266 assume !false; 1924122#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1919256#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1919249#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1919242#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1919243#L1079 assume !(0 != eval_~tmp~0#1); 1933321#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1933319#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1933317#L1291-3 assume !(0 == ~M_E~0); 1933315#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1933313#L1296-3 assume !(0 == ~T2_E~0); 1933311#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1933233#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1933230#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1933151#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1933146#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1933142#L1326-3 assume !(0 == ~T8_E~0); 1933137#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1933133#L1336-3 assume !(0 == ~T10_E~0); 1933129#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1933125#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1933120#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1933116#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1933111#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1933107#L1366-3 assume !(0 == ~E_2~0); 1933103#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1933030#L1376-3 assume !(0 == ~E_4~0); 1933024#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1932941#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1932934#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1932929#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1932923#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1932916#L1406-3 assume !(0 == ~E_10~0); 1932911#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1932904#L1416-3 assume !(0 == ~E_12~0); 1932899#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1932895#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1932894#L640-45 assume !(1 == ~m_pc~0); 1932893#L640-47 is_master_triggered_~__retres1~0#1 := 0; 1932892#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1932891#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1932890#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1932889#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1932888#L659-45 assume !(1 == ~t1_pc~0); 1932887#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 1932886#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1932885#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1932884#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1932883#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1932882#L678-45 assume !(1 == ~t2_pc~0); 1932880#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 1932879#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1932878#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1932877#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1932876#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1932875#L697-45 assume 1 == ~t3_pc~0; 1932873#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1932871#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1932869#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1932867#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1932866#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1932865#L716-45 assume !(1 == ~t4_pc~0); 1932864#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 1932863#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1932862#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1932861#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1932860#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1932859#L735-45 assume 1 == ~t5_pc~0; 1932857#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1932856#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1932855#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1932854#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1932853#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1932852#L754-45 assume !(1 == ~t6_pc~0); 1932851#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 1932850#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1932849#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1932848#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1932847#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1932846#L773-45 assume !(1 == ~t7_pc~0); 1932845#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 1932842#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1932840#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1932838#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 1932836#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1932834#L792-45 assume !(1 == ~t8_pc~0); 1932832#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 1932829#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1932827#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1932825#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1932823#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1932821#L811-45 assume !(1 == ~t9_pc~0); 1932819#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 1932817#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1932814#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1932811#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1932808#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1932807#L830-45 assume 1 == ~t10_pc~0; 1932805#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1932803#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1932801#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1932799#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1932746#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1932742#L849-45 assume !(1 == ~t11_pc~0); 1932737#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 1932732#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1932727#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1932723#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1932718#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1932714#L868-45 assume 1 == ~t12_pc~0; 1932709#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1932703#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1932624#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1932620#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1932617#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1932611#L887-45 assume 1 == ~t13_pc~0; 1932607#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1932601#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1932597#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1932524#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1932519#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1932515#L1439-3 assume !(1 == ~M_E~0); 1931102#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1932506#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1932501#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1932496#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1932491#L1459-3 assume !(1 == ~T5_E~0); 1932486#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1932480#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1932475#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1932470#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1932465#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1932460#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1932455#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1932449#L1499-3 assume !(1 == ~T13_E~0); 1932444#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1932370#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1932364#L1514-3 assume !(1 == ~E_2~0); 1932358#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1932353#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1932349#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1932346#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1932331#L1539-3 assume !(1 == ~E_7~0); 1932314#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1932310#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1932306#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1932302#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1932299#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1932296#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1932293#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1932181#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1932165#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1932162#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1932158#L1959 assume !(0 == start_simulation_~tmp~3#1); 1932159#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1924170#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1924154#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1924152#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 1924150#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1924148#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1924149#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1924135#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 1844351#L1940-2 [2022-12-13 18:37:53,605 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:53,606 INFO L85 PathProgramCache]: Analyzing trace with hash -1665183797, now seen corresponding path program 1 times [2022-12-13 18:37:53,606 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:53,606 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [185967596] [2022-12-13 18:37:53,606 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:53,606 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:53,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:53,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:53,659 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:53,659 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [185967596] [2022-12-13 18:37:53,659 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [185967596] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:53,660 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:53,660 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:53,660 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1497455790] [2022-12-13 18:37:53,660 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:53,660 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 18:37:53,661 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:37:53,661 INFO L85 PathProgramCache]: Analyzing trace with hash 882505055, now seen corresponding path program 1 times [2022-12-13 18:37:53,661 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:37:53,661 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1494181912] [2022-12-13 18:37:53,661 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:37:53,661 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:37:53,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:37:53,691 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:37:53,691 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:37:53,691 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1494181912] [2022-12-13 18:37:53,691 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1494181912] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:37:53,691 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:37:53,691 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:37:53,691 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [56396817] [2022-12-13 18:37:53,692 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:37:53,692 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:37:53,692 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:37:53,692 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 18:37:53,692 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 18:37:53,693 INFO L87 Difference]: Start difference. First operand 311139 states and 435308 transitions. cyclomatic complexity: 124201 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:37:56,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:37:56,368 INFO L93 Difference]: Finished difference Result 886882 states and 1234609 transitions. [2022-12-13 18:37:56,368 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 886882 states and 1234609 transitions. [2022-12-13 18:37:59,444 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 877020 [2022-12-13 18:38:01,373 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 886882 states to 886882 states and 1234609 transitions. [2022-12-13 18:38:01,374 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 886882 [2022-12-13 18:38:01,605 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 886882 [2022-12-13 18:38:01,605 INFO L73 IsDeterministic]: Start isDeterministic. Operand 886882 states and 1234609 transitions. [2022-12-13 18:38:01,852 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:38:01,852 INFO L218 hiAutomatonCegarLoop]: Abstraction has 886882 states and 1234609 transitions. [2022-12-13 18:38:02,165 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 886882 states and 1234609 transitions. [2022-12-13 18:38:08,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 886882 to 874338. [2022-12-13 18:38:09,044 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 874338 states, 874338 states have (on average 1.393256383686858) internal successors, (1218177), 874337 states have internal predecessors, (1218177), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:38:10,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 874338 states to 874338 states and 1218177 transitions. [2022-12-13 18:38:10,934 INFO L240 hiAutomatonCegarLoop]: Abstraction has 874338 states and 1218177 transitions. [2022-12-13 18:38:10,935 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 18:38:10,935 INFO L428 stractBuchiCegarLoop]: Abstraction has 874338 states and 1218177 transitions. [2022-12-13 18:38:10,936 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2022-12-13 18:38:10,936 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 874338 states and 1218177 transitions. [2022-12-13 18:38:13,008 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 872268 [2022-12-13 18:38:13,008 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 18:38:13,008 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 18:38:13,009 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:38:13,009 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 18:38:13,010 INFO L748 eck$LassoCheckResult]: Stem: 3040439#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 3040440#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 3041483#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3041484#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3042498#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 3041626#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3041032#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3041033#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3041955#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3041956#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3042096#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3042097#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3040775#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3040776#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3042137#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3041366#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 3041367#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 3042022#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 3041274#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3041275#L1291 assume !(0 == ~M_E~0); 3042499#L1291-2 assume !(0 == ~T1_E~0); 3042493#L1296-1 assume !(0 == ~T2_E~0); 3041435#L1301-1 assume !(0 == ~T3_E~0); 3041436#L1306-1 assume !(0 == ~T4_E~0); 3042036#L1311-1 assume !(0 == ~T5_E~0); 3040613#L1316-1 assume !(0 == ~T6_E~0); 3040614#L1321-1 assume !(0 == ~T7_E~0); 3041450#L1326-1 assume !(0 == ~T8_E~0); 3040436#L1331-1 assume !(0 == ~T9_E~0); 3040155#L1336-1 assume !(0 == ~T10_E~0); 3040156#L1341-1 assume !(0 == ~T11_E~0); 3040228#L1346-1 assume !(0 == ~T12_E~0); 3040229#L1351-1 assume !(0 == ~T13_E~0); 3040554#L1356-1 assume !(0 == ~E_M~0); 3040555#L1361-1 assume !(0 == ~E_1~0); 3042354#L1366-1 assume !(0 == ~E_2~0); 3040597#L1371-1 assume !(0 == ~E_3~0); 3040598#L1376-1 assume !(0 == ~E_4~0); 3041514#L1381-1 assume !(0 == ~E_5~0); 3041515#L1386-1 assume !(0 == ~E_6~0); 3042418#L1391-1 assume !(0 == ~E_7~0); 3042469#L1396-1 assume !(0 == ~E_8~0); 3041398#L1401-1 assume !(0 == ~E_9~0); 3041399#L1406-1 assume !(0 == ~E_10~0); 3041724#L1411-1 assume !(0 == ~E_11~0); 3041725#L1416-1 assume !(0 == ~E_12~0); 3041316#L1421-1 assume !(0 == ~E_13~0); 3040798#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3040799#L640 assume !(1 == ~m_pc~0); 3041524#L640-2 is_master_triggered_~__retres1~0#1 := 0; 3041468#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3041323#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3041324#L1603 assume !(0 != activate_threads_~tmp~1#1); 3041355#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3040954#L659 assume !(1 == ~t1_pc~0); 3040955#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3042208#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3041871#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3041086#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 3041087#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3041105#L678 assume !(1 == ~t2_pc~0); 3042237#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3042408#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3040638#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3040639#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 3041212#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3041348#L697 assume !(1 == ~t3_pc~0); 3041349#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3041495#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3042573#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3041254#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 3041255#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3042290#L716 assume !(1 == ~t4_pc~0); 3041798#L716-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3040935#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3040299#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3040300#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 3040405#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3041809#L735 assume !(1 == ~t5_pc~0); 3040373#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3040374#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3040828#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3041841#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 3041428#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3041429#L754 assume !(1 == ~t6_pc~0); 3041681#L754-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3041045#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3040617#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3040618#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 3041018#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3041945#L773 assume !(1 == ~t7_pc~0); 3040558#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3040557#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3041469#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3041439#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 3041440#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3041506#L792 assume !(1 == ~t8_pc~0); 3041692#L792-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3042098#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3042099#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3041430#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 3041351#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3041352#L811 assume !(1 == ~t9_pc~0); 3041583#L811-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3042187#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3040694#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3040695#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 3041363#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3041364#L830 assume !(1 == ~t10_pc~0); 3041055#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3042562#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3042159#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3040512#L1683 assume !(0 != activate_threads_~tmp___9~0#1); 3040513#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3041964#L849 assume !(1 == ~t11_pc~0); 3041965#L849-2 is_transmit11_triggered_~__retres1~11#1 := 0; 3040351#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3040352#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3041983#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 3041847#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 3041848#L868 assume !(1 == ~t12_pc~0); 3041196#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 3041195#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3040243#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 3040244#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 3040569#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 3040570#L887 assume 1 == ~t13_pc~0; 3041859#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 3041248#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 3041249#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 3041937#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 3040282#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3040283#L1439 assume !(1 == ~M_E~0); 3041422#L1439-2 assume !(1 == ~T1_E~0); 3040449#L1444-1 assume !(1 == ~T2_E~0); 3040450#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3040958#L1454-1 assume !(1 == ~T4_E~0); 3040959#L1459-1 assume !(1 == ~T5_E~0); 3041574#L1464-1 assume !(1 == ~T6_E~0); 3041575#L1469-1 assume !(1 == ~T7_E~0); 3041658#L1474-1 assume !(1 == ~T8_E~0); 3041317#L1479-1 assume !(1 == ~T9_E~0); 3041318#L1484-1 assume !(1 == ~T10_E~0); 3041579#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3041184#L1494-1 assume !(1 == ~T12_E~0); 3041185#L1499-1 assume !(1 == ~T13_E~0); 3041383#L1504-1 assume !(1 == ~E_M~0); 3041384#L1509-1 assume !(1 == ~E_1~0); 3042075#L1514-1 assume !(1 == ~E_2~0); 3041693#L1519-1 assume !(1 == ~E_3~0); 3041694#L1524-1 assume !(1 == ~E_4~0); 3042381#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 3042382#L1534-1 assume !(1 == ~E_6~0); 3040277#L1539-1 assume !(1 == ~E_7~0); 3040278#L1544-1 assume !(1 == ~E_8~0); 3040691#L1549-1 assume !(1 == ~E_9~0); 3042329#L1554-1 assume !(1 == ~E_10~0); 3042326#L1559-1 assume !(1 == ~E_11~0); 3042129#L1564-1 assume !(1 == ~E_12~0); 3042130#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 3042374#L1574-1 assume { :end_inline_reset_delta_events } true; 3042435#L1940-2 [2022-12-13 18:38:13,010 INFO L750 eck$LassoCheckResult]: Loop: 3042435#L1940-2 assume !false; 3341879#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3341874#L1266 assume !false; 3341873#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 3341866#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 3341858#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 3341857#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3341855#L1079 assume !(0 != eval_~tmp~0#1); 3341854#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3341853#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3341852#L1291-3 assume !(0 == ~M_E~0); 3341851#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3341850#L1296-3 assume !(0 == ~T2_E~0); 3341849#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3341848#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3341847#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3341846#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3341845#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3341844#L1326-3 assume !(0 == ~T8_E~0); 3341843#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3341842#L1336-3 assume !(0 == ~T10_E~0); 3341841#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 3341840#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 3341839#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 3341838#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3341837#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3341836#L1366-3 assume !(0 == ~E_2~0); 3341835#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3341834#L1376-3 assume !(0 == ~E_4~0); 3341833#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3341832#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3341831#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3341830#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3341829#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3341828#L1406-3 assume !(0 == ~E_10~0); 3341827#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3341826#L1416-3 assume !(0 == ~E_12~0); 3341825#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 3341824#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3341823#L640-45 assume !(1 == ~m_pc~0); 3341822#L640-47 is_master_triggered_~__retres1~0#1 := 0; 3341821#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3341820#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3341819#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3341818#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3341817#L659-45 assume !(1 == ~t1_pc~0); 3341816#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 3341815#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3341814#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3341813#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3341812#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3341811#L678-45 assume !(1 == ~t2_pc~0); 3341809#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 3341808#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3341807#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3341806#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3341805#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3341804#L697-45 assume 1 == ~t3_pc~0; 3341802#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3341800#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3341798#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3341796#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3341795#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3341794#L716-45 assume !(1 == ~t4_pc~0); 3341793#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 3341792#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3341791#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3341790#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3341789#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3341788#L735-45 assume 1 == ~t5_pc~0; 3341786#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3341785#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3341784#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3341783#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3341782#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3341781#L754-45 assume !(1 == ~t6_pc~0); 3341780#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 3341779#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3341778#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3341777#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3341776#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3341775#L773-45 assume !(1 == ~t7_pc~0); 3341774#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 3341772#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3341771#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3341770#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 3341769#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3341768#L792-45 assume !(1 == ~t8_pc~0); 3341767#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 3341766#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3341765#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3341764#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3341763#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3341762#L811-45 assume !(1 == ~t9_pc~0); 3341761#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 3341760#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3341759#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3341758#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3341757#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3341756#L830-45 assume 1 == ~t10_pc~0; 3341754#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3341752#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3341750#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3341748#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3341747#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3341746#L849-45 assume !(1 == ~t11_pc~0); 3341745#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 3341744#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3341743#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3341742#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3341741#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 3341740#L868-45 assume 1 == ~t12_pc~0; 3341738#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 3341737#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3341736#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 3341735#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 3341734#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 3341733#L887-45 assume !(1 == ~t13_pc~0); 3341730#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 3341728#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 3341726#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 3341724#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 3341722#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3341720#L1439-3 assume !(1 == ~M_E~0); 3341382#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3341717#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3341715#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3341713#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3341711#L1459-3 assume !(1 == ~T5_E~0); 3341709#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3341707#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3341705#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3341703#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3341701#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3341699#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3341697#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 3341695#L1499-3 assume !(1 == ~T13_E~0); 3341693#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3341691#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3341689#L1514-3 assume !(1 == ~E_2~0); 3341687#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3341685#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3341683#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3341681#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3341679#L1539-3 assume !(1 == ~E_7~0); 3341677#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3341675#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3341673#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3341671#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 3341669#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 3341667#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 3341665#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 3341659#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 3341645#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 3341643#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 3341640#L1959 assume !(0 == start_simulation_~tmp~3#1); 3341641#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 3341948#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 3341927#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 3341917#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 3341910#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3341907#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3341898#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 3341889#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 3042435#L1940-2 [2022-12-13 18:38:13,011 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:38:13,011 INFO L85 PathProgramCache]: Analyzing trace with hash 736341324, now seen corresponding path program 1 times [2022-12-13 18:38:13,011 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:38:13,011 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1516942571] [2022-12-13 18:38:13,011 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:38:13,012 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:38:13,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:38:13,067 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:38:13,067 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:38:13,068 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1516942571] [2022-12-13 18:38:13,068 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1516942571] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:38:13,068 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:38:13,068 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 18:38:13,068 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1008464463] [2022-12-13 18:38:13,068 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:38:13,068 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 18:38:13,069 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 18:38:13,069 INFO L85 PathProgramCache]: Analyzing trace with hash -1010937120, now seen corresponding path program 1 times [2022-12-13 18:38:13,069 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 18:38:13,069 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [258885518] [2022-12-13 18:38:13,069 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 18:38:13,069 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 18:38:13,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 18:38:13,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 18:38:13,113 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 18:38:13,114 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [258885518] [2022-12-13 18:38:13,114 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [258885518] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 18:38:13,114 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 18:38:13,114 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 18:38:13,114 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1662202657] [2022-12-13 18:38:13,114 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 18:38:13,114 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 18:38:13,115 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 18:38:13,115 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 18:38:13,115 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 18:38:13,115 INFO L87 Difference]: Start difference. First operand 874338 states and 1218177 transitions. cyclomatic complexity: 343903 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 18:38:18,230 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 18:38:18,230 INFO L93 Difference]: Finished difference Result 1675561 states and 2328734 transitions. [2022-12-13 18:38:18,230 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1675561 states and 2328734 transitions. [2022-12-13 18:38:24,599 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 1670300 [2022-12-13 18:38:28,101 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1675561 states to 1675561 states and 2328734 transitions. [2022-12-13 18:38:28,101 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1675561 [2022-12-13 18:38:28,687 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1675561 [2022-12-13 18:38:28,687 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1675561 states and 2328734 transitions. [2022-12-13 18:38:29,417 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 18:38:29,417 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1675561 states and 2328734 transitions. [2022-12-13 18:38:30,142 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1675561 states and 2328734 transitions.