./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.13.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74406b2b-89f2-4ed2-9aea-b022e808630a/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74406b2b-89f2-4ed2-9aea-b022e808630a/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74406b2b-89f2-4ed2-9aea-b022e808630a/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74406b2b-89f2-4ed2-9aea-b022e808630a/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.13.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74406b2b-89f2-4ed2-9aea-b022e808630a/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74406b2b-89f2-4ed2-9aea-b022e808630a/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0dcd4461cca64e9ab41b6ad7ff4c6eaa4177bddcca1c612fa1571b77ac664a95 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 16:30:23,762 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 16:30:23,764 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 16:30:23,776 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 16:30:23,777 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 16:30:23,778 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 16:30:23,778 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 16:30:23,780 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 16:30:23,781 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 16:30:23,781 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 16:30:23,782 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 16:30:23,783 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 16:30:23,783 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 16:30:23,784 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 16:30:23,785 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 16:30:23,785 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 16:30:23,786 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 16:30:23,787 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 16:30:23,788 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 16:30:23,789 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 16:30:23,790 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 16:30:23,791 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 16:30:23,792 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 16:30:23,792 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 16:30:23,795 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 16:30:23,795 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 16:30:23,795 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 16:30:23,796 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 16:30:23,796 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 16:30:23,797 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 16:30:23,797 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 16:30:23,798 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 16:30:23,798 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 16:30:23,799 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 16:30:23,799 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 16:30:23,799 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 16:30:23,800 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 16:30:23,800 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 16:30:23,800 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 16:30:23,801 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 16:30:23,801 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 16:30:23,802 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74406b2b-89f2-4ed2-9aea-b022e808630a/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 16:30:23,817 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 16:30:23,817 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 16:30:23,817 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 16:30:23,818 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 16:30:23,818 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 16:30:23,818 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 16:30:23,819 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 16:30:23,819 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 16:30:23,819 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 16:30:23,819 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 16:30:23,819 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 16:30:23,819 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 16:30:23,819 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 16:30:23,819 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 16:30:23,820 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 16:30:23,820 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 16:30:23,820 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 16:30:23,820 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 16:30:23,820 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 16:30:23,820 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 16:30:23,821 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 16:30:23,821 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 16:30:23,821 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 16:30:23,821 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 16:30:23,821 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 16:30:23,821 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 16:30:23,822 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 16:30:23,822 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 16:30:23,822 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 16:30:23,822 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 16:30:23,822 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 16:30:23,823 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 16:30:23,824 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74406b2b-89f2-4ed2-9aea-b022e808630a/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74406b2b-89f2-4ed2-9aea-b022e808630a/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0dcd4461cca64e9ab41b6ad7ff4c6eaa4177bddcca1c612fa1571b77ac664a95 [2022-12-13 16:30:24,007 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 16:30:24,028 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 16:30:24,030 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 16:30:24,031 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 16:30:24,032 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 16:30:24,033 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74406b2b-89f2-4ed2-9aea-b022e808630a/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/token_ring.13.cil-2.c [2022-12-13 16:30:26,572 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 16:30:26,780 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 16:30:26,781 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74406b2b-89f2-4ed2-9aea-b022e808630a/sv-benchmarks/c/systemc/token_ring.13.cil-2.c [2022-12-13 16:30:26,793 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74406b2b-89f2-4ed2-9aea-b022e808630a/bin/uautomizer-uyxdKDjOR8/data/8532368eb/879fb2b81f244519a985d7ba39b778c8/FLAG4127b4a5e [2022-12-13 16:30:27,143 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74406b2b-89f2-4ed2-9aea-b022e808630a/bin/uautomizer-uyxdKDjOR8/data/8532368eb/879fb2b81f244519a985d7ba39b778c8 [2022-12-13 16:30:27,148 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 16:30:27,151 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 16:30:27,154 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 16:30:27,155 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 16:30:27,162 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 16:30:27,163 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 04:30:27" (1/1) ... [2022-12-13 16:30:27,164 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@76ed68b1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:30:27, skipping insertion in model container [2022-12-13 16:30:27,165 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 04:30:27" (1/1) ... [2022-12-13 16:30:27,171 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 16:30:27,209 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 16:30:27,317 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74406b2b-89f2-4ed2-9aea-b022e808630a/sv-benchmarks/c/systemc/token_ring.13.cil-2.c[671,684] [2022-12-13 16:30:27,435 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 16:30:27,449 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 16:30:27,458 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74406b2b-89f2-4ed2-9aea-b022e808630a/sv-benchmarks/c/systemc/token_ring.13.cil-2.c[671,684] [2022-12-13 16:30:27,520 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 16:30:27,539 INFO L208 MainTranslator]: Completed translation [2022-12-13 16:30:27,539 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:30:27 WrapperNode [2022-12-13 16:30:27,540 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 16:30:27,541 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 16:30:27,541 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 16:30:27,541 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 16:30:27,546 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:30:27" (1/1) ... [2022-12-13 16:30:27,558 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:30:27" (1/1) ... [2022-12-13 16:30:27,643 INFO L138 Inliner]: procedures = 54, calls = 70, calls flagged for inlining = 65, calls inlined = 302, statements flattened = 4653 [2022-12-13 16:30:27,644 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 16:30:27,645 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 16:30:27,645 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 16:30:27,645 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 16:30:27,653 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:30:27" (1/1) ... [2022-12-13 16:30:27,653 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:30:27" (1/1) ... [2022-12-13 16:30:27,660 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:30:27" (1/1) ... [2022-12-13 16:30:27,661 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:30:27" (1/1) ... [2022-12-13 16:30:27,687 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:30:27" (1/1) ... [2022-12-13 16:30:27,710 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:30:27" (1/1) ... [2022-12-13 16:30:27,715 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:30:27" (1/1) ... [2022-12-13 16:30:27,723 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:30:27" (1/1) ... [2022-12-13 16:30:27,733 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 16:30:27,733 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 16:30:27,733 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 16:30:27,734 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 16:30:27,734 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:30:27" (1/1) ... [2022-12-13 16:30:27,739 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 16:30:27,747 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74406b2b-89f2-4ed2-9aea-b022e808630a/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 16:30:27,757 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74406b2b-89f2-4ed2-9aea-b022e808630a/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 16:30:27,759 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_74406b2b-89f2-4ed2-9aea-b022e808630a/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 16:30:27,793 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 16:30:27,793 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 16:30:27,793 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 16:30:27,793 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 16:30:27,891 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 16:30:27,893 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 16:30:29,482 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 16:30:29,501 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 16:30:29,501 INFO L300 CfgBuilder]: Removed 16 assume(true) statements. [2022-12-13 16:30:29,504 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 04:30:29 BoogieIcfgContainer [2022-12-13 16:30:29,504 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 16:30:29,505 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 16:30:29,505 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 16:30:29,508 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 16:30:29,509 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 16:30:29,509 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 04:30:27" (1/3) ... [2022-12-13 16:30:29,509 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@462cf6a8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 04:30:29, skipping insertion in model container [2022-12-13 16:30:29,509 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 16:30:29,510 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 04:30:27" (2/3) ... [2022-12-13 16:30:29,510 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@462cf6a8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 04:30:29, skipping insertion in model container [2022-12-13 16:30:29,510 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 16:30:29,510 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 04:30:29" (3/3) ... [2022-12-13 16:30:29,511 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.13.cil-2.c [2022-12-13 16:30:29,573 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 16:30:29,573 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 16:30:29,573 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 16:30:29,573 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 16:30:29,573 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 16:30:29,573 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 16:30:29,574 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 16:30:29,574 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 16:30:29,582 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2024 states, 2023 states have (on average 1.495798319327731) internal successors, (3026), 2023 states have internal predecessors, (3026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:29,627 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1845 [2022-12-13 16:30:29,627 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:30:29,627 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:30:29,637 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:29,637 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:29,638 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 16:30:29,640 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2024 states, 2023 states have (on average 1.495798319327731) internal successors, (3026), 2023 states have internal predecessors, (3026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:29,652 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1845 [2022-12-13 16:30:29,653 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:30:29,653 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:30:29,655 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:29,656 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:29,662 INFO L748 eck$LassoCheckResult]: Stem: 152#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1942#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 752#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1935#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1863#L902true assume !(1 == ~m_i~0);~m_st~0 := 2; 467#L902-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1616#L907-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 510#L912-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1546#L917-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 833#L922-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 986#L927-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 490#L932-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 377#L937-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 1475#L942-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 664#L947-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1535#L952-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 581#L957-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 908#L962-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 362#L967-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1958#L1279true assume 0 == ~M_E~0;~M_E~0 := 1; 1547#L1279-2true assume !(0 == ~T1_E~0); 162#L1284-1true assume !(0 == ~T2_E~0); 1774#L1289-1true assume !(0 == ~T3_E~0); 578#L1294-1true assume !(0 == ~T4_E~0); 586#L1299-1true assume !(0 == ~T5_E~0); 1853#L1304-1true assume !(0 == ~T6_E~0); 1900#L1309-1true assume !(0 == ~T7_E~0); 1869#L1314-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 125#L1319-1true assume !(0 == ~T9_E~0); 1106#L1324-1true assume !(0 == ~T10_E~0); 213#L1329-1true assume !(0 == ~T11_E~0); 1367#L1334-1true assume !(0 == ~T12_E~0); 1802#L1339-1true assume !(0 == ~T13_E~0); 1524#L1344-1true assume !(0 == ~E_M~0); 1957#L1349-1true assume !(0 == ~E_1~0); 719#L1354-1true assume 0 == ~E_2~0;~E_2~0 := 1; 1111#L1359-1true assume !(0 == ~E_3~0); 1780#L1364-1true assume !(0 == ~E_4~0); 281#L1369-1true assume !(0 == ~E_5~0); 1085#L1374-1true assume !(0 == ~E_6~0); 724#L1379-1true assume !(0 == ~E_7~0); 785#L1384-1true assume !(0 == ~E_8~0); 2001#L1389-1true assume !(0 == ~E_9~0); 1402#L1394-1true assume 0 == ~E_10~0;~E_10~0 := 1; 1868#L1399-1true assume !(0 == ~E_11~0); 1634#L1404-1true assume !(0 == ~E_12~0); 332#L1409-1true assume !(0 == ~E_13~0); 1609#L1414-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1951#L628true assume !(1 == ~m_pc~0); 1410#L628-2true is_master_triggered_~__retres1~0#1 := 0; 936#L639true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 630#is_master_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1652#L1591true assume !(0 != activate_threads_~tmp~1#1); 1885#L1591-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 613#L647true assume 1 == ~t1_pc~0; 241#L648true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 650#L658true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1057#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1631#L1599true assume !(0 != activate_threads_~tmp___0~0#1); 1501#L1599-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1912#L666true assume 1 == ~t2_pc~0; 161#L667true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 247#L677true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 236#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1529#L1607true assume !(0 != activate_threads_~tmp___1~0#1); 876#L1607-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1854#L685true assume !(1 == ~t3_pc~0); 1026#L685-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1677#L696true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1037#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 759#L1615true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1062#L1615-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 405#L704true assume 1 == ~t4_pc~0; 1237#L705true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 770#L715true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1775#L1623true assume !(0 != activate_threads_~tmp___3~0#1); 649#L1623-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 756#L723true assume !(1 == ~t5_pc~0); 947#L723-2true is_transmit5_triggered_~__retres1~5#1 := 0; 1105#L734true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1646#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 859#L1631true assume !(0 != activate_threads_~tmp___4~0#1); 880#L1631-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 272#L742true assume 1 == ~t6_pc~0; 959#L743true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 356#L753true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 231#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 110#L1639true assume !(0 != activate_threads_~tmp___5~0#1); 1359#L1639-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 313#L761true assume !(1 == ~t7_pc~0); 321#L761-2true is_transmit7_triggered_~__retres1~7#1 := 0; 245#L772true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1954#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 761#L1647true assume !(0 != activate_threads_~tmp___6~0#1); 1556#L1647-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 121#L780true assume 1 == ~t8_pc~0; 587#L781true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 267#L791true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1597#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 731#L1655true assume !(0 != activate_threads_~tmp___7~0#1); 824#L1655-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1393#L799true assume 1 == ~t9_pc~0; 915#L800true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 122#L810true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 263#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1000#L1663true assume !(0 != activate_threads_~tmp___8~0#1); 1919#L1663-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 846#L818true assume !(1 == ~t10_pc~0); 23#L818-2true is_transmit10_triggered_~__retres1~10#1 := 0; 909#L829true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1375#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 849#L1671true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1091#L1671-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 885#L837true assume 1 == ~t11_pc~0; 1796#L838true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1575#L848true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1506#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 819#L1679true assume !(0 != activate_threads_~tmp___10~0#1); 1857#L1679-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 619#L856true assume !(1 == ~t12_pc~0); 1442#L856-2true is_transmit12_triggered_~__retres1~12#1 := 0; 1244#L867true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32#is_transmit12_triggered_returnLabel#1true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1215#L1687true assume !(0 != activate_threads_~tmp___11~0#1); 1788#L1687-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1553#L875true assume 1 == ~t13_pc~0; 584#L876true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 357#L886true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1429#is_transmit13_triggered_returnLabel#1true activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 324#L1695true assume !(0 != activate_threads_~tmp___12~0#1); 907#L1695-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1896#L1427true assume !(1 == ~M_E~0); 894#L1427-2true assume !(1 == ~T1_E~0); 306#L1432-1true assume !(1 == ~T2_E~0); 1557#L1437-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1121#L1442-1true assume !(1 == ~T4_E~0); 1484#L1447-1true assume !(1 == ~T5_E~0); 954#L1452-1true assume !(1 == ~T6_E~0); 86#L1457-1true assume !(1 == ~T7_E~0); 1150#L1462-1true assume !(1 == ~T8_E~0); 1840#L1467-1true assume !(1 == ~T9_E~0); 1176#L1472-1true assume !(1 == ~T10_E~0); 1371#L1477-1true assume 1 == ~T11_E~0;~T11_E~0 := 2; 905#L1482-1true assume !(1 == ~T12_E~0); 1296#L1487-1true assume !(1 == ~T13_E~0); 252#L1492-1true assume !(1 == ~E_M~0); 662#L1497-1true assume !(1 == ~E_1~0); 455#L1502-1true assume !(1 == ~E_2~0); 1295#L1507-1true assume !(1 == ~E_3~0); 190#L1512-1true assume !(1 == ~E_4~0); 1272#L1517-1true assume 1 == ~E_5~0;~E_5~0 := 2; 1388#L1522-1true assume !(1 == ~E_6~0); 611#L1527-1true assume !(1 == ~E_7~0); 1754#L1532-1true assume !(1 == ~E_8~0); 2013#L1537-1true assume !(1 == ~E_9~0); 775#L1542-1true assume !(1 == ~E_10~0); 634#L1547-1true assume !(1 == ~E_11~0); 1784#L1552-1true assume !(1 == ~E_12~0); 42#L1557-1true assume 1 == ~E_13~0;~E_13~0 := 2; 350#L1562-1true assume { :end_inline_reset_delta_events } true; 753#L1928-2true [2022-12-13 16:30:29,664 INFO L750 eck$LassoCheckResult]: Loop: 753#L1928-2true assume !false; 659#L1929true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 496#L1254true assume false; 572#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 336#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1601#L1279-3true assume 0 == ~M_E~0;~M_E~0 := 1; 468#L1279-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 457#L1284-3true assume !(0 == ~T2_E~0); 1657#L1289-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 447#L1294-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1891#L1299-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 717#L1304-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 1138#L1309-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 381#L1314-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1969#L1319-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1203#L1324-3true assume !(0 == ~T10_E~0); 189#L1329-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1822#L1334-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 640#L1339-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 931#L1344-3true assume 0 == ~E_M~0;~E_M~0 := 1; 882#L1349-3true assume 0 == ~E_1~0;~E_1~0 := 1; 371#L1354-3true assume 0 == ~E_2~0;~E_2~0 := 1; 891#L1359-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1851#L1364-3true assume !(0 == ~E_4~0); 1741#L1369-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1433#L1374-3true assume 0 == ~E_6~0;~E_6~0 := 1; 254#L1379-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1302#L1384-3true assume 0 == ~E_8~0;~E_8~0 := 1; 370#L1389-3true assume 0 == ~E_9~0;~E_9~0 := 1; 550#L1394-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1945#L1399-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1464#L1404-3true assume !(0 == ~E_12~0); 1387#L1409-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1545#L1414-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 795#L628-45true assume !(1 == ~m_pc~0); 1317#L628-47true is_master_triggered_~__retres1~0#1 := 0; 1735#L639-15true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 963#is_master_triggered_returnLabel#16true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 390#L1591-45true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1658#L1591-47true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 914#L647-45true assume !(1 == ~t1_pc~0); 1394#L647-47true is_transmit1_triggered_~__retres1~1#1 := 0; 730#L658-15true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1855#is_transmit1_triggered_returnLabel#16true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 217#L1599-45true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1543#L1599-47true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 329#L666-45true assume !(1 == ~t2_pc~0); 626#L666-47true is_transmit2_triggered_~__retres1~2#1 := 0; 1684#L677-15true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 960#is_transmit2_triggered_returnLabel#16true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1015#L1607-45true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1011#L1607-47true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 95#L685-45true assume !(1 == ~t3_pc~0); 1413#L685-47true is_transmit3_triggered_~__retres1~3#1 := 0; 1528#L696-15true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1975#is_transmit3_triggered_returnLabel#16true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1267#L1615-45true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1549#L1615-47true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1630#L704-45true assume !(1 == ~t4_pc~0); 33#L704-47true is_transmit4_triggered_~__retres1~4#1 := 0; 488#L715-15true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1308#is_transmit4_triggered_returnLabel#16true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2016#L1623-45true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1978#L1623-47true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 821#L723-45true assume 1 == ~t5_pc~0; 1815#L724-15true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1697#L734-15true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1968#is_transmit5_triggered_returnLabel#16true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 379#L1631-45true assume !(0 != activate_threads_~tmp___4~0#1); 1925#L1631-47true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1226#L742-45true assume !(1 == ~t6_pc~0); 533#L742-47true is_transmit6_triggered_~__retres1~6#1 := 0; 890#L753-15true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 681#is_transmit6_triggered_returnLabel#16true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 919#L1639-45true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1271#L1639-47true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 991#L761-45true assume 1 == ~t7_pc~0; 1790#L762-15true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 529#L772-15true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 749#is_transmit7_triggered_returnLabel#16true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 192#L1647-45true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1950#L1647-47true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1391#L780-45true assume 1 == ~t8_pc~0; 392#L781-15true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 197#L791-15true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1727#is_transmit8_triggered_returnLabel#16true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1753#L1655-45true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 180#L1655-47true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 638#L799-45true assume !(1 == ~t9_pc~0); 296#L799-47true is_transmit9_triggered_~__retres1~9#1 := 0; 2007#L810-15true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1083#is_transmit9_triggered_returnLabel#16true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 955#L1663-45true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1816#L1663-47true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 150#L818-45true assume !(1 == ~t10_pc~0); 210#L818-47true is_transmit10_triggered_~__retres1~10#1 := 0; 935#L829-15true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1194#is_transmit10_triggered_returnLabel#16true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 487#L1671-45true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1048#L1671-47true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1520#L837-45true assume !(1 == ~t11_pc~0); 444#L837-47true is_transmit11_triggered_~__retres1~11#1 := 0; 530#L848-15true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 188#is_transmit11_triggered_returnLabel#16true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1844#L1679-45true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 223#L1679-47true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 2025#L856-45true assume !(1 == ~t12_pc~0); 224#L856-47true is_transmit12_triggered_~__retres1~12#1 := 0; 1266#L867-15true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1128#is_transmit12_triggered_returnLabel#16true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1798#L1687-45true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 729#L1687-47true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1274#L875-45true assume 1 == ~t13_pc~0; 705#L876-15true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 751#L886-15true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1071#is_transmit13_triggered_returnLabel#16true activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1483#L1695-45true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1764#L1695-47true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1364#L1427-3true assume !(1 == ~M_E~0); 575#L1427-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1558#L1432-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 998#L1437-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 718#L1442-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1016#L1447-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 49#L1452-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1977#L1457-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1251#L1462-3true assume !(1 == ~T8_E~0); 1672#L1467-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1065#L1472-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1705#L1477-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 172#L1482-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 244#L1487-3true assume 1 == ~T13_E~0;~T13_E~0 := 2; 1808#L1492-3true assume 1 == ~E_M~0;~E_M~0 := 2; 335#L1497-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1019#L1502-3true assume !(1 == ~E_2~0); 1201#L1507-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1917#L1512-3true assume 1 == ~E_4~0;~E_4~0 := 2; 359#L1517-3true assume 1 == ~E_5~0;~E_5~0 := 2; 194#L1522-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1673#L1527-3true assume 1 == ~E_7~0;~E_7~0 := 2; 176#L1532-3true assume 1 == ~E_8~0;~E_8~0 := 2; 892#L1537-3true assume 1 == ~E_9~0;~E_9~0 := 2; 1572#L1542-3true assume !(1 == ~E_10~0); 1003#L1547-3true assume 1 == ~E_11~0;~E_11~0 := 2; 706#L1552-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1396#L1557-3true assume 1 == ~E_13~0;~E_13~0 := 2; 284#L1562-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1966#L980-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1411#L1052-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 208#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 811#L1947true assume !(0 == start_simulation_~tmp~3#1); 979#L1947-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1126#L980-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1620#L1052-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 27#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 1451#L1902true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1164#L1909true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1401#stop_simulation_returnLabel#1true start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1711#L1960true assume !(0 != start_simulation_~tmp___0~1#1); 753#L1928-2true [2022-12-13 16:30:29,670 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:29,670 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 1 times [2022-12-13 16:30:29,677 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:29,678 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [934225531] [2022-12-13 16:30:29,678 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:29,678 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:29,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:29,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:29,888 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:29,888 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [934225531] [2022-12-13 16:30:29,889 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [934225531] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:29,889 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:29,889 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:29,891 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [936343123] [2022-12-13 16:30:29,891 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:29,895 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:30:29,896 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:29,896 INFO L85 PathProgramCache]: Analyzing trace with hash -686101371, now seen corresponding path program 1 times [2022-12-13 16:30:29,896 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:29,896 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1206917072] [2022-12-13 16:30:29,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:29,897 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:29,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:29,956 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:29,957 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:29,957 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1206917072] [2022-12-13 16:30:29,957 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1206917072] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:29,957 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:29,957 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 16:30:29,957 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [53958828] [2022-12-13 16:30:29,958 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:29,959 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:30:29,960 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:30:29,986 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-12-13 16:30:29,987 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-12-13 16:30:29,991 INFO L87 Difference]: Start difference. First operand has 2024 states, 2023 states have (on average 1.495798319327731) internal successors, (3026), 2023 states have internal predecessors, (3026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 79.5) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:30,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:30:30,049 INFO L93 Difference]: Finished difference Result 2023 states and 2992 transitions. [2022-12-13 16:30:30,050 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2992 transitions. [2022-12-13 16:30:30,060 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-12-13 16:30:30,072 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2018 states and 2987 transitions. [2022-12-13 16:30:30,072 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-12-13 16:30:30,074 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-12-13 16:30:30,075 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2987 transitions. [2022-12-13 16:30:30,082 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:30:30,082 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2987 transitions. [2022-12-13 16:30:30,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2987 transitions. [2022-12-13 16:30:30,147 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-12-13 16:30:30,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4801783944499505) internal successors, (2987), 2017 states have internal predecessors, (2987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:30,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2987 transitions. [2022-12-13 16:30:30,155 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2987 transitions. [2022-12-13 16:30:30,156 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-12-13 16:30:30,160 INFO L428 stractBuchiCegarLoop]: Abstraction has 2018 states and 2987 transitions. [2022-12-13 16:30:30,160 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 16:30:30,160 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2987 transitions. [2022-12-13 16:30:30,170 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-12-13 16:30:30,170 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:30:30,170 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:30:30,173 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:30,173 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:30,174 INFO L748 eck$LassoCheckResult]: Stem: 4384#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 4385#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 5362#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5363#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6061#L902 assume !(1 == ~m_i~0);~m_st~0 := 2; 4961#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4962#L907-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 5030#L912-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5031#L917-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5464#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5465#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4996#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4805#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4806#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5260#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5261#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5139#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5140#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 4779#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4780#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 5984#L1279-2 assume !(0 == ~T1_E~0); 4405#L1284-1 assume !(0 == ~T2_E~0); 4406#L1289-1 assume !(0 == ~T3_E~0); 5136#L1294-1 assume !(0 == ~T4_E~0); 5137#L1299-1 assume !(0 == ~T5_E~0); 5148#L1304-1 assume !(0 == ~T6_E~0); 6060#L1309-1 assume !(0 == ~T7_E~0); 6062#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4331#L1319-1 assume !(0 == ~T9_E~0); 4332#L1324-1 assume !(0 == ~T10_E~0); 4506#L1329-1 assume !(0 == ~T11_E~0); 4507#L1334-1 assume !(0 == ~T12_E~0); 5899#L1339-1 assume !(0 == ~T13_E~0); 5973#L1344-1 assume !(0 == ~E_M~0); 5974#L1349-1 assume !(0 == ~E_1~0); 5321#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5322#L1359-1 assume !(0 == ~E_3~0); 5728#L1364-1 assume !(0 == ~E_4~0); 4631#L1369-1 assume !(0 == ~E_5~0); 4632#L1374-1 assume !(0 == ~E_6~0); 5328#L1379-1 assume !(0 == ~E_7~0); 5329#L1384-1 assume !(0 == ~E_8~0); 5406#L1389-1 assume !(0 == ~E_9~0); 5919#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 5920#L1399-1 assume !(0 == ~E_11~0); 6015#L1404-1 assume !(0 == ~E_12~0); 4727#L1409-1 assume !(0 == ~E_13~0); 4728#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6010#L628 assume !(1 == ~m_pc~0); 4630#L628-2 is_master_triggered_~__retres1~0#1 := 0; 4629#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5209#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5210#L1591 assume !(0 != activate_threads_~tmp~1#1); 6024#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5190#L647 assume 1 == ~t1_pc~0; 4556#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4557#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5241#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5690#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 5961#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5962#L666 assume 1 == ~t2_pc~0; 4402#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4403#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4547#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4548#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 5516#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5517#L685 assume !(1 == ~t3_pc~0); 5611#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5610#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5680#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5370#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5371#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4848#L704 assume 1 == ~t4_pc~0; 4849#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5382#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4195#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4196#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 5239#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5240#L723 assume !(1 == ~t5_pc~0); 5366#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5583#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5721#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5495#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 5496#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4613#L742 assume 1 == ~t6_pc~0; 4614#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4768#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4538#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4300#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 4301#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4689#L761 assume !(1 == ~t7_pc~0); 4690#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4565#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4566#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5373#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 5374#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4323#L780 assume 1 == ~t8_pc~0; 4324#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4603#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4604#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5335#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 5336#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5452#L799 assume 1 == ~t9_pc~0; 5553#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4326#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4327#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4595#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 5654#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5477#L818 assume !(1 == ~t10_pc~0); 4107#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4108#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5546#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5480#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5481#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5523#L837 assume 1 == ~t11_pc~0; 5524#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 5360#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5965#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5445#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 5446#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5198#L856 assume !(1 == ~t12_pc~0); 5199#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 5824#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4125#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4126#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 5802#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5987#L875 assume 1 == ~t13_pc~0; 5146#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4769#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4770#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4707#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 4708#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5545#L1427 assume !(1 == ~M_E~0); 5530#L1427-2 assume !(1 == ~T1_E~0); 4676#L1432-1 assume !(1 == ~T2_E~0); 4677#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5732#L1442-1 assume !(1 == ~T4_E~0); 5733#L1447-1 assume !(1 == ~T5_E~0); 5592#L1452-1 assume !(1 == ~T6_E~0); 4247#L1457-1 assume !(1 == ~T7_E~0); 4248#L1462-1 assume !(1 == ~T8_E~0); 5750#L1467-1 assume !(1 == ~T9_E~0); 5770#L1472-1 assume !(1 == ~T10_E~0); 5771#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5541#L1482-1 assume !(1 == ~T12_E~0); 5542#L1487-1 assume !(1 == ~T13_E~0); 4576#L1492-1 assume !(1 == ~E_M~0); 4577#L1497-1 assume !(1 == ~E_1~0); 4943#L1502-1 assume !(1 == ~E_2~0); 4944#L1507-1 assume !(1 == ~E_3~0); 4458#L1512-1 assume !(1 == ~E_4~0); 4459#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 5844#L1522-1 assume !(1 == ~E_6~0); 5187#L1527-1 assume !(1 == ~E_7~0); 5188#L1532-1 assume !(1 == ~E_8~0); 6046#L1537-1 assume !(1 == ~E_9~0); 5389#L1542-1 assume !(1 == ~E_10~0); 5216#L1547-1 assume !(1 == ~E_11~0); 5217#L1552-1 assume !(1 == ~E_12~0); 4148#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 4149#L1562-1 assume { :end_inline_reset_delta_events } true; 4759#L1928-2 [2022-12-13 16:30:30,175 INFO L750 eck$LassoCheckResult]: Loop: 4759#L1928-2 assume !false; 5253#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4414#L1254 assume !false; 5005#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4483#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4484#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4678#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5830#L1067 assume !(0 != eval_~tmp~0#1); 5126#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4736#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4737#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4963#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4947#L1284-3 assume !(0 == ~T2_E~0); 4948#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4927#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4928#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5317#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5318#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4813#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4814#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5792#L1324-3 assume !(0 == ~T10_E~0); 4456#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4457#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 5222#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 5223#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5520#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4797#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4798#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5528#L1364-3 assume !(0 == ~E_4~0); 6045#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5935#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4579#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4580#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4795#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4796#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 5097#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5945#L1404-3 assume !(0 == ~E_12~0); 5909#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5910#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5418#L628-45 assume 1 == ~m_pc~0; 5092#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5094#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5600#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4828#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4829#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5552#L647-45 assume !(1 == ~t1_pc~0); 4401#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 4400#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5334#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4512#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4513#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4720#L666-45 assume !(1 == ~t2_pc~0); 4721#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 5208#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5598#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5599#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5664#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4263#L685-45 assume 1 == ~t3_pc~0; 4264#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5330#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5976#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5842#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5843#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5985#L704-45 assume 1 == ~t4_pc~0; 5863#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4128#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4993#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5864#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6073#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5447#L723-45 assume !(1 == ~t5_pc~0); 5448#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 5921#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6036#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4809#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 4810#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5812#L742-45 assume 1 == ~t6_pc~0; 5813#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5066#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5278#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5279#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5557#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5643#L761-45 assume !(1 == ~t7_pc~0); 5644#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 5060#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5061#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4462#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4463#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5913#L780-45 assume 1 == ~t8_pc~0; 4830#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4473#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4474#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6043#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4442#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4443#L799-45 assume !(1 == ~t9_pc~0); 4656#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 4657#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5709#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5593#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5594#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4379#L818-45 assume 1 == ~t10_pc~0; 4380#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4500#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5570#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4991#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4992#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5688#L837-45 assume 1 == ~t11_pc~0; 5971#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4921#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4454#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4455#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4521#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4522#L856-45 assume !(1 == ~t12_pc~0); 4523#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 4524#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 5739#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 5740#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 5332#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5333#L875-45 assume 1 == ~t13_pc~0; 5301#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 5302#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5361#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 5701#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 5955#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5897#L1427-3 assume !(1 == ~M_E~0); 5131#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5132#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5651#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5319#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5320#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4165#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4166#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5828#L1462-3 assume !(1 == ~T8_E~0); 5829#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5696#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5697#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4423#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4424#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 4564#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4734#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4735#L1502-3 assume !(1 == ~E_2~0); 5671#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5790#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4773#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4466#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4467#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4433#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4434#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5529#L1542-3 assume !(1 == ~E_10~0); 5657#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 5304#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 5305#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 4634#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4635#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4057#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4496#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 4497#L1947 assume !(0 == start_simulation_~tmp~3#1); 5436#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5625#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4693#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4115#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 4116#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5758#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5759#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 5918#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 4759#L1928-2 [2022-12-13 16:30:30,176 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:30,176 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 2 times [2022-12-13 16:30:30,176 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:30,176 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [919740684] [2022-12-13 16:30:30,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:30,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:30,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:30,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:30,261 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:30,261 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [919740684] [2022-12-13 16:30:30,261 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [919740684] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:30,261 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:30,262 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:30,262 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1098996787] [2022-12-13 16:30:30,262 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:30,262 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:30:30,263 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:30,263 INFO L85 PathProgramCache]: Analyzing trace with hash -2100544722, now seen corresponding path program 1 times [2022-12-13 16:30:30,263 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:30,264 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [410300953] [2022-12-13 16:30:30,264 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:30,264 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:30,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:30,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:30,378 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:30,379 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [410300953] [2022-12-13 16:30:30,379 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [410300953] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:30,379 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:30,379 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:30,379 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2083503250] [2022-12-13 16:30:30,380 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:30,380 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:30:30,380 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:30:30,381 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:30:30,381 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:30:30,381 INFO L87 Difference]: Start difference. First operand 2018 states and 2987 transitions. cyclomatic complexity: 970 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:30,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:30:30,437 INFO L93 Difference]: Finished difference Result 2018 states and 2986 transitions. [2022-12-13 16:30:30,437 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2986 transitions. [2022-12-13 16:30:30,449 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-12-13 16:30:30,459 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2986 transitions. [2022-12-13 16:30:30,459 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-12-13 16:30:30,461 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-12-13 16:30:30,461 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2986 transitions. [2022-12-13 16:30:30,463 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:30:30,464 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2986 transitions. [2022-12-13 16:30:30,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2986 transitions. [2022-12-13 16:30:30,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-12-13 16:30:30,493 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4796828543111993) internal successors, (2986), 2017 states have internal predecessors, (2986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:30,496 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2986 transitions. [2022-12-13 16:30:30,496 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2986 transitions. [2022-12-13 16:30:30,497 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:30:30,497 INFO L428 stractBuchiCegarLoop]: Abstraction has 2018 states and 2986 transitions. [2022-12-13 16:30:30,497 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 16:30:30,497 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2986 transitions. [2022-12-13 16:30:30,503 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-12-13 16:30:30,503 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:30:30,503 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:30:30,504 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:30,505 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:30,505 INFO L748 eck$LassoCheckResult]: Stem: 8427#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 8428#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 9405#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9406#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10104#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 9004#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9005#L907-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 9073#L912-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 9074#L917-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 9507#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9508#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9039#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8848#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8849#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9303#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9304#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9182#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9183#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 8822#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8823#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 10027#L1279-2 assume !(0 == ~T1_E~0); 8448#L1284-1 assume !(0 == ~T2_E~0); 8449#L1289-1 assume !(0 == ~T3_E~0); 9179#L1294-1 assume !(0 == ~T4_E~0); 9180#L1299-1 assume !(0 == ~T5_E~0); 9191#L1304-1 assume !(0 == ~T6_E~0); 10103#L1309-1 assume !(0 == ~T7_E~0); 10105#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8374#L1319-1 assume !(0 == ~T9_E~0); 8375#L1324-1 assume !(0 == ~T10_E~0); 8549#L1329-1 assume !(0 == ~T11_E~0); 8550#L1334-1 assume !(0 == ~T12_E~0); 9942#L1339-1 assume !(0 == ~T13_E~0); 10016#L1344-1 assume !(0 == ~E_M~0); 10017#L1349-1 assume !(0 == ~E_1~0); 9364#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 9365#L1359-1 assume !(0 == ~E_3~0); 9771#L1364-1 assume !(0 == ~E_4~0); 8674#L1369-1 assume !(0 == ~E_5~0); 8675#L1374-1 assume !(0 == ~E_6~0); 9371#L1379-1 assume !(0 == ~E_7~0); 9372#L1384-1 assume !(0 == ~E_8~0); 9449#L1389-1 assume !(0 == ~E_9~0); 9962#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 9963#L1399-1 assume !(0 == ~E_11~0); 10058#L1404-1 assume !(0 == ~E_12~0); 8770#L1409-1 assume !(0 == ~E_13~0); 8771#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10053#L628 assume !(1 == ~m_pc~0); 8673#L628-2 is_master_triggered_~__retres1~0#1 := 0; 8672#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9252#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9253#L1591 assume !(0 != activate_threads_~tmp~1#1); 10067#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9233#L647 assume 1 == ~t1_pc~0; 8599#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8600#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9284#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9733#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 10004#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10005#L666 assume 1 == ~t2_pc~0; 8445#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8446#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8590#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8591#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 9559#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9560#L685 assume !(1 == ~t3_pc~0); 9654#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9653#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9723#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9413#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9414#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8891#L704 assume 1 == ~t4_pc~0; 8892#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9425#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8238#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8239#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 9282#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9283#L723 assume !(1 == ~t5_pc~0); 9409#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9626#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9764#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9538#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 9539#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8656#L742 assume 1 == ~t6_pc~0; 8657#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8811#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8581#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8343#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 8344#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8732#L761 assume !(1 == ~t7_pc~0); 8733#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8608#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8609#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9416#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 9417#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8366#L780 assume 1 == ~t8_pc~0; 8367#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8646#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8647#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9378#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 9379#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9495#L799 assume 1 == ~t9_pc~0; 9596#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8369#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8370#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8638#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 9697#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9520#L818 assume !(1 == ~t10_pc~0); 8150#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8151#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9589#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9523#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9524#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9566#L837 assume 1 == ~t11_pc~0; 9567#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 9403#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10008#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9488#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 9489#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9241#L856 assume !(1 == ~t12_pc~0); 9242#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 9867#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8168#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8169#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 9845#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 10030#L875 assume 1 == ~t13_pc~0; 9189#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 8812#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8813#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 8750#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 8751#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9588#L1427 assume !(1 == ~M_E~0); 9573#L1427-2 assume !(1 == ~T1_E~0); 8719#L1432-1 assume !(1 == ~T2_E~0); 8720#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9775#L1442-1 assume !(1 == ~T4_E~0); 9776#L1447-1 assume !(1 == ~T5_E~0); 9635#L1452-1 assume !(1 == ~T6_E~0); 8290#L1457-1 assume !(1 == ~T7_E~0); 8291#L1462-1 assume !(1 == ~T8_E~0); 9793#L1467-1 assume !(1 == ~T9_E~0); 9813#L1472-1 assume !(1 == ~T10_E~0); 9814#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9584#L1482-1 assume !(1 == ~T12_E~0); 9585#L1487-1 assume !(1 == ~T13_E~0); 8619#L1492-1 assume !(1 == ~E_M~0); 8620#L1497-1 assume !(1 == ~E_1~0); 8986#L1502-1 assume !(1 == ~E_2~0); 8987#L1507-1 assume !(1 == ~E_3~0); 8501#L1512-1 assume !(1 == ~E_4~0); 8502#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 9887#L1522-1 assume !(1 == ~E_6~0); 9230#L1527-1 assume !(1 == ~E_7~0); 9231#L1532-1 assume !(1 == ~E_8~0); 10089#L1537-1 assume !(1 == ~E_9~0); 9432#L1542-1 assume !(1 == ~E_10~0); 9259#L1547-1 assume !(1 == ~E_11~0); 9260#L1552-1 assume !(1 == ~E_12~0); 8191#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 8192#L1562-1 assume { :end_inline_reset_delta_events } true; 8802#L1928-2 [2022-12-13 16:30:30,505 INFO L750 eck$LassoCheckResult]: Loop: 8802#L1928-2 assume !false; 9296#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8457#L1254 assume !false; 9048#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8526#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8527#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8721#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9873#L1067 assume !(0 != eval_~tmp~0#1); 9169#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8779#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8780#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9006#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8990#L1284-3 assume !(0 == ~T2_E~0); 8991#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8970#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8971#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9360#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9361#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8856#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8857#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9835#L1324-3 assume !(0 == ~T10_E~0); 8499#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 8500#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 9265#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 9266#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9563#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8840#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8841#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9571#L1364-3 assume !(0 == ~E_4~0); 10088#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9978#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8622#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8623#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8838#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8839#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9140#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 9988#L1404-3 assume !(0 == ~E_12~0); 9952#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 9953#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9461#L628-45 assume !(1 == ~m_pc~0); 9136#L628-47 is_master_triggered_~__retres1~0#1 := 0; 9137#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9643#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8871#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8872#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9595#L647-45 assume 1 == ~t1_pc~0; 8442#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8443#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9377#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8555#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8556#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8763#L666-45 assume !(1 == ~t2_pc~0); 8764#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 9251#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9641#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9642#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9707#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8306#L685-45 assume 1 == ~t3_pc~0; 8307#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9373#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10019#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9885#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9886#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10028#L704-45 assume 1 == ~t4_pc~0; 9906#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8171#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9036#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9907#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10116#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9490#L723-45 assume !(1 == ~t5_pc~0); 9491#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 9964#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10079#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8852#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 8853#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9855#L742-45 assume 1 == ~t6_pc~0; 9856#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9109#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9321#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9322#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9600#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9686#L761-45 assume !(1 == ~t7_pc~0); 9687#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 9103#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9104#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8505#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8506#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9956#L780-45 assume 1 == ~t8_pc~0; 8873#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8516#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8517#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10086#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8485#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8486#L799-45 assume !(1 == ~t9_pc~0); 8699#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 8700#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9752#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9636#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9637#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8422#L818-45 assume 1 == ~t10_pc~0; 8423#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8543#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9613#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9034#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9035#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9731#L837-45 assume !(1 == ~t11_pc~0); 8963#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 8964#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8497#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8498#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8564#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8565#L856-45 assume !(1 == ~t12_pc~0); 8566#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 8567#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 9782#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 9783#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 9375#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9376#L875-45 assume 1 == ~t13_pc~0; 9344#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 9345#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 9404#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 9744#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 9998#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9940#L1427-3 assume !(1 == ~M_E~0); 9174#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9175#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9694#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9362#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9363#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8208#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8209#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9871#L1462-3 assume !(1 == ~T8_E~0); 9872#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9739#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9740#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8466#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8467#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 8607#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8777#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8778#L1502-3 assume !(1 == ~E_2~0); 9714#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9833#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8816#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8509#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8510#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8476#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8477#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9572#L1542-3 assume !(1 == ~E_10~0); 9700#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 9347#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 9348#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 8677#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8678#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8100#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8539#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 8540#L1947 assume !(0 == start_simulation_~tmp~3#1); 9479#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9668#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8736#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8158#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 8159#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9801#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9802#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 9961#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 8802#L1928-2 [2022-12-13 16:30:30,506 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:30,506 INFO L85 PathProgramCache]: Analyzing trace with hash 1533490443, now seen corresponding path program 1 times [2022-12-13 16:30:30,506 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:30,506 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [227040206] [2022-12-13 16:30:30,506 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:30,506 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:30,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:30,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:30,545 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:30,545 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [227040206] [2022-12-13 16:30:30,546 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [227040206] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:30,546 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:30,546 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:30,546 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [961353593] [2022-12-13 16:30:30,546 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:30,547 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:30:30,547 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:30,547 INFO L85 PathProgramCache]: Analyzing trace with hash 808729199, now seen corresponding path program 1 times [2022-12-13 16:30:30,547 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:30,548 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [546750284] [2022-12-13 16:30:30,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:30,548 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:30,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:30,632 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:30,632 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:30,632 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [546750284] [2022-12-13 16:30:30,632 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [546750284] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:30,632 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:30,633 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:30,633 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [732098995] [2022-12-13 16:30:30,633 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:30,633 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:30:30,634 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:30:30,634 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:30:30,634 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:30:30,634 INFO L87 Difference]: Start difference. First operand 2018 states and 2986 transitions. cyclomatic complexity: 969 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:30,678 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:30:30,679 INFO L93 Difference]: Finished difference Result 2018 states and 2985 transitions. [2022-12-13 16:30:30,679 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2985 transitions. [2022-12-13 16:30:30,694 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-12-13 16:30:30,711 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2985 transitions. [2022-12-13 16:30:30,711 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-12-13 16:30:30,713 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-12-13 16:30:30,713 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2985 transitions. [2022-12-13 16:30:30,717 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:30:30,717 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2985 transitions. [2022-12-13 16:30:30,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2985 transitions. [2022-12-13 16:30:30,752 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-12-13 16:30:30,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4791873141724479) internal successors, (2985), 2017 states have internal predecessors, (2985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:30,760 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2985 transitions. [2022-12-13 16:30:30,760 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2985 transitions. [2022-12-13 16:30:30,761 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:30:30,761 INFO L428 stractBuchiCegarLoop]: Abstraction has 2018 states and 2985 transitions. [2022-12-13 16:30:30,761 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 16:30:30,762 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2985 transitions. [2022-12-13 16:30:30,770 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-12-13 16:30:30,770 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:30:30,770 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:30:30,772 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:30,773 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:30,773 INFO L748 eck$LassoCheckResult]: Stem: 12470#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 12471#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 13448#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13449#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14147#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 13047#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13048#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13116#L912-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 13117#L917-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13550#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13551#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13082#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12891#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12892#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13346#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13347#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 13225#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 13226#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 12865#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12866#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 14070#L1279-2 assume !(0 == ~T1_E~0); 12491#L1284-1 assume !(0 == ~T2_E~0); 12492#L1289-1 assume !(0 == ~T3_E~0); 13222#L1294-1 assume !(0 == ~T4_E~0); 13223#L1299-1 assume !(0 == ~T5_E~0); 13234#L1304-1 assume !(0 == ~T6_E~0); 14146#L1309-1 assume !(0 == ~T7_E~0); 14148#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12417#L1319-1 assume !(0 == ~T9_E~0); 12418#L1324-1 assume !(0 == ~T10_E~0); 12592#L1329-1 assume !(0 == ~T11_E~0); 12593#L1334-1 assume !(0 == ~T12_E~0); 13985#L1339-1 assume !(0 == ~T13_E~0); 14059#L1344-1 assume !(0 == ~E_M~0); 14060#L1349-1 assume !(0 == ~E_1~0); 13407#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 13408#L1359-1 assume !(0 == ~E_3~0); 13814#L1364-1 assume !(0 == ~E_4~0); 12717#L1369-1 assume !(0 == ~E_5~0); 12718#L1374-1 assume !(0 == ~E_6~0); 13414#L1379-1 assume !(0 == ~E_7~0); 13415#L1384-1 assume !(0 == ~E_8~0); 13492#L1389-1 assume !(0 == ~E_9~0); 14005#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 14006#L1399-1 assume !(0 == ~E_11~0); 14101#L1404-1 assume !(0 == ~E_12~0); 12813#L1409-1 assume !(0 == ~E_13~0); 12814#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14096#L628 assume !(1 == ~m_pc~0); 12716#L628-2 is_master_triggered_~__retres1~0#1 := 0; 12715#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13295#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13296#L1591 assume !(0 != activate_threads_~tmp~1#1); 14110#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13276#L647 assume 1 == ~t1_pc~0; 12642#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12643#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13327#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13776#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 14047#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14048#L666 assume 1 == ~t2_pc~0; 12488#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12489#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12633#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12634#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 13602#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13603#L685 assume !(1 == ~t3_pc~0); 13697#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13696#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13766#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13456#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13457#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12934#L704 assume 1 == ~t4_pc~0; 12935#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13468#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12281#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12282#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 13325#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13326#L723 assume !(1 == ~t5_pc~0); 13452#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13669#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13807#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13581#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 13582#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12699#L742 assume 1 == ~t6_pc~0; 12700#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12854#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12624#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12386#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 12387#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12775#L761 assume !(1 == ~t7_pc~0); 12776#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 12651#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12652#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13459#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 13460#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12409#L780 assume 1 == ~t8_pc~0; 12410#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12689#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12690#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13421#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 13422#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13538#L799 assume 1 == ~t9_pc~0; 13639#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12412#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12413#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12681#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 13740#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13563#L818 assume !(1 == ~t10_pc~0); 12193#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12194#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13632#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13566#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13567#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13609#L837 assume 1 == ~t11_pc~0; 13610#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 13446#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14051#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13531#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 13532#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13284#L856 assume !(1 == ~t12_pc~0); 13285#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 13910#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12211#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12212#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 13888#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 14073#L875 assume 1 == ~t13_pc~0; 13232#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12855#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12856#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 12793#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 12794#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13631#L1427 assume !(1 == ~M_E~0); 13616#L1427-2 assume !(1 == ~T1_E~0); 12762#L1432-1 assume !(1 == ~T2_E~0); 12763#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13818#L1442-1 assume !(1 == ~T4_E~0); 13819#L1447-1 assume !(1 == ~T5_E~0); 13678#L1452-1 assume !(1 == ~T6_E~0); 12333#L1457-1 assume !(1 == ~T7_E~0); 12334#L1462-1 assume !(1 == ~T8_E~0); 13836#L1467-1 assume !(1 == ~T9_E~0); 13856#L1472-1 assume !(1 == ~T10_E~0); 13857#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13627#L1482-1 assume !(1 == ~T12_E~0); 13628#L1487-1 assume !(1 == ~T13_E~0); 12662#L1492-1 assume !(1 == ~E_M~0); 12663#L1497-1 assume !(1 == ~E_1~0); 13029#L1502-1 assume !(1 == ~E_2~0); 13030#L1507-1 assume !(1 == ~E_3~0); 12544#L1512-1 assume !(1 == ~E_4~0); 12545#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 13930#L1522-1 assume !(1 == ~E_6~0); 13273#L1527-1 assume !(1 == ~E_7~0); 13274#L1532-1 assume !(1 == ~E_8~0); 14132#L1537-1 assume !(1 == ~E_9~0); 13475#L1542-1 assume !(1 == ~E_10~0); 13302#L1547-1 assume !(1 == ~E_11~0); 13303#L1552-1 assume !(1 == ~E_12~0); 12234#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 12235#L1562-1 assume { :end_inline_reset_delta_events } true; 12845#L1928-2 [2022-12-13 16:30:30,773 INFO L750 eck$LassoCheckResult]: Loop: 12845#L1928-2 assume !false; 13339#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12500#L1254 assume !false; 13091#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12569#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12570#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12764#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 13916#L1067 assume !(0 != eval_~tmp~0#1); 13212#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12822#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12823#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13049#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13033#L1284-3 assume !(0 == ~T2_E~0); 13034#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13013#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13014#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13403#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13404#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12899#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12900#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13878#L1324-3 assume !(0 == ~T10_E~0); 12542#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 12543#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 13308#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 13309#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13606#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12883#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12884#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13614#L1364-3 assume !(0 == ~E_4~0); 14131#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14021#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12665#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12666#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12881#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12882#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 13183#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14031#L1404-3 assume !(0 == ~E_12~0); 13995#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13996#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13504#L628-45 assume 1 == ~m_pc~0; 13178#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13180#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13686#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12914#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12915#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13638#L647-45 assume 1 == ~t1_pc~0; 12485#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12486#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13420#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12598#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12599#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12806#L666-45 assume !(1 == ~t2_pc~0); 12807#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 13294#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13684#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13685#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13750#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12349#L685-45 assume 1 == ~t3_pc~0; 12350#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13416#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14062#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13928#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13929#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14071#L704-45 assume !(1 == ~t4_pc~0); 12213#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 12214#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13079#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13950#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14159#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13533#L723-45 assume !(1 == ~t5_pc~0); 13534#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 14007#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14122#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12895#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 12896#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13898#L742-45 assume 1 == ~t6_pc~0; 13899#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13152#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13364#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13365#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13643#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13729#L761-45 assume !(1 == ~t7_pc~0); 13730#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 13146#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13147#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12548#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12549#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13999#L780-45 assume 1 == ~t8_pc~0; 12916#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12559#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12560#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14129#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12528#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12529#L799-45 assume !(1 == ~t9_pc~0); 12742#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 12743#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13795#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13679#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13680#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12465#L818-45 assume 1 == ~t10_pc~0; 12466#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12586#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13656#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13077#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13078#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13774#L837-45 assume 1 == ~t11_pc~0; 14057#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 13007#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12540#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12541#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 12607#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12608#L856-45 assume !(1 == ~t12_pc~0); 12609#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 12610#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 13825#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13826#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13418#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 13419#L875-45 assume 1 == ~t13_pc~0; 13387#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 13388#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13447#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 13787#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 14041#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13983#L1427-3 assume !(1 == ~M_E~0); 13217#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13218#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13737#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13405#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13406#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12251#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12252#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13914#L1462-3 assume !(1 == ~T8_E~0); 13915#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13782#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13783#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12509#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12510#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 12650#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12820#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12821#L1502-3 assume !(1 == ~E_2~0); 13757#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13876#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12859#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12552#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12553#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12519#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12520#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13615#L1542-3 assume !(1 == ~E_10~0); 13743#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 13390#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 13391#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 12720#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12721#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12143#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12582#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 12583#L1947 assume !(0 == start_simulation_~tmp~3#1); 13522#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13711#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12779#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12201#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 12202#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13844#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13845#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 14004#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 12845#L1928-2 [2022-12-13 16:30:30,774 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:30,774 INFO L85 PathProgramCache]: Analyzing trace with hash -992005239, now seen corresponding path program 1 times [2022-12-13 16:30:30,774 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:30,774 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1726120644] [2022-12-13 16:30:30,775 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:30,775 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:30,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:30,826 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:30,826 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:30,826 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1726120644] [2022-12-13 16:30:30,826 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1726120644] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:30,827 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:30,827 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:30,827 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1137664554] [2022-12-13 16:30:30,827 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:30,827 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:30:30,828 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:30,828 INFO L85 PathProgramCache]: Analyzing trace with hash -1705440914, now seen corresponding path program 1 times [2022-12-13 16:30:30,828 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:30,828 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1861712020] [2022-12-13 16:30:30,828 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:30,829 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:30,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:30,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:30,893 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:30,894 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1861712020] [2022-12-13 16:30:30,894 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1861712020] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:30,894 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:30,894 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:30,894 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [89213344] [2022-12-13 16:30:30,894 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:30,895 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:30:30,895 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:30:30,895 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:30:30,895 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:30:30,896 INFO L87 Difference]: Start difference. First operand 2018 states and 2985 transitions. cyclomatic complexity: 968 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:30,920 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:30:30,920 INFO L93 Difference]: Finished difference Result 2018 states and 2984 transitions. [2022-12-13 16:30:30,921 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2984 transitions. [2022-12-13 16:30:30,927 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-12-13 16:30:30,931 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2984 transitions. [2022-12-13 16:30:30,932 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-12-13 16:30:30,933 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-12-13 16:30:30,933 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2984 transitions. [2022-12-13 16:30:30,934 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:30:30,934 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2984 transitions. [2022-12-13 16:30:30,936 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2984 transitions. [2022-12-13 16:30:30,951 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-12-13 16:30:30,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4786917740336967) internal successors, (2984), 2017 states have internal predecessors, (2984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:30,956 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2984 transitions. [2022-12-13 16:30:30,956 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2984 transitions. [2022-12-13 16:30:30,956 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:30:30,957 INFO L428 stractBuchiCegarLoop]: Abstraction has 2018 states and 2984 transitions. [2022-12-13 16:30:30,957 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 16:30:30,957 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2984 transitions. [2022-12-13 16:30:30,962 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-12-13 16:30:30,962 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:30:30,962 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:30:30,970 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:30,971 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:30,971 INFO L748 eck$LassoCheckResult]: Stem: 16513#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 16514#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 17491#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17492#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18190#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 17090#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17091#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17159#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17160#L917-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 17593#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 17594#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17125#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16934#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16935#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17389#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17390#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17268#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 17269#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 16908#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16909#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 18113#L1279-2 assume !(0 == ~T1_E~0); 16534#L1284-1 assume !(0 == ~T2_E~0); 16535#L1289-1 assume !(0 == ~T3_E~0); 17265#L1294-1 assume !(0 == ~T4_E~0); 17266#L1299-1 assume !(0 == ~T5_E~0); 17277#L1304-1 assume !(0 == ~T6_E~0); 18189#L1309-1 assume !(0 == ~T7_E~0); 18191#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16460#L1319-1 assume !(0 == ~T9_E~0); 16461#L1324-1 assume !(0 == ~T10_E~0); 16635#L1329-1 assume !(0 == ~T11_E~0); 16636#L1334-1 assume !(0 == ~T12_E~0); 18028#L1339-1 assume !(0 == ~T13_E~0); 18102#L1344-1 assume !(0 == ~E_M~0); 18103#L1349-1 assume !(0 == ~E_1~0); 17450#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 17451#L1359-1 assume !(0 == ~E_3~0); 17857#L1364-1 assume !(0 == ~E_4~0); 16760#L1369-1 assume !(0 == ~E_5~0); 16761#L1374-1 assume !(0 == ~E_6~0); 17457#L1379-1 assume !(0 == ~E_7~0); 17458#L1384-1 assume !(0 == ~E_8~0); 17535#L1389-1 assume !(0 == ~E_9~0); 18048#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 18049#L1399-1 assume !(0 == ~E_11~0); 18144#L1404-1 assume !(0 == ~E_12~0); 16856#L1409-1 assume !(0 == ~E_13~0); 16857#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18139#L628 assume !(1 == ~m_pc~0); 16759#L628-2 is_master_triggered_~__retres1~0#1 := 0; 16758#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17338#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17339#L1591 assume !(0 != activate_threads_~tmp~1#1); 18153#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17319#L647 assume 1 == ~t1_pc~0; 16685#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16686#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17370#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17819#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 18090#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18091#L666 assume 1 == ~t2_pc~0; 16531#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16532#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16676#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16677#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 17645#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17646#L685 assume !(1 == ~t3_pc~0); 17740#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17739#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17809#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17499#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17500#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16977#L704 assume 1 == ~t4_pc~0; 16978#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17511#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16324#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16325#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 17368#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17369#L723 assume !(1 == ~t5_pc~0); 17495#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 17712#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17850#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17624#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 17625#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16742#L742 assume 1 == ~t6_pc~0; 16743#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16897#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16667#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16429#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 16430#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16818#L761 assume !(1 == ~t7_pc~0); 16819#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 16694#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16695#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17502#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 17503#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16452#L780 assume 1 == ~t8_pc~0; 16453#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16732#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16733#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17464#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 17465#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17581#L799 assume 1 == ~t9_pc~0; 17682#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16455#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16456#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16724#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 17783#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17606#L818 assume !(1 == ~t10_pc~0); 16236#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 16237#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17675#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17609#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17610#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17652#L837 assume 1 == ~t11_pc~0; 17653#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17489#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18094#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17574#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 17575#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17327#L856 assume !(1 == ~t12_pc~0); 17328#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 17953#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16254#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16255#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 17931#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 18116#L875 assume 1 == ~t13_pc~0; 17275#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 16898#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 16899#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 16836#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 16837#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17674#L1427 assume !(1 == ~M_E~0); 17659#L1427-2 assume !(1 == ~T1_E~0); 16805#L1432-1 assume !(1 == ~T2_E~0); 16806#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17861#L1442-1 assume !(1 == ~T4_E~0); 17862#L1447-1 assume !(1 == ~T5_E~0); 17721#L1452-1 assume !(1 == ~T6_E~0); 16376#L1457-1 assume !(1 == ~T7_E~0); 16377#L1462-1 assume !(1 == ~T8_E~0); 17879#L1467-1 assume !(1 == ~T9_E~0); 17899#L1472-1 assume !(1 == ~T10_E~0); 17900#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17670#L1482-1 assume !(1 == ~T12_E~0); 17671#L1487-1 assume !(1 == ~T13_E~0); 16705#L1492-1 assume !(1 == ~E_M~0); 16706#L1497-1 assume !(1 == ~E_1~0); 17072#L1502-1 assume !(1 == ~E_2~0); 17073#L1507-1 assume !(1 == ~E_3~0); 16587#L1512-1 assume !(1 == ~E_4~0); 16588#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 17973#L1522-1 assume !(1 == ~E_6~0); 17316#L1527-1 assume !(1 == ~E_7~0); 17317#L1532-1 assume !(1 == ~E_8~0); 18175#L1537-1 assume !(1 == ~E_9~0); 17518#L1542-1 assume !(1 == ~E_10~0); 17345#L1547-1 assume !(1 == ~E_11~0); 17346#L1552-1 assume !(1 == ~E_12~0); 16277#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 16278#L1562-1 assume { :end_inline_reset_delta_events } true; 16888#L1928-2 [2022-12-13 16:30:30,971 INFO L750 eck$LassoCheckResult]: Loop: 16888#L1928-2 assume !false; 17382#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16543#L1254 assume !false; 17134#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16612#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16613#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16807#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 17959#L1067 assume !(0 != eval_~tmp~0#1); 17255#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16865#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16866#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17092#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17076#L1284-3 assume !(0 == ~T2_E~0); 17077#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17056#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17057#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17446#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17447#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16942#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16943#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17921#L1324-3 assume !(0 == ~T10_E~0); 16585#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 16586#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 17351#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 17352#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17649#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16926#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16927#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17657#L1364-3 assume !(0 == ~E_4~0); 18174#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18064#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16708#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16709#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16924#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 16925#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 17226#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18074#L1404-3 assume !(0 == ~E_12~0); 18038#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 18039#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17547#L628-45 assume 1 == ~m_pc~0; 17221#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17223#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17729#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16957#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16958#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17681#L647-45 assume 1 == ~t1_pc~0; 16528#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16529#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17463#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16641#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16642#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16849#L666-45 assume !(1 == ~t2_pc~0); 16850#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 17337#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17727#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17728#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17793#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16392#L685-45 assume 1 == ~t3_pc~0; 16393#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17459#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18105#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17971#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17972#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18114#L704-45 assume !(1 == ~t4_pc~0); 16256#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 16257#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17122#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17993#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18202#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17576#L723-45 assume !(1 == ~t5_pc~0); 17577#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 18050#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18165#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16938#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 16939#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17941#L742-45 assume 1 == ~t6_pc~0; 17942#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17195#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17407#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17408#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17686#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17772#L761-45 assume !(1 == ~t7_pc~0); 17773#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 17189#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17190#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16591#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16592#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18042#L780-45 assume !(1 == ~t8_pc~0); 16960#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 16602#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16603#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18172#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16571#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16572#L799-45 assume !(1 == ~t9_pc~0); 16785#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 16786#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17838#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17722#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17723#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16508#L818-45 assume 1 == ~t10_pc~0; 16509#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16629#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17699#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17120#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17121#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17817#L837-45 assume 1 == ~t11_pc~0; 18100#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17050#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16583#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16584#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 16650#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16651#L856-45 assume 1 == ~t12_pc~0; 18112#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 16653#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 17868#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 17869#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17461#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 17462#L875-45 assume 1 == ~t13_pc~0; 17430#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 17431#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17490#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 17830#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 18084#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18026#L1427-3 assume !(1 == ~M_E~0); 17260#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17261#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17780#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17448#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17449#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16294#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16295#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17957#L1462-3 assume !(1 == ~T8_E~0); 17958#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17825#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17826#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 16552#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 16553#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 16693#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16863#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16864#L1502-3 assume !(1 == ~E_2~0); 17800#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17919#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16902#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16595#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16596#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16562#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16563#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17658#L1542-3 assume !(1 == ~E_10~0); 17786#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 17433#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 17434#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 16763#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16764#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16186#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16625#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 16626#L1947 assume !(0 == start_simulation_~tmp~3#1); 17565#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 17754#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16822#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16244#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 16245#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17887#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17888#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 18047#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 16888#L1928-2 [2022-12-13 16:30:30,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:30,972 INFO L85 PathProgramCache]: Analyzing trace with hash -380736181, now seen corresponding path program 1 times [2022-12-13 16:30:30,972 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:30,973 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [399258346] [2022-12-13 16:30:30,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:30,973 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:30,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:31,034 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:31,035 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:31,035 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [399258346] [2022-12-13 16:30:31,035 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [399258346] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:31,035 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:31,035 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:31,036 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1624175240] [2022-12-13 16:30:31,036 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:31,036 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:30:31,037 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:31,037 INFO L85 PathProgramCache]: Analyzing trace with hash 1020991086, now seen corresponding path program 1 times [2022-12-13 16:30:31,037 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:31,037 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1619340280] [2022-12-13 16:30:31,037 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:31,037 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:31,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:31,117 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:31,118 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:31,118 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1619340280] [2022-12-13 16:30:31,118 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1619340280] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:31,118 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:31,118 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:31,119 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [744750392] [2022-12-13 16:30:31,119 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:31,119 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:30:31,119 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:30:31,120 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:30:31,120 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:30:31,120 INFO L87 Difference]: Start difference. First operand 2018 states and 2984 transitions. cyclomatic complexity: 967 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:31,161 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:30:31,161 INFO L93 Difference]: Finished difference Result 2018 states and 2983 transitions. [2022-12-13 16:30:31,161 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2983 transitions. [2022-12-13 16:30:31,170 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-12-13 16:30:31,178 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2983 transitions. [2022-12-13 16:30:31,178 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-12-13 16:30:31,180 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-12-13 16:30:31,180 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2983 transitions. [2022-12-13 16:30:31,182 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:30:31,182 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2983 transitions. [2022-12-13 16:30:31,185 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2983 transitions. [2022-12-13 16:30:31,208 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-12-13 16:30:31,212 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4781962338949455) internal successors, (2983), 2017 states have internal predecessors, (2983), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:31,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2983 transitions. [2022-12-13 16:30:31,216 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2983 transitions. [2022-12-13 16:30:31,217 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:30:31,217 INFO L428 stractBuchiCegarLoop]: Abstraction has 2018 states and 2983 transitions. [2022-12-13 16:30:31,217 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 16:30:31,218 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2983 transitions. [2022-12-13 16:30:31,224 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-12-13 16:30:31,224 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:30:31,224 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:30:31,226 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:31,227 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:31,227 INFO L748 eck$LassoCheckResult]: Stem: 20556#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 20557#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 21534#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21535#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22233#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 21133#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21134#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21202#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21203#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21636#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 21637#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 21168#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20977#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 20978#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21432#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21433#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21311#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 21312#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 20951#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20952#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 22156#L1279-2 assume !(0 == ~T1_E~0); 20577#L1284-1 assume !(0 == ~T2_E~0); 20578#L1289-1 assume !(0 == ~T3_E~0); 21308#L1294-1 assume !(0 == ~T4_E~0); 21309#L1299-1 assume !(0 == ~T5_E~0); 21320#L1304-1 assume !(0 == ~T6_E~0); 22232#L1309-1 assume !(0 == ~T7_E~0); 22234#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20503#L1319-1 assume !(0 == ~T9_E~0); 20504#L1324-1 assume !(0 == ~T10_E~0); 20678#L1329-1 assume !(0 == ~T11_E~0); 20679#L1334-1 assume !(0 == ~T12_E~0); 22071#L1339-1 assume !(0 == ~T13_E~0); 22145#L1344-1 assume !(0 == ~E_M~0); 22146#L1349-1 assume !(0 == ~E_1~0); 21493#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 21494#L1359-1 assume !(0 == ~E_3~0); 21900#L1364-1 assume !(0 == ~E_4~0); 20803#L1369-1 assume !(0 == ~E_5~0); 20804#L1374-1 assume !(0 == ~E_6~0); 21500#L1379-1 assume !(0 == ~E_7~0); 21501#L1384-1 assume !(0 == ~E_8~0); 21578#L1389-1 assume !(0 == ~E_9~0); 22091#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 22092#L1399-1 assume !(0 == ~E_11~0); 22187#L1404-1 assume !(0 == ~E_12~0); 20899#L1409-1 assume !(0 == ~E_13~0); 20900#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22182#L628 assume !(1 == ~m_pc~0); 20802#L628-2 is_master_triggered_~__retres1~0#1 := 0; 20801#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21381#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21382#L1591 assume !(0 != activate_threads_~tmp~1#1); 22196#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21362#L647 assume 1 == ~t1_pc~0; 20728#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20729#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21413#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21862#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 22133#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22134#L666 assume 1 == ~t2_pc~0; 20574#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20575#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20719#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20720#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 21688#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21689#L685 assume !(1 == ~t3_pc~0); 21783#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21782#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21852#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21542#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21543#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21020#L704 assume 1 == ~t4_pc~0; 21021#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21554#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20367#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20368#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 21411#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21412#L723 assume !(1 == ~t5_pc~0); 21538#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21755#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21893#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21667#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 21668#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20785#L742 assume 1 == ~t6_pc~0; 20786#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20940#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20710#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20472#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 20473#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20861#L761 assume !(1 == ~t7_pc~0); 20862#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20737#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20738#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21545#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 21546#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20495#L780 assume 1 == ~t8_pc~0; 20496#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20775#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20776#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21507#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 21508#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21624#L799 assume 1 == ~t9_pc~0; 21725#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20498#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20499#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20767#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 21826#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21649#L818 assume !(1 == ~t10_pc~0); 20279#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 20280#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21718#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21652#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21653#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21695#L837 assume 1 == ~t11_pc~0; 21696#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21532#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22137#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21617#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 21618#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21370#L856 assume !(1 == ~t12_pc~0); 21371#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 21996#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20297#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 20298#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 21974#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 22159#L875 assume 1 == ~t13_pc~0; 21318#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 20941#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 20942#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 20879#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 20880#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21717#L1427 assume !(1 == ~M_E~0); 21702#L1427-2 assume !(1 == ~T1_E~0); 20848#L1432-1 assume !(1 == ~T2_E~0); 20849#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21904#L1442-1 assume !(1 == ~T4_E~0); 21905#L1447-1 assume !(1 == ~T5_E~0); 21764#L1452-1 assume !(1 == ~T6_E~0); 20419#L1457-1 assume !(1 == ~T7_E~0); 20420#L1462-1 assume !(1 == ~T8_E~0); 21922#L1467-1 assume !(1 == ~T9_E~0); 21942#L1472-1 assume !(1 == ~T10_E~0); 21943#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21713#L1482-1 assume !(1 == ~T12_E~0); 21714#L1487-1 assume !(1 == ~T13_E~0); 20748#L1492-1 assume !(1 == ~E_M~0); 20749#L1497-1 assume !(1 == ~E_1~0); 21115#L1502-1 assume !(1 == ~E_2~0); 21116#L1507-1 assume !(1 == ~E_3~0); 20630#L1512-1 assume !(1 == ~E_4~0); 20631#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 22016#L1522-1 assume !(1 == ~E_6~0); 21359#L1527-1 assume !(1 == ~E_7~0); 21360#L1532-1 assume !(1 == ~E_8~0); 22218#L1537-1 assume !(1 == ~E_9~0); 21561#L1542-1 assume !(1 == ~E_10~0); 21388#L1547-1 assume !(1 == ~E_11~0); 21389#L1552-1 assume !(1 == ~E_12~0); 20320#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 20321#L1562-1 assume { :end_inline_reset_delta_events } true; 20931#L1928-2 [2022-12-13 16:30:31,227 INFO L750 eck$LassoCheckResult]: Loop: 20931#L1928-2 assume !false; 21425#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20586#L1254 assume !false; 21177#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20655#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20656#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20850#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22002#L1067 assume !(0 != eval_~tmp~0#1); 21298#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20908#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20909#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21135#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21119#L1284-3 assume !(0 == ~T2_E~0); 21120#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21099#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21100#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21489#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21490#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20985#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20986#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21964#L1324-3 assume !(0 == ~T10_E~0); 20628#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20629#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21394#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 21395#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21692#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20969#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20970#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21700#L1364-3 assume !(0 == ~E_4~0); 22217#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22107#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20751#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20752#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20967#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 20968#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21269#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22117#L1404-3 assume !(0 == ~E_12~0); 22081#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 22082#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21590#L628-45 assume 1 == ~m_pc~0; 21264#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21266#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21772#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21000#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21001#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21724#L647-45 assume 1 == ~t1_pc~0; 20571#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20572#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21506#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20684#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20685#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20892#L666-45 assume !(1 == ~t2_pc~0); 20893#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 21380#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21770#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21771#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21836#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20435#L685-45 assume 1 == ~t3_pc~0; 20436#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21502#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22148#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22014#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22015#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22157#L704-45 assume 1 == ~t4_pc~0; 22035#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20300#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21165#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22036#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22245#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21619#L723-45 assume !(1 == ~t5_pc~0); 21620#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 22093#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22208#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20981#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 20982#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21984#L742-45 assume 1 == ~t6_pc~0; 21985#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21238#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21450#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21451#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21729#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21815#L761-45 assume !(1 == ~t7_pc~0); 21816#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 21232#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21233#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20634#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20635#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22085#L780-45 assume 1 == ~t8_pc~0; 21002#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20645#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20646#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22215#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20614#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20615#L799-45 assume 1 == ~t9_pc~0; 21392#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20829#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21881#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21765#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21766#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20551#L818-45 assume 1 == ~t10_pc~0; 20552#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 20672#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21742#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21163#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21164#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21860#L837-45 assume !(1 == ~t11_pc~0); 21092#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 21093#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20626#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20627#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20693#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20694#L856-45 assume !(1 == ~t12_pc~0); 20695#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 20696#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21911#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21912#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 21504#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 21505#L875-45 assume 1 == ~t13_pc~0; 21473#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 21474#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21533#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 21873#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 22127#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22069#L1427-3 assume !(1 == ~M_E~0); 21303#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21304#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21823#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21491#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21492#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20337#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20338#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22000#L1462-3 assume !(1 == ~T8_E~0); 22001#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21868#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21869#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 20595#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 20596#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 20736#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20906#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20907#L1502-3 assume !(1 == ~E_2~0); 21843#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21962#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20945#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20638#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20639#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20605#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20606#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21701#L1542-3 assume !(1 == ~E_10~0); 21829#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21476#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 21477#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 20806#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20807#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20229#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20668#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 20669#L1947 assume !(0 == start_simulation_~tmp~3#1); 21608#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 21797#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20865#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20287#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 20288#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21930#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21931#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 22090#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 20931#L1928-2 [2022-12-13 16:30:31,228 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:31,228 INFO L85 PathProgramCache]: Analyzing trace with hash 1024455497, now seen corresponding path program 1 times [2022-12-13 16:30:31,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:31,228 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1432951663] [2022-12-13 16:30:31,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:31,229 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:31,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:31,271 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:31,271 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:31,271 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1432951663] [2022-12-13 16:30:31,272 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1432951663] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:31,272 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:31,272 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:31,272 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [219114657] [2022-12-13 16:30:31,272 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:31,272 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:30:31,273 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:31,273 INFO L85 PathProgramCache]: Analyzing trace with hash 248541229, now seen corresponding path program 1 times [2022-12-13 16:30:31,273 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:31,273 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1637755757] [2022-12-13 16:30:31,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:31,273 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:31,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:31,317 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:31,317 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:31,317 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1637755757] [2022-12-13 16:30:31,317 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1637755757] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:31,317 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:31,317 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:31,318 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [480345493] [2022-12-13 16:30:31,318 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:31,318 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:30:31,318 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:30:31,318 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:30:31,318 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:30:31,318 INFO L87 Difference]: Start difference. First operand 2018 states and 2983 transitions. cyclomatic complexity: 966 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:31,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:30:31,353 INFO L93 Difference]: Finished difference Result 2018 states and 2982 transitions. [2022-12-13 16:30:31,353 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2982 transitions. [2022-12-13 16:30:31,358 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-12-13 16:30:31,363 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2982 transitions. [2022-12-13 16:30:31,363 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-12-13 16:30:31,364 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-12-13 16:30:31,364 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2982 transitions. [2022-12-13 16:30:31,366 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:30:31,366 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2982 transitions. [2022-12-13 16:30:31,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2982 transitions. [2022-12-13 16:30:31,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-12-13 16:30:31,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4777006937561943) internal successors, (2982), 2017 states have internal predecessors, (2982), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:31,397 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2982 transitions. [2022-12-13 16:30:31,398 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2982 transitions. [2022-12-13 16:30:31,398 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:30:31,398 INFO L428 stractBuchiCegarLoop]: Abstraction has 2018 states and 2982 transitions. [2022-12-13 16:30:31,398 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 16:30:31,399 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2982 transitions. [2022-12-13 16:30:31,402 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-12-13 16:30:31,402 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:30:31,402 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:30:31,404 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:31,404 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:31,404 INFO L748 eck$LassoCheckResult]: Stem: 24599#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 24600#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 25577#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25578#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26276#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 25176#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25177#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25245#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25246#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25679#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25680#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 25211#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 25020#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25021#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25475#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25476#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25354#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 25355#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 24994#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24995#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 26199#L1279-2 assume !(0 == ~T1_E~0); 24620#L1284-1 assume !(0 == ~T2_E~0); 24621#L1289-1 assume !(0 == ~T3_E~0); 25351#L1294-1 assume !(0 == ~T4_E~0); 25352#L1299-1 assume !(0 == ~T5_E~0); 25363#L1304-1 assume !(0 == ~T6_E~0); 26275#L1309-1 assume !(0 == ~T7_E~0); 26277#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24546#L1319-1 assume !(0 == ~T9_E~0); 24547#L1324-1 assume !(0 == ~T10_E~0); 24721#L1329-1 assume !(0 == ~T11_E~0); 24722#L1334-1 assume !(0 == ~T12_E~0); 26114#L1339-1 assume !(0 == ~T13_E~0); 26188#L1344-1 assume !(0 == ~E_M~0); 26189#L1349-1 assume !(0 == ~E_1~0); 25536#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 25537#L1359-1 assume !(0 == ~E_3~0); 25943#L1364-1 assume !(0 == ~E_4~0); 24846#L1369-1 assume !(0 == ~E_5~0); 24847#L1374-1 assume !(0 == ~E_6~0); 25543#L1379-1 assume !(0 == ~E_7~0); 25544#L1384-1 assume !(0 == ~E_8~0); 25621#L1389-1 assume !(0 == ~E_9~0); 26134#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 26135#L1399-1 assume !(0 == ~E_11~0); 26230#L1404-1 assume !(0 == ~E_12~0); 24942#L1409-1 assume !(0 == ~E_13~0); 24943#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26225#L628 assume !(1 == ~m_pc~0); 24845#L628-2 is_master_triggered_~__retres1~0#1 := 0; 24844#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25424#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25425#L1591 assume !(0 != activate_threads_~tmp~1#1); 26239#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25405#L647 assume 1 == ~t1_pc~0; 24771#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24772#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25456#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25905#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 26176#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26177#L666 assume 1 == ~t2_pc~0; 24617#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24618#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24762#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24763#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 25731#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25732#L685 assume !(1 == ~t3_pc~0); 25826#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25825#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25895#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25585#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25586#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25063#L704 assume 1 == ~t4_pc~0; 25064#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25597#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24410#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24411#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 25454#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25455#L723 assume !(1 == ~t5_pc~0); 25581#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 25798#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25936#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25710#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 25711#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24828#L742 assume 1 == ~t6_pc~0; 24829#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24983#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24753#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24515#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 24516#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24904#L761 assume !(1 == ~t7_pc~0); 24905#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 24780#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24781#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25588#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 25589#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24538#L780 assume 1 == ~t8_pc~0; 24539#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24818#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24819#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25550#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 25551#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25667#L799 assume 1 == ~t9_pc~0; 25768#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24541#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24542#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24810#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 25869#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25692#L818 assume !(1 == ~t10_pc~0); 24322#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 24323#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25761#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25695#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 25696#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25738#L837 assume 1 == ~t11_pc~0; 25739#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25575#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26180#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25660#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 25661#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25413#L856 assume !(1 == ~t12_pc~0); 25414#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 26039#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24340#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 24341#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 26017#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 26202#L875 assume 1 == ~t13_pc~0; 25361#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 24984#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 24985#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 24922#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 24923#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25760#L1427 assume !(1 == ~M_E~0); 25745#L1427-2 assume !(1 == ~T1_E~0); 24891#L1432-1 assume !(1 == ~T2_E~0); 24892#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25947#L1442-1 assume !(1 == ~T4_E~0); 25948#L1447-1 assume !(1 == ~T5_E~0); 25807#L1452-1 assume !(1 == ~T6_E~0); 24462#L1457-1 assume !(1 == ~T7_E~0); 24463#L1462-1 assume !(1 == ~T8_E~0); 25965#L1467-1 assume !(1 == ~T9_E~0); 25985#L1472-1 assume !(1 == ~T10_E~0); 25986#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25756#L1482-1 assume !(1 == ~T12_E~0); 25757#L1487-1 assume !(1 == ~T13_E~0); 24791#L1492-1 assume !(1 == ~E_M~0); 24792#L1497-1 assume !(1 == ~E_1~0); 25158#L1502-1 assume !(1 == ~E_2~0); 25159#L1507-1 assume !(1 == ~E_3~0); 24673#L1512-1 assume !(1 == ~E_4~0); 24674#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 26059#L1522-1 assume !(1 == ~E_6~0); 25402#L1527-1 assume !(1 == ~E_7~0); 25403#L1532-1 assume !(1 == ~E_8~0); 26261#L1537-1 assume !(1 == ~E_9~0); 25604#L1542-1 assume !(1 == ~E_10~0); 25431#L1547-1 assume !(1 == ~E_11~0); 25432#L1552-1 assume !(1 == ~E_12~0); 24363#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 24364#L1562-1 assume { :end_inline_reset_delta_events } true; 24974#L1928-2 [2022-12-13 16:30:31,404 INFO L750 eck$LassoCheckResult]: Loop: 24974#L1928-2 assume !false; 25468#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24629#L1254 assume !false; 25220#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24698#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24699#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24893#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 26045#L1067 assume !(0 != eval_~tmp~0#1); 25341#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24951#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24952#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25178#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25162#L1284-3 assume !(0 == ~T2_E~0); 25163#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25142#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25143#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25532#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25533#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25028#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25029#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 26007#L1324-3 assume !(0 == ~T10_E~0); 24671#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 24672#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 25437#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 25438#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25735#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25012#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25013#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25743#L1364-3 assume !(0 == ~E_4~0); 26260#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26150#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24794#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24795#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25010#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25011#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25312#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 26160#L1404-3 assume !(0 == ~E_12~0); 26124#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 26125#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25633#L628-45 assume 1 == ~m_pc~0; 25307#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25309#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25815#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25043#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25044#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25767#L647-45 assume 1 == ~t1_pc~0; 24614#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24615#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25549#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24727#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24728#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24935#L666-45 assume !(1 == ~t2_pc~0); 24936#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 25423#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25813#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25814#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25879#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24478#L685-45 assume !(1 == ~t3_pc~0); 24480#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 25545#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26191#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26057#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26058#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26200#L704-45 assume !(1 == ~t4_pc~0); 24342#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 24343#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25208#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26079#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26288#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25662#L723-45 assume 1 == ~t5_pc~0; 25664#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26136#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26251#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25024#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 25025#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26027#L742-45 assume !(1 == ~t6_pc~0); 25280#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 25281#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25493#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25494#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25772#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25858#L761-45 assume !(1 == ~t7_pc~0); 25859#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 25275#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25276#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24677#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24678#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26128#L780-45 assume 1 == ~t8_pc~0; 25045#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24688#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24689#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26258#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24657#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24658#L799-45 assume !(1 == ~t9_pc~0); 24871#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 24872#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25924#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25808#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25809#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24594#L818-45 assume 1 == ~t10_pc~0; 24595#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24715#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25785#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25206#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 25207#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25903#L837-45 assume 1 == ~t11_pc~0; 26186#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25136#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24669#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 24670#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 24736#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24737#L856-45 assume !(1 == ~t12_pc~0); 24738#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 24739#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25954#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25955#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 25547#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 25548#L875-45 assume 1 == ~t13_pc~0; 25516#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25517#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 25576#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 25916#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 26170#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26112#L1427-3 assume !(1 == ~M_E~0); 25346#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25347#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25866#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25534#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25535#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24380#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24381#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26043#L1462-3 assume !(1 == ~T8_E~0); 26044#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25911#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25912#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 24638#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 24639#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 24779#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 24949#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24950#L1502-3 assume !(1 == ~E_2~0); 25886#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26005#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24988#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24681#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24682#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24648#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24649#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25744#L1542-3 assume !(1 == ~E_10~0); 25872#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 25519#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 25520#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 24849#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24850#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24272#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24711#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 24712#L1947 assume !(0 == start_simulation_~tmp~3#1); 25651#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 25840#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24908#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24330#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 24331#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25973#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25974#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 26133#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 24974#L1928-2 [2022-12-13 16:30:31,404 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:31,405 INFO L85 PathProgramCache]: Analyzing trace with hash -869878389, now seen corresponding path program 1 times [2022-12-13 16:30:31,405 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:31,405 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1749048728] [2022-12-13 16:30:31,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:31,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:31,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:31,433 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:31,433 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:31,433 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1749048728] [2022-12-13 16:30:31,433 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1749048728] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:31,433 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:31,434 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:31,434 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2051630469] [2022-12-13 16:30:31,434 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:31,434 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:30:31,434 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:31,435 INFO L85 PathProgramCache]: Analyzing trace with hash -1593983953, now seen corresponding path program 1 times [2022-12-13 16:30:31,435 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:31,435 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1198702763] [2022-12-13 16:30:31,435 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:31,435 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:31,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:31,482 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:31,482 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:31,482 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1198702763] [2022-12-13 16:30:31,482 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1198702763] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:31,482 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:31,482 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:31,482 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1258719093] [2022-12-13 16:30:31,483 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:31,483 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:30:31,483 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:30:31,483 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:30:31,483 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:30:31,484 INFO L87 Difference]: Start difference. First operand 2018 states and 2982 transitions. cyclomatic complexity: 965 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:31,505 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:30:31,505 INFO L93 Difference]: Finished difference Result 2018 states and 2981 transitions. [2022-12-13 16:30:31,506 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2981 transitions. [2022-12-13 16:30:31,511 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-12-13 16:30:31,515 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2981 transitions. [2022-12-13 16:30:31,516 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-12-13 16:30:31,517 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-12-13 16:30:31,517 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2981 transitions. [2022-12-13 16:30:31,518 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:30:31,518 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2981 transitions. [2022-12-13 16:30:31,521 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2981 transitions. [2022-12-13 16:30:31,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-12-13 16:30:31,538 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.477205153617443) internal successors, (2981), 2017 states have internal predecessors, (2981), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:31,540 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2981 transitions. [2022-12-13 16:30:31,541 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2981 transitions. [2022-12-13 16:30:31,541 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:30:31,541 INFO L428 stractBuchiCegarLoop]: Abstraction has 2018 states and 2981 transitions. [2022-12-13 16:30:31,541 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 16:30:31,541 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2981 transitions. [2022-12-13 16:30:31,546 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-12-13 16:30:31,546 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:30:31,546 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:30:31,547 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:31,547 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:31,548 INFO L748 eck$LassoCheckResult]: Stem: 28642#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 28643#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 29620#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29621#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30319#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 29219#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29220#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29288#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29289#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29722#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29723#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29254#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 29063#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 29064#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29518#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29519#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29397#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29398#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 29037#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29038#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 30242#L1279-2 assume !(0 == ~T1_E~0); 28663#L1284-1 assume !(0 == ~T2_E~0); 28664#L1289-1 assume !(0 == ~T3_E~0); 29394#L1294-1 assume !(0 == ~T4_E~0); 29395#L1299-1 assume !(0 == ~T5_E~0); 29406#L1304-1 assume !(0 == ~T6_E~0); 30318#L1309-1 assume !(0 == ~T7_E~0); 30320#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28589#L1319-1 assume !(0 == ~T9_E~0); 28590#L1324-1 assume !(0 == ~T10_E~0); 28764#L1329-1 assume !(0 == ~T11_E~0); 28765#L1334-1 assume !(0 == ~T12_E~0); 30157#L1339-1 assume !(0 == ~T13_E~0); 30231#L1344-1 assume !(0 == ~E_M~0); 30232#L1349-1 assume !(0 == ~E_1~0); 29579#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 29580#L1359-1 assume !(0 == ~E_3~0); 29986#L1364-1 assume !(0 == ~E_4~0); 28889#L1369-1 assume !(0 == ~E_5~0); 28890#L1374-1 assume !(0 == ~E_6~0); 29586#L1379-1 assume !(0 == ~E_7~0); 29587#L1384-1 assume !(0 == ~E_8~0); 29664#L1389-1 assume !(0 == ~E_9~0); 30177#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 30178#L1399-1 assume !(0 == ~E_11~0); 30273#L1404-1 assume !(0 == ~E_12~0); 28985#L1409-1 assume !(0 == ~E_13~0); 28986#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30268#L628 assume !(1 == ~m_pc~0); 28888#L628-2 is_master_triggered_~__retres1~0#1 := 0; 28887#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29467#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29468#L1591 assume !(0 != activate_threads_~tmp~1#1); 30282#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29448#L647 assume 1 == ~t1_pc~0; 28814#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28815#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29499#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29948#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 30219#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30220#L666 assume 1 == ~t2_pc~0; 28660#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28661#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28805#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28806#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 29774#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29775#L685 assume !(1 == ~t3_pc~0); 29869#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29868#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29938#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29628#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29629#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29106#L704 assume 1 == ~t4_pc~0; 29107#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29640#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28453#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28454#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 29497#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29498#L723 assume !(1 == ~t5_pc~0); 29624#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 29841#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29979#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29753#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 29754#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28871#L742 assume 1 == ~t6_pc~0; 28872#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29026#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28796#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28558#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 28559#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28947#L761 assume !(1 == ~t7_pc~0); 28948#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 28823#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28824#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29631#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 29632#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28581#L780 assume 1 == ~t8_pc~0; 28582#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28861#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28862#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29593#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 29594#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29710#L799 assume 1 == ~t9_pc~0; 29811#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28584#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28585#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28853#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 29912#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29735#L818 assume !(1 == ~t10_pc~0); 28365#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 28366#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29804#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29738#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29739#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29781#L837 assume 1 == ~t11_pc~0; 29782#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29618#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30223#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29703#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 29704#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29456#L856 assume !(1 == ~t12_pc~0); 29457#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 30082#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28383#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28384#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 30060#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 30245#L875 assume 1 == ~t13_pc~0; 29404#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29027#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29028#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 28965#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 28966#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29803#L1427 assume !(1 == ~M_E~0); 29788#L1427-2 assume !(1 == ~T1_E~0); 28934#L1432-1 assume !(1 == ~T2_E~0); 28935#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29990#L1442-1 assume !(1 == ~T4_E~0); 29991#L1447-1 assume !(1 == ~T5_E~0); 29850#L1452-1 assume !(1 == ~T6_E~0); 28505#L1457-1 assume !(1 == ~T7_E~0); 28506#L1462-1 assume !(1 == ~T8_E~0); 30008#L1467-1 assume !(1 == ~T9_E~0); 30028#L1472-1 assume !(1 == ~T10_E~0); 30029#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29799#L1482-1 assume !(1 == ~T12_E~0); 29800#L1487-1 assume !(1 == ~T13_E~0); 28834#L1492-1 assume !(1 == ~E_M~0); 28835#L1497-1 assume !(1 == ~E_1~0); 29201#L1502-1 assume !(1 == ~E_2~0); 29202#L1507-1 assume !(1 == ~E_3~0); 28716#L1512-1 assume !(1 == ~E_4~0); 28717#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 30102#L1522-1 assume !(1 == ~E_6~0); 29445#L1527-1 assume !(1 == ~E_7~0); 29446#L1532-1 assume !(1 == ~E_8~0); 30304#L1537-1 assume !(1 == ~E_9~0); 29647#L1542-1 assume !(1 == ~E_10~0); 29474#L1547-1 assume !(1 == ~E_11~0); 29475#L1552-1 assume !(1 == ~E_12~0); 28406#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 28407#L1562-1 assume { :end_inline_reset_delta_events } true; 29017#L1928-2 [2022-12-13 16:30:31,548 INFO L750 eck$LassoCheckResult]: Loop: 29017#L1928-2 assume !false; 29511#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28672#L1254 assume !false; 29263#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28741#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28742#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28936#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 30088#L1067 assume !(0 != eval_~tmp~0#1); 29384#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28994#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28995#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29221#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29205#L1284-3 assume !(0 == ~T2_E~0); 29206#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29185#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29186#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29575#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29576#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29071#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29072#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30050#L1324-3 assume !(0 == ~T10_E~0); 28714#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 28715#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 29480#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 29481#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29778#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29055#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29056#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29786#L1364-3 assume !(0 == ~E_4~0); 30303#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30193#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28837#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28838#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29053#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29054#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 29355#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 30203#L1404-3 assume !(0 == ~E_12~0); 30167#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 30168#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29676#L628-45 assume 1 == ~m_pc~0; 29350#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29352#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29858#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29086#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29087#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29810#L647-45 assume 1 == ~t1_pc~0; 28657#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28658#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29592#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28770#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28771#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28978#L666-45 assume !(1 == ~t2_pc~0); 28979#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 29466#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29856#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29857#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29922#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28521#L685-45 assume 1 == ~t3_pc~0; 28522#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29588#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30234#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30100#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30101#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30243#L704-45 assume !(1 == ~t4_pc~0); 28385#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 28386#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29251#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30122#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30331#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29705#L723-45 assume !(1 == ~t5_pc~0); 29706#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 30179#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30294#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29067#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 29068#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30070#L742-45 assume 1 == ~t6_pc~0; 30071#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29324#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29536#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29537#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29815#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29901#L761-45 assume !(1 == ~t7_pc~0); 29902#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 29318#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29319#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28720#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28721#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30171#L780-45 assume 1 == ~t8_pc~0; 29088#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28731#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28732#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30301#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28700#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28701#L799-45 assume !(1 == ~t9_pc~0); 28914#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 28915#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29967#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29851#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29852#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28637#L818-45 assume 1 == ~t10_pc~0; 28638#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28758#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29828#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29249#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29250#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29946#L837-45 assume 1 == ~t11_pc~0; 30229#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29179#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28712#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28713#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28779#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28780#L856-45 assume 1 == ~t12_pc~0; 30241#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 28782#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 29997#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29998#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 29590#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 29591#L875-45 assume 1 == ~t13_pc~0; 29559#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29560#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29619#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 29959#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 30213#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30155#L1427-3 assume !(1 == ~M_E~0); 29389#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29390#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29909#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29577#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29578#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28423#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28424#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30086#L1462-3 assume !(1 == ~T8_E~0); 30087#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29954#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29955#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28681#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28682#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 28822#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 28992#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28993#L1502-3 assume !(1 == ~E_2~0); 29929#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30048#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29031#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 28724#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28725#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28691#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28692#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 29787#L1542-3 assume !(1 == ~E_10~0); 29915#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 29562#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 29563#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 28892#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28893#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28315#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28754#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 28755#L1947 assume !(0 == start_simulation_~tmp~3#1); 29694#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 29883#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28951#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28373#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 28374#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30016#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30017#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 30176#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 29017#L1928-2 [2022-12-13 16:30:31,548 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:31,548 INFO L85 PathProgramCache]: Analyzing trace with hash 1978508041, now seen corresponding path program 1 times [2022-12-13 16:30:31,548 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:31,548 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1169580211] [2022-12-13 16:30:31,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:31,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:31,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:31,576 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:31,576 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:31,576 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1169580211] [2022-12-13 16:30:31,576 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1169580211] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:31,576 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:31,576 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:31,576 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [866911504] [2022-12-13 16:30:31,576 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:31,577 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:30:31,577 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:31,577 INFO L85 PathProgramCache]: Analyzing trace with hash -1431662419, now seen corresponding path program 1 times [2022-12-13 16:30:31,577 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:31,577 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [362655210] [2022-12-13 16:30:31,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:31,577 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:31,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:31,613 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:31,613 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:31,614 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [362655210] [2022-12-13 16:30:31,614 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [362655210] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:31,614 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:31,614 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:31,614 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [506291194] [2022-12-13 16:30:31,614 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:31,614 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:30:31,615 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:30:31,615 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:30:31,615 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:30:31,615 INFO L87 Difference]: Start difference. First operand 2018 states and 2981 transitions. cyclomatic complexity: 964 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:31,646 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:30:31,646 INFO L93 Difference]: Finished difference Result 2018 states and 2980 transitions. [2022-12-13 16:30:31,646 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2980 transitions. [2022-12-13 16:30:31,651 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-12-13 16:30:31,655 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2980 transitions. [2022-12-13 16:30:31,656 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-12-13 16:30:31,656 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-12-13 16:30:31,657 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2980 transitions. [2022-12-13 16:30:31,658 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:30:31,658 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2980 transitions. [2022-12-13 16:30:31,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2980 transitions. [2022-12-13 16:30:31,674 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-12-13 16:30:31,676 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4767096134786917) internal successors, (2980), 2017 states have internal predecessors, (2980), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:31,679 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2980 transitions. [2022-12-13 16:30:31,679 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2980 transitions. [2022-12-13 16:30:31,679 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:30:31,680 INFO L428 stractBuchiCegarLoop]: Abstraction has 2018 states and 2980 transitions. [2022-12-13 16:30:31,680 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 16:30:31,680 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2980 transitions. [2022-12-13 16:30:31,684 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-12-13 16:30:31,684 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:30:31,684 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:30:31,685 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:31,685 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:31,686 INFO L748 eck$LassoCheckResult]: Stem: 32685#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 32686#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 33663#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33664#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34362#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 33262#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33263#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33331#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33332#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33765#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33766#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33297#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33106#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 33107#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33561#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 33562#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33440#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33441#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 33080#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33081#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 34285#L1279-2 assume !(0 == ~T1_E~0); 32706#L1284-1 assume !(0 == ~T2_E~0); 32707#L1289-1 assume !(0 == ~T3_E~0); 33437#L1294-1 assume !(0 == ~T4_E~0); 33438#L1299-1 assume !(0 == ~T5_E~0); 33449#L1304-1 assume !(0 == ~T6_E~0); 34361#L1309-1 assume !(0 == ~T7_E~0); 34363#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32632#L1319-1 assume !(0 == ~T9_E~0); 32633#L1324-1 assume !(0 == ~T10_E~0); 32807#L1329-1 assume !(0 == ~T11_E~0); 32808#L1334-1 assume !(0 == ~T12_E~0); 34200#L1339-1 assume !(0 == ~T13_E~0); 34274#L1344-1 assume !(0 == ~E_M~0); 34275#L1349-1 assume !(0 == ~E_1~0); 33622#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 33623#L1359-1 assume !(0 == ~E_3~0); 34029#L1364-1 assume !(0 == ~E_4~0); 32932#L1369-1 assume !(0 == ~E_5~0); 32933#L1374-1 assume !(0 == ~E_6~0); 33629#L1379-1 assume !(0 == ~E_7~0); 33630#L1384-1 assume !(0 == ~E_8~0); 33707#L1389-1 assume !(0 == ~E_9~0); 34220#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 34221#L1399-1 assume !(0 == ~E_11~0); 34316#L1404-1 assume !(0 == ~E_12~0); 33028#L1409-1 assume !(0 == ~E_13~0); 33029#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34311#L628 assume !(1 == ~m_pc~0); 32931#L628-2 is_master_triggered_~__retres1~0#1 := 0; 32930#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33510#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33511#L1591 assume !(0 != activate_threads_~tmp~1#1); 34325#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33491#L647 assume 1 == ~t1_pc~0; 32857#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 32858#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33542#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33991#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 34262#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34263#L666 assume 1 == ~t2_pc~0; 32703#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32704#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32848#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32849#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 33817#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33818#L685 assume !(1 == ~t3_pc~0); 33912#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33911#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33981#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33671#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33672#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33149#L704 assume 1 == ~t4_pc~0; 33150#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33683#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32496#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32497#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 33540#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33541#L723 assume !(1 == ~t5_pc~0); 33667#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 33884#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34022#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33796#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 33797#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32914#L742 assume 1 == ~t6_pc~0; 32915#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33069#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32839#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32601#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 32602#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32990#L761 assume !(1 == ~t7_pc~0); 32991#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 32866#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32867#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33674#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 33675#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32624#L780 assume 1 == ~t8_pc~0; 32625#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32904#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32905#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33636#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 33637#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33753#L799 assume 1 == ~t9_pc~0; 33854#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32627#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32628#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32896#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 33955#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33778#L818 assume !(1 == ~t10_pc~0); 32408#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 32409#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33847#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33781#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 33782#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33824#L837 assume 1 == ~t11_pc~0; 33825#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33661#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34266#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 33746#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 33747#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33499#L856 assume !(1 == ~t12_pc~0); 33500#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 34125#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32426#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32427#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 34103#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 34288#L875 assume 1 == ~t13_pc~0; 33447#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 33070#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 33071#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 33008#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 33009#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33846#L1427 assume !(1 == ~M_E~0); 33831#L1427-2 assume !(1 == ~T1_E~0); 32977#L1432-1 assume !(1 == ~T2_E~0); 32978#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34033#L1442-1 assume !(1 == ~T4_E~0); 34034#L1447-1 assume !(1 == ~T5_E~0); 33893#L1452-1 assume !(1 == ~T6_E~0); 32548#L1457-1 assume !(1 == ~T7_E~0); 32549#L1462-1 assume !(1 == ~T8_E~0); 34051#L1467-1 assume !(1 == ~T9_E~0); 34071#L1472-1 assume !(1 == ~T10_E~0); 34072#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33842#L1482-1 assume !(1 == ~T12_E~0); 33843#L1487-1 assume !(1 == ~T13_E~0); 32877#L1492-1 assume !(1 == ~E_M~0); 32878#L1497-1 assume !(1 == ~E_1~0); 33244#L1502-1 assume !(1 == ~E_2~0); 33245#L1507-1 assume !(1 == ~E_3~0); 32759#L1512-1 assume !(1 == ~E_4~0); 32760#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 34145#L1522-1 assume !(1 == ~E_6~0); 33488#L1527-1 assume !(1 == ~E_7~0); 33489#L1532-1 assume !(1 == ~E_8~0); 34347#L1537-1 assume !(1 == ~E_9~0); 33690#L1542-1 assume !(1 == ~E_10~0); 33517#L1547-1 assume !(1 == ~E_11~0); 33518#L1552-1 assume !(1 == ~E_12~0); 32449#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 32450#L1562-1 assume { :end_inline_reset_delta_events } true; 33060#L1928-2 [2022-12-13 16:30:31,686 INFO L750 eck$LassoCheckResult]: Loop: 33060#L1928-2 assume !false; 33554#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32715#L1254 assume !false; 33306#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32784#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32785#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 32979#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 34131#L1067 assume !(0 != eval_~tmp~0#1); 33427#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33037#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33038#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33264#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33248#L1284-3 assume !(0 == ~T2_E~0); 33249#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33228#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33229#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33618#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 33619#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33114#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33115#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 34093#L1324-3 assume !(0 == ~T10_E~0); 32757#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32758#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 33523#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 33524#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 33821#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33098#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33099#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33829#L1364-3 assume !(0 == ~E_4~0); 34346#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 34236#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32880#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 32881#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33096#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 33097#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 33398#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 34246#L1404-3 assume !(0 == ~E_12~0); 34210#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 34211#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33719#L628-45 assume 1 == ~m_pc~0; 33393#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 33395#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33901#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33129#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33130#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33853#L647-45 assume 1 == ~t1_pc~0; 32700#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 32701#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33635#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32813#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32814#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33021#L666-45 assume !(1 == ~t2_pc~0); 33022#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 33509#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33899#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33900#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33965#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32564#L685-45 assume 1 == ~t3_pc~0; 32565#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33631#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34277#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34143#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34144#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34286#L704-45 assume 1 == ~t4_pc~0; 34164#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32429#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33294#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34165#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 34374#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33748#L723-45 assume !(1 == ~t5_pc~0); 33749#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 34222#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34337#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33110#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 33111#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34113#L742-45 assume 1 == ~t6_pc~0; 34114#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33367#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33579#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33580#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33858#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33944#L761-45 assume !(1 == ~t7_pc~0); 33945#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 33361#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33362#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32763#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 32764#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 34214#L780-45 assume 1 == ~t8_pc~0; 33131#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32774#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32775#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34344#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32743#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32744#L799-45 assume 1 == ~t9_pc~0; 33521#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32958#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34010#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33894#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33895#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32680#L818-45 assume 1 == ~t10_pc~0; 32681#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 32801#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33871#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33292#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 33293#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33989#L837-45 assume 1 == ~t11_pc~0; 34272#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33222#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32755#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32756#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32822#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32823#L856-45 assume !(1 == ~t12_pc~0); 32824#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 32825#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34040#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34041#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 33633#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 33634#L875-45 assume 1 == ~t13_pc~0; 33602#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 33603#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 33662#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 34002#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 34256#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34198#L1427-3 assume !(1 == ~M_E~0); 33432#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33433#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33952#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33620#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33621#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32466#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32467#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34129#L1462-3 assume !(1 == ~T8_E~0); 34130#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 33997#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33998#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 32724#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 32725#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 32865#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33035#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33036#L1502-3 assume !(1 == ~E_2~0); 33972#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34091#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33074#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32767#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32768#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32734#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32735#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 33830#L1542-3 assume !(1 == ~E_10~0); 33958#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33605#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 33606#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 32935#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32936#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32358#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 32797#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 32798#L1947 assume !(0 == start_simulation_~tmp~3#1); 33737#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 33926#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32994#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 32416#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 32417#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34059#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34060#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 34219#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 33060#L1928-2 [2022-12-13 16:30:31,686 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:31,686 INFO L85 PathProgramCache]: Analyzing trace with hash -1393291829, now seen corresponding path program 1 times [2022-12-13 16:30:31,686 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:31,686 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [726140885] [2022-12-13 16:30:31,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:31,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:31,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:31,714 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:31,714 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:31,714 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [726140885] [2022-12-13 16:30:31,714 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [726140885] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:31,714 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:31,714 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:31,714 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2136313858] [2022-12-13 16:30:31,715 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:31,715 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:30:31,715 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:31,715 INFO L85 PathProgramCache]: Analyzing trace with hash 1279872044, now seen corresponding path program 1 times [2022-12-13 16:30:31,716 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:31,716 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [984270764] [2022-12-13 16:30:31,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:31,716 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:31,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:31,752 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:31,753 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:31,753 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [984270764] [2022-12-13 16:30:31,753 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [984270764] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:31,753 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:31,753 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:31,753 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1388072517] [2022-12-13 16:30:31,753 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:31,753 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:30:31,753 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:30:31,753 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:30:31,754 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:30:31,754 INFO L87 Difference]: Start difference. First operand 2018 states and 2980 transitions. cyclomatic complexity: 963 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:31,771 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:30:31,771 INFO L93 Difference]: Finished difference Result 2018 states and 2979 transitions. [2022-12-13 16:30:31,771 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2979 transitions. [2022-12-13 16:30:31,776 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-12-13 16:30:31,780 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2979 transitions. [2022-12-13 16:30:31,781 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-12-13 16:30:31,782 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-12-13 16:30:31,782 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2979 transitions. [2022-12-13 16:30:31,783 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:30:31,784 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2979 transitions. [2022-12-13 16:30:31,786 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2979 transitions. [2022-12-13 16:30:31,800 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-12-13 16:30:31,802 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4762140733399405) internal successors, (2979), 2017 states have internal predecessors, (2979), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:31,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2979 transitions. [2022-12-13 16:30:31,805 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2979 transitions. [2022-12-13 16:30:31,805 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:30:31,806 INFO L428 stractBuchiCegarLoop]: Abstraction has 2018 states and 2979 transitions. [2022-12-13 16:30:31,806 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 16:30:31,806 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2979 transitions. [2022-12-13 16:30:31,809 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-12-13 16:30:31,810 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:30:31,810 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:30:31,811 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:31,811 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:31,811 INFO L748 eck$LassoCheckResult]: Stem: 36728#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 36729#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 37706#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37707#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38405#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 37305#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37306#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37374#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37375#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 37808#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37809#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37340#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37149#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37150#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 37604#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 37605#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37483#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 37484#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 37123#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37124#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 38328#L1279-2 assume !(0 == ~T1_E~0); 36749#L1284-1 assume !(0 == ~T2_E~0); 36750#L1289-1 assume !(0 == ~T3_E~0); 37480#L1294-1 assume !(0 == ~T4_E~0); 37481#L1299-1 assume !(0 == ~T5_E~0); 37492#L1304-1 assume !(0 == ~T6_E~0); 38404#L1309-1 assume !(0 == ~T7_E~0); 38406#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36675#L1319-1 assume !(0 == ~T9_E~0); 36676#L1324-1 assume !(0 == ~T10_E~0); 36850#L1329-1 assume !(0 == ~T11_E~0); 36851#L1334-1 assume !(0 == ~T12_E~0); 38243#L1339-1 assume !(0 == ~T13_E~0); 38317#L1344-1 assume !(0 == ~E_M~0); 38318#L1349-1 assume !(0 == ~E_1~0); 37665#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 37666#L1359-1 assume !(0 == ~E_3~0); 38072#L1364-1 assume !(0 == ~E_4~0); 36975#L1369-1 assume !(0 == ~E_5~0); 36976#L1374-1 assume !(0 == ~E_6~0); 37672#L1379-1 assume !(0 == ~E_7~0); 37673#L1384-1 assume !(0 == ~E_8~0); 37750#L1389-1 assume !(0 == ~E_9~0); 38263#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 38264#L1399-1 assume !(0 == ~E_11~0); 38359#L1404-1 assume !(0 == ~E_12~0); 37071#L1409-1 assume !(0 == ~E_13~0); 37072#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38354#L628 assume !(1 == ~m_pc~0); 36974#L628-2 is_master_triggered_~__retres1~0#1 := 0; 36973#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37553#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37554#L1591 assume !(0 != activate_threads_~tmp~1#1); 38368#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37534#L647 assume 1 == ~t1_pc~0; 36900#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36901#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37585#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38034#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 38305#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38306#L666 assume 1 == ~t2_pc~0; 36746#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36747#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36891#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36892#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 37860#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37861#L685 assume !(1 == ~t3_pc~0); 37955#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37954#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38024#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37714#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37715#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37192#L704 assume 1 == ~t4_pc~0; 37193#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37726#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36539#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36540#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 37583#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37584#L723 assume !(1 == ~t5_pc~0); 37710#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 37927#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38065#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37839#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 37840#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36957#L742 assume 1 == ~t6_pc~0; 36958#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37112#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36882#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36644#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 36645#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37033#L761 assume !(1 == ~t7_pc~0); 37034#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 36909#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36910#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37717#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 37718#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36667#L780 assume 1 == ~t8_pc~0; 36668#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36947#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36948#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37679#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 37680#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37796#L799 assume 1 == ~t9_pc~0; 37897#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36670#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36671#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36939#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 37998#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37821#L818 assume !(1 == ~t10_pc~0); 36451#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36452#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37890#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37824#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37825#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37867#L837 assume 1 == ~t11_pc~0; 37868#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 37704#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38309#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37789#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 37790#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37542#L856 assume !(1 == ~t12_pc~0); 37543#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 38168#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36469#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 36470#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 38146#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 38331#L875 assume 1 == ~t13_pc~0; 37490#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37113#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 37114#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 37051#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 37052#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37889#L1427 assume !(1 == ~M_E~0); 37874#L1427-2 assume !(1 == ~T1_E~0); 37020#L1432-1 assume !(1 == ~T2_E~0); 37021#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38076#L1442-1 assume !(1 == ~T4_E~0); 38077#L1447-1 assume !(1 == ~T5_E~0); 37936#L1452-1 assume !(1 == ~T6_E~0); 36591#L1457-1 assume !(1 == ~T7_E~0); 36592#L1462-1 assume !(1 == ~T8_E~0); 38094#L1467-1 assume !(1 == ~T9_E~0); 38114#L1472-1 assume !(1 == ~T10_E~0); 38115#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37885#L1482-1 assume !(1 == ~T12_E~0); 37886#L1487-1 assume !(1 == ~T13_E~0); 36920#L1492-1 assume !(1 == ~E_M~0); 36921#L1497-1 assume !(1 == ~E_1~0); 37287#L1502-1 assume !(1 == ~E_2~0); 37288#L1507-1 assume !(1 == ~E_3~0); 36802#L1512-1 assume !(1 == ~E_4~0); 36803#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 38188#L1522-1 assume !(1 == ~E_6~0); 37531#L1527-1 assume !(1 == ~E_7~0); 37532#L1532-1 assume !(1 == ~E_8~0); 38390#L1537-1 assume !(1 == ~E_9~0); 37733#L1542-1 assume !(1 == ~E_10~0); 37560#L1547-1 assume !(1 == ~E_11~0); 37561#L1552-1 assume !(1 == ~E_12~0); 36492#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 36493#L1562-1 assume { :end_inline_reset_delta_events } true; 37103#L1928-2 [2022-12-13 16:30:31,812 INFO L750 eck$LassoCheckResult]: Loop: 37103#L1928-2 assume !false; 37597#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36758#L1254 assume !false; 37349#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36827#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36828#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 37022#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 38174#L1067 assume !(0 != eval_~tmp~0#1); 37470#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37080#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37081#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37307#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37291#L1284-3 assume !(0 == ~T2_E~0); 37292#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 37271#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37272#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37661#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37662#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 37157#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37158#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 38136#L1324-3 assume !(0 == ~T10_E~0); 36800#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36801#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 37566#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 37567#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 37864#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37141#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37142#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 37872#L1364-3 assume !(0 == ~E_4~0); 38389#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38279#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36923#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36924#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37139#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 37140#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 37441#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 38289#L1404-3 assume !(0 == ~E_12~0); 38253#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 38254#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37762#L628-45 assume 1 == ~m_pc~0; 37436#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 37438#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37944#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37172#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 37173#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37896#L647-45 assume 1 == ~t1_pc~0; 36743#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36744#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37678#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36856#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36857#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37064#L666-45 assume !(1 == ~t2_pc~0); 37065#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 37552#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37942#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37943#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38008#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36607#L685-45 assume 1 == ~t3_pc~0; 36608#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37674#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38320#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38186#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38187#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38329#L704-45 assume !(1 == ~t4_pc~0); 36471#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 36472#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37337#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38208#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38417#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37791#L723-45 assume !(1 == ~t5_pc~0); 37792#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 38265#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38380#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37153#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 37154#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38156#L742-45 assume !(1 == ~t6_pc~0); 37409#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 37410#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37622#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37623#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37901#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37987#L761-45 assume !(1 == ~t7_pc~0); 37988#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 37404#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37405#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36806#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 36807#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38257#L780-45 assume 1 == ~t8_pc~0; 37174#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36817#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36818#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38387#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36786#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36787#L799-45 assume !(1 == ~t9_pc~0); 37000#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 37001#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38053#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37937#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 37938#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36723#L818-45 assume 1 == ~t10_pc~0; 36724#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 36844#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37914#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37335#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37336#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38032#L837-45 assume !(1 == ~t11_pc~0); 37264#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 37265#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36798#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36799#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 36865#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36866#L856-45 assume !(1 == ~t12_pc~0); 36867#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 36868#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38083#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38084#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 37676#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37677#L875-45 assume 1 == ~t13_pc~0; 37645#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37646#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 37705#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 38045#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 38299#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38241#L1427-3 assume !(1 == ~M_E~0); 37475#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37476#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37995#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37663#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37664#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36509#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36510#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38172#L1462-3 assume !(1 == ~T8_E~0); 38173#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38040#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 38041#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 36767#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 36768#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 36908#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37078#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37079#L1502-3 assume !(1 == ~E_2~0); 38015#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38134#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37117#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36810#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36811#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 36777#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36778#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 37873#L1542-3 assume !(1 == ~E_10~0); 38001#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 37648#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 37649#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 36978#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36979#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36401#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 36840#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 36841#L1947 assume !(0 == start_simulation_~tmp~3#1); 37780#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 37969#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 37037#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 36459#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 36460#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38102#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38103#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 38262#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 37103#L1928-2 [2022-12-13 16:30:31,812 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:31,813 INFO L85 PathProgramCache]: Analyzing trace with hash -1779154231, now seen corresponding path program 1 times [2022-12-13 16:30:31,813 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:31,813 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1876236981] [2022-12-13 16:30:31,813 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:31,813 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:31,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:31,840 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:31,840 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:31,840 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1876236981] [2022-12-13 16:30:31,840 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1876236981] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:31,840 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:31,840 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:31,840 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [103185144] [2022-12-13 16:30:31,840 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:31,840 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:30:31,841 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:31,841 INFO L85 PathProgramCache]: Analyzing trace with hash 171514288, now seen corresponding path program 1 times [2022-12-13 16:30:31,841 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:31,841 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [79961211] [2022-12-13 16:30:31,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:31,841 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:31,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:31,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:31,894 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:31,894 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [79961211] [2022-12-13 16:30:31,894 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [79961211] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:31,894 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:31,894 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:31,894 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [122812568] [2022-12-13 16:30:31,894 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:31,895 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:30:31,895 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:30:31,895 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:30:31,895 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:30:31,895 INFO L87 Difference]: Start difference. First operand 2018 states and 2979 transitions. cyclomatic complexity: 962 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:31,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:30:31,917 INFO L93 Difference]: Finished difference Result 2018 states and 2978 transitions. [2022-12-13 16:30:31,917 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2978 transitions. [2022-12-13 16:30:31,921 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-12-13 16:30:31,928 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2978 transitions. [2022-12-13 16:30:31,928 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-12-13 16:30:31,929 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-12-13 16:30:31,929 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2978 transitions. [2022-12-13 16:30:31,931 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:30:31,931 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2978 transitions. [2022-12-13 16:30:31,933 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2978 transitions. [2022-12-13 16:30:31,947 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-12-13 16:30:31,950 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4757185332011893) internal successors, (2978), 2017 states have internal predecessors, (2978), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:31,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2978 transitions. [2022-12-13 16:30:31,954 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2978 transitions. [2022-12-13 16:30:31,954 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:30:31,955 INFO L428 stractBuchiCegarLoop]: Abstraction has 2018 states and 2978 transitions. [2022-12-13 16:30:31,955 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 16:30:31,955 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2978 transitions. [2022-12-13 16:30:31,959 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-12-13 16:30:31,959 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:30:31,959 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:30:31,960 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:31,961 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:31,961 INFO L748 eck$LassoCheckResult]: Stem: 40771#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 40772#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 41749#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41750#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42448#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 41348#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41349#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41417#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41418#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41851#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41852#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41383#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41192#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41193#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 41647#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41648#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 41526#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 41527#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 41166#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41167#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 42371#L1279-2 assume !(0 == ~T1_E~0); 40792#L1284-1 assume !(0 == ~T2_E~0); 40793#L1289-1 assume !(0 == ~T3_E~0); 41523#L1294-1 assume !(0 == ~T4_E~0); 41524#L1299-1 assume !(0 == ~T5_E~0); 41535#L1304-1 assume !(0 == ~T6_E~0); 42447#L1309-1 assume !(0 == ~T7_E~0); 42449#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40718#L1319-1 assume !(0 == ~T9_E~0); 40719#L1324-1 assume !(0 == ~T10_E~0); 40893#L1329-1 assume !(0 == ~T11_E~0); 40894#L1334-1 assume !(0 == ~T12_E~0); 42286#L1339-1 assume !(0 == ~T13_E~0); 42360#L1344-1 assume !(0 == ~E_M~0); 42361#L1349-1 assume !(0 == ~E_1~0); 41708#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 41709#L1359-1 assume !(0 == ~E_3~0); 42115#L1364-1 assume !(0 == ~E_4~0); 41018#L1369-1 assume !(0 == ~E_5~0); 41019#L1374-1 assume !(0 == ~E_6~0); 41715#L1379-1 assume !(0 == ~E_7~0); 41716#L1384-1 assume !(0 == ~E_8~0); 41793#L1389-1 assume !(0 == ~E_9~0); 42306#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 42307#L1399-1 assume !(0 == ~E_11~0); 42402#L1404-1 assume !(0 == ~E_12~0); 41114#L1409-1 assume !(0 == ~E_13~0); 41115#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42397#L628 assume !(1 == ~m_pc~0); 41017#L628-2 is_master_triggered_~__retres1~0#1 := 0; 41016#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41596#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41597#L1591 assume !(0 != activate_threads_~tmp~1#1); 42411#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41577#L647 assume 1 == ~t1_pc~0; 40943#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40944#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41628#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42077#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 42348#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42349#L666 assume 1 == ~t2_pc~0; 40789#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 40790#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40934#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40935#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 41903#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41904#L685 assume !(1 == ~t3_pc~0); 41998#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41997#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42067#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41757#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41758#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41235#L704 assume 1 == ~t4_pc~0; 41236#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41769#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40582#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40583#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 41626#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41627#L723 assume !(1 == ~t5_pc~0); 41753#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 41970#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42108#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41882#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 41883#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41000#L742 assume 1 == ~t6_pc~0; 41001#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41155#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40925#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40687#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 40688#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41076#L761 assume !(1 == ~t7_pc~0); 41077#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 40952#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40953#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41760#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 41761#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40710#L780 assume 1 == ~t8_pc~0; 40711#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40990#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40991#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41722#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 41723#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41839#L799 assume 1 == ~t9_pc~0; 41940#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40713#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40714#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40982#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 42041#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41864#L818 assume !(1 == ~t10_pc~0); 40494#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 40495#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41933#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41867#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41868#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41910#L837 assume 1 == ~t11_pc~0; 41911#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41747#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 42352#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 41832#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 41833#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41585#L856 assume !(1 == ~t12_pc~0); 41586#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 42211#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40512#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 40513#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 42189#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 42374#L875 assume 1 == ~t13_pc~0; 41533#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 41156#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 41157#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 41094#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 41095#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41932#L1427 assume !(1 == ~M_E~0); 41917#L1427-2 assume !(1 == ~T1_E~0); 41063#L1432-1 assume !(1 == ~T2_E~0); 41064#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42119#L1442-1 assume !(1 == ~T4_E~0); 42120#L1447-1 assume !(1 == ~T5_E~0); 41979#L1452-1 assume !(1 == ~T6_E~0); 40634#L1457-1 assume !(1 == ~T7_E~0); 40635#L1462-1 assume !(1 == ~T8_E~0); 42137#L1467-1 assume !(1 == ~T9_E~0); 42157#L1472-1 assume !(1 == ~T10_E~0); 42158#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41928#L1482-1 assume !(1 == ~T12_E~0); 41929#L1487-1 assume !(1 == ~T13_E~0); 40963#L1492-1 assume !(1 == ~E_M~0); 40964#L1497-1 assume !(1 == ~E_1~0); 41330#L1502-1 assume !(1 == ~E_2~0); 41331#L1507-1 assume !(1 == ~E_3~0); 40845#L1512-1 assume !(1 == ~E_4~0); 40846#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 42231#L1522-1 assume !(1 == ~E_6~0); 41574#L1527-1 assume !(1 == ~E_7~0); 41575#L1532-1 assume !(1 == ~E_8~0); 42433#L1537-1 assume !(1 == ~E_9~0); 41776#L1542-1 assume !(1 == ~E_10~0); 41603#L1547-1 assume !(1 == ~E_11~0); 41604#L1552-1 assume !(1 == ~E_12~0); 40535#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 40536#L1562-1 assume { :end_inline_reset_delta_events } true; 41146#L1928-2 [2022-12-13 16:30:31,961 INFO L750 eck$LassoCheckResult]: Loop: 41146#L1928-2 assume !false; 41640#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40801#L1254 assume !false; 41392#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 40870#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 40871#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 41065#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 42217#L1067 assume !(0 != eval_~tmp~0#1); 41513#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41123#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41124#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 41350#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41334#L1284-3 assume !(0 == ~T2_E~0); 41335#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41314#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41315#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 41704#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 41705#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41200#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41201#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 42179#L1324-3 assume !(0 == ~T10_E~0); 40843#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 40844#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 41609#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 41610#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 41907#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 41184#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 41185#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 41915#L1364-3 assume !(0 == ~E_4~0); 42432#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42322#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 40966#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40967#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41182#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 41183#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 41484#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 42332#L1404-3 assume !(0 == ~E_12~0); 42296#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 42297#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41805#L628-45 assume 1 == ~m_pc~0; 41479#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 41481#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41987#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41215#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 41216#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41939#L647-45 assume 1 == ~t1_pc~0; 40786#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40787#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41721#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40899#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40900#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41107#L666-45 assume !(1 == ~t2_pc~0); 41108#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 41595#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41985#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41986#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42051#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40650#L685-45 assume 1 == ~t3_pc~0; 40651#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 41717#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42363#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42229#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42230#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42372#L704-45 assume !(1 == ~t4_pc~0); 40514#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 40515#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41380#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 42251#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42460#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41834#L723-45 assume !(1 == ~t5_pc~0); 41835#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 42308#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42423#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41196#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 41197#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42199#L742-45 assume 1 == ~t6_pc~0; 42200#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41453#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41665#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41666#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 41944#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42030#L761-45 assume 1 == ~t7_pc~0; 42032#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41447#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41448#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40849#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 40850#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42300#L780-45 assume 1 == ~t8_pc~0; 41217#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40860#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40861#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42430#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40829#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40830#L799-45 assume !(1 == ~t9_pc~0); 41043#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 41044#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42096#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41980#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 41981#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40766#L818-45 assume !(1 == ~t10_pc~0); 40768#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 40887#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41957#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41378#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41379#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 42075#L837-45 assume 1 == ~t11_pc~0; 42358#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41308#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40841#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 40842#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 40908#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40909#L856-45 assume 1 == ~t12_pc~0; 42370#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 40911#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42126#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42127#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 41719#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 41720#L875-45 assume 1 == ~t13_pc~0; 41688#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 41689#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 41748#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 42088#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 42342#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42284#L1427-3 assume !(1 == ~M_E~0); 41518#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41519#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42038#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41706#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41707#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40552#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 40553#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42215#L1462-3 assume !(1 == ~T8_E~0); 42216#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42083#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 42084#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40810#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 40811#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 40951#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41121#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41122#L1502-3 assume !(1 == ~E_2~0); 42058#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42177#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41160#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40853#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 40854#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 40820#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 40821#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 41916#L1542-3 assume !(1 == ~E_10~0); 42044#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41691#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 41692#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 41021#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 41022#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 40444#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 40883#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 40884#L1947 assume !(0 == start_simulation_~tmp~3#1); 41823#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 42012#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 41080#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 40502#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 40503#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42145#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42146#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 42305#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 41146#L1928-2 [2022-12-13 16:30:31,961 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:31,961 INFO L85 PathProgramCache]: Analyzing trace with hash 584687431, now seen corresponding path program 1 times [2022-12-13 16:30:31,961 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:31,961 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1376167251] [2022-12-13 16:30:31,962 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:31,962 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:31,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:32,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:32,004 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:32,004 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1376167251] [2022-12-13 16:30:32,004 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1376167251] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:32,004 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:32,004 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:32,004 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1071262558] [2022-12-13 16:30:32,004 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:32,004 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:30:32,005 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:32,005 INFO L85 PathProgramCache]: Analyzing trace with hash 346128109, now seen corresponding path program 1 times [2022-12-13 16:30:32,005 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:32,005 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1036543477] [2022-12-13 16:30:32,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:32,005 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:32,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:32,043 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:32,043 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:32,043 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1036543477] [2022-12-13 16:30:32,043 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1036543477] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:32,043 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:32,043 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:32,043 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [192040103] [2022-12-13 16:30:32,043 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:32,044 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:30:32,044 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:30:32,044 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:30:32,044 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:30:32,045 INFO L87 Difference]: Start difference. First operand 2018 states and 2978 transitions. cyclomatic complexity: 961 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:32,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:30:32,063 INFO L93 Difference]: Finished difference Result 2018 states and 2977 transitions. [2022-12-13 16:30:32,063 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2977 transitions. [2022-12-13 16:30:32,068 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-12-13 16:30:32,072 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2977 transitions. [2022-12-13 16:30:32,072 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-12-13 16:30:32,073 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-12-13 16:30:32,073 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2977 transitions. [2022-12-13 16:30:32,075 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:30:32,075 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2977 transitions. [2022-12-13 16:30:32,077 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2977 transitions. [2022-12-13 16:30:32,091 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-12-13 16:30:32,093 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.475222993062438) internal successors, (2977), 2017 states have internal predecessors, (2977), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:32,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2977 transitions. [2022-12-13 16:30:32,095 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2977 transitions. [2022-12-13 16:30:32,095 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:30:32,096 INFO L428 stractBuchiCegarLoop]: Abstraction has 2018 states and 2977 transitions. [2022-12-13 16:30:32,096 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 16:30:32,096 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2977 transitions. [2022-12-13 16:30:32,099 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-12-13 16:30:32,099 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:30:32,099 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:30:32,100 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:32,100 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:32,101 INFO L748 eck$LassoCheckResult]: Stem: 44814#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 44815#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 45792#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45793#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46491#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 45391#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45392#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45460#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45461#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45894#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 45895#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 45426#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45235#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45236#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 45690#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 45691#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 45569#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 45570#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 45209#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45210#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 46414#L1279-2 assume !(0 == ~T1_E~0); 44835#L1284-1 assume !(0 == ~T2_E~0); 44836#L1289-1 assume !(0 == ~T3_E~0); 45566#L1294-1 assume !(0 == ~T4_E~0); 45567#L1299-1 assume !(0 == ~T5_E~0); 45578#L1304-1 assume !(0 == ~T6_E~0); 46490#L1309-1 assume !(0 == ~T7_E~0); 46492#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44761#L1319-1 assume !(0 == ~T9_E~0); 44762#L1324-1 assume !(0 == ~T10_E~0); 44936#L1329-1 assume !(0 == ~T11_E~0); 44937#L1334-1 assume !(0 == ~T12_E~0); 46329#L1339-1 assume !(0 == ~T13_E~0); 46403#L1344-1 assume !(0 == ~E_M~0); 46404#L1349-1 assume !(0 == ~E_1~0); 45751#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 45752#L1359-1 assume !(0 == ~E_3~0); 46158#L1364-1 assume !(0 == ~E_4~0); 45061#L1369-1 assume !(0 == ~E_5~0); 45062#L1374-1 assume !(0 == ~E_6~0); 45758#L1379-1 assume !(0 == ~E_7~0); 45759#L1384-1 assume !(0 == ~E_8~0); 45836#L1389-1 assume !(0 == ~E_9~0); 46349#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 46350#L1399-1 assume !(0 == ~E_11~0); 46445#L1404-1 assume !(0 == ~E_12~0); 45157#L1409-1 assume !(0 == ~E_13~0); 45158#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46440#L628 assume !(1 == ~m_pc~0); 45060#L628-2 is_master_triggered_~__retres1~0#1 := 0; 45059#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45639#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45640#L1591 assume !(0 != activate_threads_~tmp~1#1); 46454#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45620#L647 assume 1 == ~t1_pc~0; 44986#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 44987#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45671#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46120#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 46391#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46392#L666 assume 1 == ~t2_pc~0; 44832#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 44833#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44977#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44978#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 45946#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45947#L685 assume !(1 == ~t3_pc~0); 46041#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 46040#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46110#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45800#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45801#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45278#L704 assume 1 == ~t4_pc~0; 45279#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45812#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44625#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44626#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 45669#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45670#L723 assume !(1 == ~t5_pc~0); 45796#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 46013#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46151#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45925#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 45926#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45043#L742 assume 1 == ~t6_pc~0; 45044#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45198#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44968#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44730#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 44731#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45119#L761 assume !(1 == ~t7_pc~0); 45120#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 44995#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44996#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45803#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 45804#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 44753#L780 assume 1 == ~t8_pc~0; 44754#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 45033#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45034#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 45765#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 45766#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45882#L799 assume 1 == ~t9_pc~0; 45983#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44756#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44757#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45025#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 46084#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45907#L818 assume !(1 == ~t10_pc~0); 44537#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 44538#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45976#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45910#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 45911#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 45953#L837 assume 1 == ~t11_pc~0; 45954#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 45790#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46395#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 45875#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 45876#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45628#L856 assume !(1 == ~t12_pc~0); 45629#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 46254#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44555#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 44556#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 46232#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 46417#L875 assume 1 == ~t13_pc~0; 45576#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 45199#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 45200#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 45137#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 45138#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45975#L1427 assume !(1 == ~M_E~0); 45960#L1427-2 assume !(1 == ~T1_E~0); 45106#L1432-1 assume !(1 == ~T2_E~0); 45107#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46162#L1442-1 assume !(1 == ~T4_E~0); 46163#L1447-1 assume !(1 == ~T5_E~0); 46022#L1452-1 assume !(1 == ~T6_E~0); 44677#L1457-1 assume !(1 == ~T7_E~0); 44678#L1462-1 assume !(1 == ~T8_E~0); 46180#L1467-1 assume !(1 == ~T9_E~0); 46200#L1472-1 assume !(1 == ~T10_E~0); 46201#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45971#L1482-1 assume !(1 == ~T12_E~0); 45972#L1487-1 assume !(1 == ~T13_E~0); 45006#L1492-1 assume !(1 == ~E_M~0); 45007#L1497-1 assume !(1 == ~E_1~0); 45373#L1502-1 assume !(1 == ~E_2~0); 45374#L1507-1 assume !(1 == ~E_3~0); 44888#L1512-1 assume !(1 == ~E_4~0); 44889#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 46274#L1522-1 assume !(1 == ~E_6~0); 45617#L1527-1 assume !(1 == ~E_7~0); 45618#L1532-1 assume !(1 == ~E_8~0); 46476#L1537-1 assume !(1 == ~E_9~0); 45819#L1542-1 assume !(1 == ~E_10~0); 45646#L1547-1 assume !(1 == ~E_11~0); 45647#L1552-1 assume !(1 == ~E_12~0); 44578#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 44579#L1562-1 assume { :end_inline_reset_delta_events } true; 45189#L1928-2 [2022-12-13 16:30:32,101 INFO L750 eck$LassoCheckResult]: Loop: 45189#L1928-2 assume !false; 45683#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44844#L1254 assume !false; 45435#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 44913#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 44914#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 45108#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 46260#L1067 assume !(0 != eval_~tmp~0#1); 45556#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45166#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 45167#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 45393#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 45377#L1284-3 assume !(0 == ~T2_E~0); 45378#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45357#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45358#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 45747#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 45748#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 45243#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45244#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 46222#L1324-3 assume !(0 == ~T10_E~0); 44886#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 44887#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 45652#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 45653#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 45950#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45227#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 45228#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 45958#L1364-3 assume !(0 == ~E_4~0); 46475#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46365#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 45009#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 45010#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 45225#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 45226#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 45527#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 46375#L1404-3 assume !(0 == ~E_12~0); 46339#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 46340#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45848#L628-45 assume 1 == ~m_pc~0; 45522#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 45524#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46030#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45258#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 45259#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45982#L647-45 assume 1 == ~t1_pc~0; 44829#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 44830#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45764#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44942#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44943#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45150#L666-45 assume 1 == ~t2_pc~0; 45152#L667-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 45638#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46028#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46029#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46094#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44693#L685-45 assume 1 == ~t3_pc~0; 44694#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 45760#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46406#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46272#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46273#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46415#L704-45 assume 1 == ~t4_pc~0; 46293#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 44558#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45423#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46294#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 46503#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45877#L723-45 assume !(1 == ~t5_pc~0); 45878#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 46351#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46466#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45239#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 45240#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46242#L742-45 assume 1 == ~t6_pc~0; 46243#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45496#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45708#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45709#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 45987#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46073#L761-45 assume !(1 == ~t7_pc~0); 46074#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 45490#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45491#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44892#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 44893#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46343#L780-45 assume 1 == ~t8_pc~0; 45260#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 44903#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44904#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46473#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 44872#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44873#L799-45 assume 1 == ~t9_pc~0; 45650#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 45087#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46139#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46023#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 46024#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 44809#L818-45 assume 1 == ~t10_pc~0; 44810#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 44930#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 46000#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45421#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 45422#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46118#L837-45 assume 1 == ~t11_pc~0; 46401#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 45351#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44884#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 44885#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 44951#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44952#L856-45 assume !(1 == ~t12_pc~0); 44953#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 44954#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46169#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46170#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 45762#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45763#L875-45 assume 1 == ~t13_pc~0; 45731#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 45732#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 45791#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 46131#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46385#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46327#L1427-3 assume !(1 == ~M_E~0); 45561#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45562#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46081#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45749#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45750#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44595#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44596#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46258#L1462-3 assume !(1 == ~T8_E~0); 46259#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46126#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 46127#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 44853#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 44854#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 44994#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45164#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 45165#L1502-3 assume !(1 == ~E_2~0); 46101#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46220#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 45203#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 44896#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 44897#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 44863#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 44864#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 45959#L1542-3 assume !(1 == ~E_10~0); 46087#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 45734#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 45735#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 45064#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 45065#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 44487#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 44926#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 44927#L1947 assume !(0 == start_simulation_~tmp~3#1); 45866#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 46055#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 45123#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 44545#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 44546#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46188#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46189#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 46348#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 45189#L1928-2 [2022-12-13 16:30:32,101 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:32,101 INFO L85 PathProgramCache]: Analyzing trace with hash 1907866377, now seen corresponding path program 1 times [2022-12-13 16:30:32,101 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:32,101 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [308433149] [2022-12-13 16:30:32,101 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:32,101 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:32,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:32,143 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:32,144 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:32,144 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [308433149] [2022-12-13 16:30:32,144 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [308433149] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:32,144 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:32,144 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:32,144 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [564219615] [2022-12-13 16:30:32,144 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:32,145 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:30:32,145 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:32,145 INFO L85 PathProgramCache]: Analyzing trace with hash 263246571, now seen corresponding path program 1 times [2022-12-13 16:30:32,145 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:32,145 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1612190123] [2022-12-13 16:30:32,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:32,146 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:32,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:32,187 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:32,187 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:32,187 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1612190123] [2022-12-13 16:30:32,187 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1612190123] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:32,187 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:32,188 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:32,188 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [256150052] [2022-12-13 16:30:32,188 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:32,188 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:30:32,188 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:30:32,188 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:30:32,188 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:30:32,188 INFO L87 Difference]: Start difference. First operand 2018 states and 2977 transitions. cyclomatic complexity: 960 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:32,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:30:32,208 INFO L93 Difference]: Finished difference Result 2018 states and 2976 transitions. [2022-12-13 16:30:32,208 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2976 transitions. [2022-12-13 16:30:32,212 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-12-13 16:30:32,216 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2976 transitions. [2022-12-13 16:30:32,216 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-12-13 16:30:32,217 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-12-13 16:30:32,217 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2976 transitions. [2022-12-13 16:30:32,218 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:30:32,219 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2976 transitions. [2022-12-13 16:30:32,220 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2976 transitions. [2022-12-13 16:30:32,233 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-12-13 16:30:32,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.474727452923687) internal successors, (2976), 2017 states have internal predecessors, (2976), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:32,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2976 transitions. [2022-12-13 16:30:32,237 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2976 transitions. [2022-12-13 16:30:32,238 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:30:32,238 INFO L428 stractBuchiCegarLoop]: Abstraction has 2018 states and 2976 transitions. [2022-12-13 16:30:32,238 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-12-13 16:30:32,238 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2976 transitions. [2022-12-13 16:30:32,242 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-12-13 16:30:32,242 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:30:32,242 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:30:32,243 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:32,243 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:32,243 INFO L748 eck$LassoCheckResult]: Stem: 48857#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 48858#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 49835#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 49836#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50534#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 49434#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49435#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49503#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49504#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49937#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49938#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49469#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49278#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49279#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49733#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49734#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 49612#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 49613#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 49252#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49253#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 50457#L1279-2 assume !(0 == ~T1_E~0); 48878#L1284-1 assume !(0 == ~T2_E~0); 48879#L1289-1 assume !(0 == ~T3_E~0); 49609#L1294-1 assume !(0 == ~T4_E~0); 49610#L1299-1 assume !(0 == ~T5_E~0); 49621#L1304-1 assume !(0 == ~T6_E~0); 50533#L1309-1 assume !(0 == ~T7_E~0); 50535#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 48804#L1319-1 assume !(0 == ~T9_E~0); 48805#L1324-1 assume !(0 == ~T10_E~0); 48979#L1329-1 assume !(0 == ~T11_E~0); 48980#L1334-1 assume !(0 == ~T12_E~0); 50372#L1339-1 assume !(0 == ~T13_E~0); 50446#L1344-1 assume !(0 == ~E_M~0); 50447#L1349-1 assume !(0 == ~E_1~0); 49794#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 49795#L1359-1 assume !(0 == ~E_3~0); 50201#L1364-1 assume !(0 == ~E_4~0); 49104#L1369-1 assume !(0 == ~E_5~0); 49105#L1374-1 assume !(0 == ~E_6~0); 49801#L1379-1 assume !(0 == ~E_7~0); 49802#L1384-1 assume !(0 == ~E_8~0); 49879#L1389-1 assume !(0 == ~E_9~0); 50392#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 50393#L1399-1 assume !(0 == ~E_11~0); 50488#L1404-1 assume !(0 == ~E_12~0); 49200#L1409-1 assume !(0 == ~E_13~0); 49201#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50483#L628 assume !(1 == ~m_pc~0); 49103#L628-2 is_master_triggered_~__retres1~0#1 := 0; 49102#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49682#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49683#L1591 assume !(0 != activate_threads_~tmp~1#1); 50497#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49663#L647 assume 1 == ~t1_pc~0; 49029#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49030#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49714#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50163#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 50434#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50435#L666 assume 1 == ~t2_pc~0; 48875#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 48876#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49020#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49021#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 49989#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49990#L685 assume !(1 == ~t3_pc~0); 50084#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 50083#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50153#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49843#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49844#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49321#L704 assume 1 == ~t4_pc~0; 49322#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49855#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48668#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48669#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 49712#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49713#L723 assume !(1 == ~t5_pc~0); 49839#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 50056#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50194#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49968#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 49969#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49086#L742 assume 1 == ~t6_pc~0; 49087#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49241#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49011#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48773#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 48774#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49162#L761 assume !(1 == ~t7_pc~0); 49163#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 49038#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49039#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49846#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 49847#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 48796#L780 assume 1 == ~t8_pc~0; 48797#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49076#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49077#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49808#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 49809#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49925#L799 assume 1 == ~t9_pc~0; 50026#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 48799#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48800#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49068#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 50127#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49950#L818 assume !(1 == ~t10_pc~0); 48580#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 48581#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50019#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49953#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49954#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49996#L837 assume 1 == ~t11_pc~0; 49997#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49833#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50438#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 49918#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 49919#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 49671#L856 assume !(1 == ~t12_pc~0); 49672#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 50297#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 48598#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 48599#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 50275#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 50460#L875 assume 1 == ~t13_pc~0; 49619#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 49242#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 49243#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 49180#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 49181#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50018#L1427 assume !(1 == ~M_E~0); 50003#L1427-2 assume !(1 == ~T1_E~0); 49149#L1432-1 assume !(1 == ~T2_E~0); 49150#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50205#L1442-1 assume !(1 == ~T4_E~0); 50206#L1447-1 assume !(1 == ~T5_E~0); 50065#L1452-1 assume !(1 == ~T6_E~0); 48720#L1457-1 assume !(1 == ~T7_E~0); 48721#L1462-1 assume !(1 == ~T8_E~0); 50223#L1467-1 assume !(1 == ~T9_E~0); 50243#L1472-1 assume !(1 == ~T10_E~0); 50244#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50014#L1482-1 assume !(1 == ~T12_E~0); 50015#L1487-1 assume !(1 == ~T13_E~0); 49049#L1492-1 assume !(1 == ~E_M~0); 49050#L1497-1 assume !(1 == ~E_1~0); 49416#L1502-1 assume !(1 == ~E_2~0); 49417#L1507-1 assume !(1 == ~E_3~0); 48931#L1512-1 assume !(1 == ~E_4~0); 48932#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 50317#L1522-1 assume !(1 == ~E_6~0); 49660#L1527-1 assume !(1 == ~E_7~0); 49661#L1532-1 assume !(1 == ~E_8~0); 50519#L1537-1 assume !(1 == ~E_9~0); 49862#L1542-1 assume !(1 == ~E_10~0); 49689#L1547-1 assume !(1 == ~E_11~0); 49690#L1552-1 assume !(1 == ~E_12~0); 48621#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 48622#L1562-1 assume { :end_inline_reset_delta_events } true; 49232#L1928-2 [2022-12-13 16:30:32,244 INFO L750 eck$LassoCheckResult]: Loop: 49232#L1928-2 assume !false; 49726#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48887#L1254 assume !false; 49478#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 48956#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 48957#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 49151#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 50303#L1067 assume !(0 != eval_~tmp~0#1); 49599#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49209#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49210#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 49436#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 49420#L1284-3 assume !(0 == ~T2_E~0); 49421#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 49400#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49401#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 49790#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 49791#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49286#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49287#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 50265#L1324-3 assume !(0 == ~T10_E~0); 48929#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 48930#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 49695#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 49696#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 49993#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 49270#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 49271#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50001#L1364-3 assume !(0 == ~E_4~0); 50518#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50408#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 49052#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 49053#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 49268#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 49269#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 49570#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 50418#L1404-3 assume !(0 == ~E_12~0); 50382#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 50383#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49891#L628-45 assume 1 == ~m_pc~0; 49565#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 49567#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50073#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49301#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 49302#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50025#L647-45 assume 1 == ~t1_pc~0; 48872#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 48873#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49807#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48985#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 48986#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49193#L666-45 assume !(1 == ~t2_pc~0); 49194#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 49681#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50071#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50072#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50137#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48736#L685-45 assume 1 == ~t3_pc~0; 48737#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49803#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50449#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50315#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50316#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50458#L704-45 assume 1 == ~t4_pc~0; 50336#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 48601#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49466#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50337#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50546#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49920#L723-45 assume !(1 == ~t5_pc~0); 49921#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 50394#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50509#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49282#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 49283#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50285#L742-45 assume !(1 == ~t6_pc~0); 49538#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 49539#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49751#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49752#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50030#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50116#L761-45 assume !(1 == ~t7_pc~0); 50117#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 49533#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49534#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 48935#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 48936#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50386#L780-45 assume 1 == ~t8_pc~0; 49303#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 48946#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48947#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50516#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 48915#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48916#L799-45 assume !(1 == ~t9_pc~0); 49129#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 49130#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50182#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50066#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 50067#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48852#L818-45 assume 1 == ~t10_pc~0; 48853#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 48973#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50043#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49464#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49465#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 50161#L837-45 assume !(1 == ~t11_pc~0); 49393#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 49394#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48927#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 48928#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 48994#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 48995#L856-45 assume !(1 == ~t12_pc~0); 48996#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 48997#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50212#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50213#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 49805#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 49806#L875-45 assume !(1 == ~t13_pc~0); 49776#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 49775#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 49834#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 50174#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50428#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50370#L1427-3 assume !(1 == ~M_E~0); 49604#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49605#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50124#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49792#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49793#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 48638#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 48639#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50301#L1462-3 assume !(1 == ~T8_E~0); 50302#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50169#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50170#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 48896#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 48897#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 49037#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 49207#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 49208#L1502-3 assume !(1 == ~E_2~0); 50144#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50263#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49246#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 48939#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 48940#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 48906#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 48907#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 50002#L1542-3 assume !(1 == ~E_10~0); 50130#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 49777#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 49778#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 49107#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 49108#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 48530#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 48969#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 48970#L1947 assume !(0 == start_simulation_~tmp~3#1); 49909#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 50098#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 49166#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 48588#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 48589#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50231#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50232#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 50391#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 49232#L1928-2 [2022-12-13 16:30:32,244 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:32,244 INFO L85 PathProgramCache]: Analyzing trace with hash 10886919, now seen corresponding path program 1 times [2022-12-13 16:30:32,244 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:32,244 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2037676217] [2022-12-13 16:30:32,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:32,244 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:32,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:32,272 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:32,273 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:32,273 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2037676217] [2022-12-13 16:30:32,273 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2037676217] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:32,273 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:32,273 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:32,273 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [861151714] [2022-12-13 16:30:32,273 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:32,274 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:30:32,274 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:32,274 INFO L85 PathProgramCache]: Analyzing trace with hash -691936144, now seen corresponding path program 1 times [2022-12-13 16:30:32,274 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:32,274 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1546775649] [2022-12-13 16:30:32,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:32,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:32,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:32,314 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:32,314 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:32,314 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1546775649] [2022-12-13 16:30:32,314 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1546775649] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:32,314 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:32,314 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:32,314 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [45369977] [2022-12-13 16:30:32,314 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:32,315 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:30:32,315 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:30:32,315 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:30:32,315 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:30:32,316 INFO L87 Difference]: Start difference. First operand 2018 states and 2976 transitions. cyclomatic complexity: 959 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:32,333 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:30:32,333 INFO L93 Difference]: Finished difference Result 2018 states and 2975 transitions. [2022-12-13 16:30:32,333 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2018 states and 2975 transitions. [2022-12-13 16:30:32,338 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-12-13 16:30:32,343 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2018 states to 2018 states and 2975 transitions. [2022-12-13 16:30:32,344 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2018 [2022-12-13 16:30:32,345 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2018 [2022-12-13 16:30:32,345 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2018 states and 2975 transitions. [2022-12-13 16:30:32,346 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:30:32,346 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2975 transitions. [2022-12-13 16:30:32,348 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2018 states and 2975 transitions. [2022-12-13 16:30:32,376 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2018 to 2018. [2022-12-13 16:30:32,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2018 states, 2018 states have (on average 1.4742319127849355) internal successors, (2975), 2017 states have internal predecessors, (2975), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:32,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2018 states to 2018 states and 2975 transitions. [2022-12-13 16:30:32,381 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2018 states and 2975 transitions. [2022-12-13 16:30:32,381 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:30:32,382 INFO L428 stractBuchiCegarLoop]: Abstraction has 2018 states and 2975 transitions. [2022-12-13 16:30:32,382 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-12-13 16:30:32,382 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2018 states and 2975 transitions. [2022-12-13 16:30:32,387 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1843 [2022-12-13 16:30:32,388 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:30:32,388 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:30:32,389 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:32,389 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:32,389 INFO L748 eck$LassoCheckResult]: Stem: 52900#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 52901#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 53878#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53879#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54577#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 53477#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53478#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53546#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53547#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53980#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53981#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 53512#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 53321#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 53322#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 53776#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 53777#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 53655#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 53656#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 53295#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53296#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 54500#L1279-2 assume !(0 == ~T1_E~0); 52921#L1284-1 assume !(0 == ~T2_E~0); 52922#L1289-1 assume !(0 == ~T3_E~0); 53652#L1294-1 assume !(0 == ~T4_E~0); 53653#L1299-1 assume !(0 == ~T5_E~0); 53664#L1304-1 assume !(0 == ~T6_E~0); 54576#L1309-1 assume !(0 == ~T7_E~0); 54578#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 52847#L1319-1 assume !(0 == ~T9_E~0); 52848#L1324-1 assume !(0 == ~T10_E~0); 53022#L1329-1 assume !(0 == ~T11_E~0); 53023#L1334-1 assume !(0 == ~T12_E~0); 54415#L1339-1 assume !(0 == ~T13_E~0); 54489#L1344-1 assume !(0 == ~E_M~0); 54490#L1349-1 assume !(0 == ~E_1~0); 53837#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 53838#L1359-1 assume !(0 == ~E_3~0); 54244#L1364-1 assume !(0 == ~E_4~0); 53147#L1369-1 assume !(0 == ~E_5~0); 53148#L1374-1 assume !(0 == ~E_6~0); 53844#L1379-1 assume !(0 == ~E_7~0); 53845#L1384-1 assume !(0 == ~E_8~0); 53922#L1389-1 assume !(0 == ~E_9~0); 54435#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 54436#L1399-1 assume !(0 == ~E_11~0); 54531#L1404-1 assume !(0 == ~E_12~0); 53243#L1409-1 assume !(0 == ~E_13~0); 53244#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54526#L628 assume !(1 == ~m_pc~0); 53146#L628-2 is_master_triggered_~__retres1~0#1 := 0; 53145#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53725#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53726#L1591 assume !(0 != activate_threads_~tmp~1#1); 54540#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53706#L647 assume 1 == ~t1_pc~0; 53072#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53073#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53757#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 54206#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 54477#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54478#L666 assume 1 == ~t2_pc~0; 52918#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 52919#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53063#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53064#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 54032#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54033#L685 assume !(1 == ~t3_pc~0); 54127#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 54126#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54196#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53886#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53887#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53364#L704 assume 1 == ~t4_pc~0; 53365#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53898#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52711#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 52712#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 53755#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53756#L723 assume !(1 == ~t5_pc~0); 53882#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 54099#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54237#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54011#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 54012#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53129#L742 assume 1 == ~t6_pc~0; 53130#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53284#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53054#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 52816#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 52817#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53205#L761 assume !(1 == ~t7_pc~0); 53206#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 53081#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53082#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53889#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 53890#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52839#L780 assume 1 == ~t8_pc~0; 52840#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 53119#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53120#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 53851#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 53852#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53968#L799 assume 1 == ~t9_pc~0; 54069#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52842#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 52843#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 53111#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 54170#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53993#L818 assume !(1 == ~t10_pc~0); 52623#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 52624#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54062#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53996#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53997#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54039#L837 assume 1 == ~t11_pc~0; 54040#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 53876#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 54481#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 53961#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 53962#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53714#L856 assume !(1 == ~t12_pc~0); 53715#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 54340#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 52641#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 52642#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 54318#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 54503#L875 assume 1 == ~t13_pc~0; 53662#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 53285#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 53286#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 53223#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 53224#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54061#L1427 assume !(1 == ~M_E~0); 54046#L1427-2 assume !(1 == ~T1_E~0); 53192#L1432-1 assume !(1 == ~T2_E~0); 53193#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54248#L1442-1 assume !(1 == ~T4_E~0); 54249#L1447-1 assume !(1 == ~T5_E~0); 54108#L1452-1 assume !(1 == ~T6_E~0); 52763#L1457-1 assume !(1 == ~T7_E~0); 52764#L1462-1 assume !(1 == ~T8_E~0); 54266#L1467-1 assume !(1 == ~T9_E~0); 54286#L1472-1 assume !(1 == ~T10_E~0); 54287#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 54057#L1482-1 assume !(1 == ~T12_E~0); 54058#L1487-1 assume !(1 == ~T13_E~0); 53092#L1492-1 assume !(1 == ~E_M~0); 53093#L1497-1 assume !(1 == ~E_1~0); 53459#L1502-1 assume !(1 == ~E_2~0); 53460#L1507-1 assume !(1 == ~E_3~0); 52974#L1512-1 assume !(1 == ~E_4~0); 52975#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 54360#L1522-1 assume !(1 == ~E_6~0); 53703#L1527-1 assume !(1 == ~E_7~0); 53704#L1532-1 assume !(1 == ~E_8~0); 54562#L1537-1 assume !(1 == ~E_9~0); 53905#L1542-1 assume !(1 == ~E_10~0); 53732#L1547-1 assume !(1 == ~E_11~0); 53733#L1552-1 assume !(1 == ~E_12~0); 52664#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 52665#L1562-1 assume { :end_inline_reset_delta_events } true; 53275#L1928-2 [2022-12-13 16:30:32,390 INFO L750 eck$LassoCheckResult]: Loop: 53275#L1928-2 assume !false; 53769#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 52930#L1254 assume !false; 53521#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 52999#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 53000#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53194#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 54346#L1067 assume !(0 != eval_~tmp~0#1); 53642#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 53252#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 53253#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 53479#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 53463#L1284-3 assume !(0 == ~T2_E~0); 53464#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 53443#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 53444#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53833#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 53834#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53329#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53330#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 54308#L1324-3 assume !(0 == ~T10_E~0); 52972#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 52973#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 53738#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 53739#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 54036#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 53313#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 53314#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54044#L1364-3 assume !(0 == ~E_4~0); 54561#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54451#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 53095#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 53096#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 53311#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 53312#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 53613#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 54461#L1404-3 assume !(0 == ~E_12~0); 54425#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 54426#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53934#L628-45 assume 1 == ~m_pc~0; 53608#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 53610#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54116#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53344#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 53345#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54068#L647-45 assume 1 == ~t1_pc~0; 52915#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 52916#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53850#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53028#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 53029#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53236#L666-45 assume !(1 == ~t2_pc~0); 53237#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 53724#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54114#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54115#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54180#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52779#L685-45 assume 1 == ~t3_pc~0; 52780#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 53846#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54492#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54358#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54359#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54501#L704-45 assume !(1 == ~t4_pc~0); 52643#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 52644#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53509#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54380#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54589#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53963#L723-45 assume !(1 == ~t5_pc~0); 53964#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 54437#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54552#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53325#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 53326#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54328#L742-45 assume 1 == ~t6_pc~0; 54329#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53582#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53794#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53795#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54073#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54159#L761-45 assume !(1 == ~t7_pc~0); 54160#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 53576#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53577#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 52978#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 52979#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54429#L780-45 assume 1 == ~t8_pc~0; 53346#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 52989#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 52990#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54559#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 52958#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 52959#L799-45 assume !(1 == ~t9_pc~0); 53172#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 53173#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54225#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54109#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 54110#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 52895#L818-45 assume 1 == ~t10_pc~0; 52896#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 53016#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54086#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53507#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53508#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54204#L837-45 assume 1 == ~t11_pc~0; 54487#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 53437#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 52970#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 52971#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 53037#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53038#L856-45 assume 1 == ~t12_pc~0; 54499#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 53040#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 54255#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 54256#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 53848#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 53849#L875-45 assume 1 == ~t13_pc~0; 53817#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 53818#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 53877#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 54217#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 54471#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54413#L1427-3 assume !(1 == ~M_E~0); 53647#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 53648#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54167#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53835#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53836#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 52681#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 52682#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54344#L1462-3 assume !(1 == ~T8_E~0); 54345#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 54212#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 54213#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 52939#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 52940#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 53080#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 53250#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 53251#L1502-3 assume !(1 == ~E_2~0); 54187#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54306#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53289#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 52982#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 52983#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 52949#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 52950#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 54045#L1542-3 assume !(1 == ~E_10~0); 54173#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 53820#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 53821#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 53150#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 53151#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 52573#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53012#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 53013#L1947 assume !(0 == start_simulation_~tmp~3#1); 53952#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 54141#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 53209#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 52631#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 52632#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54274#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54275#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 54434#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 53275#L1928-2 [2022-12-13 16:30:32,390 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:32,390 INFO L85 PathProgramCache]: Analyzing trace with hash -327400631, now seen corresponding path program 1 times [2022-12-13 16:30:32,390 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:32,390 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [107300587] [2022-12-13 16:30:32,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:32,391 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:32,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:32,453 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:32,454 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:32,454 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [107300587] [2022-12-13 16:30:32,454 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [107300587] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:32,454 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:32,454 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 16:30:32,454 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [829921931] [2022-12-13 16:30:32,454 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:32,454 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:30:32,455 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:32,455 INFO L85 PathProgramCache]: Analyzing trace with hash -1431662419, now seen corresponding path program 2 times [2022-12-13 16:30:32,455 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:32,455 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1194047629] [2022-12-13 16:30:32,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:32,456 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:32,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:32,506 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:32,506 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:32,506 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1194047629] [2022-12-13 16:30:32,506 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1194047629] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:32,506 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:32,506 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:32,506 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [707038997] [2022-12-13 16:30:32,507 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:32,507 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:30:32,507 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:30:32,507 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:30:32,508 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:30:32,508 INFO L87 Difference]: Start difference. First operand 2018 states and 2975 transitions. cyclomatic complexity: 958 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:32,592 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:30:32,592 INFO L93 Difference]: Finished difference Result 3761 states and 5528 transitions. [2022-12-13 16:30:32,592 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3761 states and 5528 transitions. [2022-12-13 16:30:32,607 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3586 [2022-12-13 16:30:32,618 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3761 states to 3761 states and 5528 transitions. [2022-12-13 16:30:32,618 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3761 [2022-12-13 16:30:32,621 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3761 [2022-12-13 16:30:32,621 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3761 states and 5528 transitions. [2022-12-13 16:30:32,626 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:30:32,626 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3761 states and 5528 transitions. [2022-12-13 16:30:32,632 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3761 states and 5528 transitions. [2022-12-13 16:30:32,668 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3761 to 3761. [2022-12-13 16:30:32,671 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3761 states, 3761 states have (on average 1.4698218558893912) internal successors, (5528), 3760 states have internal predecessors, (5528), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:32,675 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3761 states to 3761 states and 5528 transitions. [2022-12-13 16:30:32,675 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3761 states and 5528 transitions. [2022-12-13 16:30:32,676 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:30:32,676 INFO L428 stractBuchiCegarLoop]: Abstraction has 3761 states and 5528 transitions. [2022-12-13 16:30:32,676 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-12-13 16:30:32,676 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3761 states and 5528 transitions. [2022-12-13 16:30:32,684 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3586 [2022-12-13 16:30:32,684 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:30:32,684 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:30:32,685 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:32,685 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:32,685 INFO L748 eck$LassoCheckResult]: Stem: 58686#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 58687#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 59680#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 59681#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60513#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 59270#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59271#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59339#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 59340#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 59788#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 59789#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 59307#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 59111#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 59112#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 59572#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 59573#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 59454#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 59455#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 59085#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 59086#L1279 assume !(0 == ~M_E~0); 60378#L1279-2 assume !(0 == ~T1_E~0); 58707#L1284-1 assume !(0 == ~T2_E~0); 58708#L1289-1 assume !(0 == ~T3_E~0); 59446#L1294-1 assume !(0 == ~T4_E~0); 59447#L1299-1 assume !(0 == ~T5_E~0); 59458#L1304-1 assume !(0 == ~T6_E~0); 60512#L1309-1 assume !(0 == ~T7_E~0); 60514#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 58633#L1319-1 assume !(0 == ~T9_E~0); 58634#L1324-1 assume !(0 == ~T10_E~0); 58809#L1329-1 assume !(0 == ~T11_E~0); 58810#L1334-1 assume !(0 == ~T12_E~0); 60268#L1339-1 assume !(0 == ~T13_E~0); 60362#L1344-1 assume !(0 == ~E_M~0); 60363#L1349-1 assume !(0 == ~E_1~0); 59635#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 59636#L1359-1 assume !(0 == ~E_3~0); 60057#L1364-1 assume !(0 == ~E_4~0); 58934#L1369-1 assume !(0 == ~E_5~0); 58935#L1374-1 assume !(0 == ~E_6~0); 59645#L1379-1 assume !(0 == ~E_7~0); 59646#L1384-1 assume !(0 == ~E_8~0); 59726#L1389-1 assume !(0 == ~E_9~0); 60290#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 60291#L1399-1 assume !(0 == ~E_11~0); 60421#L1404-1 assume !(0 == ~E_12~0); 59031#L1409-1 assume !(0 == ~E_13~0); 59032#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60412#L628 assume !(1 == ~m_pc~0); 58933#L628-2 is_master_triggered_~__retres1~0#1 := 0; 58932#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59519#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59520#L1591 assume !(0 != activate_threads_~tmp~1#1); 60433#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59500#L647 assume 1 == ~t1_pc~0; 58859#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 58860#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59552#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 60017#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 60344#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60345#L666 assume 1 == ~t2_pc~0; 58704#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 58705#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58852#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58853#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 59838#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59839#L685 assume !(1 == ~t3_pc~0); 59934#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 59933#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60005#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 59689#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59690#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59155#L704 assume 1 == ~t4_pc~0; 59156#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 59702#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58497#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 58498#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 59550#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59551#L723 assume !(1 == ~t5_pc~0); 59686#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 59905#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60050#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59820#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 59821#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58917#L742 assume 1 == ~t6_pc~0; 58918#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 59074#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58841#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 58604#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 58605#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58993#L761 assume !(1 == ~t7_pc~0); 58994#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 58870#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 58871#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59692#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 59693#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 58625#L780 assume 1 == ~t8_pc~0; 58626#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 58906#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 58907#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 59652#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 59653#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59774#L799 assume 1 == ~t9_pc~0; 59878#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58628#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58629#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 58898#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 59977#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 59799#L818 assume !(1 == ~t10_pc~0); 58409#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 58410#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 59868#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 59802#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 59803#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 59845#L837 assume 1 == ~t11_pc~0; 59846#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 59679#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 60349#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 59767#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 59768#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 59508#L856 assume !(1 == ~t12_pc~0); 59509#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 60172#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58427#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 58428#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 60148#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 60382#L875 assume 1 == ~t13_pc~0; 59456#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 59075#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 59076#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 59011#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 59012#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59867#L1427 assume !(1 == ~M_E~0); 59854#L1427-2 assume !(1 == ~T1_E~0); 58979#L1432-1 assume !(1 == ~T2_E~0); 58980#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 60062#L1442-1 assume !(1 == ~T4_E~0); 60063#L1447-1 assume !(1 == ~T5_E~0); 59916#L1452-1 assume !(1 == ~T6_E~0); 58549#L1457-1 assume !(1 == ~T7_E~0); 58550#L1462-1 assume !(1 == ~T8_E~0); 60085#L1467-1 assume !(1 == ~T9_E~0); 60110#L1472-1 assume !(1 == ~T10_E~0); 60111#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59863#L1482-1 assume !(1 == ~T12_E~0); 59864#L1487-1 assume !(1 == ~T13_E~0); 58879#L1492-1 assume !(1 == ~E_M~0); 58880#L1497-1 assume !(1 == ~E_1~0); 59252#L1502-1 assume !(1 == ~E_2~0); 59253#L1507-1 assume !(1 == ~E_3~0); 58761#L1512-1 assume !(1 == ~E_4~0); 58762#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 60199#L1522-1 assume !(1 == ~E_6~0); 59497#L1527-1 assume !(1 == ~E_7~0); 59498#L1532-1 assume !(1 == ~E_8~0); 60492#L1537-1 assume !(1 == ~E_9~0); 59709#L1542-1 assume !(1 == ~E_10~0); 59528#L1547-1 assume !(1 == ~E_11~0); 59529#L1552-1 assume !(1 == ~E_12~0); 58450#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 58451#L1562-1 assume { :end_inline_reset_delta_events } true; 59065#L1928-2 [2022-12-13 16:30:32,685 INFO L750 eck$LassoCheckResult]: Loop: 59065#L1928-2 assume !false; 59682#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 60657#L1254 assume !false; 60656#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 60649#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 58981#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 58982#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 60180#L1067 assume !(0 != eval_~tmp~0#1); 60181#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 60640#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 60411#L1279-3 assume !(0 == ~M_E~0); 59274#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 59256#L1284-3 assume !(0 == ~T2_E~0); 59257#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 60637#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 60636#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 60635#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 60634#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 60633#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 60632#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 60135#L1324-3 assume !(0 == ~T10_E~0); 58759#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 58760#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 59537#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 59538#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 59842#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 59103#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 59104#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 59850#L1364-3 assume !(0 == ~E_4~0); 60511#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 60307#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 58882#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 58883#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 60622#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 60621#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 60620#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 60321#L1404-3 assume !(0 == ~E_12~0); 60322#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 60377#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59738#L628-45 assume !(1 == ~m_pc~0); 59739#L628-47 is_master_triggered_~__retres1~0#1 := 0; 60480#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59922#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59923#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 60439#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59874#L647-45 assume 1 == ~t1_pc~0; 58701#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 58702#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59651#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 58815#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 58816#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60611#L666-45 assume !(1 == ~t2_pc~0); 60609#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 60453#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59920#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59921#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 59987#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58561#L685-45 assume 1 == ~t3_pc~0; 58562#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 60366#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60367#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60539#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 60379#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60380#L704-45 assume !(1 == ~t4_pc~0); 60602#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 60601#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 60226#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 60227#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 60540#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60541#L723-45 assume 1 == ~t5_pc~0; 60597#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 60458#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60459#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59115#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 59116#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 60525#L742-45 assume 1 == ~t6_pc~0; 60592#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 60591#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 60590#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 60589#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 60198#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 59966#L761-45 assume 1 == ~t7_pc~0; 59968#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 59369#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 59370#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 58765#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 58766#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 60537#L780-45 assume 1 == ~t8_pc~0; 60580#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 60579#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 60477#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 60478#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 58745#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 58746#L799-45 assume 1 == ~t9_pc~0; 59531#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58959#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 60036#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 59914#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 59915#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 58679#L818-45 assume 1 == ~t10_pc~0; 58680#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 58803#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 59892#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 60565#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 60564#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 60358#L837-45 assume 1 == ~t11_pc~0; 60359#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 59228#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 58755#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 58756#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 58824#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 58825#L856-45 assume 1 == ~t12_pc~0; 60548#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 60194#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 60071#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 60072#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 59648#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 59649#L875-45 assume !(1 == ~t13_pc~0); 60552#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 59676#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 59677#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 60027#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 60550#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60264#L1427-3 assume !(1 == ~M_E~0); 60265#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 62055#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 62054#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 62053#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 62052#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 62051#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 62050#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 62049#L1462-3 assume !(1 == ~T8_E~0); 62048#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 62047#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 62046#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 62045#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 62044#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 62043#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 62042#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 62041#L1502-3 assume !(1 == ~E_2~0); 61752#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 61751#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 61750#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 61749#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 60446#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 60447#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 60919#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 60918#L1542-3 assume !(1 == ~E_10~0); 60917#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 60913#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 60286#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 58937#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 58938#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 58359#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 58799#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 58800#L1947 assume !(0 == start_simulation_~tmp~3#1); 59758#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 59948#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 58997#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 58417#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 58418#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 60096#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 60097#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 60289#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 59065#L1928-2 [2022-12-13 16:30:32,685 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:32,686 INFO L85 PathProgramCache]: Analyzing trace with hash -867830137, now seen corresponding path program 1 times [2022-12-13 16:30:32,686 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:32,686 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [718681614] [2022-12-13 16:30:32,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:32,686 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:32,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:32,738 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:32,738 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:32,738 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [718681614] [2022-12-13 16:30:32,738 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [718681614] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:32,738 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:32,738 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:32,739 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1258408462] [2022-12-13 16:30:32,739 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:32,739 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:30:32,739 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:32,739 INFO L85 PathProgramCache]: Analyzing trace with hash 2061680938, now seen corresponding path program 1 times [2022-12-13 16:30:32,740 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:32,740 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [89747004] [2022-12-13 16:30:32,740 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:32,740 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:32,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:32,803 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:32,803 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:32,803 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [89747004] [2022-12-13 16:30:32,803 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [89747004] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:32,803 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:32,803 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:32,803 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [135228579] [2022-12-13 16:30:32,803 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:32,804 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:30:32,804 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:30:32,804 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 16:30:32,804 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 16:30:32,804 INFO L87 Difference]: Start difference. First operand 3761 states and 5528 transitions. cyclomatic complexity: 1768 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:32,902 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:30:32,902 INFO L93 Difference]: Finished difference Result 5496 states and 8063 transitions. [2022-12-13 16:30:32,902 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5496 states and 8063 transitions. [2022-12-13 16:30:32,916 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5301 [2022-12-13 16:30:32,927 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5496 states to 5496 states and 8063 transitions. [2022-12-13 16:30:32,927 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5496 [2022-12-13 16:30:32,930 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5496 [2022-12-13 16:30:32,930 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5496 states and 8063 transitions. [2022-12-13 16:30:32,934 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:30:32,934 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5496 states and 8063 transitions. [2022-12-13 16:30:32,939 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5496 states and 8063 transitions. [2022-12-13 16:30:32,971 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5496 to 3761. [2022-12-13 16:30:32,975 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3761 states, 3761 states have (on average 1.4690241956926349) internal successors, (5525), 3760 states have internal predecessors, (5525), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:32,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3761 states to 3761 states and 5525 transitions. [2022-12-13 16:30:32,979 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3761 states and 5525 transitions. [2022-12-13 16:30:32,979 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 16:30:32,980 INFO L428 stractBuchiCegarLoop]: Abstraction has 3761 states and 5525 transitions. [2022-12-13 16:30:32,980 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-12-13 16:30:32,980 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3761 states and 5525 transitions. [2022-12-13 16:30:32,987 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3586 [2022-12-13 16:30:32,987 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:30:32,987 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:30:32,988 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:32,988 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:32,988 INFO L748 eck$LassoCheckResult]: Stem: 67953#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 67954#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 68933#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 68934#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 69639#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 68530#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68531#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68599#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 68600#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 69037#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 69038#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 68567#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 68374#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 68375#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 68830#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 68831#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 68714#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 68715#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 68348#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68349#L1279 assume !(0 == ~M_E~0); 69559#L1279-2 assume !(0 == ~T1_E~0); 67974#L1284-1 assume !(0 == ~T2_E~0); 67975#L1289-1 assume !(0 == ~T3_E~0); 68706#L1294-1 assume !(0 == ~T4_E~0); 68707#L1299-1 assume !(0 == ~T5_E~0); 68718#L1304-1 assume !(0 == ~T6_E~0); 69638#L1309-1 assume !(0 == ~T7_E~0); 69640#L1314-1 assume !(0 == ~T8_E~0); 67902#L1319-1 assume !(0 == ~T9_E~0); 67903#L1324-1 assume !(0 == ~T10_E~0); 68075#L1329-1 assume !(0 == ~T11_E~0); 68076#L1334-1 assume !(0 == ~T12_E~0); 69472#L1339-1 assume !(0 == ~T13_E~0); 69549#L1344-1 assume !(0 == ~E_M~0); 69550#L1349-1 assume !(0 == ~E_1~0); 68894#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 68895#L1359-1 assume !(0 == ~E_3~0); 69299#L1364-1 assume !(0 == ~E_4~0); 68200#L1369-1 assume !(0 == ~E_5~0); 68201#L1374-1 assume !(0 == ~E_6~0); 68901#L1379-1 assume !(0 == ~E_7~0); 68902#L1384-1 assume !(0 == ~E_8~0); 68977#L1389-1 assume !(0 == ~E_9~0); 69493#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 69494#L1399-1 assume !(0 == ~E_11~0); 69591#L1404-1 assume !(0 == ~E_12~0); 68296#L1409-1 assume !(0 == ~E_13~0); 68297#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69586#L628 assume !(1 == ~m_pc~0); 68199#L628-2 is_master_triggered_~__retres1~0#1 := 0; 68198#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68779#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 68780#L1591 assume !(0 != activate_threads_~tmp~1#1); 69601#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68760#L647 assume 1 == ~t1_pc~0; 68125#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 68126#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68811#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 69261#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 69536#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69537#L666 assume 1 == ~t2_pc~0; 67971#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 67972#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68118#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 68119#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 69087#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69088#L685 assume !(1 == ~t3_pc~0); 69182#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 69181#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69251#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 68942#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 68943#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68417#L704 assume 1 == ~t4_pc~0; 68418#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 68953#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 67764#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 67765#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 68809#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 68810#L723 assume !(1 == ~t5_pc~0); 68938#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 69156#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 69292#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 69069#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 69070#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 68183#L742 assume 1 == ~t6_pc~0; 68184#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 68337#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 68107#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 67871#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 67872#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 68258#L761 assume !(1 == ~t7_pc~0); 68259#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 68136#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 68137#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 68944#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 68945#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 67892#L780 assume 1 == ~t8_pc~0; 67893#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 68173#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 68174#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 68906#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 68907#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 69026#L799 assume 1 == ~t9_pc~0; 69127#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 67895#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 67896#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 68164#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 69227#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 69048#L818 assume !(1 == ~t10_pc~0); 67676#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 67677#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 69119#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 69051#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 69052#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69094#L837 assume 1 == ~t11_pc~0; 69095#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 68932#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 69540#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 69016#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 69017#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 68771#L856 assume !(1 == ~t12_pc~0); 68772#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 69397#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 67694#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 67695#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 69377#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 69562#L875 assume 1 == ~t13_pc~0; 68716#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 68338#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 68339#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 68276#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 68277#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69116#L1427 assume !(1 == ~M_E~0); 69103#L1427-2 assume !(1 == ~T1_E~0); 68245#L1432-1 assume !(1 == ~T2_E~0); 68246#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69303#L1442-1 assume !(1 == ~T4_E~0); 69304#L1447-1 assume !(1 == ~T5_E~0); 69165#L1452-1 assume !(1 == ~T6_E~0); 67816#L1457-1 assume !(1 == ~T7_E~0); 67817#L1462-1 assume !(1 == ~T8_E~0); 69322#L1467-1 assume !(1 == ~T9_E~0); 69342#L1472-1 assume !(1 == ~T10_E~0); 69343#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 69112#L1482-1 assume !(1 == ~T12_E~0); 69113#L1487-1 assume !(1 == ~T13_E~0); 68145#L1492-1 assume !(1 == ~E_M~0); 68146#L1497-1 assume !(1 == ~E_1~0); 68512#L1502-1 assume !(1 == ~E_2~0); 68513#L1507-1 assume !(1 == ~E_3~0); 68027#L1512-1 assume !(1 == ~E_4~0); 68028#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 69417#L1522-1 assume !(1 == ~E_6~0); 68758#L1527-1 assume !(1 == ~E_7~0); 68759#L1532-1 assume !(1 == ~E_8~0); 69624#L1537-1 assume !(1 == ~E_9~0); 68963#L1542-1 assume !(1 == ~E_10~0); 68787#L1547-1 assume !(1 == ~E_11~0); 68788#L1552-1 assume !(1 == ~E_12~0); 67719#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 67720#L1562-1 assume { :end_inline_reset_delta_events } true; 68328#L1928-2 [2022-12-13 16:30:32,988 INFO L750 eck$LassoCheckResult]: Loop: 68328#L1928-2 assume !false; 68823#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 67983#L1254 assume !false; 68574#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68052#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68053#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68247#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 69403#L1067 assume !(0 != eval_~tmp~0#1); 68696#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 68305#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 68306#L1279-3 assume !(0 == ~M_E~0); 68532#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 68516#L1284-3 assume !(0 == ~T2_E~0); 68517#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 68496#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 68497#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 68888#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 68889#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 68383#L1314-3 assume !(0 == ~T8_E~0); 68384#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 69365#L1324-3 assume !(0 == ~T10_E~0); 68025#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 68026#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 68792#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 68793#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 69091#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 68366#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 68367#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 69099#L1364-3 assume !(0 == ~E_4~0); 69623#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 69509#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 68148#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 68149#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 68364#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 68365#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 68666#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 69519#L1404-3 assume !(0 == ~E_12~0); 69483#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 69484#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68989#L628-45 assume 1 == ~m_pc~0; 68661#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 68663#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69171#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 68397#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 68398#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69123#L647-45 assume 1 == ~t1_pc~0; 67968#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 67969#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68905#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 68081#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 68082#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68289#L666-45 assume 1 == ~t2_pc~0; 68291#L667-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 68778#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69169#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 69170#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 69235#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67832#L685-45 assume 1 == ~t3_pc~0; 67833#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 68900#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69551#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 69415#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 69416#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69560#L704-45 assume !(1 == ~t4_pc~0); 67699#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 67700#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68562#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 69437#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 69651#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69018#L723-45 assume !(1 == ~t5_pc~0); 69019#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 69495#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 69613#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 68378#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 68379#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69385#L742-45 assume !(1 == ~t6_pc~0); 68635#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 68636#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 68848#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 68849#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 69128#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 69214#L761-45 assume 1 == ~t7_pc~0; 69216#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 68629#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 68630#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 68031#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 68032#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 69487#L780-45 assume !(1 == ~t8_pc~0); 68400#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 68044#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 68045#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 69621#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 68011#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 68012#L799-45 assume !(1 == ~t9_pc~0); 68228#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 68229#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 69280#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 69163#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 69164#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 67948#L818-45 assume 1 == ~t10_pc~0; 67949#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 68071#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 69141#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 68560#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 68561#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69259#L837-45 assume !(1 == ~t11_pc~0); 68488#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 68489#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 68021#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 68022#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 68090#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 68091#L856-45 assume 1 == ~t12_pc~0; 69558#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 68093#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 69311#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 69312#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 68903#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 68904#L875-45 assume 1 == ~t13_pc~0; 68872#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 68873#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 68930#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 69271#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 69527#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69470#L1427-3 assume !(1 == ~M_E~0); 68701#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 68702#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 69222#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 68890#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 68891#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 67734#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 67735#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 69401#L1462-3 assume !(1 == ~T8_E~0); 69402#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 69267#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 69268#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 67992#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 67993#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 68133#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 68298#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 68299#L1502-3 assume !(1 == ~E_2~0); 69242#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 69363#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 68342#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 68035#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 68036#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 68002#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 68003#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 69100#L1542-3 assume !(1 == ~E_10~0); 69228#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 68875#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 68876#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 68203#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68204#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 67626#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68063#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 68064#L1947 assume !(0 == start_simulation_~tmp~3#1); 69007#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 69196#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68262#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 67684#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 67685#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 69327#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 69328#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 69491#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 68328#L1928-2 [2022-12-13 16:30:32,989 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:32,989 INFO L85 PathProgramCache]: Analyzing trace with hash 1809696709, now seen corresponding path program 1 times [2022-12-13 16:30:32,989 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:32,989 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1066031529] [2022-12-13 16:30:32,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:32,989 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:32,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:33,028 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:33,028 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:33,028 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1066031529] [2022-12-13 16:30:33,028 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1066031529] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:33,028 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:33,029 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 16:30:33,029 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1623730073] [2022-12-13 16:30:33,029 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:33,029 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:30:33,029 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:33,030 INFO L85 PathProgramCache]: Analyzing trace with hash 1347020522, now seen corresponding path program 1 times [2022-12-13 16:30:33,030 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:33,030 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1847216404] [2022-12-13 16:30:33,030 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:33,030 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:33,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:33,069 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:33,070 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:33,070 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1847216404] [2022-12-13 16:30:33,070 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1847216404] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:33,070 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:33,070 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:33,070 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1995159829] [2022-12-13 16:30:33,070 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:33,071 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:30:33,071 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:30:33,071 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:30:33,071 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:30:33,071 INFO L87 Difference]: Start difference. First operand 3761 states and 5525 transitions. cyclomatic complexity: 1765 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:33,131 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:30:33,131 INFO L93 Difference]: Finished difference Result 3761 states and 5487 transitions. [2022-12-13 16:30:33,131 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3761 states and 5487 transitions. [2022-12-13 16:30:33,142 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3586 [2022-12-13 16:30:33,162 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3761 states to 3761 states and 5487 transitions. [2022-12-13 16:30:33,163 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3761 [2022-12-13 16:30:33,164 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3761 [2022-12-13 16:30:33,164 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3761 states and 5487 transitions. [2022-12-13 16:30:33,166 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:30:33,167 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3761 states and 5487 transitions. [2022-12-13 16:30:33,169 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3761 states and 5487 transitions. [2022-12-13 16:30:33,193 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3761 to 3761. [2022-12-13 16:30:33,196 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3761 states, 3761 states have (on average 1.4589204998670566) internal successors, (5487), 3760 states have internal predecessors, (5487), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:33,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3761 states to 3761 states and 5487 transitions. [2022-12-13 16:30:33,201 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3761 states and 5487 transitions. [2022-12-13 16:30:33,201 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:30:33,201 INFO L428 stractBuchiCegarLoop]: Abstraction has 3761 states and 5487 transitions. [2022-12-13 16:30:33,201 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-12-13 16:30:33,201 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3761 states and 5487 transitions. [2022-12-13 16:30:33,208 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3586 [2022-12-13 16:30:33,208 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:30:33,208 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:30:33,209 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:33,209 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:33,210 INFO L748 eck$LassoCheckResult]: Stem: 75483#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 75484#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 76469#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 76470#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77286#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 76060#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76061#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76129#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76130#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 76581#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76582#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 76097#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 75902#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 75903#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 76360#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 76361#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 76243#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 76244#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 75876#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 75877#L1279 assume !(0 == ~M_E~0); 77168#L1279-2 assume !(0 == ~T1_E~0); 75503#L1284-1 assume !(0 == ~T2_E~0); 75504#L1289-1 assume !(0 == ~T3_E~0); 76235#L1294-1 assume !(0 == ~T4_E~0); 76236#L1299-1 assume !(0 == ~T5_E~0); 76247#L1304-1 assume !(0 == ~T6_E~0); 77283#L1309-1 assume !(0 == ~T7_E~0); 77287#L1314-1 assume !(0 == ~T8_E~0); 75431#L1319-1 assume !(0 == ~T9_E~0); 75432#L1324-1 assume !(0 == ~T10_E~0); 75604#L1329-1 assume !(0 == ~T11_E~0); 75605#L1334-1 assume !(0 == ~T12_E~0); 77056#L1339-1 assume !(0 == ~T13_E~0); 77152#L1344-1 assume !(0 == ~E_M~0); 77153#L1349-1 assume !(0 == ~E_1~0); 76426#L1354-1 assume !(0 == ~E_2~0); 76427#L1359-1 assume !(0 == ~E_3~0); 76852#L1364-1 assume !(0 == ~E_4~0); 75728#L1369-1 assume !(0 == ~E_5~0); 75729#L1374-1 assume !(0 == ~E_6~0); 76434#L1379-1 assume !(0 == ~E_7~0); 76435#L1384-1 assume !(0 == ~E_8~0); 76517#L1389-1 assume !(0 == ~E_9~0); 77077#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 77078#L1399-1 assume !(0 == ~E_11~0); 77205#L1404-1 assume !(0 == ~E_12~0); 75823#L1409-1 assume !(0 == ~E_13~0); 75824#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77198#L628 assume !(1 == ~m_pc~0); 75727#L628-2 is_master_triggered_~__retres1~0#1 := 0; 75726#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76309#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 76310#L1591 assume !(0 != activate_threads_~tmp~1#1); 77215#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76290#L647 assume 1 == ~t1_pc~0; 75653#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 75654#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76341#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 76811#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 77135#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77136#L666 assume !(1 == ~t2_pc~0); 75502#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 75666#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75646#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 75647#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 76631#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76632#L685 assume !(1 == ~t3_pc~0); 76728#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 76727#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76799#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 76479#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 76480#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75945#L704 assume 1 == ~t4_pc~0; 75946#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 76492#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75293#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 75294#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 76339#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76340#L723 assume !(1 == ~t5_pc~0); 76476#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 76701#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76845#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76613#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 76614#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 75711#L742 assume 1 == ~t6_pc~0; 75712#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 75865#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 75635#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75400#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 75401#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 75786#L761 assume !(1 == ~t7_pc~0); 75787#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 75664#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 75665#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 76482#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 76483#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 75421#L780 assume 1 == ~t8_pc~0; 75422#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 75701#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 75702#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 76440#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 76441#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 76570#L799 assume 1 == ~t9_pc~0; 76671#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 75424#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 75425#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 75693#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 76773#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 76592#L818 assume !(1 == ~t10_pc~0); 75205#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 75206#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 76661#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 76595#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 76596#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 76638#L837 assume 1 == ~t11_pc~0; 76639#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 76468#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 77141#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 76558#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 76559#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 76301#L856 assume !(1 == ~t12_pc~0); 76302#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 76960#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 75223#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 75224#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 76938#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 77172#L875 assume 1 == ~t13_pc~0; 76245#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 75866#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 75867#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 75804#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 75805#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76660#L1427 assume !(1 == ~M_E~0); 76647#L1427-2 assume !(1 == ~T1_E~0); 75773#L1432-1 assume !(1 == ~T2_E~0); 75774#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 76857#L1442-1 assume !(1 == ~T4_E~0); 76858#L1447-1 assume !(1 == ~T5_E~0); 76710#L1452-1 assume !(1 == ~T6_E~0); 75345#L1457-1 assume !(1 == ~T7_E~0); 75346#L1462-1 assume !(1 == ~T8_E~0); 76879#L1467-1 assume !(1 == ~T9_E~0); 76901#L1472-1 assume !(1 == ~T10_E~0); 76902#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 76656#L1482-1 assume !(1 == ~T12_E~0); 76657#L1487-1 assume !(1 == ~T13_E~0); 75674#L1492-1 assume !(1 == ~E_M~0); 75675#L1497-1 assume !(1 == ~E_1~0); 76042#L1502-1 assume !(1 == ~E_2~0); 76043#L1507-1 assume !(1 == ~E_3~0); 75556#L1512-1 assume !(1 == ~E_4~0); 75557#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 76986#L1522-1 assume !(1 == ~E_6~0); 76288#L1527-1 assume !(1 == ~E_7~0); 76289#L1532-1 assume !(1 == ~E_8~0); 77261#L1537-1 assume !(1 == ~E_9~0); 76500#L1542-1 assume !(1 == ~E_10~0); 76317#L1547-1 assume !(1 == ~E_11~0); 76318#L1552-1 assume !(1 == ~E_12~0); 75248#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 75249#L1562-1 assume { :end_inline_reset_delta_events } true; 75856#L1928-2 [2022-12-13 16:30:33,210 INFO L750 eck$LassoCheckResult]: Loop: 75856#L1928-2 assume !false; 76353#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 75512#L1254 assume !false; 76107#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 75581#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 75582#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 75775#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 76968#L1067 assume !(0 != eval_~tmp~0#1); 76969#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 77406#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 77197#L1279-3 assume !(0 == ~M_E~0); 76064#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 76047#L1284-3 assume !(0 == ~T2_E~0); 76048#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 77403#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 77402#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 77401#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 77400#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 77399#L1314-3 assume !(0 == ~T8_E~0); 77398#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 76926#L1324-3 assume !(0 == ~T10_E~0); 75554#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 75555#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 76326#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 76327#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 76635#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 75894#L1354-3 assume !(0 == ~E_2~0); 75895#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 76643#L1364-3 assume !(0 == ~E_4~0); 77281#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 77096#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 75676#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 75677#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 77388#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 77387#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 77386#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 77111#L1404-3 assume !(0 == ~E_12~0); 77112#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 77167#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76529#L628-45 assume 1 == ~m_pc~0; 76531#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 77254#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76716#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 76717#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 77219#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76667#L647-45 assume 1 == ~t1_pc~0; 75498#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 75499#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76439#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 75609#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 75610#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77376#L666-45 assume !(1 == ~t2_pc~0); 77375#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 77231#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76714#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 76715#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 76781#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75360#L685-45 assume 1 == ~t3_pc~0; 75361#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 77156#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77157#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 77308#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 77169#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77170#L704-45 assume 1 == ~t4_pc~0; 77369#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 77367#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77013#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 77014#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 77309#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77310#L723-45 assume 1 == ~t5_pc~0; 77363#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 77236#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77237#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 75906#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 75907#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 77298#L742-45 assume !(1 == ~t6_pc~0); 77359#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 77357#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 77356#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 77355#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 76985#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76760#L761-45 assume !(1 == ~t7_pc~0); 76761#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 76159#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 76160#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 75560#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 75561#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 77306#L780-45 assume !(1 == ~t8_pc~0); 77347#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 77345#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 77251#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 77252#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 75540#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 75541#L799-45 assume 1 == ~t9_pc~0; 76320#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 75754#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 76833#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 76708#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 76709#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 75478#L818-45 assume 1 == ~t10_pc~0; 75479#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 75598#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 76686#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 77331#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 77330#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77147#L837-45 assume !(1 == ~t11_pc~0); 76017#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 76018#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 75552#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 75553#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 75618#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 75619#L856-45 assume !(1 == ~t12_pc~0); 77315#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 76982#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 76865#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 76866#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 76437#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 76438#L875-45 assume 1 == ~t13_pc~0; 77319#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 76465#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 76466#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 76821#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 77316#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77053#L1427-3 assume !(1 == ~M_E~0); 77054#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 77698#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 77696#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77694#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 77692#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 77690#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 77689#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 77688#L1462-3 assume !(1 == ~T8_E~0); 77687#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 77686#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 77685#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 77684#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 77683#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 77682#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 77681#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 77680#L1502-3 assume !(1 == ~E_2~0); 77679#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 77678#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 77677#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 77676#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 77675#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 77674#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 77673#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 77672#L1542-3 assume !(1 == ~E_10~0); 77671#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 77670#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 77669#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 77668#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 77666#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 77652#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 77649#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 77647#L1947 assume !(0 == start_simulation_~tmp~3#1); 77644#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 77465#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 77452#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 77451#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 77450#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 76888#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 76889#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 77076#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 75856#L1928-2 [2022-12-13 16:30:33,210 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:33,210 INFO L85 PathProgramCache]: Analyzing trace with hash 350046660, now seen corresponding path program 1 times [2022-12-13 16:30:33,210 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:33,210 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [59944646] [2022-12-13 16:30:33,210 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:33,210 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:33,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:33,258 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:33,258 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:33,258 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [59944646] [2022-12-13 16:30:33,259 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [59944646] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:33,259 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:33,259 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:33,259 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [743894765] [2022-12-13 16:30:33,259 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:33,259 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:30:33,259 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:33,260 INFO L85 PathProgramCache]: Analyzing trace with hash 1666226024, now seen corresponding path program 1 times [2022-12-13 16:30:33,260 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:33,260 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1201567910] [2022-12-13 16:30:33,260 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:33,260 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:33,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:33,300 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:33,300 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:33,300 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1201567910] [2022-12-13 16:30:33,300 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1201567910] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:33,300 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:33,301 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:33,301 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1461903362] [2022-12-13 16:30:33,301 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:33,301 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:30:33,301 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:30:33,301 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 16:30:33,302 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 16:30:33,302 INFO L87 Difference]: Start difference. First operand 3761 states and 5487 transitions. cyclomatic complexity: 1727 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:33,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:30:33,441 INFO L93 Difference]: Finished difference Result 5381 states and 7833 transitions. [2022-12-13 16:30:33,441 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5381 states and 7833 transitions. [2022-12-13 16:30:33,456 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5201 [2022-12-13 16:30:33,467 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5381 states to 5381 states and 7833 transitions. [2022-12-13 16:30:33,467 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5381 [2022-12-13 16:30:33,473 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5381 [2022-12-13 16:30:33,473 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5381 states and 7833 transitions. [2022-12-13 16:30:33,478 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:30:33,478 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5381 states and 7833 transitions. [2022-12-13 16:30:33,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5381 states and 7833 transitions. [2022-12-13 16:30:33,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5381 to 3761. [2022-12-13 16:30:33,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3761 states, 3761 states have (on average 1.4581228396703005) internal successors, (5484), 3760 states have internal predecessors, (5484), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:33,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3761 states to 3761 states and 5484 transitions. [2022-12-13 16:30:33,539 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3761 states and 5484 transitions. [2022-12-13 16:30:33,539 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 16:30:33,540 INFO L428 stractBuchiCegarLoop]: Abstraction has 3761 states and 5484 transitions. [2022-12-13 16:30:33,540 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-12-13 16:30:33,540 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3761 states and 5484 transitions. [2022-12-13 16:30:33,547 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3586 [2022-12-13 16:30:33,548 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:30:33,548 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:30:33,549 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:33,549 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:33,549 INFO L748 eck$LassoCheckResult]: Stem: 84633#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 84634#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 85611#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 85612#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 86323#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 85208#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 85209#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 85277#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 85278#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 85715#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 85716#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 85245#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 85051#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 85052#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 85507#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 85508#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 85391#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 85392#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 85026#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 85027#L1279 assume !(0 == ~M_E~0); 86241#L1279-2 assume !(0 == ~T1_E~0); 84653#L1284-1 assume !(0 == ~T2_E~0); 84654#L1289-1 assume !(0 == ~T3_E~0); 85383#L1294-1 assume !(0 == ~T4_E~0); 85384#L1299-1 assume !(0 == ~T5_E~0); 85395#L1304-1 assume !(0 == ~T6_E~0); 86322#L1309-1 assume !(0 == ~T7_E~0); 86324#L1314-1 assume !(0 == ~T8_E~0); 84582#L1319-1 assume !(0 == ~T9_E~0); 84583#L1324-1 assume !(0 == ~T10_E~0); 84755#L1329-1 assume !(0 == ~T11_E~0); 84756#L1334-1 assume !(0 == ~T12_E~0); 86152#L1339-1 assume !(0 == ~T13_E~0); 86231#L1344-1 assume !(0 == ~E_M~0); 86232#L1349-1 assume !(0 == ~E_1~0); 85572#L1354-1 assume !(0 == ~E_2~0); 85573#L1359-1 assume !(0 == ~E_3~0); 85979#L1364-1 assume !(0 == ~E_4~0); 84879#L1369-1 assume !(0 == ~E_5~0); 84880#L1374-1 assume !(0 == ~E_6~0); 85579#L1379-1 assume !(0 == ~E_7~0); 85580#L1384-1 assume !(0 == ~E_8~0); 85655#L1389-1 assume !(0 == ~E_9~0); 86173#L1394-1 assume !(0 == ~E_10~0); 86174#L1399-1 assume !(0 == ~E_11~0); 86275#L1404-1 assume !(0 == ~E_12~0); 84974#L1409-1 assume !(0 == ~E_13~0); 84975#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86270#L628 assume !(1 == ~m_pc~0); 84878#L628-2 is_master_triggered_~__retres1~0#1 := 0; 84877#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 85456#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 85457#L1591 assume !(0 != activate_threads_~tmp~1#1); 86284#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 85437#L647 assume 1 == ~t1_pc~0; 84804#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 84805#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 85488#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 85940#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 86218#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86219#L666 assume !(1 == ~t2_pc~0); 84652#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 84819#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 84797#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 84798#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 85765#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 85766#L685 assume !(1 == ~t3_pc~0); 85860#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 85859#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 85929#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 85620#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 85621#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 85094#L704 assume 1 == ~t4_pc~0; 85095#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 85631#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 84445#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 84446#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 85486#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 85487#L723 assume !(1 == ~t5_pc~0); 85616#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 85834#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 85972#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 85747#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 85748#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 84862#L742 assume 1 == ~t6_pc~0; 84863#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 85015#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 84786#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 84551#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 84552#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 84937#L761 assume !(1 == ~t7_pc~0); 84938#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 84815#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 84816#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 85622#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 85623#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 84572#L780 assume 1 == ~t8_pc~0; 84573#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 84852#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 84853#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 85584#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 85585#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 85704#L799 assume 1 == ~t9_pc~0; 85805#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 84575#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 84576#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 84844#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 85905#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 85726#L818 assume !(1 == ~t10_pc~0); 84357#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 84358#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 85797#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 85729#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 85730#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 85772#L837 assume 1 == ~t11_pc~0; 85773#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 85610#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 86222#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 85694#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 85695#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 85448#L856 assume !(1 == ~t12_pc~0); 85449#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 86075#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 84375#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 84376#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 86055#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 86244#L875 assume 1 == ~t13_pc~0; 85393#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 85016#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 85017#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 84955#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 84956#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 85794#L1427 assume !(1 == ~M_E~0); 85781#L1427-2 assume !(1 == ~T1_E~0); 84924#L1432-1 assume !(1 == ~T2_E~0); 84925#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 85983#L1442-1 assume !(1 == ~T4_E~0); 85984#L1447-1 assume !(1 == ~T5_E~0); 85843#L1452-1 assume !(1 == ~T6_E~0); 84496#L1457-1 assume !(1 == ~T7_E~0); 84497#L1462-1 assume !(1 == ~T8_E~0); 86001#L1467-1 assume !(1 == ~T9_E~0); 86021#L1472-1 assume !(1 == ~T10_E~0); 86022#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 85790#L1482-1 assume !(1 == ~T12_E~0); 85791#L1487-1 assume !(1 == ~T13_E~0); 84825#L1492-1 assume !(1 == ~E_M~0); 84826#L1497-1 assume !(1 == ~E_1~0); 85189#L1502-1 assume !(1 == ~E_2~0); 85190#L1507-1 assume !(1 == ~E_3~0); 84707#L1512-1 assume !(1 == ~E_4~0); 84708#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 86095#L1522-1 assume !(1 == ~E_6~0); 85435#L1527-1 assume !(1 == ~E_7~0); 85436#L1532-1 assume !(1 == ~E_8~0); 86307#L1537-1 assume !(1 == ~E_9~0); 85641#L1542-1 assume !(1 == ~E_10~0); 85464#L1547-1 assume !(1 == ~E_11~0); 85465#L1552-1 assume !(1 == ~E_12~0); 84400#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 84401#L1562-1 assume { :end_inline_reset_delta_events } true; 85006#L1928-2 [2022-12-13 16:30:33,549 INFO L750 eck$LassoCheckResult]: Loop: 85006#L1928-2 assume !false; 85500#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 84663#L1254 assume !false; 85252#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 84732#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 84733#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 84926#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 86081#L1067 assume !(0 != eval_~tmp~0#1); 85377#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 84983#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 84984#L1279-3 assume !(0 == ~M_E~0); 85210#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 85193#L1284-3 assume !(0 == ~T2_E~0); 85194#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 85173#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 85174#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 85566#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 85567#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 85060#L1314-3 assume !(0 == ~T8_E~0); 85061#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 86043#L1324-3 assume !(0 == ~T10_E~0); 84705#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 84706#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 85469#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 85470#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 85769#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 85044#L1354-3 assume !(0 == ~E_2~0); 85045#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 85777#L1364-3 assume !(0 == ~E_4~0); 86306#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 86190#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 84828#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 84829#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 85042#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 85043#L1394-3 assume !(0 == ~E_10~0); 85344#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 86200#L1404-3 assume !(0 == ~E_12~0); 86163#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 86164#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 85667#L628-45 assume 1 == ~m_pc~0; 85339#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 85341#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 85849#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 85074#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 85075#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 85801#L647-45 assume 1 == ~t1_pc~0; 84648#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 84649#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 85583#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 84760#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 84761#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 84967#L666-45 assume !(1 == ~t2_pc~0); 84968#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 85455#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 85847#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 85848#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 85913#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 84512#L685-45 assume 1 == ~t3_pc~0; 84513#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 85578#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86233#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 86093#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 86094#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 86242#L704-45 assume 1 == ~t4_pc~0; 86115#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 84381#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 85240#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 86116#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 86338#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 85696#L723-45 assume !(1 == ~t5_pc~0); 85697#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 86175#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 86296#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 85055#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 85056#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 86063#L742-45 assume !(1 == ~t6_pc~0); 85313#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 85314#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85525#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 85526#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 85806#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 85893#L761-45 assume 1 == ~t7_pc~0; 85895#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 85307#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 85308#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 84711#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 84712#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 86167#L780-45 assume !(1 == ~t8_pc~0); 85077#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 84724#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 84725#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 86304#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 84691#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 84692#L799-45 assume !(1 == ~t9_pc~0); 84903#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 84904#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 85960#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 85841#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 85842#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 84625#L818-45 assume !(1 == ~t10_pc~0); 84627#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 84749#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 85819#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 85233#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 85234#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 85937#L837-45 assume 1 == ~t11_pc~0; 86226#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 85166#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 84701#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 84702#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 84769#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 84770#L856-45 assume 1 == ~t12_pc~0; 86240#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 84772#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 85990#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 85991#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 85581#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 85582#L875-45 assume !(1 == ~t13_pc~0); 85552#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 85551#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 85608#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 85950#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 86209#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86150#L1427-3 assume !(1 == ~M_E~0); 85378#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 85379#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 85900#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 85568#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 85569#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 84415#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 84416#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 86079#L1462-3 assume !(1 == ~T8_E~0); 86080#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 85946#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 85947#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 84672#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 84673#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 84812#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 84981#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 84982#L1502-3 assume !(1 == ~E_2~0); 85920#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 86041#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 85020#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 84715#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 84716#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 84682#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 84683#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 85778#L1542-3 assume !(1 == ~E_10~0); 85906#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 85553#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 85554#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 84882#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 84883#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 84307#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 84743#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 84744#L1947 assume !(0 == start_simulation_~tmp~3#1); 85685#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 85874#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 84941#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 84365#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 84366#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 86009#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 86010#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 86171#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 85006#L1928-2 [2022-12-13 16:30:33,549 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:33,550 INFO L85 PathProgramCache]: Analyzing trace with hash -1492429054, now seen corresponding path program 1 times [2022-12-13 16:30:33,550 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:33,550 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2142113628] [2022-12-13 16:30:33,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:33,550 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:33,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:33,597 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:33,597 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:33,597 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2142113628] [2022-12-13 16:30:33,597 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2142113628] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:33,597 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:33,597 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:33,597 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1369195922] [2022-12-13 16:30:33,597 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:33,598 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:30:33,598 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:33,598 INFO L85 PathProgramCache]: Analyzing trace with hash 1448446119, now seen corresponding path program 1 times [2022-12-13 16:30:33,598 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:33,598 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2120969661] [2022-12-13 16:30:33,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:33,598 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:33,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:33,652 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:33,652 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:33,653 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2120969661] [2022-12-13 16:30:33,653 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2120969661] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:33,653 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:33,653 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 16:30:33,653 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1137784748] [2022-12-13 16:30:33,653 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:33,653 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:30:33,654 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:30:33,654 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 16:30:33,654 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 16:30:33,654 INFO L87 Difference]: Start difference. First operand 3761 states and 5484 transitions. cyclomatic complexity: 1724 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:33,905 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:30:33,905 INFO L93 Difference]: Finished difference Result 10616 states and 15321 transitions. [2022-12-13 16:30:33,905 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10616 states and 15321 transitions. [2022-12-13 16:30:33,954 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10233 [2022-12-13 16:30:33,994 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10616 states to 10616 states and 15321 transitions. [2022-12-13 16:30:33,994 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10616 [2022-12-13 16:30:34,001 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10616 [2022-12-13 16:30:34,001 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10616 states and 15321 transitions. [2022-12-13 16:30:34,012 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:30:34,012 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10616 states and 15321 transitions. [2022-12-13 16:30:34,022 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10616 states and 15321 transitions. [2022-12-13 16:30:34,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10616 to 10232. [2022-12-13 16:30:34,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10232 states, 10232 states have (on average 1.44517200938233) internal successors, (14787), 10231 states have internal predecessors, (14787), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:34,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10232 states to 10232 states and 14787 transitions. [2022-12-13 16:30:34,161 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10232 states and 14787 transitions. [2022-12-13 16:30:34,161 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 16:30:34,162 INFO L428 stractBuchiCegarLoop]: Abstraction has 10232 states and 14787 transitions. [2022-12-13 16:30:34,162 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-12-13 16:30:34,162 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10232 states and 14787 transitions. [2022-12-13 16:30:34,197 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10049 [2022-12-13 16:30:34,197 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:30:34,198 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:30:34,200 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:34,200 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:34,201 INFO L748 eck$LassoCheckResult]: Stem: 99030#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 99031#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 100055#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 100056#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 101027#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 99613#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 99614#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 99689#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 99690#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 100172#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 100173#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 99652#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 99448#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 99449#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 99934#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 99935#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 99803#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 99804#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 99422#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 99423#L1279 assume !(0 == ~M_E~0); 100865#L1279-2 assume !(0 == ~T1_E~0); 99050#L1284-1 assume !(0 == ~T2_E~0); 99051#L1289-1 assume !(0 == ~T3_E~0); 99800#L1294-1 assume !(0 == ~T4_E~0); 99801#L1299-1 assume !(0 == ~T5_E~0); 99814#L1304-1 assume !(0 == ~T6_E~0); 101022#L1309-1 assume !(0 == ~T7_E~0); 101028#L1314-1 assume !(0 == ~T8_E~0); 98973#L1319-1 assume !(0 == ~T9_E~0); 98974#L1324-1 assume !(0 == ~T10_E~0); 99151#L1329-1 assume !(0 == ~T11_E~0); 99152#L1334-1 assume !(0 == ~T12_E~0); 100735#L1339-1 assume !(0 == ~T13_E~0); 100844#L1344-1 assume !(0 == ~E_M~0); 100845#L1349-1 assume !(0 == ~E_1~0); 100008#L1354-1 assume !(0 == ~E_2~0); 100009#L1359-1 assume !(0 == ~E_3~0); 100489#L1364-1 assume !(0 == ~E_4~0); 99274#L1369-1 assume !(0 == ~E_5~0); 99275#L1374-1 assume !(0 == ~E_6~0); 100015#L1379-1 assume !(0 == ~E_7~0); 100016#L1384-1 assume !(0 == ~E_8~0); 100103#L1389-1 assume !(0 == ~E_9~0); 100762#L1394-1 assume !(0 == ~E_10~0); 100763#L1399-1 assume !(0 == ~E_11~0); 100920#L1404-1 assume !(0 == ~E_12~0); 99371#L1409-1 assume !(0 == ~E_13~0); 99372#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 100904#L628 assume !(1 == ~m_pc~0); 100768#L628-2 is_master_triggered_~__retres1~0#1 := 0; 100302#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 99880#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 99881#L1591 assume !(0 != activate_threads_~tmp~1#1); 100936#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 99857#L647 assume !(1 == ~t1_pc~0); 99858#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 99912#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 99913#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 100440#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 100827#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 100828#L666 assume !(1 == ~t2_pc~0); 99049#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 99213#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 99192#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 99193#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 100237#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 100238#L685 assume !(1 == ~t3_pc~0); 100345#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 100344#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 100426#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 100066#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 100067#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 99498#L704 assume 1 == ~t4_pc~0; 99499#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 100079#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 98834#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 98835#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 99910#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 99911#L723 assume !(1 == ~t5_pc~0); 100062#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 100315#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 100481#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 100214#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 100215#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 99260#L742 assume 1 == ~t6_pc~0; 99261#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 99411#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 99183#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 98941#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 98942#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 99334#L761 assume !(1 == ~t7_pc~0); 99335#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 99211#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 99212#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 100069#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 100070#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 98965#L780 assume 1 == ~t8_pc~0; 98966#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 99251#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 99252#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 100026#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 100027#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 100160#L799 assume 1 == ~t9_pc~0; 100283#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 98968#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 98969#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 99243#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 100395#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 100191#L818 assume !(1 == ~t10_pc~0); 98746#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 98747#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 100273#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 100194#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 100195#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 100247#L837 assume 1 == ~t11_pc~0; 100248#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 100054#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 100834#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 100150#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 100151#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 99867#L856 assume !(1 == ~t12_pc~0); 99868#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 100625#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 98764#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 98765#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 100595#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 100869#L875 assume 1 == ~t13_pc~0; 99810#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 99412#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 99413#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 99352#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 99353#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 100272#L1427 assume !(1 == ~M_E~0); 100257#L1427-2 assume !(1 == ~T1_E~0); 99320#L1432-1 assume !(1 == ~T2_E~0); 99321#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 100496#L1442-1 assume !(1 == ~T4_E~0); 100497#L1447-1 assume !(1 == ~T5_E~0); 100327#L1452-1 assume !(1 == ~T6_E~0); 98885#L1457-1 assume !(1 == ~T7_E~0); 98886#L1462-1 assume !(1 == ~T8_E~0); 100527#L1467-1 assume !(1 == ~T9_E~0); 100550#L1472-1 assume !(1 == ~T10_E~0); 100551#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 100268#L1482-1 assume !(1 == ~T12_E~0); 100269#L1487-1 assume !(1 == ~T13_E~0); 99222#L1492-1 assume !(1 == ~E_M~0); 99223#L1497-1 assume !(1 == ~E_1~0); 99595#L1502-1 assume !(1 == ~E_2~0); 99596#L1507-1 assume !(1 == ~E_3~0); 99104#L1512-1 assume !(1 == ~E_4~0); 99105#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 100648#L1522-1 assume !(1 == ~E_6~0); 99854#L1527-1 assume !(1 == ~E_7~0); 99855#L1532-1 assume !(1 == ~E_8~0); 100992#L1537-1 assume !(1 == ~E_9~0); 100086#L1542-1 assume !(1 == ~E_10~0); 99888#L1547-1 assume !(1 == ~E_11~0); 99889#L1552-1 assume !(1 == ~E_12~0); 98787#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 98788#L1562-1 assume { :end_inline_reset_delta_events } true; 99402#L1928-2 [2022-12-13 16:30:34,201 INFO L750 eck$LassoCheckResult]: Loop: 99402#L1928-2 assume !false; 100057#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 99661#L1254 assume !false; 99662#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 99128#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 99129#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 100666#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 100667#L1067 assume !(0 != eval_~tmp~0#1); 99790#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 99380#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 99381#L1279-3 assume !(0 == ~M_E~0); 100903#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 107514#L1284-3 assume !(0 == ~T2_E~0); 100938#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 99578#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 99579#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 100004#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 100005#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 99458#L1314-3 assume !(0 == ~T8_E~0); 99459#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 101073#L1324-3 assume !(0 == ~T10_E~0); 107507#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 107506#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 99893#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 99894#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 100241#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 100242#L1354-3 assume !(0 == ~E_2~0); 107503#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 107502#L1364-3 assume !(0 == ~E_4~0); 107501#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 100795#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 99225#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 99226#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 107499#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 107498#L1394-3 assume !(0 == ~E_10~0); 107497#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 107496#L1404-3 assume !(0 == ~E_12~0); 107495#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 100864#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 100118#L628-45 assume !(1 == ~m_pc~0); 100119#L628-47 is_master_triggered_~__retres1~0#1 := 0; 100689#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 107492#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 107491#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 100939#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 100281#L647-45 assume !(1 == ~t1_pc~0); 100282#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 100024#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 100025#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 99157#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 99158#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 99364#L666-45 assume !(1 == ~t2_pc~0); 99365#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 107620#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 100331#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 100332#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 100405#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 100406#L685-45 assume 1 == ~t3_pc~0; 100017#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 100018#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 107619#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 107618#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 100866#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 100867#L704-45 assume 1 == ~t4_pc~0; 100683#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 98767#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 100684#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 100685#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 101080#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 100155#L723-45 assume 1 == ~t5_pc~0; 100157#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 107616#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 101072#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 99452#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 99453#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 100607#L742-45 assume 1 == ~t6_pc~0; 100608#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 99728#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 107527#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 107526#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 107525#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 107524#L761-45 assume !(1 == ~t7_pc~0); 107523#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 99722#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 99723#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 99108#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 99109#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 100750#L780-45 assume !(1 == ~t8_pc~0); 100752#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 107441#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 107440#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 107439#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 107438#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 107437#L799-45 assume !(1 == ~t9_pc~0); 107435#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 107434#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 107433#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 107432#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 107431#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 107430#L818-45 assume !(1 == ~t10_pc~0); 107429#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 107427#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 100573#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 99641#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 99642#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 100436#L837-45 assume !(1 == ~t11_pc~0); 99570#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 99571#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 99721#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 107420#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 107419#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 107418#L856-45 assume !(1 == ~t12_pc~0); 107417#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 100645#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 100506#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 100507#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 100021#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 100022#L875-45 assume !(1 == ~t13_pc~0); 107411#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 107410#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 107409#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 107408#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 107407#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 100732#L1427-3 assume !(1 == ~M_E~0); 100733#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 107851#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 107850#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 107849#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 107848#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 107847#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 107846#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 107845#L1462-3 assume !(1 == ~T8_E~0); 107844#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 107843#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 107842#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 107841#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 107840#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 107839#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 107838#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 107837#L1502-3 assume !(1 == ~E_2~0); 107836#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 107835#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 107834#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 107833#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 107832#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 107831#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 107830#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 107829#L1542-3 assume !(1 == ~E_10~0); 107828#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 107827#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 107826#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 107825#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 107823#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 100769#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 100770#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 100139#L1947 assume !(0 == start_simulation_~tmp~3#1); 100141#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 100505#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 99338#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 98754#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 98755#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 100538#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 100539#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 100761#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 99402#L1928-2 [2022-12-13 16:30:34,202 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:34,202 INFO L85 PathProgramCache]: Analyzing trace with hash -121367293, now seen corresponding path program 1 times [2022-12-13 16:30:34,202 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:34,202 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1181581720] [2022-12-13 16:30:34,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:34,202 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:34,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:34,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:34,289 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:34,289 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1181581720] [2022-12-13 16:30:34,289 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1181581720] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:34,289 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:34,289 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 16:30:34,289 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1224543542] [2022-12-13 16:30:34,290 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:34,290 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:30:34,290 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:34,291 INFO L85 PathProgramCache]: Analyzing trace with hash 1347360490, now seen corresponding path program 1 times [2022-12-13 16:30:34,291 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:34,291 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [787764894] [2022-12-13 16:30:34,291 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:34,291 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:34,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:34,355 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:34,355 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:34,356 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [787764894] [2022-12-13 16:30:34,356 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [787764894] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:34,356 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:34,356 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 16:30:34,356 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1353906753] [2022-12-13 16:30:34,356 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:34,356 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:30:34,357 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:30:34,357 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 16:30:34,357 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 16:30:34,357 INFO L87 Difference]: Start difference. First operand 10232 states and 14787 transitions. cyclomatic complexity: 4557 Second operand has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:34,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:30:34,681 INFO L93 Difference]: Finished difference Result 28024 states and 40569 transitions. [2022-12-13 16:30:34,681 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28024 states and 40569 transitions. [2022-12-13 16:30:34,754 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 27620 [2022-12-13 16:30:34,819 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28024 states to 28024 states and 40569 transitions. [2022-12-13 16:30:34,819 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28024 [2022-12-13 16:30:34,832 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28024 [2022-12-13 16:30:34,832 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28024 states and 40569 transitions. [2022-12-13 16:30:34,853 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:30:34,853 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28024 states and 40569 transitions. [2022-12-13 16:30:34,865 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28024 states and 40569 transitions. [2022-12-13 16:30:34,988 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28024 to 10496. [2022-12-13 16:30:34,996 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10496 states, 10496 states have (on average 1.4339748475609757) internal successors, (15051), 10495 states have internal predecessors, (15051), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:35,007 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10496 states to 10496 states and 15051 transitions. [2022-12-13 16:30:35,007 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10496 states and 15051 transitions. [2022-12-13 16:30:35,007 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 16:30:35,008 INFO L428 stractBuchiCegarLoop]: Abstraction has 10496 states and 15051 transitions. [2022-12-13 16:30:35,008 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-12-13 16:30:35,008 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10496 states and 15051 transitions. [2022-12-13 16:30:35,029 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10310 [2022-12-13 16:30:35,029 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:30:35,029 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:30:35,031 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:35,031 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:35,031 INFO L748 eck$LassoCheckResult]: Stem: 137297#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 137298#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 138334#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 138335#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 139355#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 137890#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 137891#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 137969#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 137970#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 138459#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 138460#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 137933#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 137720#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 137721#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 138215#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 138216#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 138088#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 138089#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 137695#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 137696#L1279 assume !(0 == ~M_E~0); 139166#L1279-2 assume !(0 == ~T1_E~0); 137319#L1284-1 assume !(0 == ~T2_E~0); 137320#L1289-1 assume !(0 == ~T3_E~0); 138080#L1294-1 assume !(0 == ~T4_E~0); 138081#L1299-1 assume !(0 == ~T5_E~0); 138092#L1304-1 assume !(0 == ~T6_E~0); 139352#L1309-1 assume !(0 == ~T7_E~0); 139357#L1314-1 assume !(0 == ~T8_E~0); 137241#L1319-1 assume !(0 == ~T9_E~0); 137242#L1324-1 assume !(0 == ~T10_E~0); 137419#L1329-1 assume !(0 == ~T11_E~0); 137420#L1334-1 assume !(0 == ~T12_E~0); 139027#L1339-1 assume !(0 == ~T13_E~0); 139144#L1344-1 assume !(0 == ~E_M~0); 139145#L1349-1 assume !(0 == ~E_1~0); 138288#L1354-1 assume !(0 == ~E_2~0); 138289#L1359-1 assume !(0 == ~E_3~0); 138789#L1364-1 assume !(0 == ~E_4~0); 137541#L1369-1 assume !(0 == ~E_5~0); 137542#L1374-1 assume !(0 == ~E_6~0); 138298#L1379-1 assume !(0 == ~E_7~0); 138299#L1384-1 assume !(0 == ~E_8~0); 138388#L1389-1 assume !(0 == ~E_9~0); 139059#L1394-1 assume !(0 == ~E_10~0); 139060#L1399-1 assume !(0 == ~E_11~0); 139235#L1404-1 assume !(0 == ~E_12~0); 137642#L1409-1 assume !(0 == ~E_13~0); 137643#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 139218#L628 assume !(1 == ~m_pc~0); 139064#L628-2 is_master_triggered_~__retres1~0#1 := 0; 138586#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 138160#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 138161#L1591 assume !(0 != activate_threads_~tmp~1#1); 139251#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 138137#L647 assume !(1 == ~t1_pc~0); 138138#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 138194#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 138195#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 138736#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 139129#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 139130#L666 assume !(1 == ~t2_pc~0); 137318#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 137479#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 137460#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 137461#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 138520#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 138521#L685 assume !(1 == ~t3_pc~0); 138634#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 138714#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 139266#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 138344#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 138345#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 137771#L704 assume 1 == ~t4_pc~0; 137772#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 138360#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 137104#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 137105#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 138192#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 138193#L723 assume !(1 == ~t5_pc~0); 138340#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 138602#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 138781#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 138496#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 138497#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 137527#L742 assume 1 == ~t6_pc~0; 137528#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 137684#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 137451#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 137211#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 137212#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 137601#L761 assume !(1 == ~t7_pc~0); 137602#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 137477#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 137478#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 138347#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 138348#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 137233#L780 assume 1 == ~t8_pc~0; 137234#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 137517#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 137518#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 138306#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 138307#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 138444#L799 assume 1 == ~t9_pc~0; 138563#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 137236#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 137237#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 137509#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 138686#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 138472#L818 assume !(1 == ~t10_pc~0); 137016#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 137017#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 138554#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 138477#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 138478#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 138530#L837 assume 1 == ~t11_pc~0; 138531#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 138333#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 139135#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 138437#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 138438#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 138147#L856 assume !(1 == ~t12_pc~0); 138148#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 138923#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 137034#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 137035#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 138894#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 139170#L875 assume 1 == ~t13_pc~0; 138090#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 137685#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 137686#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 137623#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 137624#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 138553#L1427 assume !(1 == ~M_E~0); 138540#L1427-2 assume !(1 == ~T1_E~0); 137587#L1432-1 assume !(1 == ~T2_E~0); 137588#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 138794#L1442-1 assume !(1 == ~T4_E~0); 138795#L1447-1 assume !(1 == ~T5_E~0); 138615#L1452-1 assume !(1 == ~T6_E~0); 137155#L1457-1 assume !(1 == ~T7_E~0); 137156#L1462-1 assume !(1 == ~T8_E~0); 138825#L1467-1 assume !(1 == ~T9_E~0); 138846#L1472-1 assume !(1 == ~T10_E~0); 138847#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 138549#L1482-1 assume !(1 == ~T12_E~0); 138550#L1487-1 assume !(1 == ~T13_E~0); 137487#L1492-1 assume !(1 == ~E_M~0); 137488#L1497-1 assume !(1 == ~E_1~0); 137870#L1502-1 assume !(1 == ~E_2~0); 137871#L1507-1 assume !(1 == ~E_3~0); 137372#L1512-1 assume !(1 == ~E_4~0); 137373#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 138948#L1522-1 assume !(1 == ~E_6~0); 138134#L1527-1 assume !(1 == ~E_7~0); 138135#L1532-1 assume !(1 == ~E_8~0); 139301#L1537-1 assume !(1 == ~E_9~0); 138368#L1542-1 assume !(1 == ~E_10~0); 138168#L1547-1 assume !(1 == ~E_11~0); 138169#L1552-1 assume !(1 == ~E_12~0); 137057#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 137058#L1562-1 assume { :end_inline_reset_delta_events } true; 137674#L1928-2 [2022-12-13 16:30:35,031 INFO L750 eck$LassoCheckResult]: Loop: 137674#L1928-2 assume !false; 143344#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 143339#L1254 assume !false; 143338#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 143331#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 143323#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 143322#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 143320#L1067 assume !(0 != eval_~tmp~0#1); 143321#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 146862#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 146859#L1279-3 assume !(0 == ~M_E~0); 146856#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 146853#L1284-3 assume !(0 == ~T2_E~0); 146850#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 146848#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 146846#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 146843#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 146840#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 146837#L1314-3 assume !(0 == ~T8_E~0); 146834#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 146831#L1324-3 assume !(0 == ~T10_E~0); 146828#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 139333#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 138176#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 138177#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 138527#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 137713#L1354-3 assume !(0 == ~E_2~0); 137714#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 138536#L1364-3 assume !(0 == ~E_4~0); 142738#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 142654#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 142655#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 142645#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 142646#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 142639#L1394-3 assume !(0 == ~E_10~0); 142640#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 142486#L1404-3 assume !(0 == ~E_12~0); 142487#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 146659#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 138403#L628-45 assume !(1 == ~m_pc~0); 138404#L628-47 is_master_triggered_~__retres1~0#1 := 0; 138981#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 138621#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 137743#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 137744#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 138560#L647-45 assume !(1 == ~t1_pc~0); 138561#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 139051#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 147409#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 147408#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 139163#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 137633#L666-45 assume !(1 == ~t2_pc~0); 137634#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 147405#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 138619#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 138620#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 138699#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 138700#L685-45 assume 1 == ~t3_pc~0; 138295#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 138296#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 139398#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 139399#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 138947#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 139167#L704-45 assume 1 == ~t4_pc~0; 138976#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 137037#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 137928#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 138977#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 139403#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 138439#L723-45 assume !(1 == ~t5_pc~0); 138440#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 139061#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 139280#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 137724#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 137725#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 147267#L742-45 assume !(1 == ~t6_pc~0); 147264#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 147261#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 147259#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 147257#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 147255#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 147254#L761-45 assume 1 == ~t7_pc~0; 147251#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 147248#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 147246#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 147244#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 147242#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 147239#L780-45 assume 1 == ~t8_pc~0; 147235#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 147233#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 147232#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 147192#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 147191#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 147190#L799-45 assume !(1 == ~t9_pc~0); 147188#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 147187#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 147186#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 147185#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 147184#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 147183#L818-45 assume !(1 == ~t10_pc~0); 147182#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 147176#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 147173#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 147168#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 147167#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 147166#L837-45 assume !(1 == ~t11_pc~0); 147164#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 147163#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 147162#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 139342#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 137434#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 137435#L856-45 assume 1 == ~t12_pc~0; 139162#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 137437#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 138803#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 138804#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 138303#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 138304#L875-45 assume !(1 == ~t13_pc~0); 146603#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 145533#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 145530#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 145529#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 145528#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 144867#L1427-3 assume !(1 == ~M_E~0); 144865#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 144863#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 144861#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 144859#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 144856#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 144855#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 144854#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 144853#L1462-3 assume !(1 == ~T8_E~0); 144799#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 144793#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 144788#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 144783#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 144777#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 144772#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 144766#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 144760#L1502-3 assume !(1 == ~E_2~0); 144756#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 144752#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 144747#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 144743#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 144738#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 144733#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 144729#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 144725#L1542-3 assume !(1 == ~E_10~0); 144720#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 144152#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 144149#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 137544#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 137545#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 142428#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 142429#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 138426#L1947 assume !(0 == start_simulation_~tmp~3#1); 138428#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 138802#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 137605#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 137024#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 137025#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 138834#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 138835#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 143345#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 137674#L1928-2 [2022-12-13 16:30:35,032 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:35,032 INFO L85 PathProgramCache]: Analyzing trace with hash -2061949307, now seen corresponding path program 1 times [2022-12-13 16:30:35,032 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:35,032 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [153498655] [2022-12-13 16:30:35,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:35,032 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:35,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:35,086 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:35,087 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:35,087 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [153498655] [2022-12-13 16:30:35,087 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [153498655] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:35,087 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:35,087 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 16:30:35,087 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1713575700] [2022-12-13 16:30:35,087 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:35,088 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:30:35,088 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:35,088 INFO L85 PathProgramCache]: Analyzing trace with hash -945124567, now seen corresponding path program 1 times [2022-12-13 16:30:35,088 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:35,088 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [392734702] [2022-12-13 16:30:35,088 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:35,089 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:35,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:35,136 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:35,136 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:35,136 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [392734702] [2022-12-13 16:30:35,136 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [392734702] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:35,136 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:35,136 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 16:30:35,136 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2034833012] [2022-12-13 16:30:35,136 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:35,137 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:30:35,137 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:30:35,137 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:30:35,137 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:30:35,137 INFO L87 Difference]: Start difference. First operand 10496 states and 15051 transitions. cyclomatic complexity: 4557 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:35,245 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:30:35,246 INFO L93 Difference]: Finished difference Result 20116 states and 28733 transitions. [2022-12-13 16:30:35,246 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20116 states and 28733 transitions. [2022-12-13 16:30:35,297 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 19909 [2022-12-13 16:30:35,331 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20116 states to 20116 states and 28733 transitions. [2022-12-13 16:30:35,332 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20116 [2022-12-13 16:30:35,340 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20116 [2022-12-13 16:30:35,340 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20116 states and 28733 transitions. [2022-12-13 16:30:35,353 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:30:35,353 INFO L218 hiAutomatonCegarLoop]: Abstraction has 20116 states and 28733 transitions. [2022-12-13 16:30:35,364 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20116 states and 28733 transitions. [2022-12-13 16:30:35,524 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20116 to 20104. [2022-12-13 16:30:35,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20104 states, 20104 states have (on average 1.4286211699164346) internal successors, (28721), 20103 states have internal predecessors, (28721), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:35,572 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20104 states to 20104 states and 28721 transitions. [2022-12-13 16:30:35,572 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20104 states and 28721 transitions. [2022-12-13 16:30:35,573 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:30:35,573 INFO L428 stractBuchiCegarLoop]: Abstraction has 20104 states and 28721 transitions. [2022-12-13 16:30:35,573 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-12-13 16:30:35,573 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20104 states and 28721 transitions. [2022-12-13 16:30:35,625 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 19897 [2022-12-13 16:30:35,625 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:30:35,625 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:30:35,626 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:35,626 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:35,626 INFO L748 eck$LassoCheckResult]: Stem: 167915#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 167916#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 168902#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 168903#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 169752#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 168487#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 168488#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 168558#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 168559#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 169010#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 169011#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 168526#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 168331#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 168332#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 168792#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 168793#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 168671#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 168672#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 168306#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 168307#L1279 assume !(0 == ~M_E~0); 169630#L1279-2 assume !(0 == ~T1_E~0); 167936#L1284-1 assume !(0 == ~T2_E~0); 167937#L1289-1 assume !(0 == ~T3_E~0); 168663#L1294-1 assume !(0 == ~T4_E~0); 168664#L1299-1 assume !(0 == ~T5_E~0); 168675#L1304-1 assume !(0 == ~T6_E~0); 169751#L1309-1 assume !(0 == ~T7_E~0); 169754#L1314-1 assume !(0 == ~T8_E~0); 167860#L1319-1 assume !(0 == ~T9_E~0); 167861#L1324-1 assume !(0 == ~T10_E~0); 168038#L1329-1 assume !(0 == ~T11_E~0); 168039#L1334-1 assume !(0 == ~T12_E~0); 169519#L1339-1 assume !(0 == ~T13_E~0); 169613#L1344-1 assume !(0 == ~E_M~0); 169614#L1349-1 assume !(0 == ~E_1~0); 168860#L1354-1 assume !(0 == ~E_2~0); 168861#L1359-1 assume !(0 == ~E_3~0); 169314#L1364-1 assume !(0 == ~E_4~0); 168158#L1369-1 assume !(0 == ~E_5~0); 168159#L1374-1 assume !(0 == ~E_6~0); 168868#L1379-1 assume !(0 == ~E_7~0); 168869#L1384-1 assume !(0 == ~E_8~0); 168949#L1389-1 assume !(0 == ~E_9~0); 169544#L1394-1 assume !(0 == ~E_10~0); 169545#L1399-1 assume !(0 == ~E_11~0); 169672#L1404-1 assume !(0 == ~E_12~0); 168254#L1409-1 assume !(0 == ~E_13~0); 168255#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 169661#L628 assume !(1 == ~m_pc~0); 169553#L628-2 is_master_triggered_~__retres1~0#1 := 0; 169131#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 168739#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 168740#L1591 assume !(0 != activate_threads_~tmp~1#1); 169683#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 168718#L647 assume !(1 == ~t1_pc~0); 168719#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 168771#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 168772#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 169270#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 169599#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 169600#L666 assume !(1 == ~t2_pc~0); 167935#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 168098#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 168081#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 168082#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 169069#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 169070#L685 assume !(1 == ~t3_pc~0); 169179#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 169251#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 169692#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 168912#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 168913#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 168374#L704 assume !(1 == ~t4_pc~0); 168375#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 168925#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 167725#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 167726#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 168769#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 168770#L723 assume !(1 == ~t5_pc~0); 168909#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 169147#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 169306#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 169047#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 169048#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 168143#L742 assume 1 == ~t6_pc~0; 168144#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 168295#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 168070#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 167832#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 167833#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 168216#L761 assume !(1 == ~t7_pc~0); 168217#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 168096#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 168097#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 168915#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 168916#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 167852#L780 assume 1 == ~t8_pc~0; 167853#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 168133#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 168134#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 168875#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 168876#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 168998#L799 assume 1 == ~t9_pc~0; 169109#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 167855#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 167856#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 168125#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 169229#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 169023#L818 assume !(1 == ~t10_pc~0); 167637#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 167638#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 169101#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 169027#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 169028#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 169077#L837 assume 1 == ~t11_pc~0; 169078#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 168901#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 169605#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 168991#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 168992#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 168728#L856 assume !(1 == ~t12_pc~0); 168729#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 169432#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 167655#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 167656#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 169406#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 169633#L875 assume 1 == ~t13_pc~0; 168673#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 168296#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 168297#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 168235#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 168236#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 169100#L1427 assume !(1 == ~M_E~0); 169086#L1427-2 assume !(1 == ~T1_E~0); 168203#L1432-1 assume !(1 == ~T2_E~0); 168204#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 169321#L1442-1 assume !(1 == ~T4_E~0); 169322#L1447-1 assume !(1 == ~T5_E~0); 169160#L1452-1 assume !(1 == ~T6_E~0); 167776#L1457-1 assume !(1 == ~T7_E~0); 167777#L1462-1 assume !(1 == ~T8_E~0); 169344#L1467-1 assume !(1 == ~T9_E~0); 169364#L1472-1 assume !(1 == ~T10_E~0); 169365#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 169096#L1482-1 assume !(1 == ~T12_E~0); 169097#L1487-1 assume !(1 == ~T13_E~0); 168106#L1492-1 assume !(1 == ~E_M~0); 168107#L1497-1 assume !(1 == ~E_1~0); 168468#L1502-1 assume !(1 == ~E_2~0); 168469#L1507-1 assume !(1 == ~E_3~0); 167990#L1512-1 assume !(1 == ~E_4~0); 167991#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 169454#L1522-1 assume !(1 == ~E_6~0); 168714#L1527-1 assume !(1 == ~E_7~0); 168715#L1532-1 assume !(1 == ~E_8~0); 169720#L1537-1 assume !(1 == ~E_9~0); 168932#L1542-1 assume !(1 == ~E_10~0); 168747#L1547-1 assume !(1 == ~E_11~0); 168748#L1552-1 assume !(1 == ~E_12~0); 167678#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 167679#L1562-1 assume { :end_inline_reset_delta_events } true; 168285#L1928-2 [2022-12-13 16:30:35,627 INFO L750 eck$LassoCheckResult]: Loop: 168285#L1928-2 assume !false; 183459#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 183452#L1254 assume !false; 183450#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 183432#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 183422#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 183420#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 183418#L1067 assume !(0 != eval_~tmp~0#1); 168657#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 168263#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 168264#L1279-3 assume !(0 == ~M_E~0); 168491#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 168472#L1284-3 assume !(0 == ~T2_E~0); 168473#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 168452#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 168453#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 168856#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 168857#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 168340#L1314-3 assume !(0 == ~T8_E~0); 168341#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 169392#L1324-3 assume !(0 == ~T10_E~0); 167988#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 167989#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 168755#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 168756#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 169074#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 168324#L1354-3 assume !(0 == ~E_2~0); 168325#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 169082#L1364-3 assume !(0 == ~E_4~0); 169719#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 169571#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 168109#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 168110#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 168322#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 168323#L1394-3 assume !(0 == ~E_10~0); 168624#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 169582#L1404-3 assume !(0 == ~E_12~0); 169531#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 169532#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 168961#L628-45 assume !(1 == ~m_pc~0); 168962#L628-47 is_master_triggered_~__retres1~0#1 := 0; 169479#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 169167#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 168353#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 168354#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 169107#L647-45 assume !(1 == ~t1_pc~0); 169108#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 168873#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 168874#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 168043#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 168044#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 168245#L666-45 assume !(1 == ~t2_pc~0); 168246#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 168738#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 169165#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 169166#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 169241#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 167788#L685-45 assume !(1 == ~t3_pc~0); 167790#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 169555#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 169616#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 169452#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 169453#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 169631#L704-45 assume !(1 == ~t4_pc~0); 167657#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 167658#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 168521#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 169475#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 169778#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 168993#L723-45 assume !(1 == ~t5_pc~0); 168994#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 169546#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 169700#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 168335#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 168336#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 169414#L742-45 assume !(1 == ~t6_pc~0); 168593#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 168594#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 168812#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 168813#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 169114#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 169215#L761-45 assume !(1 == ~t7_pc~0); 169216#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 168588#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 168589#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 167994#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 167995#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 169535#L780-45 assume 1 == ~t8_pc~0; 168355#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 168003#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 168004#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 169717#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 167974#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 167975#L799-45 assume !(1 == ~t9_pc~0); 168182#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 168183#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 169782#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 186089#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 186088#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 186087#L818-45 assume !(1 == ~t10_pc~0); 186086#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 186084#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 186083#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 186082#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 186081#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 186080#L837-45 assume !(1 == ~t11_pc~0); 186050#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 186048#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 186046#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 186044#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 186041#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 186039#L856-45 assume 1 == ~t12_pc~0; 186036#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 186034#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 186032#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 186030#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 186027#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 186025#L875-45 assume !(1 == ~t13_pc~0); 186022#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 186020#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 186018#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 186016#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 186013#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 186011#L1427-3 assume !(1 == ~M_E~0); 169517#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 186009#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 186008#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 186006#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 186005#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 186004#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 186003#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 186002#L1462-3 assume !(1 == ~T8_E~0); 186001#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 186000#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 185999#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 185997#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 185995#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 185993#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 185990#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 185988#L1502-3 assume !(1 == ~E_2~0); 185986#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 185984#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 185982#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 185980#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 185976#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 185974#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 185972#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 185970#L1542-3 assume !(1 == ~E_10~0); 185967#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 185965#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 185963#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 185961#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 183515#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 183501#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 183499#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 183497#L1947 assume !(0 == start_simulation_~tmp~3#1); 183494#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 183487#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 183473#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 183471#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 183468#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 183466#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 183464#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 183462#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 168285#L1928-2 [2022-12-13 16:30:35,627 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:35,627 INFO L85 PathProgramCache]: Analyzing trace with hash 846336710, now seen corresponding path program 1 times [2022-12-13 16:30:35,627 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:35,627 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1474965141] [2022-12-13 16:30:35,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:35,627 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:35,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:35,672 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:35,672 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:35,672 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1474965141] [2022-12-13 16:30:35,672 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1474965141] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:35,672 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:35,672 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:35,672 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [477639479] [2022-12-13 16:30:35,672 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:35,673 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:30:35,673 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:35,673 INFO L85 PathProgramCache]: Analyzing trace with hash 257370990, now seen corresponding path program 1 times [2022-12-13 16:30:35,673 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:35,673 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1745195287] [2022-12-13 16:30:35,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:35,674 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:35,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:35,733 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:35,733 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:35,733 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1745195287] [2022-12-13 16:30:35,733 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1745195287] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:35,733 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:35,734 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 16:30:35,734 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [83618871] [2022-12-13 16:30:35,734 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:35,734 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:30:35,734 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:30:35,734 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 16:30:35,735 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 16:30:35,735 INFO L87 Difference]: Start difference. First operand 20104 states and 28721 transitions. cyclomatic complexity: 8621 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:36,160 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:30:36,160 INFO L93 Difference]: Finished difference Result 57725 states and 81880 transitions. [2022-12-13 16:30:36,160 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57725 states and 81880 transitions. [2022-12-13 16:30:36,366 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 56583 [2022-12-13 16:30:36,492 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57725 states to 57725 states and 81880 transitions. [2022-12-13 16:30:36,492 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 57725 [2022-12-13 16:30:36,519 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 57725 [2022-12-13 16:30:36,519 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57725 states and 81880 transitions. [2022-12-13 16:30:36,547 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:30:36,547 INFO L218 hiAutomatonCegarLoop]: Abstraction has 57725 states and 81880 transitions. [2022-12-13 16:30:36,574 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57725 states and 81880 transitions. [2022-12-13 16:30:36,951 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57725 to 56169. [2022-12-13 16:30:36,993 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 56169 states, 56169 states have (on average 1.420000356068294) internal successors, (79760), 56168 states have internal predecessors, (79760), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:37,063 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56169 states to 56169 states and 79760 transitions. [2022-12-13 16:30:37,063 INFO L240 hiAutomatonCegarLoop]: Abstraction has 56169 states and 79760 transitions. [2022-12-13 16:30:37,063 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 16:30:37,064 INFO L428 stractBuchiCegarLoop]: Abstraction has 56169 states and 79760 transitions. [2022-12-13 16:30:37,064 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-12-13 16:30:37,064 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 56169 states and 79760 transitions. [2022-12-13 16:30:37,230 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 55899 [2022-12-13 16:30:37,231 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:30:37,231 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:30:37,233 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:37,233 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:37,234 INFO L748 eck$LassoCheckResult]: Stem: 245754#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 245755#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 246740#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 246741#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 247590#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 246323#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 246324#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 246394#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 246395#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 246847#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 246848#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 246361#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 246163#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 246164#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 246633#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 246634#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 246509#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 246510#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 246138#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 246139#L1279 assume !(0 == ~M_E~0); 247458#L1279-2 assume !(0 == ~T1_E~0); 245775#L1284-1 assume !(0 == ~T2_E~0); 245776#L1289-1 assume !(0 == ~T3_E~0); 246506#L1294-1 assume !(0 == ~T4_E~0); 246507#L1299-1 assume !(0 == ~T5_E~0); 246518#L1304-1 assume !(0 == ~T6_E~0); 247589#L1309-1 assume !(0 == ~T7_E~0); 247591#L1314-1 assume !(0 == ~T8_E~0); 245701#L1319-1 assume !(0 == ~T9_E~0); 245702#L1324-1 assume !(0 == ~T10_E~0); 245875#L1329-1 assume !(0 == ~T11_E~0); 245876#L1334-1 assume !(0 == ~T12_E~0); 247353#L1339-1 assume !(0 == ~T13_E~0); 247444#L1344-1 assume !(0 == ~E_M~0); 247445#L1349-1 assume !(0 == ~E_1~0); 246699#L1354-1 assume !(0 == ~E_2~0); 246700#L1359-1 assume !(0 == ~E_3~0); 247141#L1364-1 assume !(0 == ~E_4~0); 245994#L1369-1 assume !(0 == ~E_5~0); 245995#L1374-1 assume !(0 == ~E_6~0); 246706#L1379-1 assume !(0 == ~E_7~0); 246707#L1384-1 assume !(0 == ~E_8~0); 246785#L1389-1 assume !(0 == ~E_9~0); 247378#L1394-1 assume !(0 == ~E_10~0); 247379#L1399-1 assume !(0 == ~E_11~0); 247503#L1404-1 assume !(0 == ~E_12~0); 246089#L1409-1 assume !(0 == ~E_13~0); 246090#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 247490#L628 assume !(1 == ~m_pc~0); 247383#L628-2 is_master_triggered_~__retres1~0#1 := 0; 246966#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 246581#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 246582#L1591 assume !(0 != activate_threads_~tmp~1#1); 247514#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 246561#L647 assume !(1 == ~t1_pc~0); 246562#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 246613#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 246614#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 247098#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 247430#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 247431#L666 assume !(1 == ~t2_pc~0); 245774#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 245934#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 245915#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 245916#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 246905#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 246906#L685 assume !(1 == ~t3_pc~0); 247009#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 247079#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 247524#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 246749#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 246750#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 246209#L704 assume !(1 == ~t4_pc~0); 246210#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 246762#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 245567#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 245568#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 246611#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 246612#L723 assume !(1 == ~t5_pc~0); 246745#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 246978#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 247133#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 246882#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 246883#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 245980#L742 assume !(1 == ~t6_pc~0); 245981#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 246127#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 245906#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 245671#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 245672#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 246052#L761 assume !(1 == ~t7_pc~0); 246053#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 245930#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 245931#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 246752#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 246753#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 245693#L780 assume 1 == ~t8_pc~0; 245694#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 245971#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 245972#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 246713#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 246714#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 246835#L799 assume 1 == ~t9_pc~0; 246945#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 245696#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 245697#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 245963#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 247058#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 246860#L818 assume !(1 == ~t10_pc~0); 245479#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 245480#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 246937#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 246863#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 246864#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 246914#L837 assume 1 == ~t11_pc~0; 246915#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 246738#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 247436#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 246828#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 246829#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 246570#L856 assume !(1 == ~t12_pc~0); 246571#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 247257#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 245497#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 245498#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 247230#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 247461#L875 assume 1 == ~t13_pc~0; 246516#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 246128#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 246129#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 246070#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 246071#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 246936#L1427 assume !(1 == ~M_E~0); 246921#L1427-2 assume !(1 == ~T1_E~0); 246039#L1432-1 assume !(1 == ~T2_E~0); 246040#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 247146#L1442-1 assume !(1 == ~T4_E~0); 247147#L1447-1 assume !(1 == ~T5_E~0); 246989#L1452-1 assume !(1 == ~T6_E~0); 245618#L1457-1 assume !(1 == ~T7_E~0); 245619#L1462-1 assume !(1 == ~T8_E~0); 247173#L1467-1 assume !(1 == ~T9_E~0); 247193#L1472-1 assume !(1 == ~T10_E~0); 247194#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 246932#L1482-1 assume !(1 == ~T12_E~0); 246933#L1487-1 assume !(1 == ~T13_E~0); 245942#L1492-1 assume !(1 == ~E_M~0); 245943#L1497-1 assume !(1 == ~E_1~0); 246304#L1502-1 assume !(1 == ~E_2~0); 246305#L1507-1 assume !(1 == ~E_3~0); 245828#L1512-1 assume !(1 == ~E_4~0); 245829#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 247281#L1522-1 assume !(1 == ~E_6~0); 246558#L1527-1 assume !(1 == ~E_7~0); 246559#L1532-1 assume !(1 == ~E_8~0); 247553#L1537-1 assume !(1 == ~E_9~0); 246769#L1542-1 assume !(1 == ~E_10~0); 246588#L1547-1 assume !(1 == ~E_11~0); 246589#L1552-1 assume !(1 == ~E_12~0); 245520#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 245521#L1562-1 assume { :end_inline_reset_delta_events } true; 246119#L1928-2 [2022-12-13 16:30:37,234 INFO L750 eck$LassoCheckResult]: Loop: 246119#L1928-2 assume !false; 276905#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 276898#L1254 assume !false; 276896#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 276878#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 276868#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 276866#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 276863#L1067 assume !(0 != eval_~tmp~0#1); 276864#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 292097#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 292087#L1279-3 assume !(0 == ~M_E~0); 292083#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 292080#L1284-3 assume !(0 == ~T2_E~0); 292076#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 292073#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 282220#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 282212#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 282205#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 282197#L1314-3 assume !(0 == ~T8_E~0); 282189#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 282181#L1324-3 assume !(0 == ~T10_E~0); 282173#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 282166#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 282159#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 282150#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 282142#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 282135#L1354-3 assume !(0 == ~E_2~0); 282127#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 282119#L1364-3 assume !(0 == ~E_4~0); 282111#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 282104#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 282097#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 282090#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 282080#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 282073#L1394-3 assume !(0 == ~E_10~0); 282066#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 282058#L1404-3 assume !(0 == ~E_12~0); 281918#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 278294#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 278289#L628-45 assume !(1 == ~m_pc~0); 278285#L628-47 is_master_triggered_~__retres1~0#1 := 0; 278279#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 278274#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 278265#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 278259#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 278254#L647-45 assume !(1 == ~t1_pc~0); 278248#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 278242#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 278237#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 278230#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 278225#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 278219#L666-45 assume !(1 == ~t2_pc~0); 278213#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 278206#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 278200#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 278193#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 278185#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 278177#L685-45 assume 1 == ~t3_pc~0; 278168#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 278150#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 278141#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 278132#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 278125#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 278118#L704-45 assume !(1 == ~t4_pc~0); 278112#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 278106#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 276838#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 276837#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 276836#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 276835#L723-45 assume 1 == ~t5_pc~0; 276833#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 276832#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 276831#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 276830#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 276828#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 276827#L742-45 assume !(1 == ~t6_pc~0); 276826#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 276825#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 276824#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 276823#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 276822#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 276821#L761-45 assume !(1 == ~t7_pc~0); 276820#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 276818#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 276817#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 276816#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 276815#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 276814#L780-45 assume 1 == ~t8_pc~0; 276812#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 276811#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 276810#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 276809#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 276808#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 276807#L799-45 assume !(1 == ~t9_pc~0); 276805#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 276804#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 276803#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 276802#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 276801#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 276800#L818-45 assume 1 == ~t10_pc~0; 276798#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 276796#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 276795#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 276794#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 276793#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 276792#L837-45 assume !(1 == ~t11_pc~0); 276790#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 276789#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 276787#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 276785#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 276783#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 276781#L856-45 assume 1 == ~t12_pc~0; 276778#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 276776#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 276774#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 276772#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 276770#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 276768#L875-45 assume !(1 == ~t13_pc~0); 276765#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 276763#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 276762#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 276759#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 276757#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 276755#L1427-3 assume !(1 == ~M_E~0); 275154#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 276752#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 276750#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 276746#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 276744#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 276742#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 276740#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 276737#L1462-3 assume !(1 == ~T8_E~0); 276735#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 276733#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 276730#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 276728#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 276726#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 276724#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 276722#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 276720#L1502-3 assume !(1 == ~E_2~0); 276717#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 276715#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 276713#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 276711#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 276709#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 276707#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 276705#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 276703#L1542-3 assume !(1 == ~E_10~0); 276701#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 276699#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 276697#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 276695#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 276688#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 276674#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 276672#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 276668#L1947 assume !(0 == start_simulation_~tmp~3#1); 276669#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 276933#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 276919#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 276917#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 276914#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 276912#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 276910#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 276908#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 246119#L1928-2 [2022-12-13 16:30:37,235 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:37,235 INFO L85 PathProgramCache]: Analyzing trace with hash -995977081, now seen corresponding path program 1 times [2022-12-13 16:30:37,235 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:37,235 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1851212206] [2022-12-13 16:30:37,235 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:37,236 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:37,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:37,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:37,274 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:37,274 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1851212206] [2022-12-13 16:30:37,274 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1851212206] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:37,274 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:37,274 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 16:30:37,274 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1705457311] [2022-12-13 16:30:37,274 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:37,275 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:30:37,275 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:37,275 INFO L85 PathProgramCache]: Analyzing trace with hash 669136937, now seen corresponding path program 1 times [2022-12-13 16:30:37,275 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:37,275 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [232553433] [2022-12-13 16:30:37,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:37,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:37,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:37,302 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:37,302 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:37,302 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [232553433] [2022-12-13 16:30:37,302 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [232553433] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:37,302 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:37,302 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:37,302 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [574990818] [2022-12-13 16:30:37,302 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:37,302 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:30:37,302 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:30:37,303 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:30:37,303 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:30:37,303 INFO L87 Difference]: Start difference. First operand 56169 states and 79760 transitions. cyclomatic complexity: 23599 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:37,700 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:30:37,700 INFO L93 Difference]: Finished difference Result 108069 states and 152952 transitions. [2022-12-13 16:30:37,700 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 108069 states and 152952 transitions. [2022-12-13 16:30:38,110 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 107632 [2022-12-13 16:30:38,343 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 108069 states to 108069 states and 152952 transitions. [2022-12-13 16:30:38,343 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 108069 [2022-12-13 16:30:38,393 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 108069 [2022-12-13 16:30:38,394 INFO L73 IsDeterministic]: Start isDeterministic. Operand 108069 states and 152952 transitions. [2022-12-13 16:30:38,524 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:30:38,525 INFO L218 hiAutomatonCegarLoop]: Abstraction has 108069 states and 152952 transitions. [2022-12-13 16:30:38,558 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108069 states and 152952 transitions. [2022-12-13 16:30:39,129 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108069 to 107997. [2022-12-13 16:30:39,183 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 107997 states, 107997 states have (on average 1.4155948776354899) internal successors, (152880), 107996 states have internal predecessors, (152880), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:39,325 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 107997 states to 107997 states and 152880 transitions. [2022-12-13 16:30:39,325 INFO L240 hiAutomatonCegarLoop]: Abstraction has 107997 states and 152880 transitions. [2022-12-13 16:30:39,325 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:30:39,326 INFO L428 stractBuchiCegarLoop]: Abstraction has 107997 states and 152880 transitions. [2022-12-13 16:30:39,326 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-12-13 16:30:39,326 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 107997 states and 152880 transitions. [2022-12-13 16:30:39,567 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 107560 [2022-12-13 16:30:39,567 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:30:39,567 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:30:39,569 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:39,569 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:39,569 INFO L748 eck$LassoCheckResult]: Stem: 410000#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 410001#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 410992#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 410993#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 411921#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 410572#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 410573#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 410645#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 410646#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 411102#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 411103#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 410611#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 410418#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 410419#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 410885#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 410886#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 410760#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 410761#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 410392#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 410393#L1279 assume !(0 == ~M_E~0); 411775#L1279-2 assume !(0 == ~T1_E~0); 410024#L1284-1 assume !(0 == ~T2_E~0); 410025#L1289-1 assume !(0 == ~T3_E~0); 410757#L1294-1 assume !(0 == ~T4_E~0); 410758#L1299-1 assume !(0 == ~T5_E~0); 410770#L1304-1 assume !(0 == ~T6_E~0); 411919#L1309-1 assume !(0 == ~T7_E~0); 411922#L1314-1 assume !(0 == ~T8_E~0); 409947#L1319-1 assume !(0 == ~T9_E~0); 409948#L1324-1 assume !(0 == ~T10_E~0); 410126#L1329-1 assume !(0 == ~T11_E~0); 410127#L1334-1 assume !(0 == ~T12_E~0); 411644#L1339-1 assume !(0 == ~T13_E~0); 411756#L1344-1 assume !(0 == ~E_M~0); 411757#L1349-1 assume !(0 == ~E_1~0); 410948#L1354-1 assume !(0 == ~E_2~0); 410949#L1359-1 assume !(0 == ~E_3~0); 411415#L1364-1 assume !(0 == ~E_4~0); 410246#L1369-1 assume !(0 == ~E_5~0); 410247#L1374-1 assume !(0 == ~E_6~0); 410956#L1379-1 assume !(0 == ~E_7~0); 410957#L1384-1 assume !(0 == ~E_8~0); 411039#L1389-1 assume !(0 == ~E_9~0); 411670#L1394-1 assume !(0 == ~E_10~0); 411671#L1399-1 assume !(0 == ~E_11~0); 411827#L1404-1 assume !(0 == ~E_12~0); 410341#L1409-1 assume !(0 == ~E_13~0); 410342#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 411812#L628 assume !(1 == ~m_pc~0); 411676#L628-2 is_master_triggered_~__retres1~0#1 := 0; 411223#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 410833#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 410834#L1591 assume !(0 != activate_threads_~tmp~1#1); 411838#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 410813#L647 assume !(1 == ~t1_pc~0); 410814#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 410865#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 410866#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 411369#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 411735#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 411736#L666 assume !(1 == ~t2_pc~0); 410023#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 410185#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 410166#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 410167#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 411158#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 411159#L685 assume !(1 == ~t3_pc~0); 411268#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 411346#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 411848#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 411001#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 411002#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 410462#L704 assume !(1 == ~t4_pc~0); 410463#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 411015#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 409811#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 409812#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 410863#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 410864#L723 assume !(1 == ~t5_pc~0); 410997#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 411236#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 411408#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 411137#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 411138#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 410231#L742 assume !(1 == ~t6_pc~0); 410232#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 410381#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 410157#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 409915#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 409916#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 410304#L761 assume !(1 == ~t7_pc~0); 410305#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 410181#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 410182#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 411005#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 411006#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 409939#L780 assume !(1 == ~t8_pc~0); 409940#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 410222#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 410223#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 410965#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 410966#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 411089#L799 assume 1 == ~t9_pc~0; 411200#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 409941#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 409942#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 410214#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 411322#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 411115#L818 assume !(1 == ~t10_pc~0); 409723#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 409724#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 411192#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 411118#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 411119#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 411167#L837 assume 1 == ~t11_pc~0; 411168#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 410990#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 411743#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 411080#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 411081#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 410822#L856 assume !(1 == ~t12_pc~0); 410823#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 411548#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 409741#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 409742#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 411518#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 411780#L875 assume 1 == ~t13_pc~0; 410767#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 410382#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 410383#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 410322#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 410323#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 411191#L1427 assume !(1 == ~M_E~0); 411175#L1427-2 assume !(1 == ~T1_E~0); 410291#L1432-1 assume !(1 == ~T2_E~0); 410292#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 411421#L1442-1 assume !(1 == ~T4_E~0); 411422#L1447-1 assume !(1 == ~T5_E~0); 411248#L1452-1 assume !(1 == ~T6_E~0); 409862#L1457-1 assume !(1 == ~T7_E~0); 409863#L1462-1 assume !(1 == ~T8_E~0); 411450#L1467-1 assume !(1 == ~T9_E~0); 411479#L1472-1 assume !(1 == ~T10_E~0); 411480#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 411187#L1482-1 assume !(1 == ~T12_E~0); 411188#L1487-1 assume !(1 == ~T13_E~0); 410193#L1492-1 assume !(1 == ~E_M~0); 410194#L1497-1 assume !(1 == ~E_1~0); 410555#L1502-1 assume !(1 == ~E_2~0); 410556#L1507-1 assume !(1 == ~E_3~0); 410079#L1512-1 assume !(1 == ~E_4~0); 410080#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 411576#L1522-1 assume !(1 == ~E_6~0); 410809#L1527-1 assume !(1 == ~E_7~0); 410810#L1532-1 assume !(1 == ~E_8~0); 411885#L1537-1 assume !(1 == ~E_9~0); 411022#L1542-1 assume !(1 == ~E_10~0); 410840#L1547-1 assume !(1 == ~E_11~0); 410841#L1552-1 assume !(1 == ~E_12~0); 409764#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 409765#L1562-1 assume { :end_inline_reset_delta_events } true; 410373#L1928-2 [2022-12-13 16:30:39,569 INFO L750 eck$LassoCheckResult]: Loop: 410373#L1928-2 assume !false; 465597#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 465591#L1254 assume !false; 465589#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 464919#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 464910#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 464908#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 464905#L1067 assume !(0 != eval_~tmp~0#1); 464906#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 473052#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 473050#L1279-3 assume !(0 == ~M_E~0); 473048#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 473046#L1284-3 assume !(0 == ~T2_E~0); 473044#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 473042#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 473041#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 473040#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 473039#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 473038#L1314-3 assume !(0 == ~T8_E~0); 473037#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 473036#L1324-3 assume !(0 == ~T10_E~0); 473035#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 473034#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 473033#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 473032#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 473031#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 473030#L1354-3 assume !(0 == ~E_2~0); 473029#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 473028#L1364-3 assume !(0 == ~E_4~0); 473027#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 473025#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 473024#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 473023#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 473021#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 473020#L1394-3 assume !(0 == ~E_10~0); 473019#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 473018#L1404-3 assume !(0 == ~E_12~0); 473017#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 473016#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 473014#L628-45 assume !(1 == ~m_pc~0); 473012#L628-47 is_master_triggered_~__retres1~0#1 := 0; 473010#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 473008#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 473006#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 473004#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 473002#L647-45 assume !(1 == ~t1_pc~0); 473000#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 472998#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 472996#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 472994#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 472992#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 472987#L666-45 assume !(1 == ~t2_pc~0); 472985#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 472983#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 472981#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 472979#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 472975#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 472973#L685-45 assume 1 == ~t3_pc~0; 472971#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 472972#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 473026#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 472961#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 472959#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 472957#L704-45 assume !(1 == ~t4_pc~0); 472955#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 472953#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 472951#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 472949#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 472947#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 472946#L723-45 assume !(1 == ~t5_pc~0); 472943#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 472940#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 472938#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 472936#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 472934#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 472932#L742-45 assume !(1 == ~t6_pc~0); 472931#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 472929#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 472927#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 472925#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 472923#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 472921#L761-45 assume !(1 == ~t7_pc~0); 472918#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 472915#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 472913#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 472911#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 472909#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 472907#L780-45 assume !(1 == ~t8_pc~0); 472905#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 472903#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 472901#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 472899#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 472897#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 472895#L799-45 assume 1 == ~t9_pc~0; 472892#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 472889#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 472887#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 472885#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 472883#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 472881#L818-45 assume !(1 == ~t10_pc~0); 472878#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 472875#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 472873#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 472871#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 472869#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 472867#L837-45 assume 1 == ~t11_pc~0; 472814#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 472811#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 472809#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 472807#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 472805#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 472803#L856-45 assume !(1 == ~t12_pc~0); 472800#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 472797#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 472795#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 472793#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 472791#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 472789#L875-45 assume 1 == ~t13_pc~0; 472788#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 472785#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 472783#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 472781#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 472779#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 472768#L1427-3 assume !(1 == ~M_E~0); 472766#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 472764#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 472762#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 472760#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 472758#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 472756#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 472754#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 472752#L1462-3 assume !(1 == ~T8_E~0); 472750#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 472747#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 472745#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 472743#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 472741#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 472739#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 472737#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 472736#L1502-3 assume !(1 == ~E_2~0); 472733#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 472731#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 472729#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 472727#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 472725#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 472723#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 472720#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 472613#L1542-3 assume !(1 == ~E_10~0); 472600#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 472590#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 472582#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 472575#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 472442#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 472421#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 472413#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 472403#L1947 assume !(0 == start_simulation_~tmp~3#1); 472394#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 465627#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 465612#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 465609#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 465607#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 465605#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 465603#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 465601#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 410373#L1928-2 [2022-12-13 16:30:39,569 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:39,570 INFO L85 PathProgramCache]: Analyzing trace with hash -618334264, now seen corresponding path program 1 times [2022-12-13 16:30:39,570 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:39,570 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [33581303] [2022-12-13 16:30:39,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:39,570 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:39,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:39,766 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:39,766 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:39,766 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [33581303] [2022-12-13 16:30:39,766 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [33581303] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:39,767 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:39,767 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:39,767 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1238221222] [2022-12-13 16:30:39,767 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:39,767 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:30:39,768 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:39,768 INFO L85 PathProgramCache]: Analyzing trace with hash -611262102, now seen corresponding path program 1 times [2022-12-13 16:30:39,768 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:39,768 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1662634386] [2022-12-13 16:30:39,768 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:39,768 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:39,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:39,823 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:39,823 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:39,823 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1662634386] [2022-12-13 16:30:39,823 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1662634386] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:39,823 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:39,823 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 16:30:39,823 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [900813014] [2022-12-13 16:30:39,824 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:39,824 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:30:39,824 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:30:39,824 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 16:30:39,824 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 16:30:39,825 INFO L87 Difference]: Start difference. First operand 107997 states and 152880 transitions. cyclomatic complexity: 44899 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:40,982 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:30:40,983 INFO L93 Difference]: Finished difference Result 309396 states and 435421 transitions. [2022-12-13 16:30:40,983 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 309396 states and 435421 transitions. [2022-12-13 16:30:41,943 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 304880 [2022-12-13 16:30:42,355 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 309396 states to 309396 states and 435421 transitions. [2022-12-13 16:30:42,355 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 309396 [2022-12-13 16:30:42,537 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 309396 [2022-12-13 16:30:42,537 INFO L73 IsDeterministic]: Start isDeterministic. Operand 309396 states and 435421 transitions. [2022-12-13 16:30:42,600 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:30:42,600 INFO L218 hiAutomatonCegarLoop]: Abstraction has 309396 states and 435421 transitions. [2022-12-13 16:30:42,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 309396 states and 435421 transitions. [2022-12-13 16:30:44,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 309396 to 303172. [2022-12-13 16:30:44,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 303172 states, 303172 states have (on average 1.4087217816948794) internal successors, (427085), 303171 states have internal predecessors, (427085), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:45,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 303172 states to 303172 states and 427085 transitions. [2022-12-13 16:30:45,468 INFO L240 hiAutomatonCegarLoop]: Abstraction has 303172 states and 427085 transitions. [2022-12-13 16:30:45,469 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 16:30:45,469 INFO L428 stractBuchiCegarLoop]: Abstraction has 303172 states and 427085 transitions. [2022-12-13 16:30:45,469 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-12-13 16:30:45,469 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 303172 states and 427085 transitions. [2022-12-13 16:30:46,072 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 302288 [2022-12-13 16:30:46,072 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:30:46,073 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:30:46,074 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:46,074 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:46,074 INFO L748 eck$LassoCheckResult]: Stem: 827404#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 827405#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 828406#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 828407#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 829305#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 827972#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 827973#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 828043#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 828044#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 828514#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 828515#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 828012#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 827814#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 827815#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 828291#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 828292#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 828166#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 828167#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 827789#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 827790#L1279 assume !(0 == ~M_E~0); 829161#L1279-2 assume !(0 == ~T1_E~0); 827425#L1284-1 assume !(0 == ~T2_E~0); 827426#L1289-1 assume !(0 == ~T3_E~0); 828154#L1294-1 assume !(0 == ~T4_E~0); 828155#L1299-1 assume !(0 == ~T5_E~0); 828171#L1304-1 assume !(0 == ~T6_E~0); 829304#L1309-1 assume !(0 == ~T7_E~0); 829307#L1314-1 assume !(0 == ~T8_E~0); 827352#L1319-1 assume !(0 == ~T9_E~0); 827353#L1324-1 assume !(0 == ~T10_E~0); 827524#L1329-1 assume !(0 == ~T11_E~0); 827525#L1334-1 assume !(0 == ~T12_E~0); 829040#L1339-1 assume !(0 == ~T13_E~0); 829148#L1344-1 assume !(0 == ~E_M~0); 829149#L1349-1 assume !(0 == ~E_1~0); 828361#L1354-1 assume !(0 == ~E_2~0); 828362#L1359-1 assume !(0 == ~E_3~0); 828809#L1364-1 assume !(0 == ~E_4~0); 827643#L1369-1 assume !(0 == ~E_5~0); 827644#L1374-1 assume !(0 == ~E_6~0); 828368#L1379-1 assume !(0 == ~E_7~0); 828369#L1384-1 assume !(0 == ~E_8~0); 828450#L1389-1 assume !(0 == ~E_9~0); 829070#L1394-1 assume !(0 == ~E_10~0); 829071#L1399-1 assume !(0 == ~E_11~0); 829206#L1404-1 assume !(0 == ~E_12~0); 827737#L1409-1 assume !(0 == ~E_13~0); 827738#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 829194#L628 assume !(1 == ~m_pc~0); 829076#L628-2 is_master_triggered_~__retres1~0#1 := 0; 828625#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 828235#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 828236#L1591 assume !(0 != activate_threads_~tmp~1#1); 829218#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 828213#L647 assume !(1 == ~t1_pc~0); 828214#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 828270#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 828271#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 828763#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 829132#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 829133#L666 assume !(1 == ~t2_pc~0); 827424#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 827586#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 827567#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 827568#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 828567#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 828568#L685 assume !(1 == ~t3_pc~0); 828668#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 828739#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 829231#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 828415#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 828416#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 827859#L704 assume !(1 == ~t4_pc~0); 827860#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 828427#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 827215#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 827216#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 828268#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 828269#L723 assume !(1 == ~t5_pc~0); 828411#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 828638#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 828801#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 828549#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 828550#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 827631#L742 assume !(1 == ~t6_pc~0); 827632#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 827778#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 827556#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 827322#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 827323#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 827700#L761 assume !(1 == ~t7_pc~0); 827701#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 827582#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 827583#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 828417#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 828418#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 827343#L780 assume !(1 == ~t8_pc~0); 827344#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 827621#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 827622#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 828374#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 828375#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 828503#L799 assume !(1 == ~t9_pc~0); 827835#L799-2 is_transmit9_triggered_~__retres1~9#1 := 0; 827345#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 827346#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 827613#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 828716#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 828525#L818 assume !(1 == ~t10_pc~0); 827128#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 827129#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 828600#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 828528#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 828529#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 828575#L837 assume 1 == ~t11_pc~0; 828576#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 828404#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 829136#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 828493#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 828494#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 828226#L856 assume !(1 == ~t12_pc~0); 828227#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 828938#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 827146#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 827147#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 828909#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 829164#L875 assume 1 == ~t13_pc~0; 828168#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 827779#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 827780#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 827719#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 827720#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 828597#L1427 assume !(1 == ~M_E~0); 828584#L1427-2 assume !(1 == ~T1_E~0); 827688#L1432-1 assume !(1 == ~T2_E~0); 827689#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 828813#L1442-1 assume !(1 == ~T4_E~0); 828814#L1447-1 assume !(1 == ~T5_E~0); 828649#L1452-1 assume !(1 == ~T6_E~0); 827266#L1457-1 assume !(1 == ~T7_E~0); 827267#L1462-1 assume !(1 == ~T8_E~0); 828845#L1467-1 assume !(1 == ~T9_E~0); 828869#L1472-1 assume !(1 == ~T10_E~0); 828870#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 828593#L1482-1 assume !(1 == ~T12_E~0); 828594#L1487-1 assume !(1 == ~T13_E~0); 827592#L1492-1 assume !(1 == ~E_M~0); 827593#L1497-1 assume !(1 == ~E_1~0); 827954#L1502-1 assume !(1 == ~E_2~0); 827955#L1507-1 assume !(1 == ~E_3~0); 827478#L1512-1 assume !(1 == ~E_4~0); 827479#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 828968#L1522-1 assume !(1 == ~E_6~0); 828211#L1527-1 assume !(1 == ~E_7~0); 828212#L1532-1 assume !(1 == ~E_8~0); 829266#L1537-1 assume !(1 == ~E_9~0); 828436#L1542-1 assume !(1 == ~E_10~0); 828245#L1547-1 assume !(1 == ~E_11~0); 828246#L1552-1 assume !(1 == ~E_12~0); 827170#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 827171#L1562-1 assume { :end_inline_reset_delta_events } true; 827770#L1928-2 [2022-12-13 16:30:46,075 INFO L750 eck$LassoCheckResult]: Loop: 827770#L1928-2 assume !false; 992031#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 992021#L1254 assume !false; 992019#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 991847#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 991834#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 991833#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 991831#L1067 assume !(0 != eval_~tmp~0#1); 991832#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 994329#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 994323#L1279-3 assume !(0 == ~M_E~0); 994318#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 994312#L1284-3 assume !(0 == ~T2_E~0); 994306#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 994299#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 994293#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 994287#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 994280#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 994274#L1314-3 assume !(0 == ~T8_E~0); 994266#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 994261#L1324-3 assume !(0 == ~T10_E~0); 994256#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 994252#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 994247#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 994242#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 994236#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 994230#L1354-3 assume !(0 == ~E_2~0); 994224#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 994217#L1364-3 assume !(0 == ~E_4~0); 994210#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 994204#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 994199#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 994193#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 994187#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 994180#L1394-3 assume !(0 == ~E_10~0); 994174#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 994168#L1404-3 assume !(0 == ~E_12~0); 994159#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 994153#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 994147#L628-45 assume !(1 == ~m_pc~0); 994140#L628-47 is_master_triggered_~__retres1~0#1 := 0; 994135#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 994130#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 994125#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 994120#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 994114#L647-45 assume !(1 == ~t1_pc~0); 994106#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 994100#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 994095#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 994089#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 994084#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 994078#L666-45 assume !(1 == ~t2_pc~0); 994072#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 994066#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 994059#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 994052#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 994046#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 994042#L685-45 assume !(1 == ~t3_pc~0); 994039#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 994033#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 994026#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 994020#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 994013#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 994006#L704-45 assume !(1 == ~t4_pc~0); 994000#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 993995#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 993990#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 993985#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 993978#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 993972#L723-45 assume !(1 == ~t5_pc~0); 993965#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 993957#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 993950#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 993943#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 993939#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 993935#L742-45 assume !(1 == ~t6_pc~0); 993930#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 993925#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 993920#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 993914#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 993907#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 993900#L761-45 assume !(1 == ~t7_pc~0); 993893#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 993887#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 993882#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 993877#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 993871#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 993866#L780-45 assume !(1 == ~t8_pc~0); 993861#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 993856#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 993850#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 993843#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 993835#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 993829#L799-45 assume !(1 == ~t9_pc~0); 993822#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 993816#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 993810#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 993804#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 993797#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 993790#L818-45 assume !(1 == ~t10_pc~0); 993783#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 993774#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 993765#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 993757#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 993749#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 993743#L837-45 assume 1 == ~t11_pc~0; 993737#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 993730#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 993725#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 993719#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 993713#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 993705#L856-45 assume !(1 == ~t12_pc~0); 993698#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 993690#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 993684#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 993678#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 993672#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 993666#L875-45 assume 1 == ~t13_pc~0; 993660#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 993653#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 993647#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 993639#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 993633#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 993625#L1427-3 assume !(1 == ~M_E~0); 993079#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 993613#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 993607#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 993600#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 993594#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 993588#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 993581#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 993574#L1462-3 assume !(1 == ~T8_E~0); 993567#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 993558#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 993553#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 993548#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 993542#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 993537#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 993532#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 993525#L1502-3 assume !(1 == ~E_2~0); 993518#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 993511#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 993505#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 993498#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 993490#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 993484#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 993479#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 993470#L1542-3 assume !(1 == ~E_10~0); 993465#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 993460#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 993457#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 993456#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 992353#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 992331#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 992325#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 992319#L1947 assume !(0 == start_simulation_~tmp~3#1); 992314#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 992093#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 992080#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 992076#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 992074#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 992072#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 992071#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 992066#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 827770#L1928-2 [2022-12-13 16:30:46,075 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:46,075 INFO L85 PathProgramCache]: Analyzing trace with hash -1649665079, now seen corresponding path program 1 times [2022-12-13 16:30:46,075 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:46,076 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1156054107] [2022-12-13 16:30:46,076 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:46,076 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:46,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:46,137 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:46,137 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:46,137 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1156054107] [2022-12-13 16:30:46,137 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1156054107] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:46,137 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:46,137 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 16:30:46,137 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [79238205] [2022-12-13 16:30:46,137 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:46,138 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:30:46,138 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:46,138 INFO L85 PathProgramCache]: Analyzing trace with hash 1066051694, now seen corresponding path program 1 times [2022-12-13 16:30:46,138 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:46,138 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1846195934] [2022-12-13 16:30:46,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:46,139 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:46,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:46,181 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:46,181 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:46,181 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1846195934] [2022-12-13 16:30:46,181 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1846195934] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:46,181 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:46,181 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 16:30:46,181 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [853377451] [2022-12-13 16:30:46,181 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:46,182 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:30:46,182 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:30:46,182 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 16:30:46,182 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 16:30:46,182 INFO L87 Difference]: Start difference. First operand 303172 states and 427085 transitions. cyclomatic complexity: 123945 Second operand has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:47,971 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:30:47,971 INFO L93 Difference]: Finished difference Result 709361 states and 1009908 transitions. [2022-12-13 16:30:47,971 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 709361 states and 1009908 transitions. [2022-12-13 16:30:50,190 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 707004 [2022-12-13 16:30:51,786 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 709361 states to 709361 states and 1009908 transitions. [2022-12-13 16:30:51,786 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 709361 [2022-12-13 16:30:51,961 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 709361 [2022-12-13 16:30:51,961 INFO L73 IsDeterministic]: Start isDeterministic. Operand 709361 states and 1009908 transitions. [2022-12-13 16:30:52,185 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:30:52,185 INFO L218 hiAutomatonCegarLoop]: Abstraction has 709361 states and 1009908 transitions. [2022-12-13 16:30:52,438 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 709361 states and 1009908 transitions. [2022-12-13 16:30:55,147 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 709361 to 310819. [2022-12-13 16:30:55,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 310819 states, 310819 states have (on average 1.3986661047104585) internal successors, (434732), 310818 states have internal predecessors, (434732), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:55,814 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 310819 states to 310819 states and 434732 transitions. [2022-12-13 16:30:55,814 INFO L240 hiAutomatonCegarLoop]: Abstraction has 310819 states and 434732 transitions. [2022-12-13 16:30:55,814 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 16:30:55,815 INFO L428 stractBuchiCegarLoop]: Abstraction has 310819 states and 434732 transitions. [2022-12-13 16:30:55,815 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-12-13 16:30:55,815 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 310819 states and 434732 transitions. [2022-12-13 16:30:56,524 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 309932 [2022-12-13 16:30:56,524 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:30:56,525 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:30:56,526 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:56,526 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:30:56,526 INFO L748 eck$LassoCheckResult]: Stem: 1839948#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1839949#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1840958#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1840959#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1841897#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 1840521#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1840522#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1840590#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1840591#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1841067#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1841068#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1840556#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1840364#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1840365#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1840839#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1840840#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1840708#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1840709#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1840338#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1840339#L1279 assume !(0 == ~M_E~0); 1841743#L1279-2 assume !(0 == ~T1_E~0); 1839969#L1284-1 assume !(0 == ~T2_E~0); 1839970#L1289-1 assume !(0 == ~T3_E~0); 1840701#L1294-1 assume !(0 == ~T4_E~0); 1840702#L1299-1 assume !(0 == ~T5_E~0); 1840717#L1304-1 assume !(0 == ~T6_E~0); 1841895#L1309-1 assume !(0 == ~T7_E~0); 1841898#L1314-1 assume !(0 == ~T8_E~0); 1839894#L1319-1 assume !(0 == ~T9_E~0); 1839895#L1324-1 assume !(0 == ~T10_E~0); 1840071#L1329-1 assume !(0 == ~T11_E~0); 1840072#L1334-1 assume !(0 == ~T12_E~0); 1841614#L1339-1 assume !(0 == ~T13_E~0); 1841724#L1344-1 assume !(0 == ~E_M~0); 1841725#L1349-1 assume !(0 == ~E_1~0); 1840912#L1354-1 assume !(0 == ~E_2~0); 1840913#L1359-1 assume !(0 == ~E_3~0); 1841374#L1364-1 assume !(0 == ~E_4~0); 1840189#L1369-1 assume !(0 == ~E_5~0); 1840190#L1374-1 assume !(0 == ~E_6~0); 1840919#L1379-1 assume !(0 == ~E_7~0); 1840920#L1384-1 assume !(0 == ~E_8~0); 1841005#L1389-1 assume !(0 == ~E_9~0); 1841642#L1394-1 assume !(0 == ~E_10~0); 1841643#L1399-1 assume !(0 == ~E_11~0); 1841792#L1404-1 assume !(0 == ~E_12~0); 1840285#L1409-1 assume !(0 == ~E_13~0); 1840286#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1841780#L628 assume !(1 == ~m_pc~0); 1841647#L628-2 is_master_triggered_~__retres1~0#1 := 0; 1841183#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1840782#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1840783#L1591 assume !(0 != activate_threads_~tmp~1#1); 1841807#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1840761#L647 assume !(1 == ~t1_pc~0); 1840762#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1840818#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1840819#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1841330#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 1841707#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1841708#L666 assume !(1 == ~t2_pc~0); 1839968#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1840130#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1840111#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1840112#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 1841124#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1841125#L685 assume !(1 == ~t3_pc~0); 1841230#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1841307#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1841819#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1840967#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 1840968#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1840408#L704 assume !(1 == ~t4_pc~0); 1840409#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1840981#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1839763#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1839764#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 1840816#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1840817#L723 assume !(1 == ~t5_pc~0); 1840963#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1841199#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1841366#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1841101#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 1841102#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1840176#L742 assume !(1 == ~t6_pc~0); 1840177#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1840327#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1840102#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1839866#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 1839867#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1840247#L761 assume !(1 == ~t7_pc~0); 1840248#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1840126#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1840127#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1840970#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 1840971#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1839887#L780 assume !(1 == ~t8_pc~0); 1839888#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1840167#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1840168#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1840926#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 1840927#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1841055#L799 assume !(1 == ~t9_pc~0); 1840385#L799-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1839889#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1839890#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1840159#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 1841280#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1841081#L818 assume !(1 == ~t10_pc~0); 1839676#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1839677#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1841156#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1841084#L1671 assume !(0 != activate_threads_~tmp___9~0#1); 1841085#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1841133#L837 assume 1 == ~t11_pc~0; 1841134#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1840956#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1841712#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1841048#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 1841049#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1840770#L856 assume !(1 == ~t12_pc~0); 1840771#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1841509#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1839694#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1839695#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 1841482#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1841746#L875 assume 1 == ~t13_pc~0; 1840715#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1840328#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1840329#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1840266#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 1840267#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1841155#L1427 assume !(1 == ~M_E~0); 1841140#L1427-2 assume !(1 == ~T1_E~0); 1840235#L1432-1 assume !(1 == ~T2_E~0); 1840236#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1841378#L1442-1 assume !(1 == ~T4_E~0); 1841379#L1447-1 assume !(1 == ~T5_E~0); 1841209#L1452-1 assume !(1 == ~T6_E~0); 1839814#L1457-1 assume !(1 == ~T7_E~0); 1839815#L1462-1 assume !(1 == ~T8_E~0); 1841417#L1467-1 assume !(1 == ~T9_E~0); 1841442#L1472-1 assume !(1 == ~T10_E~0); 1841443#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1841151#L1482-1 assume !(1 == ~T12_E~0); 1841152#L1487-1 assume !(1 == ~T13_E~0); 1840138#L1492-1 assume !(1 == ~E_M~0); 1840139#L1497-1 assume !(1 == ~E_1~0); 1840502#L1502-1 assume !(1 == ~E_2~0); 1840503#L1507-1 assume !(1 == ~E_3~0); 1840024#L1512-1 assume !(1 == ~E_4~0); 1840025#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1841538#L1522-1 assume !(1 == ~E_6~0); 1840758#L1527-1 assume !(1 == ~E_7~0); 1840759#L1532-1 assume !(1 == ~E_8~0); 1841857#L1537-1 assume !(1 == ~E_9~0); 1840988#L1542-1 assume !(1 == ~E_10~0); 1840789#L1547-1 assume !(1 == ~E_11~0); 1840790#L1552-1 assume !(1 == ~E_12~0); 1839716#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 1839717#L1562-1 assume { :end_inline_reset_delta_events } true; 1840318#L1928-2 [2022-12-13 16:30:56,527 INFO L750 eck$LassoCheckResult]: Loop: 1840318#L1928-2 assume !false; 2026574#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2026565#L1254 assume !false; 2026564#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 2026460#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 2026451#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 2026449#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2026446#L1067 assume !(0 != eval_~tmp~0#1); 2026447#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2028888#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2028886#L1279-3 assume !(0 == ~M_E~0); 2028884#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2028882#L1284-3 assume !(0 == ~T2_E~0); 2028880#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2028878#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2028876#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2028874#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2028872#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2028870#L1314-3 assume !(0 == ~T8_E~0); 2028868#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2028866#L1324-3 assume !(0 == ~T10_E~0); 2028864#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 2028862#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 2028860#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 2028858#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2028456#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2028454#L1354-3 assume !(0 == ~E_2~0); 2028452#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2028443#L1364-3 assume !(0 == ~E_4~0); 2028434#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2028426#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2028420#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2028418#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2028414#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2028411#L1394-3 assume !(0 == ~E_10~0); 2028410#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 2028409#L1404-3 assume !(0 == ~E_12~0); 2028408#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 2028407#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2028406#L628-45 assume !(1 == ~m_pc~0); 2028405#L628-47 is_master_triggered_~__retres1~0#1 := 0; 2028404#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2028403#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2028402#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2028401#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2028400#L647-45 assume !(1 == ~t1_pc~0); 2028399#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 2028398#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2028397#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2028396#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2028395#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2028393#L666-45 assume !(1 == ~t2_pc~0); 2028392#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 2028391#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2028390#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2028389#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2028388#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2028387#L685-45 assume !(1 == ~t3_pc~0); 2028386#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 2028384#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2028382#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2028380#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 2028378#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2028377#L704-45 assume !(1 == ~t4_pc~0); 2028376#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 2028375#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2028374#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2028373#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2028372#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2028371#L723-45 assume !(1 == ~t5_pc~0); 2028370#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 2028368#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2028367#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2028366#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 2028365#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2028364#L742-45 assume !(1 == ~t6_pc~0); 2028363#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 2028362#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2028361#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2028360#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2028359#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2028358#L761-45 assume 1 == ~t7_pc~0; 2028356#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2028355#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2028354#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2028353#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2028352#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2028351#L780-45 assume !(1 == ~t8_pc~0); 2028350#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 2028349#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2028348#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2028347#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2028346#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2028345#L799-45 assume !(1 == ~t9_pc~0); 2028344#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 2028343#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2028342#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 2028341#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2028340#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2028339#L818-45 assume !(1 == ~t10_pc~0); 2028338#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 2028336#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2028334#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 2028332#L1671-45 assume !(0 != activate_threads_~tmp___9~0#1); 2028329#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2028327#L837-45 assume !(1 == ~t11_pc~0); 2028324#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 2028322#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2028320#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 2028318#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2028316#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 2028314#L856-45 assume !(1 == ~t12_pc~0); 2028312#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 2028309#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 2028307#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 2028305#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 2028303#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 2028301#L875-45 assume !(1 == ~t13_pc~0); 2028298#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 2028296#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 2028294#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 2028292#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 2028290#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2028182#L1427-3 assume !(1 == ~M_E~0); 2028180#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2028179#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2028178#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2028176#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2028174#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2028172#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2028170#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2028168#L1462-3 assume !(1 == ~T8_E~0); 2028166#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2028164#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2028162#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 2028160#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 2028158#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 2028156#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2028154#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2028152#L1502-3 assume !(1 == ~E_2~0); 2028150#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2028148#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2028146#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2028144#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2028142#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2028140#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2028138#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2028136#L1542-3 assume !(1 == ~E_10~0); 2028135#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 2028106#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 2028103#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 2028101#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 2027939#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 2027922#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 2027841#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 2027835#L1947 assume !(0 == start_simulation_~tmp~3#1); 2027756#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 2027568#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 2027546#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 2027537#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 2027527#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2027518#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2026640#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 2026638#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 1840318#L1928-2 [2022-12-13 16:30:56,527 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:56,527 INFO L85 PathProgramCache]: Analyzing trace with hash -1665183797, now seen corresponding path program 1 times [2022-12-13 16:30:56,527 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:56,528 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [659896803] [2022-12-13 16:30:56,528 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:56,528 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:56,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:56,595 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:56,595 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:56,595 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [659896803] [2022-12-13 16:30:56,595 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [659896803] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:56,595 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:56,595 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 16:30:56,596 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [327773520] [2022-12-13 16:30:56,596 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:56,596 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:30:56,596 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:30:56,596 INFO L85 PathProgramCache]: Analyzing trace with hash 1503001073, now seen corresponding path program 1 times [2022-12-13 16:30:56,597 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:30:56,597 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [462103887] [2022-12-13 16:30:56,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:30:56,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:30:56,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:30:56,650 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:30:56,650 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:30:56,650 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [462103887] [2022-12-13 16:30:56,651 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [462103887] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:30:56,651 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:30:56,651 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 16:30:56,651 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [123475297] [2022-12-13 16:30:56,651 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:30:56,651 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:30:56,651 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:30:56,652 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 16:30:56,652 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 16:30:56,652 INFO L87 Difference]: Start difference. First operand 310819 states and 434732 transitions. cyclomatic complexity: 123945 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:30:59,123 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:30:59,123 INFO L93 Difference]: Finished difference Result 886242 states and 1233457 transitions. [2022-12-13 16:30:59,123 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 886242 states and 1233457 transitions. [2022-12-13 16:31:02,323 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 876380 [2022-12-13 16:31:04,256 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 886242 states to 886242 states and 1233457 transitions. [2022-12-13 16:31:04,256 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 886242 [2022-12-13 16:31:04,588 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 886242 [2022-12-13 16:31:04,588 INFO L73 IsDeterministic]: Start isDeterministic. Operand 886242 states and 1233457 transitions. [2022-12-13 16:31:04,987 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:31:04,987 INFO L218 hiAutomatonCegarLoop]: Abstraction has 886242 states and 1233457 transitions. [2022-12-13 16:31:05,256 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 886242 states and 1233457 transitions. [2022-12-13 16:31:10,574 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 886242 to 873698. [2022-12-13 16:31:10,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 873698 states, 873698 states have (on average 1.3929584364391356) internal successors, (1217025), 873697 states have internal predecessors, (1217025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:31:12,966 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 873698 states to 873698 states and 1217025 transitions. [2022-12-13 16:31:12,967 INFO L240 hiAutomatonCegarLoop]: Abstraction has 873698 states and 1217025 transitions. [2022-12-13 16:31:12,967 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 16:31:12,968 INFO L428 stractBuchiCegarLoop]: Abstraction has 873698 states and 1217025 transitions. [2022-12-13 16:31:12,968 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2022-12-13 16:31:12,968 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 873698 states and 1217025 transitions. [2022-12-13 16:31:14,816 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 871628 [2022-12-13 16:31:14,816 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 16:31:14,816 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 16:31:14,818 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:31:14,818 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 16:31:14,819 INFO L748 eck$LassoCheckResult]: Stem: 3037022#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 3037023#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 3038061#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3038062#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3039154#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 3037607#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3037608#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3037681#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3037682#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3038177#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3038178#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3037645#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3037443#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3037444#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3037939#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3037940#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 3037804#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 3037805#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 3037418#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3037419#L1279 assume !(0 == ~M_E~0); 3038956#L1279-2 assume !(0 == ~T1_E~0); 3037043#L1284-1 assume !(0 == ~T2_E~0); 3037044#L1289-1 assume !(0 == ~T3_E~0); 3037799#L1294-1 assume !(0 == ~T4_E~0); 3037800#L1299-1 assume !(0 == ~T5_E~0); 3037815#L1304-1 assume !(0 == ~T6_E~0); 3039150#L1309-1 assume !(0 == ~T7_E~0); 3039157#L1314-1 assume !(0 == ~T8_E~0); 3036969#L1319-1 assume !(0 == ~T9_E~0); 3036970#L1324-1 assume !(0 == ~T10_E~0); 3037145#L1329-1 assume !(0 == ~T11_E~0); 3037146#L1334-1 assume !(0 == ~T12_E~0); 3038807#L1339-1 assume !(0 == ~T13_E~0); 3038938#L1344-1 assume !(0 == ~E_M~0); 3038939#L1349-1 assume !(0 == ~E_1~0); 3038015#L1354-1 assume !(0 == ~E_2~0); 3038016#L1359-1 assume !(0 == ~E_3~0); 3038528#L1364-1 assume !(0 == ~E_4~0); 3037266#L1369-1 assume !(0 == ~E_5~0); 3037267#L1374-1 assume !(0 == ~E_6~0); 3038022#L1379-1 assume !(0 == ~E_7~0); 3038023#L1384-1 assume !(0 == ~E_8~0); 3038111#L1389-1 assume !(0 == ~E_9~0); 3038837#L1394-1 assume !(0 == ~E_10~0); 3038838#L1399-1 assume !(0 == ~E_11~0); 3039013#L1404-1 assume !(0 == ~E_12~0); 3037365#L1409-1 assume !(0 == ~E_13~0); 3037366#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3039000#L628 assume !(1 == ~m_pc~0); 3038844#L628-2 is_master_triggered_~__retres1~0#1 := 0; 3038310#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3037881#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3037882#L1591 assume !(0 != activate_threads_~tmp~1#1); 3039027#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3037858#L647 assume !(1 == ~t1_pc~0); 3037859#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3037918#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3037919#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3038475#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 3038917#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3038918#L666 assume !(1 == ~t2_pc~0); 3037042#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3037205#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3037186#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3037187#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 3038243#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3038244#L685 assume !(1 == ~t3_pc~0); 3038358#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3038438#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3039047#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3038070#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 3038071#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3037490#L704 assume !(1 == ~t4_pc~0); 3037491#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3038087#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3036835#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3036836#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 3037916#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3037917#L723 assume !(1 == ~t5_pc~0); 3038066#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3038323#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3038519#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3038217#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 3038218#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3037253#L742 assume !(1 == ~t6_pc~0); 3037254#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3037407#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3037177#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3036939#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 3036940#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3037329#L761 assume !(1 == ~t7_pc~0); 3037330#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3037201#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3037202#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3038074#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 3038075#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3036962#L780 assume !(1 == ~t8_pc~0); 3036963#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3037244#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3037245#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3038031#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 3038032#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3038166#L799 assume !(1 == ~t9_pc~0); 3037464#L799-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3036964#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3036965#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3037236#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 3038410#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3038196#L818 assume !(1 == ~t10_pc~0); 3036748#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3036749#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3038279#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3038199#L1671 assume !(0 != activate_threads_~tmp___9~0#1); 3038200#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3038251#L837 assume !(1 == ~t11_pc~0); 3038058#L837-2 is_transmit11_triggered_~__retres1~11#1 := 0; 3038059#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3038924#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3038159#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 3038160#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 3037868#L856 assume !(1 == ~t12_pc~0); 3037869#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 3038683#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3036766#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3036767#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 3038642#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 3038962#L875 assume 1 == ~t13_pc~0; 3037812#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 3037408#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 3037409#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 3037347#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 3037348#L1695-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3038278#L1427 assume !(1 == ~M_E~0); 3038259#L1427-2 assume !(1 == ~T1_E~0); 3037315#L1432-1 assume !(1 == ~T2_E~0); 3037316#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3038535#L1442-1 assume !(1 == ~T4_E~0); 3038536#L1447-1 assume !(1 == ~T5_E~0); 3038335#L1452-1 assume !(1 == ~T6_E~0); 3036886#L1457-1 assume !(1 == ~T7_E~0); 3036887#L1462-1 assume !(1 == ~T8_E~0); 3038572#L1467-1 assume !(1 == ~T9_E~0); 3038599#L1472-1 assume !(1 == ~T10_E~0); 3038600#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3038274#L1482-1 assume !(1 == ~T12_E~0); 3038275#L1487-1 assume !(1 == ~T13_E~0); 3037214#L1492-1 assume !(1 == ~E_M~0); 3037215#L1497-1 assume !(1 == ~E_1~0); 3037587#L1502-1 assume !(1 == ~E_2~0); 3037588#L1507-1 assume !(1 == ~E_3~0); 3037098#L1512-1 assume !(1 == ~E_4~0); 3037099#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 3038712#L1522-1 assume !(1 == ~E_6~0); 3037855#L1527-1 assume !(1 == ~E_7~0); 3037856#L1532-1 assume !(1 == ~E_8~0); 3039103#L1537-1 assume !(1 == ~E_9~0); 3038094#L1542-1 assume !(1 == ~E_10~0); 3037889#L1547-1 assume !(1 == ~E_11~0); 3037890#L1552-1 assume !(1 == ~E_12~0); 3036788#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 3036789#L1562-1 assume { :end_inline_reset_delta_events } true; 3037397#L1928-2 [2022-12-13 16:31:14,819 INFO L750 eck$LassoCheckResult]: Loop: 3037397#L1928-2 assume !false; 3477792#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3477787#L1254 assume !false; 3477786#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 3477779#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 3477771#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 3477769#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3477766#L1067 assume !(0 != eval_~tmp~0#1); 3477764#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3477762#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3477760#L1279-3 assume !(0 == ~M_E~0); 3477758#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3477756#L1284-3 assume !(0 == ~T2_E~0); 3477754#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3477752#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3477750#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3477748#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3477746#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3477743#L1314-3 assume !(0 == ~T8_E~0); 3477741#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3477739#L1324-3 assume !(0 == ~T10_E~0); 3477737#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 3477735#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 3477733#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 3477729#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3477727#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3477725#L1354-3 assume !(0 == ~E_2~0); 3477723#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3477720#L1364-3 assume !(0 == ~E_4~0); 3477718#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3477716#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3477714#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3477712#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3477710#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3477708#L1394-3 assume !(0 == ~E_10~0); 3477706#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3477704#L1404-3 assume !(0 == ~E_12~0); 3477701#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 3477699#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3477697#L628-45 assume !(1 == ~m_pc~0); 3477695#L628-47 is_master_triggered_~__retres1~0#1 := 0; 3477693#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3477691#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3477690#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3477688#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3477686#L647-45 assume !(1 == ~t1_pc~0); 3477684#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 3477682#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3477680#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3477677#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3477675#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3477671#L666-45 assume !(1 == ~t2_pc~0); 3477669#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 3477667#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3477665#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3477663#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3477661#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3477659#L685-45 assume !(1 == ~t3_pc~0); 3477655#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 3477653#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3477652#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3477650#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 3477647#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3477645#L704-45 assume !(1 == ~t4_pc~0); 3477643#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 3477642#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3477638#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3477636#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3477634#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3477632#L723-45 assume !(1 == ~t5_pc~0); 3477629#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 3477626#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3477624#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3477622#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 3477620#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3477618#L742-45 assume !(1 == ~t6_pc~0); 3477616#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 3477614#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3477612#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3477609#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3477607#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3477605#L761-45 assume !(1 == ~t7_pc~0); 3477603#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 3477600#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3477598#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3477595#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3477593#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3477591#L780-45 assume !(1 == ~t8_pc~0); 3477590#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 3477589#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3477588#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3477587#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3477586#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3477584#L799-45 assume !(1 == ~t9_pc~0); 3477583#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 3477582#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3477581#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3477580#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3477579#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3477578#L818-45 assume !(1 == ~t10_pc~0); 3477574#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 3477573#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3477572#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3477570#L1671-45 assume !(0 != activate_threads_~tmp___9~0#1); 3477568#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3477567#L837-45 assume !(1 == ~t11_pc~0); 3477566#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 3477565#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3477564#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3477563#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3477562#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 3477561#L856-45 assume 1 == ~t12_pc~0; 3477559#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 3477558#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3477557#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3477556#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 3477555#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 3477554#L875-45 assume 1 == ~t13_pc~0; 3477553#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 3477550#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 3477548#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 3477546#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 3477544#L1695-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3477542#L1427-3 assume !(1 == ~M_E~0); 3476584#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3477539#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3477537#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3477535#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3477533#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3477531#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3477529#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3477527#L1462-3 assume !(1 == ~T8_E~0); 3477525#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3477523#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3477521#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3477519#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 3477517#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 3477515#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3477513#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3477511#L1502-3 assume !(1 == ~E_2~0); 3477509#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3477507#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3477505#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3477503#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3477501#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3477499#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3477497#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3477495#L1542-3 assume !(1 == ~E_10~0); 3477493#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 3477491#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 3477489#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 3477487#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 3477481#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 3477467#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 3477465#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 3477462#L1947 assume !(0 == start_simulation_~tmp~3#1); 3477463#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 3477827#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 3477811#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 3477809#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 3477807#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3477806#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3477801#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 3477797#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 3037397#L1928-2 [2022-12-13 16:31:14,819 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:31:14,820 INFO L85 PathProgramCache]: Analyzing trace with hash 736341324, now seen corresponding path program 1 times [2022-12-13 16:31:14,820 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:31:14,820 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [796304838] [2022-12-13 16:31:14,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:31:14,820 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:31:14,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:31:14,871 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:31:14,871 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:31:14,871 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [796304838] [2022-12-13 16:31:14,871 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [796304838] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:31:14,871 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:31:14,872 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 16:31:14,872 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [805134646] [2022-12-13 16:31:14,872 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:31:14,872 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 16:31:14,873 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 16:31:14,873 INFO L85 PathProgramCache]: Analyzing trace with hash -2024893264, now seen corresponding path program 1 times [2022-12-13 16:31:14,873 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 16:31:14,873 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1343385636] [2022-12-13 16:31:14,873 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 16:31:14,873 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 16:31:14,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 16:31:14,930 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 16:31:14,930 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 16:31:14,930 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1343385636] [2022-12-13 16:31:14,930 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1343385636] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 16:31:14,930 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 16:31:14,931 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 16:31:14,931 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [13187876] [2022-12-13 16:31:14,931 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 16:31:14,931 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 16:31:14,931 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 16:31:14,932 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 16:31:14,932 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 16:31:14,932 INFO L87 Difference]: Start difference. First operand 873698 states and 1217025 transitions. cyclomatic complexity: 343391 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:31:19,506 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 16:31:19,506 INFO L93 Difference]: Finished difference Result 1674281 states and 2326430 transitions. [2022-12-13 16:31:19,506 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1674281 states and 2326430 transitions. [2022-12-13 16:31:26,035 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 1669020 [2022-12-13 16:31:29,287 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1674281 states to 1674281 states and 2326430 transitions. [2022-12-13 16:31:29,287 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1674281 [2022-12-13 16:31:30,082 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1674281 [2022-12-13 16:31:30,082 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1674281 states and 2326430 transitions. [2022-12-13 16:31:30,521 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 16:31:30,522 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1674281 states and 2326430 transitions. [2022-12-13 16:31:31,184 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1674281 states and 2326430 transitions. [2022-12-13 16:31:41,961 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1674281 to 1672985. [2022-12-13 16:31:42,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1672985 states, 1672985 states have (on average 1.3898116241329121) internal successors, (2325134), 1672984 states have internal predecessors, (2325134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 16:31:46,945 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1672985 states to 1672985 states and 2325134 transitions. [2022-12-13 16:31:46,945 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1672985 states and 2325134 transitions. [2022-12-13 16:31:46,946 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 16:31:46,946 INFO L428 stractBuchiCegarLoop]: Abstraction has 1672985 states and 2325134 transitions. [2022-12-13 16:31:46,946 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2022-12-13 16:31:46,946 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1672985 states and 2325134 transitions.