./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.14.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_22eafda1-2df3-4642-8bea-c4d332d694ac/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_22eafda1-2df3-4642-8bea-c4d332d694ac/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_22eafda1-2df3-4642-8bea-c4d332d694ac/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_22eafda1-2df3-4642-8bea-c4d332d694ac/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.14.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_22eafda1-2df3-4642-8bea-c4d332d694ac/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_22eafda1-2df3-4642-8bea-c4d332d694ac/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 78a96934dff25285973ef889167a345947d7e73ab8a2ec405d96bd61e690530f --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 15:11:51,768 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 15:11:51,769 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 15:11:51,782 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 15:11:51,782 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 15:11:51,783 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 15:11:51,785 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 15:11:51,786 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 15:11:51,787 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 15:11:51,787 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 15:11:51,788 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 15:11:51,788 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 15:11:51,789 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 15:11:51,789 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 15:11:51,790 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 15:11:51,791 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 15:11:51,791 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 15:11:51,792 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 15:11:51,793 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 15:11:51,794 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 15:11:51,794 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 15:11:51,795 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 15:11:51,796 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 15:11:51,797 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 15:11:51,798 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 15:11:51,799 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 15:11:51,799 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 15:11:51,799 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 15:11:51,800 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 15:11:51,800 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 15:11:51,800 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 15:11:51,801 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 15:11:51,801 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 15:11:51,802 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 15:11:51,802 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 15:11:51,803 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 15:11:51,803 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 15:11:51,804 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 15:11:51,804 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 15:11:51,804 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 15:11:51,805 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 15:11:51,805 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_22eafda1-2df3-4642-8bea-c4d332d694ac/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 15:11:51,820 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 15:11:51,820 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 15:11:51,820 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 15:11:51,820 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 15:11:51,821 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 15:11:51,821 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 15:11:51,821 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 15:11:51,822 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 15:11:51,822 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 15:11:51,826 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 15:11:51,827 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 15:11:51,827 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 15:11:51,827 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 15:11:51,827 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 15:11:51,827 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 15:11:51,828 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 15:11:51,828 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 15:11:51,828 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 15:11:51,828 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 15:11:51,828 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 15:11:51,828 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 15:11:51,829 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 15:11:51,829 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 15:11:51,829 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 15:11:51,829 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 15:11:51,829 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 15:11:51,830 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 15:11:51,830 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 15:11:51,830 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 15:11:51,830 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 15:11:51,831 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 15:11:51,831 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 15:11:51,832 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_22eafda1-2df3-4642-8bea-c4d332d694ac/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_22eafda1-2df3-4642-8bea-c4d332d694ac/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 78a96934dff25285973ef889167a345947d7e73ab8a2ec405d96bd61e690530f [2022-12-13 15:11:52,045 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 15:11:52,060 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 15:11:52,062 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 15:11:52,063 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 15:11:52,063 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 15:11:52,064 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_22eafda1-2df3-4642-8bea-c4d332d694ac/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/token_ring.14.cil.c [2022-12-13 15:11:54,671 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 15:11:54,851 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 15:11:54,852 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_22eafda1-2df3-4642-8bea-c4d332d694ac/sv-benchmarks/c/systemc/token_ring.14.cil.c [2022-12-13 15:11:54,864 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_22eafda1-2df3-4642-8bea-c4d332d694ac/bin/uautomizer-uyxdKDjOR8/data/e75c05282/105ae9302a3f4509b5029c43a4c3f499/FLAG1a6ee2cd1 [2022-12-13 15:11:55,227 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_22eafda1-2df3-4642-8bea-c4d332d694ac/bin/uautomizer-uyxdKDjOR8/data/e75c05282/105ae9302a3f4509b5029c43a4c3f499 [2022-12-13 15:11:55,230 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 15:11:55,231 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 15:11:55,232 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 15:11:55,233 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 15:11:55,235 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 15:11:55,236 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 03:11:55" (1/1) ... [2022-12-13 15:11:55,236 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3ff53be5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:11:55, skipping insertion in model container [2022-12-13 15:11:55,237 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 03:11:55" (1/1) ... [2022-12-13 15:11:55,242 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 15:11:55,281 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 15:11:55,389 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_22eafda1-2df3-4642-8bea-c4d332d694ac/sv-benchmarks/c/systemc/token_ring.14.cil.c[669,682] [2022-12-13 15:11:55,501 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 15:11:55,515 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 15:11:55,523 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_22eafda1-2df3-4642-8bea-c4d332d694ac/sv-benchmarks/c/systemc/token_ring.14.cil.c[669,682] [2022-12-13 15:11:55,582 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 15:11:55,599 INFO L208 MainTranslator]: Completed translation [2022-12-13 15:11:55,599 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:11:55 WrapperNode [2022-12-13 15:11:55,600 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 15:11:55,600 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 15:11:55,601 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 15:11:55,601 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 15:11:55,605 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:11:55" (1/1) ... [2022-12-13 15:11:55,617 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:11:55" (1/1) ... [2022-12-13 15:11:55,699 INFO L138 Inliner]: procedures = 52, calls = 68, calls flagged for inlining = 63, calls inlined = 270, statements flattened = 4144 [2022-12-13 15:11:55,700 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 15:11:55,700 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 15:11:55,700 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 15:11:55,700 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 15:11:55,709 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:11:55" (1/1) ... [2022-12-13 15:11:55,709 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:11:55" (1/1) ... [2022-12-13 15:11:55,718 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:11:55" (1/1) ... [2022-12-13 15:11:55,719 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:11:55" (1/1) ... [2022-12-13 15:11:55,773 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:11:55" (1/1) ... [2022-12-13 15:11:55,803 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:11:55" (1/1) ... [2022-12-13 15:11:55,807 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:11:55" (1/1) ... [2022-12-13 15:11:55,814 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:11:55" (1/1) ... [2022-12-13 15:11:55,823 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 15:11:55,823 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 15:11:55,823 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 15:11:55,823 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 15:11:55,824 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:11:55" (1/1) ... [2022-12-13 15:11:55,830 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 15:11:55,840 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_22eafda1-2df3-4642-8bea-c4d332d694ac/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 15:11:55,851 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_22eafda1-2df3-4642-8bea-c4d332d694ac/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 15:11:55,853 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_22eafda1-2df3-4642-8bea-c4d332d694ac/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 15:11:55,888 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 15:11:55,888 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 15:11:55,888 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 15:11:55,889 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 15:11:55,986 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 15:11:55,988 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 15:11:57,513 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 15:11:57,535 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 15:11:57,535 INFO L300 CfgBuilder]: Removed 15 assume(true) statements. [2022-12-13 15:11:57,539 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 03:11:57 BoogieIcfgContainer [2022-12-13 15:11:57,539 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 15:11:57,540 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 15:11:57,540 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 15:11:57,543 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 15:11:57,543 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 15:11:57,544 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 03:11:55" (1/3) ... [2022-12-13 15:11:57,544 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7791a34d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 03:11:57, skipping insertion in model container [2022-12-13 15:11:57,544 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 15:11:57,545 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:11:55" (2/3) ... [2022-12-13 15:11:57,545 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7791a34d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 03:11:57, skipping insertion in model container [2022-12-13 15:11:57,545 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 15:11:57,545 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 03:11:57" (3/3) ... [2022-12-13 15:11:57,547 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.14.cil.c [2022-12-13 15:11:57,613 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 15:11:57,613 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 15:11:57,613 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 15:11:57,613 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 15:11:57,613 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 15:11:57,613 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 15:11:57,613 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 15:11:57,613 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 15:11:57,622 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1796 states, 1795 states have (on average 1.4991643454038996) internal successors, (2691), 1795 states have internal predecessors, (2691), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:57,689 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1629 [2022-12-13 15:11:57,689 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:11:57,689 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:11:57,703 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:57,703 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:57,703 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 15:11:57,706 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1796 states, 1795 states have (on average 1.4991643454038996) internal successors, (2691), 1795 states have internal predecessors, (2691), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:57,719 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1629 [2022-12-13 15:11:57,719 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:11:57,719 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:11:57,723 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:57,723 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:57,731 INFO L748 eck$LassoCheckResult]: Stem: 134#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1701#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 644#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1696#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1353#L848true assume !(1 == ~m_i~0);~m_st~0 := 2; 1465#L848-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 425#L853-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 301#L858-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2#L863-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 740#L868-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 830#L873-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1597#L878-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1563#L883-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 1648#L888-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 377#L893-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 763#L898-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 1773#L903-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 690#L908-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 400#L1201true assume !(0 == ~M_E~0); 1176#L1201-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1594#L1206-1true assume !(0 == ~T2_E~0); 1148#L1211-1true assume !(0 == ~T3_E~0); 1296#L1216-1true assume !(0 == ~T4_E~0); 289#L1221-1true assume !(0 == ~T5_E~0); 1240#L1226-1true assume !(0 == ~T6_E~0); 98#L1231-1true assume !(0 == ~T7_E~0); 1376#L1236-1true assume !(0 == ~T8_E~0); 1221#L1241-1true assume 0 == ~T9_E~0;~T9_E~0 := 1; 313#L1246-1true assume !(0 == ~T10_E~0); 398#L1251-1true assume !(0 == ~T11_E~0); 865#L1256-1true assume !(0 == ~T12_E~0); 6#L1261-1true assume !(0 == ~E_M~0); 1567#L1266-1true assume !(0 == ~E_1~0); 1506#L1271-1true assume !(0 == ~E_2~0); 818#L1276-1true assume !(0 == ~E_3~0); 1501#L1281-1true assume 0 == ~E_4~0;~E_4~0 := 1; 775#L1286-1true assume !(0 == ~E_5~0); 231#L1291-1true assume !(0 == ~E_6~0); 1592#L1296-1true assume !(0 == ~E_7~0); 601#L1301-1true assume !(0 == ~E_8~0); 1090#L1306-1true assume !(0 == ~E_9~0); 1064#L1311-1true assume !(0 == ~E_10~0); 207#L1316-1true assume !(0 == ~E_11~0); 1450#L1321-1true assume 0 == ~E_12~0;~E_12~0 := 1; 615#L1326-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 732#L593true assume 1 == ~m_pc~0; 851#L594true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1464#L604true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 534#is_master_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 783#L1492true assume !(0 != activate_threads_~tmp~1#1); 1223#L1492-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1114#L612true assume !(1 == ~t1_pc~0); 1656#L612-2true is_transmit1_triggered_~__retres1~1#1 := 0; 1532#L623true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 911#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 148#L1500true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 432#L1500-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 385#L631true assume 1 == ~t2_pc~0; 345#L632true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41#L642true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 214#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 513#L1508true assume !(0 != activate_threads_~tmp___1~0#1); 1301#L1508-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 183#L650true assume !(1 == ~t3_pc~0); 949#L650-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1213#L661true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 890#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22#L1516true assume !(0 != activate_threads_~tmp___2~0#1); 959#L1516-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 759#L669true assume 1 == ~t4_pc~0; 1265#L670true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1781#L680true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 114#L1524true assume !(0 != activate_threads_~tmp___3~0#1); 238#L1524-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 975#L688true assume !(1 == ~t5_pc~0); 124#L688-2true is_transmit5_triggered_~__retres1~5#1 := 0; 1463#L699true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1438#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 658#L1532true assume !(0 != activate_threads_~tmp___4~0#1); 769#L1532-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1286#L707true assume 1 == ~t6_pc~0; 1333#L708true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 492#L718true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 208#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1359#L1540true assume !(0 != activate_threads_~tmp___5~0#1); 719#L1540-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 399#L726true assume 1 == ~t7_pc~0; 338#L727true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 901#L737true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1718#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1297#L1548true assume !(0 != activate_threads_~tmp___6~0#1); 55#L1548-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 286#L745true assume !(1 == ~t8_pc~0); 1100#L745-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1188#L756true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1381#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 539#L1556true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1012#L1556-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1786#L764true assume 1 == ~t9_pc~0; 396#L765true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 786#L775true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 249#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1425#L1564true assume !(0 != activate_threads_~tmp___8~0#1); 67#L1564-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1378#L783true assume !(1 == ~t10_pc~0); 92#L783-2true is_transmit10_triggered_~__retres1~10#1 := 0; 186#L794true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1204#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 372#L1572true assume !(0 != activate_threads_~tmp___9~0#1); 1164#L1572-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1268#L802true assume 1 == ~t11_pc~0; 1135#L803true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39#L813true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1295#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 290#L1580true assume !(0 != activate_threads_~tmp___10~0#1); 356#L1580-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 522#L821true assume !(1 == ~t12_pc~0); 592#L821-2true is_transmit12_triggered_~__retres1~12#1 := 0; 1323#L832true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 43#is_transmit12_triggered_returnLabel#1true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1239#L1588true assume !(0 != activate_threads_~tmp___11~0#1); 1244#L1588-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 792#L1339true assume !(1 == ~M_E~0); 1447#L1339-2true assume !(1 == ~T1_E~0); 1306#L1344-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1720#L1349-1true assume !(1 == ~T3_E~0); 611#L1354-1true assume !(1 == ~T4_E~0); 982#L1359-1true assume !(1 == ~T5_E~0); 1542#L1364-1true assume !(1 == ~T6_E~0); 265#L1369-1true assume !(1 == ~T7_E~0); 952#L1374-1true assume !(1 == ~T8_E~0); 613#L1379-1true assume !(1 == ~T9_E~0); 687#L1384-1true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1760#L1389-1true assume !(1 == ~T11_E~0); 1228#L1394-1true assume !(1 == ~T12_E~0); 1623#L1399-1true assume !(1 == ~E_M~0); 1428#L1404-1true assume !(1 == ~E_1~0); 316#L1409-1true assume !(1 == ~E_2~0); 1395#L1414-1true assume !(1 == ~E_3~0); 852#L1419-1true assume !(1 == ~E_4~0); 119#L1424-1true assume 1 == ~E_5~0;~E_5~0 := 2; 619#L1429-1true assume !(1 == ~E_6~0); 1256#L1434-1true assume !(1 == ~E_7~0); 1599#L1439-1true assume !(1 == ~E_8~0); 141#L1444-1true assume !(1 == ~E_9~0); 806#L1449-1true assume !(1 == ~E_10~0); 348#L1454-1true assume !(1 == ~E_11~0); 1294#L1459-1true assume !(1 == ~E_12~0); 717#L1464-1true assume { :end_inline_reset_delta_events } true; 482#L1810-2true [2022-12-13 15:11:57,733 INFO L750 eck$LassoCheckResult]: Loop: 482#L1810-2true assume !false; 1330#L1811true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1770#L1176true assume false; 486#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 317#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1044#L1201-3true assume 0 == ~M_E~0;~M_E~0 := 1; 810#L1201-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1596#L1206-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 715#L1211-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 181#L1216-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 460#L1221-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1010#L1226-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 224#L1231-3true assume !(0 == ~T7_E~0); 364#L1236-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1771#L1241-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1329#L1246-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1139#L1251-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 795#L1256-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 191#L1261-3true assume 0 == ~E_M~0;~E_M~0 := 1; 507#L1266-3true assume 0 == ~E_1~0;~E_1~0 := 1; 220#L1271-3true assume !(0 == ~E_2~0); 480#L1276-3true assume 0 == ~E_3~0;~E_3~0 := 1; 445#L1281-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1198#L1286-3true assume 0 == ~E_5~0;~E_5~0 := 1; 849#L1291-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1609#L1296-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1533#L1301-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1415#L1306-3true assume 0 == ~E_9~0;~E_9~0 := 1; 518#L1311-3true assume !(0 == ~E_10~0); 152#L1316-3true assume 0 == ~E_11~0;~E_11~0 := 1; 192#L1321-3true assume 0 == ~E_12~0;~E_12~0 := 1; 591#L1326-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1208#L593-42true assume !(1 == ~m_pc~0); 721#L593-44true is_master_triggered_~__retres1~0#1 := 0; 1755#L604-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 378#is_master_triggered_returnLabel#15true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1717#L1492-42true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 101#L1492-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 677#L612-42true assume 1 == ~t1_pc~0; 1725#L613-14true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1580#L623-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1610#is_transmit1_triggered_returnLabel#15true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 147#L1500-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1751#L1500-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 565#L631-42true assume 1 == ~t2_pc~0; 34#L632-14true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 554#L642-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 558#is_transmit2_triggered_returnLabel#15true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 479#L1508-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1630#L1508-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 233#L650-42true assume 1 == ~t3_pc~0; 19#L651-14true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1713#L661-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 878#is_transmit3_triggered_returnLabel#15true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 344#L1516-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1363#L1516-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1264#L669-42true assume !(1 == ~t4_pc~0); 18#L669-44true is_transmit4_triggered_~__retres1~4#1 := 0; 987#L680-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 961#is_transmit4_triggered_returnLabel#15true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 861#L1524-42true assume !(0 != activate_threads_~tmp___3~0#1); 768#L1524-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 848#L688-42true assume !(1 == ~t5_pc~0); 1092#L688-44true is_transmit5_triggered_~__retres1~5#1 := 0; 1342#L699-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 604#is_transmit5_triggered_returnLabel#15true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 113#L1532-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1422#L1532-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31#L707-42true assume 1 == ~t6_pc~0; 1432#L708-14true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1690#L718-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 188#is_transmit6_triggered_returnLabel#15true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1285#L1540-42true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 743#L1540-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1020#L726-42true assume !(1 == ~t7_pc~0); 1785#L726-44true is_transmit7_triggered_~__retres1~7#1 := 0; 1061#L737-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 621#is_transmit7_triggered_returnLabel#15true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 520#L1548-42true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 595#L1548-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1184#L745-42true assume !(1 == ~t8_pc~0); 808#L745-44true is_transmit8_triggered_~__retres1~8#1 := 0; 1419#L756-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 760#is_transmit8_triggered_returnLabel#15true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26#L1556-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 417#L1556-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 504#L764-42true assume 1 == ~t9_pc~0; 1657#L765-14true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 781#L775-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1636#is_transmit9_triggered_returnLabel#15true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 158#L1564-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 187#L1564-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 237#L783-42true assume 1 == ~t10_pc~0; 7#L784-14true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 308#L794-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 755#is_transmit10_triggered_returnLabel#15true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1535#L1572-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1513#L1572-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 947#L802-42true assume 1 == ~t11_pc~0; 269#L803-14true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 70#L813-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1350#is_transmit11_triggered_returnLabel#15true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46#L1580-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1550#L1580-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 790#L821-42true assume 1 == ~t12_pc~0; 1688#L822-14true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 997#L832-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 589#is_transmit12_triggered_returnLabel#15true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1152#L1588-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 545#L1588-44true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 538#L1339-3true assume !(1 == ~M_E~0); 660#L1339-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 798#L1344-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 758#L1349-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 336#L1354-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 765#L1359-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1605#L1364-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1497#L1369-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1254#L1374-3true assume !(1 == ~T8_E~0); 235#L1379-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1143#L1384-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 335#L1389-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 472#L1394-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1704#L1399-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1274#L1404-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1220#L1409-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1328#L1414-3true assume !(1 == ~E_3~0); 1347#L1419-3true assume 1 == ~E_4~0;~E_4~0 := 2; 950#L1424-3true assume 1 == ~E_5~0;~E_5~0 := 2; 168#L1429-3true assume 1 == ~E_6~0;~E_6~0 := 2; 764#L1434-3true assume 1 == ~E_7~0;~E_7~0 := 2; 917#L1439-3true assume 1 == ~E_8~0;~E_8~0 := 2; 135#L1444-3true assume 1 == ~E_9~0;~E_9~0 := 2; 196#L1449-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1414#L1454-3true assume !(1 == ~E_11~0); 761#L1459-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1769#L1464-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 493#L921-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1724#L988-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 184#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1449#L1829true assume !(0 == start_simulation_~tmp~3#1); 81#L1829-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1027#L921-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 541#L988-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 776#L1784true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1544#L1791true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1226#stop_simulation_returnLabel#1true start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 213#L1842true assume !(0 != start_simulation_~tmp___0~1#1); 482#L1810-2true [2022-12-13 15:11:57,740 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:57,740 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 1 times [2022-12-13 15:11:57,749 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:57,750 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1962706082] [2022-12-13 15:11:57,750 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:57,751 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:57,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:58,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:58,016 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:58,016 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1962706082] [2022-12-13 15:11:58,017 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1962706082] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:58,017 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:58,017 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:11:58,018 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2043079762] [2022-12-13 15:11:58,019 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:58,022 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:11:58,023 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:58,023 INFO L85 PathProgramCache]: Analyzing trace with hash -666770825, now seen corresponding path program 1 times [2022-12-13 15:11:58,024 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:58,024 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1889853608] [2022-12-13 15:11:58,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:58,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:58,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:58,099 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:58,099 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:58,099 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1889853608] [2022-12-13 15:11:58,099 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1889853608] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:58,100 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:58,100 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 15:11:58,100 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1210993155] [2022-12-13 15:11:58,100 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:58,101 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:11:58,102 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:11:58,134 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-12-13 15:11:58,135 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-12-13 15:11:58,140 INFO L87 Difference]: Start difference. First operand has 1796 states, 1795 states have (on average 1.4991643454038996) internal successors, (2691), 1795 states have internal predecessors, (2691), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 74.5) internal successors, (149), 2 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:58,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:11:58,207 INFO L93 Difference]: Finished difference Result 1794 states and 2657 transitions. [2022-12-13 15:11:58,209 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1794 states and 2657 transitions. [2022-12-13 15:11:58,224 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-12-13 15:11:58,239 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1794 states to 1788 states and 2651 transitions. [2022-12-13 15:11:58,240 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-12-13 15:11:58,243 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-12-13 15:11:58,244 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2651 transitions. [2022-12-13 15:11:58,251 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:11:58,251 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2651 transitions. [2022-12-13 15:11:58,275 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2651 transitions. [2022-12-13 15:11:58,325 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-12-13 15:11:58,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.482662192393736) internal successors, (2651), 1787 states have internal predecessors, (2651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:58,332 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2651 transitions. [2022-12-13 15:11:58,333 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2651 transitions. [2022-12-13 15:11:58,334 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-12-13 15:11:58,336 INFO L428 stractBuchiCegarLoop]: Abstraction has 1788 states and 2651 transitions. [2022-12-13 15:11:58,336 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 15:11:58,336 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2651 transitions. [2022-12-13 15:11:58,342 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-12-13 15:11:58,342 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:11:58,342 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:11:58,344 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:58,344 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:58,345 INFO L748 eck$LassoCheckResult]: Stem: 3885#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 3886#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 4708#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4709#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5305#L848 assume !(1 == ~m_i~0);~m_st~0 := 2; 5306#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4392#L853-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4188#L858-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3599#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3600#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4820#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4926#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5368#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5369#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4318#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4319#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4848#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4771#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4354#L1201 assume !(0 == ~M_E~0); 4355#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5215#L1206-1 assume !(0 == ~T2_E~0); 5198#L1211-1 assume !(0 == ~T3_E~0); 5199#L1216-1 assume !(0 == ~T4_E~0); 4169#L1221-1 assume !(0 == ~T5_E~0); 4170#L1226-1 assume !(0 == ~T6_E~0); 3811#L1231-1 assume !(0 == ~T7_E~0); 3812#L1236-1 assume !(0 == ~T8_E~0); 5239#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4207#L1246-1 assume !(0 == ~T10_E~0); 4208#L1251-1 assume !(0 == ~T11_E~0); 4352#L1256-1 assume !(0 == ~T12_E~0); 3608#L1261-1 assume !(0 == ~E_M~0); 3609#L1266-1 assume !(0 == ~E_1~0); 5353#L1271-1 assume !(0 == ~E_2~0); 4910#L1276-1 assume !(0 == ~E_3~0); 4911#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4860#L1286-1 assume !(0 == ~E_5~0); 4066#L1291-1 assume !(0 == ~E_6~0); 4067#L1296-1 assume !(0 == ~E_7~0); 4644#L1301-1 assume !(0 == ~E_8~0); 4645#L1306-1 assume !(0 == ~E_9~0); 5132#L1311-1 assume !(0 == ~E_10~0); 4020#L1316-1 assume !(0 == ~E_11~0); 4021#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 4663#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4664#L593 assume 1 == ~m_pc~0; 4813#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3910#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4555#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4556#L1492 assume !(0 != activate_threads_~tmp~1#1); 4870#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5167#L612 assume !(1 == ~t1_pc~0); 5168#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5301#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5006#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3913#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3914#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4334#L631 assume 1 == ~t2_pc~0; 4265#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3689#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3690#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4034#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 4520#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3981#L650 assume !(1 == ~t3_pc~0); 3982#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4686#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4986#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3646#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 3647#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4841#L669 assume 1 == ~t4_pc~0; 4842#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5206#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3727#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3728#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 3848#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4076#L688 assume !(1 == ~t5_pc~0); 3867#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3868#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5334#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4728#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 4729#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4855#L707 assume 1 == ~t6_pc~0; 5272#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4489#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4022#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4023#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 4799#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4353#L726 assume 1 == ~t7_pc~0; 4253#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3950#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4997#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5276#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 3717#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3718#L745 assume !(1 == ~t8_pc~0); 4162#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4182#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5221#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4564#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4565#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5087#L764 assume 1 == ~t9_pc~0; 4351#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4190#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4092#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4093#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 3743#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3744#L783 assume !(1 == ~t10_pc~0); 3798#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3799#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3988#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4308#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 4309#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5208#L802 assume 1 == ~t11_pc~0; 5190#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3686#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3687#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4171#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 4172#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4285#L821 assume !(1 == ~t12_pc~0); 4533#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4636#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3693#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3694#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 5249#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4880#L1339 assume !(1 == ~M_E~0); 4881#L1339-2 assume !(1 == ~T1_E~0); 5279#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5280#L1349-1 assume !(1 == ~T3_E~0); 4656#L1354-1 assume !(1 == ~T4_E~0); 4657#L1359-1 assume !(1 == ~T5_E~0); 5064#L1364-1 assume !(1 == ~T6_E~0); 4123#L1369-1 assume !(1 == ~T7_E~0); 4124#L1374-1 assume !(1 == ~T8_E~0); 4659#L1379-1 assume !(1 == ~T9_E~0); 4660#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4768#L1389-1 assume !(1 == ~T11_E~0); 5244#L1394-1 assume !(1 == ~T12_E~0); 5245#L1399-1 assume !(1 == ~E_M~0); 5326#L1404-1 assume !(1 == ~E_1~0); 4214#L1409-1 assume !(1 == ~E_2~0); 4215#L1414-1 assume !(1 == ~E_3~0); 4946#L1419-1 assume !(1 == ~E_4~0); 3857#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 3858#L1429-1 assume !(1 == ~E_6~0); 4671#L1434-1 assume !(1 == ~E_7~0); 5261#L1439-1 assume !(1 == ~E_8~0); 3899#L1444-1 assume !(1 == ~E_9~0); 3900#L1449-1 assume !(1 == ~E_10~0); 4270#L1454-1 assume !(1 == ~E_11~0); 4271#L1459-1 assume !(1 == ~E_12~0); 4798#L1464-1 assume { :end_inline_reset_delta_events } true; 4033#L1810-2 [2022-12-13 15:11:58,345 INFO L750 eck$LassoCheckResult]: Loop: 4033#L1810-2 assume !false; 4473#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5010#L1176 assume !false; 4956#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4517#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3725#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 5008#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5185#L1003 assume !(0 != eval_~tmp~0#1); 4480#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4216#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4217#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4900#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4901#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4796#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3976#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3977#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4445#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4052#L1231-3 assume !(0 == ~T7_E~0); 4053#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4297#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5292#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5193#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4888#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 3996#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3997#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4044#L1271-3 assume !(0 == ~E_2~0); 4045#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4420#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4421#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4943#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4944#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5365#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5323#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4525#L1311-3 assume !(0 == ~E_10~0); 3922#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3923#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 3998#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4635#L593-42 assume !(1 == ~m_pc~0); 4800#L593-44 is_master_triggered_~__retres1~0#1 := 0; 4801#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4320#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4321#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3818#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3819#L612-42 assume !(1 == ~t1_pc~0); 4755#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 5145#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5374#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3911#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3912#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4599#L631-42 assume 1 == ~t2_pc~0; 3673#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3674#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4584#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4471#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4472#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4071#L650-42 assume 1 == ~t3_pc~0; 3638#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3639#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4976#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4263#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4264#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5263#L669-42 assume !(1 == ~t4_pc~0); 3636#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 3637#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5046#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4954#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 4853#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4854#L688-42 assume 1 == ~t5_pc~0; 4941#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5148#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4647#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3846#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3847#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3666#L707-42 assume !(1 == ~t6_pc~0); 3667#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 5329#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3990#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3991#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4822#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4823#L726-42 assume 1 == ~t7_pc~0; 5096#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5129#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4674#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4528#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4529#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4639#L745-42 assume 1 == ~t8_pc~0; 4677#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4679#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4844#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3654#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3655#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4379#L764-42 assume 1 == ~t9_pc~0; 4508#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4867#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4868#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3932#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3933#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3989#L783-42 assume 1 == ~t10_pc~0; 3610#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3611#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4199#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4836#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5356#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5036#L802-42 assume 1 == ~t11_pc~0; 4132#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3750#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3751#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3699#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3700#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4876#L821-42 assume 1 == ~t12_pc~0; 4877#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4240#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4632#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4633#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4570#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4562#L1339-3 assume !(1 == ~M_E~0); 4563#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4732#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4840#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4249#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4250#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4850#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5350#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5259#L1374-3 assume !(1 == ~T8_E~0); 4073#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4074#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4247#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4248#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4459#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5268#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5237#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5238#L1414-3 assume !(1 == ~E_3~0); 5291#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5039#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3954#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3955#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4849#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3887#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3888#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4001#L1454-3 assume !(1 == ~E_11~0); 4845#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4846#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4490#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3790#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3984#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 3985#L1829 assume !(0 == start_simulation_~tmp~3#1); 3772#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 3773#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4568#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3679#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 3680#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4861#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5243#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 4032#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 4033#L1810-2 [2022-12-13 15:11:58,346 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:58,346 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 2 times [2022-12-13 15:11:58,346 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:58,346 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [783329599] [2022-12-13 15:11:58,346 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:58,347 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:58,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:58,402 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:58,402 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:58,402 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [783329599] [2022-12-13 15:11:58,402 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [783329599] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:58,403 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:58,403 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:11:58,403 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [413675837] [2022-12-13 15:11:58,403 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:58,404 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:11:58,404 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:58,404 INFO L85 PathProgramCache]: Analyzing trace with hash -1070579181, now seen corresponding path program 1 times [2022-12-13 15:11:58,405 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:58,405 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1204076807] [2022-12-13 15:11:58,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:58,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:58,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:58,511 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:58,511 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:58,512 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1204076807] [2022-12-13 15:11:58,512 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1204076807] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:58,512 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:58,512 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:11:58,512 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [435970392] [2022-12-13 15:11:58,513 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:58,513 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:11:58,513 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:11:58,514 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:11:58,514 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:11:58,514 INFO L87 Difference]: Start difference. First operand 1788 states and 2651 transitions. cyclomatic complexity: 864 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:58,556 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:11:58,556 INFO L93 Difference]: Finished difference Result 1788 states and 2650 transitions. [2022-12-13 15:11:58,557 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2650 transitions. [2022-12-13 15:11:58,563 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-12-13 15:11:58,568 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2650 transitions. [2022-12-13 15:11:58,568 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-12-13 15:11:58,569 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-12-13 15:11:58,569 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2650 transitions. [2022-12-13 15:11:58,571 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:11:58,571 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2650 transitions. [2022-12-13 15:11:58,573 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2650 transitions. [2022-12-13 15:11:58,587 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-12-13 15:11:58,589 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4821029082774049) internal successors, (2650), 1787 states have internal predecessors, (2650), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:58,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2650 transitions. [2022-12-13 15:11:58,592 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2650 transitions. [2022-12-13 15:11:58,592 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:11:58,593 INFO L428 stractBuchiCegarLoop]: Abstraction has 1788 states and 2650 transitions. [2022-12-13 15:11:58,593 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 15:11:58,593 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2650 transitions. [2022-12-13 15:11:58,598 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-12-13 15:11:58,598 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:11:58,598 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:11:58,599 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:58,599 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:58,600 INFO L748 eck$LassoCheckResult]: Stem: 7468#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 7469#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 8291#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8292#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8888#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 8889#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7975#L853-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 7771#L858-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 7182#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7183#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8403#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8509#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8951#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8952#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7901#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7902#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 8431#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 8354#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7937#L1201 assume !(0 == ~M_E~0); 7938#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8798#L1206-1 assume !(0 == ~T2_E~0); 8781#L1211-1 assume !(0 == ~T3_E~0); 8782#L1216-1 assume !(0 == ~T4_E~0); 7752#L1221-1 assume !(0 == ~T5_E~0); 7753#L1226-1 assume !(0 == ~T6_E~0); 7394#L1231-1 assume !(0 == ~T7_E~0); 7395#L1236-1 assume !(0 == ~T8_E~0); 8822#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7790#L1246-1 assume !(0 == ~T10_E~0); 7791#L1251-1 assume !(0 == ~T11_E~0); 7935#L1256-1 assume !(0 == ~T12_E~0); 7191#L1261-1 assume !(0 == ~E_M~0); 7192#L1266-1 assume !(0 == ~E_1~0); 8936#L1271-1 assume !(0 == ~E_2~0); 8493#L1276-1 assume !(0 == ~E_3~0); 8494#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 8443#L1286-1 assume !(0 == ~E_5~0); 7649#L1291-1 assume !(0 == ~E_6~0); 7650#L1296-1 assume !(0 == ~E_7~0); 8227#L1301-1 assume !(0 == ~E_8~0); 8228#L1306-1 assume !(0 == ~E_9~0); 8715#L1311-1 assume !(0 == ~E_10~0); 7603#L1316-1 assume !(0 == ~E_11~0); 7604#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 8246#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8247#L593 assume 1 == ~m_pc~0; 8396#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7493#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8138#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8139#L1492 assume !(0 != activate_threads_~tmp~1#1); 8453#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8750#L612 assume !(1 == ~t1_pc~0); 8751#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8884#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8589#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7496#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7497#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7917#L631 assume 1 == ~t2_pc~0; 7848#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7272#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7273#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7617#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 8103#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7564#L650 assume !(1 == ~t3_pc~0); 7565#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8269#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8569#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7229#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 7230#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8424#L669 assume 1 == ~t4_pc~0; 8425#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8789#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7310#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7311#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 7431#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7659#L688 assume !(1 == ~t5_pc~0); 7450#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7451#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8917#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8311#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 8312#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8438#L707 assume 1 == ~t6_pc~0; 8855#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8072#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7605#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7606#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 8382#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7936#L726 assume 1 == ~t7_pc~0; 7836#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7533#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8580#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8859#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 7300#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7301#L745 assume !(1 == ~t8_pc~0); 7745#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7765#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8804#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8147#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8148#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8670#L764 assume 1 == ~t9_pc~0; 7934#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7773#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7675#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7676#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 7326#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7327#L783 assume !(1 == ~t10_pc~0); 7381#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 7382#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7571#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 7891#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 7892#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8791#L802 assume 1 == ~t11_pc~0; 8773#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7269#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7270#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7754#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 7755#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7868#L821 assume !(1 == ~t12_pc~0); 8116#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 8219#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7276#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7277#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 8832#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8463#L1339 assume !(1 == ~M_E~0); 8464#L1339-2 assume !(1 == ~T1_E~0); 8862#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8863#L1349-1 assume !(1 == ~T3_E~0); 8239#L1354-1 assume !(1 == ~T4_E~0); 8240#L1359-1 assume !(1 == ~T5_E~0); 8647#L1364-1 assume !(1 == ~T6_E~0); 7706#L1369-1 assume !(1 == ~T7_E~0); 7707#L1374-1 assume !(1 == ~T8_E~0); 8242#L1379-1 assume !(1 == ~T9_E~0); 8243#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8351#L1389-1 assume !(1 == ~T11_E~0); 8827#L1394-1 assume !(1 == ~T12_E~0); 8828#L1399-1 assume !(1 == ~E_M~0); 8909#L1404-1 assume !(1 == ~E_1~0); 7797#L1409-1 assume !(1 == ~E_2~0); 7798#L1414-1 assume !(1 == ~E_3~0); 8529#L1419-1 assume !(1 == ~E_4~0); 7440#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 7441#L1429-1 assume !(1 == ~E_6~0); 8254#L1434-1 assume !(1 == ~E_7~0); 8844#L1439-1 assume !(1 == ~E_8~0); 7482#L1444-1 assume !(1 == ~E_9~0); 7483#L1449-1 assume !(1 == ~E_10~0); 7853#L1454-1 assume !(1 == ~E_11~0); 7854#L1459-1 assume !(1 == ~E_12~0); 8381#L1464-1 assume { :end_inline_reset_delta_events } true; 7616#L1810-2 [2022-12-13 15:11:58,600 INFO L750 eck$LassoCheckResult]: Loop: 7616#L1810-2 assume !false; 8056#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8593#L1176 assume !false; 8539#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8100#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7308#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 8591#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8768#L1003 assume !(0 != eval_~tmp~0#1); 8063#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7799#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7800#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8483#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8484#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8379#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7559#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7560#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8028#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7635#L1231-3 assume !(0 == ~T7_E~0); 7636#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7880#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8875#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8776#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 8471#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 7579#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7580#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7627#L1271-3 assume !(0 == ~E_2~0); 7628#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8003#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8004#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8526#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8527#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8948#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8906#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8108#L1311-3 assume !(0 == ~E_10~0); 7505#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7506#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 7581#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8218#L593-42 assume 1 == ~m_pc~0; 8613#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8384#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7903#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7904#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7401#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7402#L612-42 assume !(1 == ~t1_pc~0); 8338#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 8728#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8957#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7494#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7495#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8182#L631-42 assume 1 == ~t2_pc~0; 7256#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7257#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8167#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8054#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8055#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7654#L650-42 assume 1 == ~t3_pc~0; 7221#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7222#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8559#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7846#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7847#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8846#L669-42 assume !(1 == ~t4_pc~0); 7219#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 7220#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8629#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8537#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 8436#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8437#L688-42 assume 1 == ~t5_pc~0; 8524#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8731#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8230#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7429#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7430#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7249#L707-42 assume !(1 == ~t6_pc~0); 7250#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 8912#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7573#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7574#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8405#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8406#L726-42 assume 1 == ~t7_pc~0; 8679#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8712#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8257#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8111#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8112#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8222#L745-42 assume 1 == ~t8_pc~0; 8260#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8262#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8427#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7237#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7238#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7962#L764-42 assume 1 == ~t9_pc~0; 8091#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8450#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8451#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7515#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7516#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7572#L783-42 assume 1 == ~t10_pc~0; 7193#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7194#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7782#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8419#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8939#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8619#L802-42 assume 1 == ~t11_pc~0; 7715#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7333#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7334#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7282#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7283#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8459#L821-42 assume 1 == ~t12_pc~0; 8460#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7823#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8215#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8216#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 8153#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8145#L1339-3 assume !(1 == ~M_E~0); 8146#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8315#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8423#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7832#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7833#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8433#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8933#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8842#L1374-3 assume !(1 == ~T8_E~0); 7656#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7657#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 7830#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 7831#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8042#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8851#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8820#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8821#L1414-3 assume !(1 == ~E_3~0); 8874#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8622#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7537#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7538#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8432#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7470#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7471#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 7584#L1454-3 assume !(1 == ~E_11~0); 8428#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8429#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8073#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7373#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7567#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 7568#L1829 assume !(0 == start_simulation_~tmp~3#1); 7355#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 7356#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 8151#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7262#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 7263#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8444#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8826#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 7615#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 7616#L1810-2 [2022-12-13 15:11:58,601 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:58,601 INFO L85 PathProgramCache]: Analyzing trace with hash -494851220, now seen corresponding path program 1 times [2022-12-13 15:11:58,601 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:58,601 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2126025117] [2022-12-13 15:11:58,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:58,601 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:58,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:58,639 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:58,639 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:58,640 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2126025117] [2022-12-13 15:11:58,640 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2126025117] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:58,640 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:58,640 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:11:58,640 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1418430745] [2022-12-13 15:11:58,640 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:58,641 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:11:58,641 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:58,642 INFO L85 PathProgramCache]: Analyzing trace with hash -488091310, now seen corresponding path program 1 times [2022-12-13 15:11:58,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:58,642 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1311498235] [2022-12-13 15:11:58,642 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:58,642 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:58,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:58,717 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:58,717 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:58,717 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1311498235] [2022-12-13 15:11:58,718 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1311498235] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:58,718 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:58,718 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:11:58,718 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [783786444] [2022-12-13 15:11:58,718 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:58,719 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:11:58,719 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:11:58,719 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:11:58,719 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:11:58,720 INFO L87 Difference]: Start difference. First operand 1788 states and 2650 transitions. cyclomatic complexity: 863 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:58,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:11:58,767 INFO L93 Difference]: Finished difference Result 1788 states and 2649 transitions. [2022-12-13 15:11:58,767 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2649 transitions. [2022-12-13 15:11:58,777 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-12-13 15:11:58,784 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2649 transitions. [2022-12-13 15:11:58,785 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-12-13 15:11:58,786 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-12-13 15:11:58,787 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2649 transitions. [2022-12-13 15:11:58,789 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:11:58,790 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2649 transitions. [2022-12-13 15:11:58,792 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2649 transitions. [2022-12-13 15:11:58,814 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-12-13 15:11:58,818 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4815436241610738) internal successors, (2649), 1787 states have internal predecessors, (2649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:58,822 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2649 transitions. [2022-12-13 15:11:58,822 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2649 transitions. [2022-12-13 15:11:58,823 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:11:58,823 INFO L428 stractBuchiCegarLoop]: Abstraction has 1788 states and 2649 transitions. [2022-12-13 15:11:58,823 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 15:11:58,823 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2649 transitions. [2022-12-13 15:11:58,832 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-12-13 15:11:58,832 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:11:58,832 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:11:58,835 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:58,835 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:58,835 INFO L748 eck$LassoCheckResult]: Stem: 11051#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 11052#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 11874#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11875#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12471#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 12472#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11558#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11354#L858-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 10765#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10766#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11986#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12092#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12534#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12535#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11484#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 11485#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12014#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 11937#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11520#L1201 assume !(0 == ~M_E~0); 11521#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12381#L1206-1 assume !(0 == ~T2_E~0); 12364#L1211-1 assume !(0 == ~T3_E~0); 12365#L1216-1 assume !(0 == ~T4_E~0); 11335#L1221-1 assume !(0 == ~T5_E~0); 11336#L1226-1 assume !(0 == ~T6_E~0); 10977#L1231-1 assume !(0 == ~T7_E~0); 10978#L1236-1 assume !(0 == ~T8_E~0); 12405#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11373#L1246-1 assume !(0 == ~T10_E~0); 11374#L1251-1 assume !(0 == ~T11_E~0); 11518#L1256-1 assume !(0 == ~T12_E~0); 10774#L1261-1 assume !(0 == ~E_M~0); 10775#L1266-1 assume !(0 == ~E_1~0); 12519#L1271-1 assume !(0 == ~E_2~0); 12076#L1276-1 assume !(0 == ~E_3~0); 12077#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 12026#L1286-1 assume !(0 == ~E_5~0); 11232#L1291-1 assume !(0 == ~E_6~0); 11233#L1296-1 assume !(0 == ~E_7~0); 11810#L1301-1 assume !(0 == ~E_8~0); 11811#L1306-1 assume !(0 == ~E_9~0); 12298#L1311-1 assume !(0 == ~E_10~0); 11186#L1316-1 assume !(0 == ~E_11~0); 11187#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 11829#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11830#L593 assume 1 == ~m_pc~0; 11979#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11076#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11721#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11722#L1492 assume !(0 != activate_threads_~tmp~1#1); 12036#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12333#L612 assume !(1 == ~t1_pc~0); 12334#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12467#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12172#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11079#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11080#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11500#L631 assume 1 == ~t2_pc~0; 11431#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10855#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10856#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11200#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 11686#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11147#L650 assume !(1 == ~t3_pc~0); 11148#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 11852#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12152#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10812#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 10813#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12007#L669 assume 1 == ~t4_pc~0; 12008#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12372#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10893#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10894#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 11014#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11242#L688 assume !(1 == ~t5_pc~0); 11033#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11034#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12500#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11894#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 11895#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12021#L707 assume 1 == ~t6_pc~0; 12438#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11655#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11188#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11189#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 11965#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11519#L726 assume 1 == ~t7_pc~0; 11419#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11116#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12163#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12442#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 10883#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10884#L745 assume !(1 == ~t8_pc~0); 11328#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 11348#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12387#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11730#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11731#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12253#L764 assume 1 == ~t9_pc~0; 11517#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11356#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11258#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11259#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 10909#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10910#L783 assume !(1 == ~t10_pc~0); 10964#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 10965#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11154#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11474#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 11475#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12374#L802 assume 1 == ~t11_pc~0; 12356#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10852#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10853#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11337#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 11338#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11451#L821 assume !(1 == ~t12_pc~0); 11699#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 11802#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10859#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 10860#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 12415#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12046#L1339 assume !(1 == ~M_E~0); 12047#L1339-2 assume !(1 == ~T1_E~0); 12445#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12446#L1349-1 assume !(1 == ~T3_E~0); 11822#L1354-1 assume !(1 == ~T4_E~0); 11823#L1359-1 assume !(1 == ~T5_E~0); 12230#L1364-1 assume !(1 == ~T6_E~0); 11289#L1369-1 assume !(1 == ~T7_E~0); 11290#L1374-1 assume !(1 == ~T8_E~0); 11825#L1379-1 assume !(1 == ~T9_E~0); 11826#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11934#L1389-1 assume !(1 == ~T11_E~0); 12410#L1394-1 assume !(1 == ~T12_E~0); 12411#L1399-1 assume !(1 == ~E_M~0); 12492#L1404-1 assume !(1 == ~E_1~0); 11380#L1409-1 assume !(1 == ~E_2~0); 11381#L1414-1 assume !(1 == ~E_3~0); 12112#L1419-1 assume !(1 == ~E_4~0); 11023#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 11024#L1429-1 assume !(1 == ~E_6~0); 11837#L1434-1 assume !(1 == ~E_7~0); 12427#L1439-1 assume !(1 == ~E_8~0); 11065#L1444-1 assume !(1 == ~E_9~0); 11066#L1449-1 assume !(1 == ~E_10~0); 11436#L1454-1 assume !(1 == ~E_11~0); 11437#L1459-1 assume !(1 == ~E_12~0); 11964#L1464-1 assume { :end_inline_reset_delta_events } true; 11199#L1810-2 [2022-12-13 15:11:58,836 INFO L750 eck$LassoCheckResult]: Loop: 11199#L1810-2 assume !false; 11639#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12176#L1176 assume !false; 12122#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11683#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10891#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 12174#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12351#L1003 assume !(0 != eval_~tmp~0#1); 11646#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11382#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11383#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12066#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12067#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11962#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11142#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11143#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11611#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11218#L1231-3 assume !(0 == ~T7_E~0); 11219#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11463#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12458#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12359#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 12054#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 11162#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11163#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11210#L1271-3 assume !(0 == ~E_2~0); 11211#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11586#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11587#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12109#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12110#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12531#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12489#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11691#L1311-3 assume !(0 == ~E_10~0); 11088#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 11089#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 11164#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11801#L593-42 assume 1 == ~m_pc~0; 12196#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11967#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11486#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11487#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10984#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10985#L612-42 assume !(1 == ~t1_pc~0); 11921#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 12311#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12540#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11077#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11078#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11765#L631-42 assume 1 == ~t2_pc~0; 10839#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10840#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11750#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11637#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11638#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11237#L650-42 assume 1 == ~t3_pc~0; 10804#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10805#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12142#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11429#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11430#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12429#L669-42 assume !(1 == ~t4_pc~0); 10802#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 10803#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12212#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12120#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 12019#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12020#L688-42 assume 1 == ~t5_pc~0; 12107#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12314#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11813#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11012#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11013#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10832#L707-42 assume !(1 == ~t6_pc~0); 10833#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 12495#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11156#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11157#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11988#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11989#L726-42 assume 1 == ~t7_pc~0; 12262#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12295#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11840#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11694#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11695#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11805#L745-42 assume 1 == ~t8_pc~0; 11843#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11845#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12010#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10820#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10821#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11545#L764-42 assume 1 == ~t9_pc~0; 11674#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12033#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12034#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11098#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11099#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11155#L783-42 assume 1 == ~t10_pc~0; 10776#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 10777#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11365#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12002#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12522#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12202#L802-42 assume 1 == ~t11_pc~0; 11298#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10916#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10917#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 10865#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 10866#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12042#L821-42 assume 1 == ~t12_pc~0; 12043#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 11406#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11798#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11799#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 11736#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11728#L1339-3 assume !(1 == ~M_E~0); 11729#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11898#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12006#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11415#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11416#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12016#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12516#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12425#L1374-3 assume !(1 == ~T8_E~0); 11239#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11240#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11413#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 11414#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 11625#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12434#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12403#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12404#L1414-3 assume !(1 == ~E_3~0); 12457#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12205#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11120#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11121#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12015#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11053#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 11054#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 11167#L1454-3 assume !(1 == ~E_11~0); 12011#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12012#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11656#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10956#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11150#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 11151#L1829 assume !(0 == start_simulation_~tmp~3#1); 10938#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 10939#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11734#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 10845#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 10846#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12027#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12409#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 11198#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 11199#L1810-2 [2022-12-13 15:11:58,836 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:58,836 INFO L85 PathProgramCache]: Analyzing trace with hash -833138770, now seen corresponding path program 1 times [2022-12-13 15:11:58,837 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:58,837 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1820626410] [2022-12-13 15:11:58,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:58,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:58,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:58,890 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:58,891 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:58,891 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1820626410] [2022-12-13 15:11:58,891 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1820626410] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:58,891 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:58,891 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:11:58,892 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [188477045] [2022-12-13 15:11:58,892 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:58,892 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:11:58,892 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:58,893 INFO L85 PathProgramCache]: Analyzing trace with hash -488091310, now seen corresponding path program 2 times [2022-12-13 15:11:58,893 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:58,893 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [699716437] [2022-12-13 15:11:58,893 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:58,893 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:58,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:58,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:58,943 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:58,944 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [699716437] [2022-12-13 15:11:58,944 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [699716437] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:58,944 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:58,944 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:11:58,944 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1419708347] [2022-12-13 15:11:58,944 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:58,945 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:11:58,945 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:11:58,945 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:11:58,946 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:11:58,946 INFO L87 Difference]: Start difference. First operand 1788 states and 2649 transitions. cyclomatic complexity: 862 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:58,978 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:11:58,978 INFO L93 Difference]: Finished difference Result 1788 states and 2648 transitions. [2022-12-13 15:11:58,978 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2648 transitions. [2022-12-13 15:11:58,985 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-12-13 15:11:58,989 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2648 transitions. [2022-12-13 15:11:58,989 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-12-13 15:11:58,990 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-12-13 15:11:58,991 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2648 transitions. [2022-12-13 15:11:58,992 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:11:58,992 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2648 transitions. [2022-12-13 15:11:58,994 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2648 transitions. [2022-12-13 15:11:59,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-12-13 15:11:59,018 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4809843400447427) internal successors, (2648), 1787 states have internal predecessors, (2648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:59,021 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2648 transitions. [2022-12-13 15:11:59,021 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2648 transitions. [2022-12-13 15:11:59,021 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:11:59,022 INFO L428 stractBuchiCegarLoop]: Abstraction has 1788 states and 2648 transitions. [2022-12-13 15:11:59,022 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 15:11:59,022 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2648 transitions. [2022-12-13 15:11:59,027 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-12-13 15:11:59,027 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:11:59,028 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:11:59,029 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:59,029 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:59,029 INFO L748 eck$LassoCheckResult]: Stem: 14634#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 14635#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 15457#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15458#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16054#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 16055#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15141#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14937#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14348#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 14349#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 15569#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 15675#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16117#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16118#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15067#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 15068#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 15597#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 15520#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15103#L1201 assume !(0 == ~M_E~0); 15104#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15964#L1206-1 assume !(0 == ~T2_E~0); 15947#L1211-1 assume !(0 == ~T3_E~0); 15948#L1216-1 assume !(0 == ~T4_E~0); 14918#L1221-1 assume !(0 == ~T5_E~0); 14919#L1226-1 assume !(0 == ~T6_E~0); 14560#L1231-1 assume !(0 == ~T7_E~0); 14561#L1236-1 assume !(0 == ~T8_E~0); 15988#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14956#L1246-1 assume !(0 == ~T10_E~0); 14957#L1251-1 assume !(0 == ~T11_E~0); 15101#L1256-1 assume !(0 == ~T12_E~0); 14357#L1261-1 assume !(0 == ~E_M~0); 14358#L1266-1 assume !(0 == ~E_1~0); 16102#L1271-1 assume !(0 == ~E_2~0); 15659#L1276-1 assume !(0 == ~E_3~0); 15660#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 15609#L1286-1 assume !(0 == ~E_5~0); 14815#L1291-1 assume !(0 == ~E_6~0); 14816#L1296-1 assume !(0 == ~E_7~0); 15393#L1301-1 assume !(0 == ~E_8~0); 15394#L1306-1 assume !(0 == ~E_9~0); 15881#L1311-1 assume !(0 == ~E_10~0); 14769#L1316-1 assume !(0 == ~E_11~0); 14770#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 15412#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15413#L593 assume 1 == ~m_pc~0; 15562#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14659#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15304#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15305#L1492 assume !(0 != activate_threads_~tmp~1#1); 15619#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15916#L612 assume !(1 == ~t1_pc~0); 15917#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16050#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15755#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14662#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14663#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15083#L631 assume 1 == ~t2_pc~0; 15014#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14438#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14439#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14783#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 15269#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14730#L650 assume !(1 == ~t3_pc~0); 14731#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15435#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15735#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14395#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 14396#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15590#L669 assume 1 == ~t4_pc~0; 15591#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15955#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14476#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14477#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 14597#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14825#L688 assume !(1 == ~t5_pc~0); 14616#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 14617#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16083#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15477#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 15478#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15604#L707 assume 1 == ~t6_pc~0; 16021#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15238#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14771#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14772#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 15548#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15102#L726 assume 1 == ~t7_pc~0; 15002#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14699#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15746#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16025#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 14466#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14467#L745 assume !(1 == ~t8_pc~0); 14911#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14931#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15970#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15313#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15314#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15836#L764 assume 1 == ~t9_pc~0; 15100#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14939#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14841#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14842#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 14492#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14493#L783 assume !(1 == ~t10_pc~0); 14547#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 14548#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14737#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15057#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 15058#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15957#L802 assume 1 == ~t11_pc~0; 15939#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14435#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14436#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14920#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 14921#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15034#L821 assume !(1 == ~t12_pc~0); 15282#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 15385#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14442#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 14443#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 15998#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15629#L1339 assume !(1 == ~M_E~0); 15630#L1339-2 assume !(1 == ~T1_E~0); 16028#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16029#L1349-1 assume !(1 == ~T3_E~0); 15405#L1354-1 assume !(1 == ~T4_E~0); 15406#L1359-1 assume !(1 == ~T5_E~0); 15813#L1364-1 assume !(1 == ~T6_E~0); 14872#L1369-1 assume !(1 == ~T7_E~0); 14873#L1374-1 assume !(1 == ~T8_E~0); 15408#L1379-1 assume !(1 == ~T9_E~0); 15409#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 15517#L1389-1 assume !(1 == ~T11_E~0); 15993#L1394-1 assume !(1 == ~T12_E~0); 15994#L1399-1 assume !(1 == ~E_M~0); 16075#L1404-1 assume !(1 == ~E_1~0); 14963#L1409-1 assume !(1 == ~E_2~0); 14964#L1414-1 assume !(1 == ~E_3~0); 15695#L1419-1 assume !(1 == ~E_4~0); 14606#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 14607#L1429-1 assume !(1 == ~E_6~0); 15420#L1434-1 assume !(1 == ~E_7~0); 16010#L1439-1 assume !(1 == ~E_8~0); 14648#L1444-1 assume !(1 == ~E_9~0); 14649#L1449-1 assume !(1 == ~E_10~0); 15019#L1454-1 assume !(1 == ~E_11~0); 15020#L1459-1 assume !(1 == ~E_12~0); 15547#L1464-1 assume { :end_inline_reset_delta_events } true; 14782#L1810-2 [2022-12-13 15:11:59,030 INFO L750 eck$LassoCheckResult]: Loop: 14782#L1810-2 assume !false; 15222#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15759#L1176 assume !false; 15705#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15266#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14474#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 15757#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 15934#L1003 assume !(0 != eval_~tmp~0#1); 15229#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14965#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14966#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15649#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15650#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15545#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14725#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14726#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15194#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14801#L1231-3 assume !(0 == ~T7_E~0); 14802#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15046#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16041#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15942#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 15637#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 14745#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14746#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14793#L1271-3 assume !(0 == ~E_2~0); 14794#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15169#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15170#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15692#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15693#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16114#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16072#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15274#L1311-3 assume !(0 == ~E_10~0); 14671#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14672#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 14747#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15384#L593-42 assume 1 == ~m_pc~0; 15779#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15550#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15069#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15070#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14567#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14568#L612-42 assume !(1 == ~t1_pc~0); 15504#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 15894#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16123#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14660#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14661#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15348#L631-42 assume 1 == ~t2_pc~0; 14422#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14423#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15333#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15220#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15221#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14820#L650-42 assume 1 == ~t3_pc~0; 14387#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14388#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15725#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15012#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15013#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16012#L669-42 assume !(1 == ~t4_pc~0); 14385#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 14386#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15795#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15703#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 15602#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15603#L688-42 assume 1 == ~t5_pc~0; 15690#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15897#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15396#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14595#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14596#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14415#L707-42 assume !(1 == ~t6_pc~0); 14416#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 16078#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14739#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14740#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15571#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15572#L726-42 assume 1 == ~t7_pc~0; 15845#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15878#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15423#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15277#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15278#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15388#L745-42 assume 1 == ~t8_pc~0; 15426#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15428#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15593#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14403#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14404#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15128#L764-42 assume 1 == ~t9_pc~0; 15257#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15616#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15617#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14681#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14682#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14738#L783-42 assume 1 == ~t10_pc~0; 14359#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 14360#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14948#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15585#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16105#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15785#L802-42 assume 1 == ~t11_pc~0; 14881#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14499#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14500#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14448#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14449#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15625#L821-42 assume 1 == ~t12_pc~0; 15626#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 14989#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15381#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 15382#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 15319#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15311#L1339-3 assume !(1 == ~M_E~0); 15312#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15481#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15589#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14998#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14999#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15599#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16099#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16008#L1374-3 assume !(1 == ~T8_E~0); 14822#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14823#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14996#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 14997#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 15208#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16017#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15986#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15987#L1414-3 assume !(1 == ~E_3~0); 16040#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15788#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14703#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14704#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15598#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14636#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14637#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 14750#L1454-3 assume !(1 == ~E_11~0); 15594#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 15595#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15239#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14539#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14733#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 14734#L1829 assume !(0 == start_simulation_~tmp~3#1); 14521#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 14522#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 15317#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14428#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 14429#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15610#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15992#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 14781#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 14782#L1810-2 [2022-12-13 15:11:59,030 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:59,030 INFO L85 PathProgramCache]: Analyzing trace with hash -1259693268, now seen corresponding path program 1 times [2022-12-13 15:11:59,030 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:59,031 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1750831074] [2022-12-13 15:11:59,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:59,031 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:59,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:59,065 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:59,065 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:59,065 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1750831074] [2022-12-13 15:11:59,065 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1750831074] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:59,066 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:59,066 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:11:59,066 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1548161874] [2022-12-13 15:11:59,066 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:59,066 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:11:59,067 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:59,067 INFO L85 PathProgramCache]: Analyzing trace with hash -488091310, now seen corresponding path program 3 times [2022-12-13 15:11:59,067 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:59,067 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1028505712] [2022-12-13 15:11:59,068 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:59,068 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:59,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:59,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:59,130 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:59,130 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1028505712] [2022-12-13 15:11:59,130 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1028505712] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:59,130 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:59,130 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:11:59,130 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [227202112] [2022-12-13 15:11:59,131 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:59,131 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:11:59,131 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:11:59,132 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:11:59,132 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:11:59,132 INFO L87 Difference]: Start difference. First operand 1788 states and 2648 transitions. cyclomatic complexity: 861 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:59,168 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:11:59,168 INFO L93 Difference]: Finished difference Result 1788 states and 2647 transitions. [2022-12-13 15:11:59,168 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2647 transitions. [2022-12-13 15:11:59,177 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-12-13 15:11:59,183 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2647 transitions. [2022-12-13 15:11:59,184 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-12-13 15:11:59,185 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-12-13 15:11:59,185 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2647 transitions. [2022-12-13 15:11:59,188 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:11:59,188 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2647 transitions. [2022-12-13 15:11:59,190 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2647 transitions. [2022-12-13 15:11:59,226 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-12-13 15:11:59,230 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4804250559284116) internal successors, (2647), 1787 states have internal predecessors, (2647), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:59,235 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2647 transitions. [2022-12-13 15:11:59,236 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2647 transitions. [2022-12-13 15:11:59,236 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:11:59,237 INFO L428 stractBuchiCegarLoop]: Abstraction has 1788 states and 2647 transitions. [2022-12-13 15:11:59,237 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 15:11:59,237 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2647 transitions. [2022-12-13 15:11:59,244 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-12-13 15:11:59,245 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:11:59,245 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:11:59,248 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:59,248 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:59,248 INFO L748 eck$LassoCheckResult]: Stem: 18217#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 18218#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 19041#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19042#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19637#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 19638#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18725#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18520#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17931#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17932#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 19152#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 19259#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19700#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19701#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18650#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18651#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 19180#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 19103#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18686#L1201 assume !(0 == ~M_E~0); 18687#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19547#L1206-1 assume !(0 == ~T2_E~0); 19530#L1211-1 assume !(0 == ~T3_E~0); 19531#L1216-1 assume !(0 == ~T4_E~0); 18502#L1221-1 assume !(0 == ~T5_E~0); 18503#L1226-1 assume !(0 == ~T6_E~0); 18143#L1231-1 assume !(0 == ~T7_E~0); 18144#L1236-1 assume !(0 == ~T8_E~0); 19571#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18542#L1246-1 assume !(0 == ~T10_E~0); 18543#L1251-1 assume !(0 == ~T11_E~0); 18684#L1256-1 assume !(0 == ~T12_E~0); 17940#L1261-1 assume !(0 == ~E_M~0); 17941#L1266-1 assume !(0 == ~E_1~0); 19685#L1271-1 assume !(0 == ~E_2~0); 19242#L1276-1 assume !(0 == ~E_3~0); 19243#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 19192#L1286-1 assume !(0 == ~E_5~0); 18398#L1291-1 assume !(0 == ~E_6~0); 18399#L1296-1 assume !(0 == ~E_7~0); 18976#L1301-1 assume !(0 == ~E_8~0); 18977#L1306-1 assume !(0 == ~E_9~0); 19464#L1311-1 assume !(0 == ~E_10~0); 18352#L1316-1 assume !(0 == ~E_11~0); 18353#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 18995#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18996#L593 assume 1 == ~m_pc~0; 19145#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18242#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18887#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18888#L1492 assume !(0 != activate_threads_~tmp~1#1); 19202#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19499#L612 assume !(1 == ~t1_pc~0); 19500#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19633#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19338#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18245#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18246#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18666#L631 assume 1 == ~t2_pc~0; 18597#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18021#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18022#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18366#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 18852#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18315#L650 assume !(1 == ~t3_pc~0); 18316#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19018#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19318#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17978#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 17979#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19173#L669 assume 1 == ~t4_pc~0; 19174#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19539#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18063#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18064#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 18180#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18408#L688 assume !(1 == ~t5_pc~0); 18199#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 18200#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19666#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19062#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 19063#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19190#L707 assume 1 == ~t6_pc~0; 19604#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18821#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18354#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18355#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 19133#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18685#L726 assume 1 == ~t7_pc~0; 18587#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18282#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19330#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19609#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 18049#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18050#L745 assume !(1 == ~t8_pc~0); 18494#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 18514#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19553#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18896#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18897#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19419#L764 assume 1 == ~t9_pc~0; 18683#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18522#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18424#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18425#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 18075#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18076#L783 assume !(1 == ~t10_pc~0); 18130#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 18131#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18320#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18645#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 18646#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19540#L802 assume 1 == ~t11_pc~0; 19522#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18018#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18019#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18504#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 18505#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 18617#L821 assume !(1 == ~t12_pc~0); 18865#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 18968#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18027#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 18028#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 19581#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19212#L1339 assume !(1 == ~M_E~0); 19213#L1339-2 assume !(1 == ~T1_E~0); 19611#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19612#L1349-1 assume !(1 == ~T3_E~0); 18989#L1354-1 assume !(1 == ~T4_E~0); 18990#L1359-1 assume !(1 == ~T5_E~0); 19398#L1364-1 assume !(1 == ~T6_E~0); 18455#L1369-1 assume !(1 == ~T7_E~0); 18456#L1374-1 assume !(1 == ~T8_E~0); 18993#L1379-1 assume !(1 == ~T9_E~0); 18994#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19100#L1389-1 assume !(1 == ~T11_E~0); 19576#L1394-1 assume !(1 == ~T12_E~0); 19577#L1399-1 assume !(1 == ~E_M~0); 19658#L1404-1 assume !(1 == ~E_1~0); 18546#L1409-1 assume !(1 == ~E_2~0); 18547#L1414-1 assume !(1 == ~E_3~0); 19278#L1419-1 assume !(1 == ~E_4~0); 18189#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 18190#L1429-1 assume !(1 == ~E_6~0); 19003#L1434-1 assume !(1 == ~E_7~0); 19593#L1439-1 assume !(1 == ~E_8~0); 18231#L1444-1 assume !(1 == ~E_9~0); 18232#L1449-1 assume !(1 == ~E_10~0); 18604#L1454-1 assume !(1 == ~E_11~0); 18605#L1459-1 assume !(1 == ~E_12~0); 19130#L1464-1 assume { :end_inline_reset_delta_events } true; 18365#L1810-2 [2022-12-13 15:11:59,249 INFO L750 eck$LassoCheckResult]: Loop: 18365#L1810-2 assume !false; 18805#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19342#L1176 assume !false; 19288#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18851#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18057#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 19340#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19519#L1003 assume !(0 != eval_~tmp~0#1); 18812#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18548#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18549#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19232#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19233#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19129#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18308#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18309#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18777#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18384#L1231-3 assume !(0 == ~T7_E~0); 18385#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18629#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19624#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19525#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 19220#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 18328#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 18329#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18376#L1271-3 assume !(0 == ~E_2~0); 18377#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18752#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18753#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19275#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19276#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19697#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19655#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18857#L1311-3 assume !(0 == ~E_10~0); 18254#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18255#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 18330#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18967#L593-42 assume 1 == ~m_pc~0; 19362#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19132#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18652#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18653#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18150#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18151#L612-42 assume 1 == ~t1_pc~0; 19088#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19477#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19706#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18243#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18244#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18931#L631-42 assume 1 == ~t2_pc~0; 18005#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18006#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18916#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18803#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18804#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18403#L650-42 assume 1 == ~t3_pc~0; 17970#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17971#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19308#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18595#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18596#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19595#L669-42 assume !(1 == ~t4_pc~0); 17968#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 17969#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19378#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19286#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 19185#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19186#L688-42 assume 1 == ~t5_pc~0; 19273#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19480#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18979#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18175#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18176#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17998#L707-42 assume 1 == ~t6_pc~0; 18000#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19661#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18322#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18323#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19154#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19155#L726-42 assume 1 == ~t7_pc~0; 19428#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19461#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19006#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18860#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18861#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18971#L745-42 assume 1 == ~t8_pc~0; 19009#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19011#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19176#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17986#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17987#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18711#L764-42 assume 1 == ~t9_pc~0; 18840#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19199#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19200#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18264#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18265#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18321#L783-42 assume 1 == ~t10_pc~0; 17942#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 17943#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18531#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19168#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19688#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19368#L802-42 assume 1 == ~t11_pc~0; 18464#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18082#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18083#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18031#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18032#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19208#L821-42 assume 1 == ~t12_pc~0; 19209#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 18572#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18964#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 18965#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 18902#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18894#L1339-3 assume !(1 == ~M_E~0); 18895#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19064#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19172#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18581#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18582#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19182#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19682#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19591#L1374-3 assume !(1 == ~T8_E~0); 18404#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18405#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18579#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18580#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18791#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19600#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19569#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19570#L1414-3 assume !(1 == ~E_3~0); 19623#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19371#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18286#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18287#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19181#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18219#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 18220#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 18333#L1454-3 assume !(1 == ~E_11~0); 19177#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 19178#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18822#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18122#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18313#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 18314#L1829 assume !(0 == start_simulation_~tmp~3#1); 18104#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18105#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18900#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18011#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 18012#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19193#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19575#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 18364#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 18365#L1810-2 [2022-12-13 15:11:59,250 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:59,250 INFO L85 PathProgramCache]: Analyzing trace with hash -719263762, now seen corresponding path program 1 times [2022-12-13 15:11:59,250 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:59,250 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2130949643] [2022-12-13 15:11:59,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:59,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:59,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:59,312 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:59,312 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:59,312 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2130949643] [2022-12-13 15:11:59,312 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2130949643] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:59,312 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:59,313 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:11:59,313 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [742735209] [2022-12-13 15:11:59,313 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:59,313 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:11:59,314 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:59,314 INFO L85 PathProgramCache]: Analyzing trace with hash 1621802640, now seen corresponding path program 1 times [2022-12-13 15:11:59,314 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:59,314 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1358606247] [2022-12-13 15:11:59,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:59,315 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:59,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:59,366 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:59,367 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:59,367 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1358606247] [2022-12-13 15:11:59,367 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1358606247] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:59,367 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:59,367 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:11:59,367 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1660321479] [2022-12-13 15:11:59,368 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:59,368 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:11:59,368 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:11:59,368 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:11:59,369 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:11:59,369 INFO L87 Difference]: Start difference. First operand 1788 states and 2647 transitions. cyclomatic complexity: 860 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:59,397 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:11:59,397 INFO L93 Difference]: Finished difference Result 1788 states and 2646 transitions. [2022-12-13 15:11:59,397 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2646 transitions. [2022-12-13 15:11:59,402 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-12-13 15:11:59,406 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2646 transitions. [2022-12-13 15:11:59,406 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-12-13 15:11:59,407 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-12-13 15:11:59,407 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2646 transitions. [2022-12-13 15:11:59,409 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:11:59,409 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2646 transitions. [2022-12-13 15:11:59,411 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2646 transitions. [2022-12-13 15:11:59,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-12-13 15:11:59,427 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4798657718120805) internal successors, (2646), 1787 states have internal predecessors, (2646), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:59,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2646 transitions. [2022-12-13 15:11:59,430 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2646 transitions. [2022-12-13 15:11:59,430 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:11:59,430 INFO L428 stractBuchiCegarLoop]: Abstraction has 1788 states and 2646 transitions. [2022-12-13 15:11:59,430 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 15:11:59,431 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2646 transitions. [2022-12-13 15:11:59,435 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-12-13 15:11:59,435 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:11:59,435 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:11:59,436 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:59,437 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:59,437 INFO L748 eck$LassoCheckResult]: Stem: 21800#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 21801#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 22623#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22624#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23220#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 23221#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22308#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22103#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21514#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21515#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22735#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 22842#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23283#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 23284#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22233#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22234#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 22763#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 22686#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22269#L1201 assume !(0 == ~M_E~0); 22270#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23130#L1206-1 assume !(0 == ~T2_E~0); 23113#L1211-1 assume !(0 == ~T3_E~0); 23114#L1216-1 assume !(0 == ~T4_E~0); 22085#L1221-1 assume !(0 == ~T5_E~0); 22086#L1226-1 assume !(0 == ~T6_E~0); 21726#L1231-1 assume !(0 == ~T7_E~0); 21727#L1236-1 assume !(0 == ~T8_E~0); 23154#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22125#L1246-1 assume !(0 == ~T10_E~0); 22126#L1251-1 assume !(0 == ~T11_E~0); 22267#L1256-1 assume !(0 == ~T12_E~0); 21523#L1261-1 assume !(0 == ~E_M~0); 21524#L1266-1 assume !(0 == ~E_1~0); 23268#L1271-1 assume !(0 == ~E_2~0); 22825#L1276-1 assume !(0 == ~E_3~0); 22826#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 22775#L1286-1 assume !(0 == ~E_5~0); 21981#L1291-1 assume !(0 == ~E_6~0); 21982#L1296-1 assume !(0 == ~E_7~0); 22559#L1301-1 assume !(0 == ~E_8~0); 22560#L1306-1 assume !(0 == ~E_9~0); 23047#L1311-1 assume !(0 == ~E_10~0); 21935#L1316-1 assume !(0 == ~E_11~0); 21936#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 22578#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22579#L593 assume 1 == ~m_pc~0; 22728#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21825#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22470#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22471#L1492 assume !(0 != activate_threads_~tmp~1#1); 22785#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23082#L612 assume !(1 == ~t1_pc~0); 23083#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23216#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22921#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21828#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21829#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22249#L631 assume 1 == ~t2_pc~0; 22180#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21604#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21605#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21949#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 22435#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21898#L650 assume !(1 == ~t3_pc~0); 21899#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22601#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22901#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21561#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 21562#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22756#L669 assume 1 == ~t4_pc~0; 22757#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23122#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21646#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21647#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 21763#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21991#L688 assume !(1 == ~t5_pc~0); 21782#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21783#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23249#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22643#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 22644#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22773#L707 assume 1 == ~t6_pc~0; 23187#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22404#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21937#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21938#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 22714#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22268#L726 assume 1 == ~t7_pc~0; 22170#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21865#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22913#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23191#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 21632#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21633#L745 assume !(1 == ~t8_pc~0); 22077#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22097#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23136#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22479#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22480#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23002#L764 assume 1 == ~t9_pc~0; 22266#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22105#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22007#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22008#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 21658#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21659#L783 assume !(1 == ~t10_pc~0); 21713#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 21714#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21903#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22228#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 22229#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23123#L802 assume 1 == ~t11_pc~0; 23105#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21601#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21602#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 22087#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 22088#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22200#L821 assume !(1 == ~t12_pc~0); 22448#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 22551#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21610#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21611#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 23164#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22795#L1339 assume !(1 == ~M_E~0); 22796#L1339-2 assume !(1 == ~T1_E~0); 23194#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23195#L1349-1 assume !(1 == ~T3_E~0); 22572#L1354-1 assume !(1 == ~T4_E~0); 22573#L1359-1 assume !(1 == ~T5_E~0); 22979#L1364-1 assume !(1 == ~T6_E~0); 22038#L1369-1 assume !(1 == ~T7_E~0); 22039#L1374-1 assume !(1 == ~T8_E~0); 22574#L1379-1 assume !(1 == ~T9_E~0); 22575#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22683#L1389-1 assume !(1 == ~T11_E~0); 23159#L1394-1 assume !(1 == ~T12_E~0); 23160#L1399-1 assume !(1 == ~E_M~0); 23241#L1404-1 assume !(1 == ~E_1~0); 22129#L1409-1 assume !(1 == ~E_2~0); 22130#L1414-1 assume !(1 == ~E_3~0); 22861#L1419-1 assume !(1 == ~E_4~0); 21772#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 21773#L1429-1 assume !(1 == ~E_6~0); 22586#L1434-1 assume !(1 == ~E_7~0); 23176#L1439-1 assume !(1 == ~E_8~0); 21814#L1444-1 assume !(1 == ~E_9~0); 21815#L1449-1 assume !(1 == ~E_10~0); 22187#L1454-1 assume !(1 == ~E_11~0); 22188#L1459-1 assume !(1 == ~E_12~0); 22713#L1464-1 assume { :end_inline_reset_delta_events } true; 21948#L1810-2 [2022-12-13 15:11:59,437 INFO L750 eck$LassoCheckResult]: Loop: 21948#L1810-2 assume !false; 22388#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22925#L1176 assume !false; 22871#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22434#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21640#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 22923#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 23102#L1003 assume !(0 != eval_~tmp~0#1); 22395#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22131#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22132#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22815#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22816#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22711#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21891#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21892#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22360#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21969#L1231-3 assume !(0 == ~T7_E~0); 21970#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22213#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23207#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 23108#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 22803#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21911#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21912#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21959#L1271-3 assume !(0 == ~E_2~0); 21960#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22335#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22336#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22859#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22860#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23280#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23238#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22440#L1311-3 assume !(0 == ~E_10~0); 21837#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 21838#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 21913#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22550#L593-42 assume 1 == ~m_pc~0; 22946#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22716#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22237#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22238#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21736#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21737#L612-42 assume !(1 == ~t1_pc~0); 22670#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 23061#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23289#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21826#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21827#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22513#L631-42 assume 1 == ~t2_pc~0; 21588#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21589#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22497#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22386#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22387#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21983#L650-42 assume 1 == ~t3_pc~0; 21553#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21554#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22891#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22178#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22179#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23178#L669-42 assume 1 == ~t4_pc~0; 22453#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21550#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22961#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22869#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 22768#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22769#L688-42 assume 1 == ~t5_pc~0; 22856#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23063#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22562#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21758#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21759#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21579#L707-42 assume !(1 == ~t6_pc~0); 21580#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 23244#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21905#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21906#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22737#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22738#L726-42 assume 1 == ~t7_pc~0; 23011#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23044#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22589#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22443#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22444#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22554#L745-42 assume !(1 == ~t8_pc~0); 22592#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 22593#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22759#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21569#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21570#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22292#L764-42 assume 1 == ~t9_pc~0; 22423#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22782#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22783#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21847#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21848#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21904#L783-42 assume 1 == ~t10_pc~0; 21525#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21526#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22114#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22751#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23271#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22951#L802-42 assume !(1 == ~t11_pc~0); 22048#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 21665#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21666#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21614#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 21615#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22791#L821-42 assume 1 == ~t12_pc~0; 22792#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 22155#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 22547#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 22548#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 22485#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22477#L1339-3 assume !(1 == ~M_E~0); 22478#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22647#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22755#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22164#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22165#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22765#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23265#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23174#L1374-3 assume !(1 == ~T8_E~0); 21987#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21988#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22162#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22163#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 22374#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 23183#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23152#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23153#L1414-3 assume !(1 == ~E_3~0); 23206#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22954#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21869#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21870#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22764#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21802#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21803#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 21916#L1454-3 assume !(1 == ~E_11~0); 22760#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 22761#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22405#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21705#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21896#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 21897#L1829 assume !(0 == start_simulation_~tmp~3#1); 21687#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 21688#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 22483#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21594#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 21595#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22776#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23158#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 21947#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 21948#L1810-2 [2022-12-13 15:11:59,437 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:59,438 INFO L85 PathProgramCache]: Analyzing trace with hash -563283220, now seen corresponding path program 1 times [2022-12-13 15:11:59,438 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:59,438 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1619654627] [2022-12-13 15:11:59,438 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:59,438 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:59,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:59,468 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:59,469 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:59,469 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1619654627] [2022-12-13 15:11:59,469 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1619654627] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:59,469 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:59,469 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:11:59,469 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [527582940] [2022-12-13 15:11:59,469 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:59,470 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:11:59,470 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:59,470 INFO L85 PathProgramCache]: Analyzing trace with hash 1726478675, now seen corresponding path program 1 times [2022-12-13 15:11:59,470 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:59,470 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [749947592] [2022-12-13 15:11:59,471 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:59,471 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:59,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:59,520 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:59,520 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:59,520 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [749947592] [2022-12-13 15:11:59,520 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [749947592] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:59,521 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:59,521 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:11:59,521 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [212495688] [2022-12-13 15:11:59,521 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:59,521 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:11:59,521 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:11:59,522 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:11:59,522 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:11:59,522 INFO L87 Difference]: Start difference. First operand 1788 states and 2646 transitions. cyclomatic complexity: 859 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:59,545 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:11:59,545 INFO L93 Difference]: Finished difference Result 1788 states and 2645 transitions. [2022-12-13 15:11:59,545 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2645 transitions. [2022-12-13 15:11:59,549 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-12-13 15:11:59,554 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2645 transitions. [2022-12-13 15:11:59,554 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-12-13 15:11:59,555 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-12-13 15:11:59,555 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2645 transitions. [2022-12-13 15:11:59,557 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:11:59,557 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2645 transitions. [2022-12-13 15:11:59,559 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2645 transitions. [2022-12-13 15:11:59,572 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-12-13 15:11:59,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4793064876957494) internal successors, (2645), 1787 states have internal predecessors, (2645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:59,577 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2645 transitions. [2022-12-13 15:11:59,577 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2645 transitions. [2022-12-13 15:11:59,578 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:11:59,578 INFO L428 stractBuchiCegarLoop]: Abstraction has 1788 states and 2645 transitions. [2022-12-13 15:11:59,578 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 15:11:59,578 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2645 transitions. [2022-12-13 15:11:59,582 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-12-13 15:11:59,582 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:11:59,582 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:11:59,583 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:59,583 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:59,583 INFO L748 eck$LassoCheckResult]: Stem: 25383#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 25384#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 26206#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26207#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26803#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 26804#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25890#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25686#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25097#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25098#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26318#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26424#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 26866#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 26867#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25816#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25817#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 26346#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 26269#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25852#L1201 assume !(0 == ~M_E~0); 25853#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26713#L1206-1 assume !(0 == ~T2_E~0); 26696#L1211-1 assume !(0 == ~T3_E~0); 26697#L1216-1 assume !(0 == ~T4_E~0); 25668#L1221-1 assume !(0 == ~T5_E~0); 25669#L1226-1 assume !(0 == ~T6_E~0); 25309#L1231-1 assume !(0 == ~T7_E~0); 25310#L1236-1 assume !(0 == ~T8_E~0); 26737#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25705#L1246-1 assume !(0 == ~T10_E~0); 25706#L1251-1 assume !(0 == ~T11_E~0); 25850#L1256-1 assume !(0 == ~T12_E~0); 25106#L1261-1 assume !(0 == ~E_M~0); 25107#L1266-1 assume !(0 == ~E_1~0); 26851#L1271-1 assume !(0 == ~E_2~0); 26408#L1276-1 assume !(0 == ~E_3~0); 26409#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 26358#L1286-1 assume !(0 == ~E_5~0); 25564#L1291-1 assume !(0 == ~E_6~0); 25565#L1296-1 assume !(0 == ~E_7~0); 26142#L1301-1 assume !(0 == ~E_8~0); 26143#L1306-1 assume !(0 == ~E_9~0); 26630#L1311-1 assume !(0 == ~E_10~0); 25518#L1316-1 assume !(0 == ~E_11~0); 25519#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 26161#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26162#L593 assume 1 == ~m_pc~0; 26311#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25408#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26053#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26054#L1492 assume !(0 != activate_threads_~tmp~1#1); 26368#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26665#L612 assume !(1 == ~t1_pc~0); 26666#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26799#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26504#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25411#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25412#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25832#L631 assume 1 == ~t2_pc~0; 25763#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25187#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25188#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25532#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 26018#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25481#L650 assume !(1 == ~t3_pc~0); 25482#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26184#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26484#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25144#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 25145#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26339#L669 assume 1 == ~t4_pc~0; 26340#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26704#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25229#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25230#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 25346#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25574#L688 assume !(1 == ~t5_pc~0); 25365#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 25366#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26832#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26226#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 26227#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26356#L707 assume 1 == ~t6_pc~0; 26770#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25987#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25520#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25521#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 26297#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25851#L726 assume 1 == ~t7_pc~0; 25753#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25448#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26495#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26774#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 25215#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25216#L745 assume !(1 == ~t8_pc~0); 25660#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25680#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26719#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26062#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26063#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26585#L764 assume 1 == ~t9_pc~0; 25849#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25688#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25590#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25591#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 25241#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25242#L783 assume !(1 == ~t10_pc~0); 25296#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25297#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25486#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25808#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 25809#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26706#L802 assume 1 == ~t11_pc~0; 26688#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25184#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25185#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25670#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 25671#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25783#L821 assume !(1 == ~t12_pc~0); 26031#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 26134#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25193#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25194#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 26747#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26378#L1339 assume !(1 == ~M_E~0); 26379#L1339-2 assume !(1 == ~T1_E~0); 26777#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26778#L1349-1 assume !(1 == ~T3_E~0); 26155#L1354-1 assume !(1 == ~T4_E~0); 26156#L1359-1 assume !(1 == ~T5_E~0); 26562#L1364-1 assume !(1 == ~T6_E~0); 25621#L1369-1 assume !(1 == ~T7_E~0); 25622#L1374-1 assume !(1 == ~T8_E~0); 26157#L1379-1 assume !(1 == ~T9_E~0); 26158#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 26266#L1389-1 assume !(1 == ~T11_E~0); 26742#L1394-1 assume !(1 == ~T12_E~0); 26743#L1399-1 assume !(1 == ~E_M~0); 26824#L1404-1 assume !(1 == ~E_1~0); 25712#L1409-1 assume !(1 == ~E_2~0); 25713#L1414-1 assume !(1 == ~E_3~0); 26444#L1419-1 assume !(1 == ~E_4~0); 25355#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 25356#L1429-1 assume !(1 == ~E_6~0); 26169#L1434-1 assume !(1 == ~E_7~0); 26759#L1439-1 assume !(1 == ~E_8~0); 25397#L1444-1 assume !(1 == ~E_9~0); 25398#L1449-1 assume !(1 == ~E_10~0); 25770#L1454-1 assume !(1 == ~E_11~0); 25771#L1459-1 assume !(1 == ~E_12~0); 26296#L1464-1 assume { :end_inline_reset_delta_events } true; 25531#L1810-2 [2022-12-13 15:11:59,584 INFO L750 eck$LassoCheckResult]: Loop: 25531#L1810-2 assume !false; 25971#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26508#L1176 assume !false; 26454#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26015#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25223#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 26506#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 26685#L1003 assume !(0 != eval_~tmp~0#1); 25978#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25714#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25715#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26398#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26399#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26294#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25474#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25475#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25943#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25550#L1231-3 assume !(0 == ~T7_E~0); 25551#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25796#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 26790#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 26691#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 26386#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 25494#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25495#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25542#L1271-3 assume !(0 == ~E_2~0); 25543#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25918#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25919#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26442#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 26443#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26863#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26821#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26023#L1311-3 assume !(0 == ~E_10~0); 25420#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25421#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 25496#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26133#L593-42 assume 1 == ~m_pc~0; 26529#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26299#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25820#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25821#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25316#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25317#L612-42 assume !(1 == ~t1_pc~0); 26253#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 26644#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26872#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25409#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25410#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26097#L631-42 assume 1 == ~t2_pc~0; 25174#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25175#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26082#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25969#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25970#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25569#L650-42 assume 1 == ~t3_pc~0; 25139#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25140#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26474#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25761#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25762#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26761#L669-42 assume 1 == ~t4_pc~0; 26039#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25135#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26544#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26452#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 26351#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26352#L688-42 assume 1 == ~t5_pc~0; 26439#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26646#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26145#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25344#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25345#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25164#L707-42 assume !(1 == ~t6_pc~0); 25165#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 26829#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25488#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25489#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26319#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26320#L726-42 assume !(1 == ~t7_pc~0); 26592#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 26627#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26172#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26026#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26027#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26137#L745-42 assume 1 == ~t8_pc~0; 26174#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26176#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26342#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25152#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25153#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25875#L764-42 assume 1 == ~t9_pc~0; 26006#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26365#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26366#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25430#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25431#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25487#L783-42 assume 1 == ~t10_pc~0; 25108#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25109#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25695#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26334#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26854#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26534#L802-42 assume 1 == ~t11_pc~0; 25630#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25248#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25249#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25197#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25198#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 26374#L821-42 assume 1 == ~t12_pc~0; 26375#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 25738#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 26130#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 26131#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 26068#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26057#L1339-3 assume !(1 == ~M_E~0); 26058#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26230#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26338#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25747#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25748#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26348#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26848#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26757#L1374-3 assume !(1 == ~T8_E~0); 25570#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25571#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25745#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25746#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 25957#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26766#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26735#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26736#L1414-3 assume !(1 == ~E_3~0); 26789#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26537#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25452#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25453#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 26347#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25385#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25386#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25499#L1454-3 assume !(1 == ~E_11~0); 26343#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 26344#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25988#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25288#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25479#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 25480#L1829 assume !(0 == start_simulation_~tmp~3#1); 25270#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25271#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 26066#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25177#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 25178#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26359#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26741#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 25530#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 25531#L1810-2 [2022-12-13 15:11:59,584 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:59,584 INFO L85 PathProgramCache]: Analyzing trace with hash -973893586, now seen corresponding path program 1 times [2022-12-13 15:11:59,584 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:59,585 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [788466059] [2022-12-13 15:11:59,585 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:59,585 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:59,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:59,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:59,614 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:59,614 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [788466059] [2022-12-13 15:11:59,614 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [788466059] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:59,614 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:59,614 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:11:59,615 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1183783783] [2022-12-13 15:11:59,615 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:59,615 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:11:59,615 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:59,615 INFO L85 PathProgramCache]: Analyzing trace with hash -1464176750, now seen corresponding path program 1 times [2022-12-13 15:11:59,616 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:59,616 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1197322890] [2022-12-13 15:11:59,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:59,616 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:59,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:59,654 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:59,654 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:59,654 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1197322890] [2022-12-13 15:11:59,655 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1197322890] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:59,655 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:59,655 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:11:59,655 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1474199166] [2022-12-13 15:11:59,655 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:59,655 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:11:59,656 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:11:59,656 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:11:59,656 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:11:59,656 INFO L87 Difference]: Start difference. First operand 1788 states and 2645 transitions. cyclomatic complexity: 858 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:59,683 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:11:59,683 INFO L93 Difference]: Finished difference Result 1788 states and 2644 transitions. [2022-12-13 15:11:59,684 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2644 transitions. [2022-12-13 15:11:59,688 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-12-13 15:11:59,692 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2644 transitions. [2022-12-13 15:11:59,692 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-12-13 15:11:59,693 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-12-13 15:11:59,693 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2644 transitions. [2022-12-13 15:11:59,695 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:11:59,695 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2644 transitions. [2022-12-13 15:11:59,697 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2644 transitions. [2022-12-13 15:11:59,721 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-12-13 15:11:59,723 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4787472035794182) internal successors, (2644), 1787 states have internal predecessors, (2644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:59,726 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2644 transitions. [2022-12-13 15:11:59,726 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2644 transitions. [2022-12-13 15:11:59,727 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:11:59,727 INFO L428 stractBuchiCegarLoop]: Abstraction has 1788 states and 2644 transitions. [2022-12-13 15:11:59,727 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 15:11:59,727 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2644 transitions. [2022-12-13 15:11:59,732 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-12-13 15:11:59,732 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:11:59,733 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:11:59,733 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:59,734 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:59,734 INFO L748 eck$LassoCheckResult]: Stem: 28966#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 28967#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 29789#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29790#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30386#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 30387#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29473#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29269#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28680#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28681#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29901#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30007#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 30449#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 30450#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29399#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29400#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29929#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29852#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29435#L1201 assume !(0 == ~M_E~0); 29436#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30296#L1206-1 assume !(0 == ~T2_E~0); 30279#L1211-1 assume !(0 == ~T3_E~0); 30280#L1216-1 assume !(0 == ~T4_E~0); 29250#L1221-1 assume !(0 == ~T5_E~0); 29251#L1226-1 assume !(0 == ~T6_E~0); 28892#L1231-1 assume !(0 == ~T7_E~0); 28893#L1236-1 assume !(0 == ~T8_E~0); 30320#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29288#L1246-1 assume !(0 == ~T10_E~0); 29289#L1251-1 assume !(0 == ~T11_E~0); 29433#L1256-1 assume !(0 == ~T12_E~0); 28689#L1261-1 assume !(0 == ~E_M~0); 28690#L1266-1 assume !(0 == ~E_1~0); 30434#L1271-1 assume !(0 == ~E_2~0); 29991#L1276-1 assume !(0 == ~E_3~0); 29992#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 29941#L1286-1 assume !(0 == ~E_5~0); 29147#L1291-1 assume !(0 == ~E_6~0); 29148#L1296-1 assume !(0 == ~E_7~0); 29725#L1301-1 assume !(0 == ~E_8~0); 29726#L1306-1 assume !(0 == ~E_9~0); 30213#L1311-1 assume !(0 == ~E_10~0); 29101#L1316-1 assume !(0 == ~E_11~0); 29102#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 29744#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29745#L593 assume 1 == ~m_pc~0; 29894#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28991#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29636#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29637#L1492 assume !(0 != activate_threads_~tmp~1#1); 29951#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30248#L612 assume !(1 == ~t1_pc~0); 30249#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30382#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30087#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28994#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28995#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29415#L631 assume 1 == ~t2_pc~0; 29346#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28770#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28771#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29115#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 29601#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29062#L650 assume !(1 == ~t3_pc~0); 29063#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29767#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30067#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28727#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 28728#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29922#L669 assume 1 == ~t4_pc~0; 29923#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30287#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28808#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28809#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 28929#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29157#L688 assume !(1 == ~t5_pc~0); 28948#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 28949#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30415#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29809#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 29810#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29936#L707 assume 1 == ~t6_pc~0; 30353#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29570#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29103#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29104#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 29880#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29434#L726 assume 1 == ~t7_pc~0; 29334#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29031#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30078#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30357#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 28798#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28799#L745 assume !(1 == ~t8_pc~0); 29243#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 29263#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30302#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29645#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29646#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30168#L764 assume 1 == ~t9_pc~0; 29432#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29271#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29173#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29174#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 28824#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28825#L783 assume !(1 == ~t10_pc~0); 28879#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 28880#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29069#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29389#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 29390#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30289#L802 assume 1 == ~t11_pc~0; 30271#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28767#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28768#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29252#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 29253#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29366#L821 assume !(1 == ~t12_pc~0); 29614#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 29717#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28774#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28775#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 30330#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29961#L1339 assume !(1 == ~M_E~0); 29962#L1339-2 assume !(1 == ~T1_E~0); 30360#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30361#L1349-1 assume !(1 == ~T3_E~0); 29737#L1354-1 assume !(1 == ~T4_E~0); 29738#L1359-1 assume !(1 == ~T5_E~0); 30145#L1364-1 assume !(1 == ~T6_E~0); 29204#L1369-1 assume !(1 == ~T7_E~0); 29205#L1374-1 assume !(1 == ~T8_E~0); 29740#L1379-1 assume !(1 == ~T9_E~0); 29741#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29849#L1389-1 assume !(1 == ~T11_E~0); 30325#L1394-1 assume !(1 == ~T12_E~0); 30326#L1399-1 assume !(1 == ~E_M~0); 30407#L1404-1 assume !(1 == ~E_1~0); 29295#L1409-1 assume !(1 == ~E_2~0); 29296#L1414-1 assume !(1 == ~E_3~0); 30027#L1419-1 assume !(1 == ~E_4~0); 28938#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 28939#L1429-1 assume !(1 == ~E_6~0); 29752#L1434-1 assume !(1 == ~E_7~0); 30342#L1439-1 assume !(1 == ~E_8~0); 28980#L1444-1 assume !(1 == ~E_9~0); 28981#L1449-1 assume !(1 == ~E_10~0); 29351#L1454-1 assume !(1 == ~E_11~0); 29352#L1459-1 assume !(1 == ~E_12~0); 29879#L1464-1 assume { :end_inline_reset_delta_events } true; 29114#L1810-2 [2022-12-13 15:11:59,734 INFO L750 eck$LassoCheckResult]: Loop: 29114#L1810-2 assume !false; 29554#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30091#L1176 assume !false; 30037#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29598#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 28806#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 30089#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 30266#L1003 assume !(0 != eval_~tmp~0#1); 29561#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29297#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29298#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29981#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29982#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29877#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29057#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29058#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29526#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29133#L1231-3 assume !(0 == ~T7_E~0); 29134#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29378#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30373#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30274#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29969#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 29077#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29078#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29125#L1271-3 assume !(0 == ~E_2~0); 29126#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29501#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29502#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30024#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30025#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30446#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30404#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29606#L1311-3 assume !(0 == ~E_10~0); 29003#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 29004#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 29079#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29716#L593-42 assume !(1 == ~m_pc~0); 29881#L593-44 is_master_triggered_~__retres1~0#1 := 0; 29882#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29401#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29402#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28899#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28900#L612-42 assume !(1 == ~t1_pc~0); 29836#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 30226#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30455#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28992#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28993#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29680#L631-42 assume 1 == ~t2_pc~0; 28754#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28755#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29665#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29552#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29553#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29152#L650-42 assume !(1 == ~t3_pc~0); 28721#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 28720#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30057#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29344#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29345#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30344#L669-42 assume 1 == ~t4_pc~0; 29619#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28718#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30127#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30035#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 29934#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29935#L688-42 assume 1 == ~t5_pc~0; 30022#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30229#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29728#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28927#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28928#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28747#L707-42 assume !(1 == ~t6_pc~0); 28748#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 30410#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29071#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29072#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29903#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29904#L726-42 assume 1 == ~t7_pc~0; 30177#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30210#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29755#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29609#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29610#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29720#L745-42 assume 1 == ~t8_pc~0; 29758#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29760#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29925#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28735#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28736#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29460#L764-42 assume 1 == ~t9_pc~0; 29589#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29948#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29949#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29013#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29014#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29070#L783-42 assume 1 == ~t10_pc~0; 28691#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28692#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29280#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29917#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30437#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30117#L802-42 assume 1 == ~t11_pc~0; 29213#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28831#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28832#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28780#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28781#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29957#L821-42 assume 1 == ~t12_pc~0; 29958#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 29321#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 29713#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29714#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 29651#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29643#L1339-3 assume !(1 == ~M_E~0); 29644#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29813#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29921#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29330#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29331#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29931#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30431#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30340#L1374-3 assume !(1 == ~T8_E~0); 29154#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29155#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29328#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29329#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 29540#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30349#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30318#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30319#L1414-3 assume !(1 == ~E_3~0); 30372#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30120#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29035#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29036#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 29930#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28968#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28969#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29082#L1454-3 assume !(1 == ~E_11~0); 29926#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 29927#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29571#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 28871#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29065#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 29066#L1829 assume !(0 == start_simulation_~tmp~3#1); 28853#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 28854#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29649#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 28760#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 28761#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29942#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30324#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 29113#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 29114#L1810-2 [2022-12-13 15:11:59,734 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:59,735 INFO L85 PathProgramCache]: Analyzing trace with hash 813976236, now seen corresponding path program 1 times [2022-12-13 15:11:59,735 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:59,735 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [179422028] [2022-12-13 15:11:59,735 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:59,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:59,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:59,765 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:59,765 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:59,765 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [179422028] [2022-12-13 15:11:59,766 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [179422028] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:59,766 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:59,766 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:11:59,766 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1970004246] [2022-12-13 15:11:59,766 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:59,766 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:11:59,767 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:59,767 INFO L85 PathProgramCache]: Analyzing trace with hash -3363501, now seen corresponding path program 1 times [2022-12-13 15:11:59,767 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:59,767 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1520330544] [2022-12-13 15:11:59,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:59,768 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:59,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:59,807 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:59,807 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:59,807 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1520330544] [2022-12-13 15:11:59,808 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1520330544] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:59,808 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:59,808 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:11:59,808 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1602575445] [2022-12-13 15:11:59,808 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:59,808 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:11:59,808 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:11:59,809 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:11:59,809 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:11:59,809 INFO L87 Difference]: Start difference. First operand 1788 states and 2644 transitions. cyclomatic complexity: 857 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:59,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:11:59,833 INFO L93 Difference]: Finished difference Result 1788 states and 2643 transitions. [2022-12-13 15:11:59,833 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2643 transitions. [2022-12-13 15:11:59,837 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-12-13 15:11:59,841 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2643 transitions. [2022-12-13 15:11:59,842 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-12-13 15:11:59,842 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-12-13 15:11:59,842 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2643 transitions. [2022-12-13 15:11:59,844 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:11:59,844 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2643 transitions. [2022-12-13 15:11:59,846 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2643 transitions. [2022-12-13 15:11:59,858 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-12-13 15:11:59,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4781879194630871) internal successors, (2643), 1787 states have internal predecessors, (2643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:59,862 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2643 transitions. [2022-12-13 15:11:59,863 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2643 transitions. [2022-12-13 15:11:59,863 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:11:59,863 INFO L428 stractBuchiCegarLoop]: Abstraction has 1788 states and 2643 transitions. [2022-12-13 15:11:59,863 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 15:11:59,863 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2643 transitions. [2022-12-13 15:11:59,868 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-12-13 15:11:59,869 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:11:59,869 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:11:59,870 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:59,870 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:59,870 INFO L748 eck$LassoCheckResult]: Stem: 32549#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 32550#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 33372#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33373#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33969#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 33970#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33056#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32852#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32263#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32264#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33484#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33590#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34032#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 34033#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 32982#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 32983#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33512#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33435#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33018#L1201 assume !(0 == ~M_E~0); 33019#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33879#L1206-1 assume !(0 == ~T2_E~0); 33862#L1211-1 assume !(0 == ~T3_E~0); 33863#L1216-1 assume !(0 == ~T4_E~0); 32833#L1221-1 assume !(0 == ~T5_E~0); 32834#L1226-1 assume !(0 == ~T6_E~0); 32475#L1231-1 assume !(0 == ~T7_E~0); 32476#L1236-1 assume !(0 == ~T8_E~0); 33903#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32871#L1246-1 assume !(0 == ~T10_E~0); 32872#L1251-1 assume !(0 == ~T11_E~0); 33016#L1256-1 assume !(0 == ~T12_E~0); 32272#L1261-1 assume !(0 == ~E_M~0); 32273#L1266-1 assume !(0 == ~E_1~0); 34017#L1271-1 assume !(0 == ~E_2~0); 33574#L1276-1 assume !(0 == ~E_3~0); 33575#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 33524#L1286-1 assume !(0 == ~E_5~0); 32730#L1291-1 assume !(0 == ~E_6~0); 32731#L1296-1 assume !(0 == ~E_7~0); 33308#L1301-1 assume !(0 == ~E_8~0); 33309#L1306-1 assume !(0 == ~E_9~0); 33796#L1311-1 assume !(0 == ~E_10~0); 32684#L1316-1 assume !(0 == ~E_11~0); 32685#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 33327#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33328#L593 assume 1 == ~m_pc~0; 33477#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32574#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33219#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33220#L1492 assume !(0 != activate_threads_~tmp~1#1); 33534#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33831#L612 assume !(1 == ~t1_pc~0); 33832#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 33965#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33670#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32577#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32578#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32998#L631 assume 1 == ~t2_pc~0; 32929#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32353#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32354#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32698#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 33184#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32645#L650 assume !(1 == ~t3_pc~0); 32646#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33350#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33650#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32310#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 32311#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33505#L669 assume 1 == ~t4_pc~0; 33506#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33870#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32391#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32392#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 32512#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32740#L688 assume !(1 == ~t5_pc~0); 32531#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 32532#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33998#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33392#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 33393#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33519#L707 assume 1 == ~t6_pc~0; 33936#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33153#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32686#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32687#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 33463#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33017#L726 assume 1 == ~t7_pc~0; 32917#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32614#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33661#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33940#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 32381#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32382#L745 assume !(1 == ~t8_pc~0); 32826#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 32846#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33885#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33228#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33229#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33751#L764 assume 1 == ~t9_pc~0; 33015#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32854#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32756#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32757#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 32407#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32408#L783 assume !(1 == ~t10_pc~0); 32462#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 32463#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32652#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 32972#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 32973#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33872#L802 assume 1 == ~t11_pc~0; 33854#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32350#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32351#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32835#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 32836#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32949#L821 assume !(1 == ~t12_pc~0); 33197#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 33300#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32357#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32358#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 33913#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33544#L1339 assume !(1 == ~M_E~0); 33545#L1339-2 assume !(1 == ~T1_E~0); 33943#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33944#L1349-1 assume !(1 == ~T3_E~0); 33320#L1354-1 assume !(1 == ~T4_E~0); 33321#L1359-1 assume !(1 == ~T5_E~0); 33728#L1364-1 assume !(1 == ~T6_E~0); 32787#L1369-1 assume !(1 == ~T7_E~0); 32788#L1374-1 assume !(1 == ~T8_E~0); 33323#L1379-1 assume !(1 == ~T9_E~0); 33324#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33432#L1389-1 assume !(1 == ~T11_E~0); 33908#L1394-1 assume !(1 == ~T12_E~0); 33909#L1399-1 assume !(1 == ~E_M~0); 33990#L1404-1 assume !(1 == ~E_1~0); 32878#L1409-1 assume !(1 == ~E_2~0); 32879#L1414-1 assume !(1 == ~E_3~0); 33610#L1419-1 assume !(1 == ~E_4~0); 32521#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 32522#L1429-1 assume !(1 == ~E_6~0); 33335#L1434-1 assume !(1 == ~E_7~0); 33925#L1439-1 assume !(1 == ~E_8~0); 32563#L1444-1 assume !(1 == ~E_9~0); 32564#L1449-1 assume !(1 == ~E_10~0); 32934#L1454-1 assume !(1 == ~E_11~0); 32935#L1459-1 assume !(1 == ~E_12~0); 33462#L1464-1 assume { :end_inline_reset_delta_events } true; 32697#L1810-2 [2022-12-13 15:11:59,870 INFO L750 eck$LassoCheckResult]: Loop: 32697#L1810-2 assume !false; 33137#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33674#L1176 assume !false; 33620#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33181#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32389#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 33672#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 33849#L1003 assume !(0 != eval_~tmp~0#1); 33144#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32880#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32881#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33564#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33565#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33460#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32640#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32641#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33109#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32716#L1231-3 assume !(0 == ~T7_E~0); 32717#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32961#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33956#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33857#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 33552#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 32660#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 32661#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32708#L1271-3 assume !(0 == ~E_2~0); 32709#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33084#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33085#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33607#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33608#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34029#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33987#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 33189#L1311-3 assume !(0 == ~E_10~0); 32586#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32587#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 32662#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33299#L593-42 assume !(1 == ~m_pc~0); 33464#L593-44 is_master_triggered_~__retres1~0#1 := 0; 33465#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32984#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32985#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32482#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32483#L612-42 assume !(1 == ~t1_pc~0); 33419#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 33809#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34038#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32575#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32576#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33263#L631-42 assume 1 == ~t2_pc~0; 32337#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32338#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33248#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33135#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33136#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32735#L650-42 assume !(1 == ~t3_pc~0); 32304#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 32303#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33640#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32927#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32928#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33927#L669-42 assume 1 == ~t4_pc~0; 33202#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32301#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33710#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33618#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 33517#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33518#L688-42 assume 1 == ~t5_pc~0; 33605#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33812#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33311#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32510#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 32511#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32330#L707-42 assume !(1 == ~t6_pc~0); 32331#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 33993#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32654#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32655#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33486#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33487#L726-42 assume 1 == ~t7_pc~0; 33760#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33793#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33338#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33192#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33193#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33303#L745-42 assume 1 == ~t8_pc~0; 33341#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33343#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33508#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32318#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32319#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33043#L764-42 assume 1 == ~t9_pc~0; 33172#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33531#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33532#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32596#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 32597#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32653#L783-42 assume 1 == ~t10_pc~0; 32274#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 32275#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32863#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33500#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34020#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33700#L802-42 assume 1 == ~t11_pc~0; 32796#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32414#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32415#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32363#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32364#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33540#L821-42 assume 1 == ~t12_pc~0; 33541#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 32904#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 33296#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 33297#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 33234#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33226#L1339-3 assume !(1 == ~M_E~0); 33227#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33396#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33504#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32913#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32914#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33514#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34014#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33923#L1374-3 assume !(1 == ~T8_E~0); 32737#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32738#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32911#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 32912#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 33123#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33932#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33901#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33902#L1414-3 assume !(1 == ~E_3~0); 33955#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33703#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32618#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32619#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33513#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32551#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32552#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32665#L1454-3 assume !(1 == ~E_11~0); 33509#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 33510#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33154#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32454#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32648#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 32649#L1829 assume !(0 == start_simulation_~tmp~3#1); 32436#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 32437#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 33232#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32343#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 32344#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33525#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33907#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 32696#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 32697#L1810-2 [2022-12-13 15:11:59,871 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:59,871 INFO L85 PathProgramCache]: Analyzing trace with hash -1345107858, now seen corresponding path program 1 times [2022-12-13 15:11:59,871 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:59,871 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [86913045] [2022-12-13 15:11:59,871 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:59,871 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:59,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:59,912 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:59,912 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:59,913 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [86913045] [2022-12-13 15:11:59,913 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [86913045] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:59,913 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:59,913 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:11:59,913 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [371082971] [2022-12-13 15:11:59,913 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:59,913 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:11:59,913 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:59,914 INFO L85 PathProgramCache]: Analyzing trace with hash -3363501, now seen corresponding path program 2 times [2022-12-13 15:11:59,914 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:59,914 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1829600386] [2022-12-13 15:11:59,914 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:59,914 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:59,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:59,951 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:59,951 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:59,952 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1829600386] [2022-12-13 15:11:59,952 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1829600386] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:59,952 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:59,952 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:11:59,952 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1926747833] [2022-12-13 15:11:59,952 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:59,952 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:11:59,952 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:11:59,952 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:11:59,953 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:11:59,953 INFO L87 Difference]: Start difference. First operand 1788 states and 2643 transitions. cyclomatic complexity: 856 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:59,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:11:59,972 INFO L93 Difference]: Finished difference Result 1788 states and 2642 transitions. [2022-12-13 15:11:59,972 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2642 transitions. [2022-12-13 15:11:59,977 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-12-13 15:11:59,981 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2642 transitions. [2022-12-13 15:11:59,981 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-12-13 15:11:59,982 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-12-13 15:11:59,982 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2642 transitions. [2022-12-13 15:11:59,984 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:11:59,984 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2642 transitions. [2022-12-13 15:11:59,986 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2642 transitions. [2022-12-13 15:11:59,998 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-12-13 15:12:00,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4776286353467563) internal successors, (2642), 1787 states have internal predecessors, (2642), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:00,002 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2642 transitions. [2022-12-13 15:12:00,002 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2642 transitions. [2022-12-13 15:12:00,002 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:12:00,003 INFO L428 stractBuchiCegarLoop]: Abstraction has 1788 states and 2642 transitions. [2022-12-13 15:12:00,003 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 15:12:00,003 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2642 transitions. [2022-12-13 15:12:00,006 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-12-13 15:12:00,006 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:00,006 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:00,007 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:00,007 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:00,007 INFO L748 eck$LassoCheckResult]: Stem: 36132#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 36133#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 36955#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 36956#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37552#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 37553#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36639#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36435#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35846#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35847#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37067#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37173#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37615#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37616#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36565#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36566#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37095#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 37018#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36601#L1201 assume !(0 == ~M_E~0); 36602#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37462#L1206-1 assume !(0 == ~T2_E~0); 37445#L1211-1 assume !(0 == ~T3_E~0); 37446#L1216-1 assume !(0 == ~T4_E~0); 36416#L1221-1 assume !(0 == ~T5_E~0); 36417#L1226-1 assume !(0 == ~T6_E~0); 36058#L1231-1 assume !(0 == ~T7_E~0); 36059#L1236-1 assume !(0 == ~T8_E~0); 37486#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36454#L1246-1 assume !(0 == ~T10_E~0); 36455#L1251-1 assume !(0 == ~T11_E~0); 36599#L1256-1 assume !(0 == ~T12_E~0); 35855#L1261-1 assume !(0 == ~E_M~0); 35856#L1266-1 assume !(0 == ~E_1~0); 37600#L1271-1 assume !(0 == ~E_2~0); 37157#L1276-1 assume !(0 == ~E_3~0); 37158#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 37107#L1286-1 assume !(0 == ~E_5~0); 36313#L1291-1 assume !(0 == ~E_6~0); 36314#L1296-1 assume !(0 == ~E_7~0); 36891#L1301-1 assume !(0 == ~E_8~0); 36892#L1306-1 assume !(0 == ~E_9~0); 37379#L1311-1 assume !(0 == ~E_10~0); 36267#L1316-1 assume !(0 == ~E_11~0); 36268#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 36910#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36911#L593 assume 1 == ~m_pc~0; 37060#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36157#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36802#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36803#L1492 assume !(0 != activate_threads_~tmp~1#1); 37117#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37414#L612 assume !(1 == ~t1_pc~0); 37415#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 37548#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37253#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36160#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36161#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36581#L631 assume 1 == ~t2_pc~0; 36512#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35936#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35937#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36281#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 36767#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36228#L650 assume !(1 == ~t3_pc~0); 36229#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 36933#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37233#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35893#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 35894#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37088#L669 assume 1 == ~t4_pc~0; 37089#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37453#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35974#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35975#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 36095#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36323#L688 assume !(1 == ~t5_pc~0); 36114#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 36115#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37581#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36975#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 36976#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37102#L707 assume 1 == ~t6_pc~0; 37519#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36736#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36269#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36270#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 37046#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36600#L726 assume 1 == ~t7_pc~0; 36500#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36197#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37244#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37523#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 35964#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35965#L745 assume !(1 == ~t8_pc~0); 36409#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 36429#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37468#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36811#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36812#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37334#L764 assume 1 == ~t9_pc~0; 36598#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36437#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36339#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36340#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 35990#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35991#L783 assume !(1 == ~t10_pc~0); 36045#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36046#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36235#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 36555#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 36556#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37455#L802 assume 1 == ~t11_pc~0; 37437#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 35933#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35934#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36418#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 36419#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36532#L821 assume !(1 == ~t12_pc~0); 36780#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 36883#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35940#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 35941#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 37496#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37127#L1339 assume !(1 == ~M_E~0); 37128#L1339-2 assume !(1 == ~T1_E~0); 37526#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37527#L1349-1 assume !(1 == ~T3_E~0); 36903#L1354-1 assume !(1 == ~T4_E~0); 36904#L1359-1 assume !(1 == ~T5_E~0); 37311#L1364-1 assume !(1 == ~T6_E~0); 36370#L1369-1 assume !(1 == ~T7_E~0); 36371#L1374-1 assume !(1 == ~T8_E~0); 36906#L1379-1 assume !(1 == ~T9_E~0); 36907#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37015#L1389-1 assume !(1 == ~T11_E~0); 37491#L1394-1 assume !(1 == ~T12_E~0); 37492#L1399-1 assume !(1 == ~E_M~0); 37573#L1404-1 assume !(1 == ~E_1~0); 36461#L1409-1 assume !(1 == ~E_2~0); 36462#L1414-1 assume !(1 == ~E_3~0); 37193#L1419-1 assume !(1 == ~E_4~0); 36104#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 36105#L1429-1 assume !(1 == ~E_6~0); 36918#L1434-1 assume !(1 == ~E_7~0); 37508#L1439-1 assume !(1 == ~E_8~0); 36146#L1444-1 assume !(1 == ~E_9~0); 36147#L1449-1 assume !(1 == ~E_10~0); 36517#L1454-1 assume !(1 == ~E_11~0); 36518#L1459-1 assume !(1 == ~E_12~0); 37045#L1464-1 assume { :end_inline_reset_delta_events } true; 36280#L1810-2 [2022-12-13 15:12:00,008 INFO L750 eck$LassoCheckResult]: Loop: 36280#L1810-2 assume !false; 36720#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37257#L1176 assume !false; 37203#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 36764#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 35972#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 37255#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 37432#L1003 assume !(0 != eval_~tmp~0#1); 36727#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36463#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36464#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37147#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37148#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37043#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36223#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36224#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36692#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36299#L1231-3 assume !(0 == ~T7_E~0); 36300#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36544#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37539#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37440#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 37135#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 36243#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36244#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36291#L1271-3 assume !(0 == ~E_2~0); 36292#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36667#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36668#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 37190#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37191#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37612#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37570#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 36772#L1311-3 assume !(0 == ~E_10~0); 36169#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36170#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 36245#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36882#L593-42 assume !(1 == ~m_pc~0); 37047#L593-44 is_master_triggered_~__retres1~0#1 := 0; 37048#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36567#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36568#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36065#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36066#L612-42 assume !(1 == ~t1_pc~0); 37002#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 37392#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37621#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36158#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36159#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36846#L631-42 assume 1 == ~t2_pc~0; 35920#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35921#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36831#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36718#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36719#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36318#L650-42 assume 1 == ~t3_pc~0; 35885#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 35886#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37223#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36510#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36511#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37510#L669-42 assume 1 == ~t4_pc~0; 36785#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 35884#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37293#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37201#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 37100#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37101#L688-42 assume 1 == ~t5_pc~0; 37188#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37395#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36894#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36093#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 36094#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35913#L707-42 assume !(1 == ~t6_pc~0); 35914#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 37576#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36237#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36238#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37069#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37070#L726-42 assume !(1 == ~t7_pc~0); 37344#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 37376#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36921#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36775#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 36776#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36886#L745-42 assume 1 == ~t8_pc~0; 36924#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36926#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37091#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35901#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35902#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36626#L764-42 assume 1 == ~t9_pc~0; 36755#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37114#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37115#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36179#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36180#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36236#L783-42 assume 1 == ~t10_pc~0; 35857#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35858#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36446#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37083#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37603#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37283#L802-42 assume 1 == ~t11_pc~0; 36379#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 35997#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35998#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 35946#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35947#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37123#L821-42 assume 1 == ~t12_pc~0; 37124#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 36487#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36879#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 36880#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 36817#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36809#L1339-3 assume !(1 == ~M_E~0); 36810#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36979#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37087#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36496#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36497#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37097#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37597#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37506#L1374-3 assume !(1 == ~T8_E~0); 36320#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36321#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36494#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 36495#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 36706#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37515#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37484#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37485#L1414-3 assume !(1 == ~E_3~0); 37538#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37286#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36201#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36202#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37096#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36134#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 36135#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 36248#L1454-3 assume !(1 == ~E_11~0); 37092#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 37093#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 36737#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36037#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36231#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 36232#L1829 assume !(0 == start_simulation_~tmp~3#1); 36019#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 36020#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36815#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 35926#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 35927#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37108#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37490#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 36279#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 36280#L1810-2 [2022-12-13 15:12:00,008 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:00,008 INFO L85 PathProgramCache]: Analyzing trace with hash -1762996560, now seen corresponding path program 1 times [2022-12-13 15:12:00,008 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:00,008 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [599942527] [2022-12-13 15:12:00,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:00,008 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:00,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:00,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:00,038 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:00,038 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [599942527] [2022-12-13 15:12:00,038 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [599942527] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:00,038 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:00,038 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:00,038 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1903776471] [2022-12-13 15:12:00,038 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:00,039 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:00,039 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:00,039 INFO L85 PathProgramCache]: Analyzing trace with hash -2046664621, now seen corresponding path program 1 times [2022-12-13 15:12:00,039 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:00,039 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [862018853] [2022-12-13 15:12:00,039 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:00,039 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:00,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:00,083 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:00,083 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:00,083 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [862018853] [2022-12-13 15:12:00,084 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [862018853] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:00,084 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:00,084 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:00,084 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1568211716] [2022-12-13 15:12:00,084 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:00,084 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:00,084 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:00,084 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:12:00,084 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:12:00,085 INFO L87 Difference]: Start difference. First operand 1788 states and 2642 transitions. cyclomatic complexity: 855 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:00,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:00,129 INFO L93 Difference]: Finished difference Result 1788 states and 2641 transitions. [2022-12-13 15:12:00,130 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2641 transitions. [2022-12-13 15:12:00,138 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-12-13 15:12:00,145 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2641 transitions. [2022-12-13 15:12:00,145 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-12-13 15:12:00,147 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-12-13 15:12:00,147 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2641 transitions. [2022-12-13 15:12:00,150 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:12:00,150 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2641 transitions. [2022-12-13 15:12:00,153 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2641 transitions. [2022-12-13 15:12:00,178 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-12-13 15:12:00,182 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4770693512304252) internal successors, (2641), 1787 states have internal predecessors, (2641), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:00,187 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2641 transitions. [2022-12-13 15:12:00,187 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2641 transitions. [2022-12-13 15:12:00,188 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:12:00,188 INFO L428 stractBuchiCegarLoop]: Abstraction has 1788 states and 2641 transitions. [2022-12-13 15:12:00,188 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 15:12:00,188 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2641 transitions. [2022-12-13 15:12:00,196 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-12-13 15:12:00,196 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:00,196 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:00,199 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:00,199 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:00,200 INFO L748 eck$LassoCheckResult]: Stem: 39715#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 39716#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 40538#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40539#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41135#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 41136#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40222#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40018#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39429#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39430#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40650#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40756#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41198#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41199#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 40148#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 40149#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 40678#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 40601#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40184#L1201 assume !(0 == ~M_E~0); 40185#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41045#L1206-1 assume !(0 == ~T2_E~0); 41028#L1211-1 assume !(0 == ~T3_E~0); 41029#L1216-1 assume !(0 == ~T4_E~0); 39999#L1221-1 assume !(0 == ~T5_E~0); 40000#L1226-1 assume !(0 == ~T6_E~0); 39641#L1231-1 assume !(0 == ~T7_E~0); 39642#L1236-1 assume !(0 == ~T8_E~0); 41069#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 40037#L1246-1 assume !(0 == ~T10_E~0); 40038#L1251-1 assume !(0 == ~T11_E~0); 40182#L1256-1 assume !(0 == ~T12_E~0); 39438#L1261-1 assume !(0 == ~E_M~0); 39439#L1266-1 assume !(0 == ~E_1~0); 41183#L1271-1 assume !(0 == ~E_2~0); 40740#L1276-1 assume !(0 == ~E_3~0); 40741#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 40690#L1286-1 assume !(0 == ~E_5~0); 39896#L1291-1 assume !(0 == ~E_6~0); 39897#L1296-1 assume !(0 == ~E_7~0); 40474#L1301-1 assume !(0 == ~E_8~0); 40475#L1306-1 assume !(0 == ~E_9~0); 40962#L1311-1 assume !(0 == ~E_10~0); 39850#L1316-1 assume !(0 == ~E_11~0); 39851#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 40493#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40494#L593 assume 1 == ~m_pc~0; 40643#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 39740#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40385#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40386#L1492 assume !(0 != activate_threads_~tmp~1#1); 40700#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40997#L612 assume !(1 == ~t1_pc~0); 40998#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 41131#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40836#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39743#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39744#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40164#L631 assume 1 == ~t2_pc~0; 40095#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39519#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39520#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39864#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 40350#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39811#L650 assume !(1 == ~t3_pc~0); 39812#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 40516#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40816#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39476#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 39477#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40671#L669 assume 1 == ~t4_pc~0; 40672#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41036#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39557#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39558#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 39678#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39906#L688 assume !(1 == ~t5_pc~0); 39697#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 39698#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41164#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40558#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 40559#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40685#L707 assume 1 == ~t6_pc~0; 41102#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40319#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39852#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 39853#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 40629#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40183#L726 assume 1 == ~t7_pc~0; 40083#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39780#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40827#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41106#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 39547#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39548#L745 assume !(1 == ~t8_pc~0); 39992#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 40012#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41051#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40394#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40395#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40917#L764 assume 1 == ~t9_pc~0; 40181#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40020#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39922#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39923#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 39573#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39574#L783 assume !(1 == ~t10_pc~0); 39628#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 39629#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39818#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40138#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 40139#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41038#L802 assume 1 == ~t11_pc~0; 41020#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39516#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39517#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 40001#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 40002#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40115#L821 assume !(1 == ~t12_pc~0); 40363#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 40466#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 39523#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 39524#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 41079#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40710#L1339 assume !(1 == ~M_E~0); 40711#L1339-2 assume !(1 == ~T1_E~0); 41109#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 41110#L1349-1 assume !(1 == ~T3_E~0); 40486#L1354-1 assume !(1 == ~T4_E~0); 40487#L1359-1 assume !(1 == ~T5_E~0); 40894#L1364-1 assume !(1 == ~T6_E~0); 39953#L1369-1 assume !(1 == ~T7_E~0); 39954#L1374-1 assume !(1 == ~T8_E~0); 40489#L1379-1 assume !(1 == ~T9_E~0); 40490#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40598#L1389-1 assume !(1 == ~T11_E~0); 41074#L1394-1 assume !(1 == ~T12_E~0); 41075#L1399-1 assume !(1 == ~E_M~0); 41156#L1404-1 assume !(1 == ~E_1~0); 40044#L1409-1 assume !(1 == ~E_2~0); 40045#L1414-1 assume !(1 == ~E_3~0); 40776#L1419-1 assume !(1 == ~E_4~0); 39687#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 39688#L1429-1 assume !(1 == ~E_6~0); 40501#L1434-1 assume !(1 == ~E_7~0); 41091#L1439-1 assume !(1 == ~E_8~0); 39729#L1444-1 assume !(1 == ~E_9~0); 39730#L1449-1 assume !(1 == ~E_10~0); 40100#L1454-1 assume !(1 == ~E_11~0); 40101#L1459-1 assume !(1 == ~E_12~0); 40628#L1464-1 assume { :end_inline_reset_delta_events } true; 39863#L1810-2 [2022-12-13 15:12:00,200 INFO L750 eck$LassoCheckResult]: Loop: 39863#L1810-2 assume !false; 40303#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40840#L1176 assume !false; 40786#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40347#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39555#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 40838#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 41015#L1003 assume !(0 != eval_~tmp~0#1); 40310#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40046#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40047#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40730#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40731#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 40626#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 39806#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 39807#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40275#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 39882#L1231-3 assume !(0 == ~T7_E~0); 39883#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40127#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41122#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41023#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 40718#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 39826#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 39827#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 39874#L1271-3 assume !(0 == ~E_2~0); 39875#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40250#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40251#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40773#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 40774#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 41195#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41153#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 40355#L1311-3 assume !(0 == ~E_10~0); 39752#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 39753#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 39828#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40465#L593-42 assume !(1 == ~m_pc~0); 40630#L593-44 is_master_triggered_~__retres1~0#1 := 0; 40631#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40150#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40151#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39648#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39649#L612-42 assume !(1 == ~t1_pc~0); 40585#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 40975#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41204#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39741#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39742#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40429#L631-42 assume !(1 == ~t2_pc~0); 39505#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 39504#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40414#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40301#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 40302#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39901#L650-42 assume 1 == ~t3_pc~0; 39468#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 39469#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40806#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40093#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40094#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41093#L669-42 assume 1 == ~t4_pc~0; 40368#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39467#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40876#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40784#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 40683#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40684#L688-42 assume 1 == ~t5_pc~0; 40771#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40978#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40477#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39676#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 39677#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39496#L707-42 assume !(1 == ~t6_pc~0); 39497#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 41159#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39820#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 39821#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40652#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40653#L726-42 assume 1 == ~t7_pc~0; 40926#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 40959#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40504#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40358#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 40359#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40469#L745-42 assume 1 == ~t8_pc~0; 40507#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40509#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40674#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39484#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39485#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40209#L764-42 assume 1 == ~t9_pc~0; 40338#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40697#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40698#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39762#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 39763#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39819#L783-42 assume 1 == ~t10_pc~0; 39440#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 39441#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40029#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40666#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41186#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40866#L802-42 assume 1 == ~t11_pc~0; 39962#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39580#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39581#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39529#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39530#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40706#L821-42 assume 1 == ~t12_pc~0; 40707#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 40070#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40462#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 40463#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 40400#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40392#L1339-3 assume !(1 == ~M_E~0); 40393#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40562#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40670#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40079#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40080#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40680#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41180#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41089#L1374-3 assume !(1 == ~T8_E~0); 39903#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 39904#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40077#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40078#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 40289#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41098#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41067#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41068#L1414-3 assume !(1 == ~E_3~0); 41121#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 40869#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 39784#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 39785#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 40679#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 39717#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 39718#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 39831#L1454-3 assume !(1 == ~E_11~0); 40675#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 40676#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40320#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39620#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 39814#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 39815#L1829 assume !(0 == start_simulation_~tmp~3#1); 39602#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 39603#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 40398#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 39509#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 39510#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40691#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 41073#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 39862#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 39863#L1810-2 [2022-12-13 15:12:00,201 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:00,201 INFO L85 PathProgramCache]: Analyzing trace with hash 1133017134, now seen corresponding path program 1 times [2022-12-13 15:12:00,201 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:00,201 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [666046071] [2022-12-13 15:12:00,201 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:00,202 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:00,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:00,256 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:00,256 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:00,256 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [666046071] [2022-12-13 15:12:00,257 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [666046071] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:00,257 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:00,257 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:00,257 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2061330455] [2022-12-13 15:12:00,257 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:00,258 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:00,258 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:00,258 INFO L85 PathProgramCache]: Analyzing trace with hash -1900304237, now seen corresponding path program 1 times [2022-12-13 15:12:00,259 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:00,259 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [130988086] [2022-12-13 15:12:00,259 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:00,259 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:00,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:00,316 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:00,316 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:00,316 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [130988086] [2022-12-13 15:12:00,316 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [130988086] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:00,316 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:00,316 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:00,317 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1716403322] [2022-12-13 15:12:00,317 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:00,317 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:00,317 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:00,317 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:12:00,317 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:12:00,318 INFO L87 Difference]: Start difference. First operand 1788 states and 2641 transitions. cyclomatic complexity: 854 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:00,348 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:00,348 INFO L93 Difference]: Finished difference Result 1788 states and 2640 transitions. [2022-12-13 15:12:00,348 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2640 transitions. [2022-12-13 15:12:00,355 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-12-13 15:12:00,361 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2640 transitions. [2022-12-13 15:12:00,361 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-12-13 15:12:00,362 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-12-13 15:12:00,362 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2640 transitions. [2022-12-13 15:12:00,365 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:12:00,365 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2640 transitions. [2022-12-13 15:12:00,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2640 transitions. [2022-12-13 15:12:00,386 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-12-13 15:12:00,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.476510067114094) internal successors, (2640), 1787 states have internal predecessors, (2640), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:00,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2640 transitions. [2022-12-13 15:12:00,393 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2640 transitions. [2022-12-13 15:12:00,394 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:12:00,394 INFO L428 stractBuchiCegarLoop]: Abstraction has 1788 states and 2640 transitions. [2022-12-13 15:12:00,394 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-12-13 15:12:00,394 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2640 transitions. [2022-12-13 15:12:00,399 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-12-13 15:12:00,400 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:00,400 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:00,401 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:00,401 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:00,402 INFO L748 eck$LassoCheckResult]: Stem: 43298#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 43299#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 44121#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 44122#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 44718#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 44719#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43805#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43601#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43012#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43013#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44233#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 44339#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 44781#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 44782#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 43731#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 43732#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 44261#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 44184#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43767#L1201 assume !(0 == ~M_E~0); 43768#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44628#L1206-1 assume !(0 == ~T2_E~0); 44611#L1211-1 assume !(0 == ~T3_E~0); 44612#L1216-1 assume !(0 == ~T4_E~0); 43582#L1221-1 assume !(0 == ~T5_E~0); 43583#L1226-1 assume !(0 == ~T6_E~0); 43224#L1231-1 assume !(0 == ~T7_E~0); 43225#L1236-1 assume !(0 == ~T8_E~0); 44652#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 43620#L1246-1 assume !(0 == ~T10_E~0); 43621#L1251-1 assume !(0 == ~T11_E~0); 43765#L1256-1 assume !(0 == ~T12_E~0); 43021#L1261-1 assume !(0 == ~E_M~0); 43022#L1266-1 assume !(0 == ~E_1~0); 44766#L1271-1 assume !(0 == ~E_2~0); 44323#L1276-1 assume !(0 == ~E_3~0); 44324#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 44273#L1286-1 assume !(0 == ~E_5~0); 43479#L1291-1 assume !(0 == ~E_6~0); 43480#L1296-1 assume !(0 == ~E_7~0); 44057#L1301-1 assume !(0 == ~E_8~0); 44058#L1306-1 assume !(0 == ~E_9~0); 44545#L1311-1 assume !(0 == ~E_10~0); 43433#L1316-1 assume !(0 == ~E_11~0); 43434#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 44076#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44077#L593 assume 1 == ~m_pc~0; 44226#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 43323#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43968#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43969#L1492 assume !(0 != activate_threads_~tmp~1#1); 44283#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44580#L612 assume !(1 == ~t1_pc~0); 44581#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 44714#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44419#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43326#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43327#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43747#L631 assume 1 == ~t2_pc~0; 43678#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43102#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43103#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43447#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 43933#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43394#L650 assume !(1 == ~t3_pc~0); 43395#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 44099#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44399#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43059#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 43060#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44254#L669 assume 1 == ~t4_pc~0; 44255#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 44619#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43140#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43141#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 43261#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43489#L688 assume !(1 == ~t5_pc~0); 43280#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 43281#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44747#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44141#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 44142#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44268#L707 assume 1 == ~t6_pc~0; 44685#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 43902#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43435#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43436#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 44212#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43766#L726 assume 1 == ~t7_pc~0; 43666#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 43363#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44410#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44689#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 43130#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43131#L745 assume !(1 == ~t8_pc~0); 43575#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 43595#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44634#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43977#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43978#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44500#L764 assume 1 == ~t9_pc~0; 43764#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43603#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43505#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43506#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 43156#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43157#L783 assume !(1 == ~t10_pc~0); 43211#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 43212#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43401#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43721#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 43722#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44621#L802 assume 1 == ~t11_pc~0; 44603#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 43099#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43100#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43584#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 43585#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43698#L821 assume !(1 == ~t12_pc~0); 43946#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 44049#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 43106#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 43107#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 44662#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44293#L1339 assume !(1 == ~M_E~0); 44294#L1339-2 assume !(1 == ~T1_E~0); 44692#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44693#L1349-1 assume !(1 == ~T3_E~0); 44069#L1354-1 assume !(1 == ~T4_E~0); 44070#L1359-1 assume !(1 == ~T5_E~0); 44477#L1364-1 assume !(1 == ~T6_E~0); 43536#L1369-1 assume !(1 == ~T7_E~0); 43537#L1374-1 assume !(1 == ~T8_E~0); 44072#L1379-1 assume !(1 == ~T9_E~0); 44073#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 44181#L1389-1 assume !(1 == ~T11_E~0); 44657#L1394-1 assume !(1 == ~T12_E~0); 44658#L1399-1 assume !(1 == ~E_M~0); 44739#L1404-1 assume !(1 == ~E_1~0); 43627#L1409-1 assume !(1 == ~E_2~0); 43628#L1414-1 assume !(1 == ~E_3~0); 44359#L1419-1 assume !(1 == ~E_4~0); 43270#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 43271#L1429-1 assume !(1 == ~E_6~0); 44084#L1434-1 assume !(1 == ~E_7~0); 44674#L1439-1 assume !(1 == ~E_8~0); 43312#L1444-1 assume !(1 == ~E_9~0); 43313#L1449-1 assume !(1 == ~E_10~0); 43683#L1454-1 assume !(1 == ~E_11~0); 43684#L1459-1 assume !(1 == ~E_12~0); 44211#L1464-1 assume { :end_inline_reset_delta_events } true; 43446#L1810-2 [2022-12-13 15:12:00,402 INFO L750 eck$LassoCheckResult]: Loop: 43446#L1810-2 assume !false; 43886#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44423#L1176 assume !false; 44369#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 43930#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43138#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 44421#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 44598#L1003 assume !(0 != eval_~tmp~0#1); 43893#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 43629#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43630#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44313#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44314#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 44209#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 43389#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 43390#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 43858#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43465#L1231-3 assume !(0 == ~T7_E~0); 43466#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 43710#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 44705#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 44606#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 44301#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 43409#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 43410#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 43457#L1271-3 assume !(0 == ~E_2~0); 43458#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 43833#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 43834#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 44356#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 44357#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 44778#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 44736#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 43938#L1311-3 assume !(0 == ~E_10~0); 43335#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43336#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 43411#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44048#L593-42 assume !(1 == ~m_pc~0); 44213#L593-44 is_master_triggered_~__retres1~0#1 := 0; 44214#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43733#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43734#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43231#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43232#L612-42 assume !(1 == ~t1_pc~0); 44168#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 44558#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44787#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43324#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43325#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44012#L631-42 assume !(1 == ~t2_pc~0); 43088#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 43087#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43997#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43884#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 43885#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43484#L650-42 assume 1 == ~t3_pc~0; 43051#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43052#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44389#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43676#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43677#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44676#L669-42 assume !(1 == ~t4_pc~0); 43049#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 43050#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44459#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44367#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 44266#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44267#L688-42 assume 1 == ~t5_pc~0; 44354#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44561#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44060#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43259#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 43260#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43079#L707-42 assume !(1 == ~t6_pc~0); 43080#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 44742#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43403#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43404#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 44235#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44236#L726-42 assume 1 == ~t7_pc~0; 44509#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 44542#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44087#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43941#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 43942#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 44052#L745-42 assume 1 == ~t8_pc~0; 44090#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 44092#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44257#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43067#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43068#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43792#L764-42 assume 1 == ~t9_pc~0; 43921#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44280#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44281#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43345#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 43346#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43402#L783-42 assume !(1 == ~t10_pc~0); 43025#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 43024#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43612#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44249#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 44769#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44449#L802-42 assume 1 == ~t11_pc~0; 43545#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 43163#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43164#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43112#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 43113#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44289#L821-42 assume 1 == ~t12_pc~0; 44290#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 43653#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44045#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 44046#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 43983#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43975#L1339-3 assume !(1 == ~M_E~0); 43976#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44145#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44253#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43662#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43663#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44263#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44763#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44672#L1374-3 assume !(1 == ~T8_E~0); 43486#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 43487#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43660#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43661#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 43872#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 44681#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44650#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44651#L1414-3 assume !(1 == ~E_3~0); 44704#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44452#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43367#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43368#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 44262#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 43300#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43301#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 43414#L1454-3 assume !(1 == ~E_11~0); 44258#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 44259#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 43903#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43203#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43397#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 43398#L1829 assume !(0 == start_simulation_~tmp~3#1); 43185#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 43186#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43981#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43092#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 43093#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44274#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44656#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 43445#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 43446#L1810-2 [2022-12-13 15:12:00,402 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:00,402 INFO L85 PathProgramCache]: Analyzing trace with hash -1544509712, now seen corresponding path program 1 times [2022-12-13 15:12:00,403 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:00,403 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [91710844] [2022-12-13 15:12:00,403 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:00,403 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:00,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:00,453 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:00,453 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:00,453 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [91710844] [2022-12-13 15:12:00,453 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [91710844] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:00,454 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:00,454 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 15:12:00,454 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [139526473] [2022-12-13 15:12:00,454 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:00,454 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:00,454 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:00,454 INFO L85 PathProgramCache]: Analyzing trace with hash -542851947, now seen corresponding path program 1 times [2022-12-13 15:12:00,454 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:00,454 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1197206414] [2022-12-13 15:12:00,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:00,455 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:00,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:00,498 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:00,498 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:00,498 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1197206414] [2022-12-13 15:12:00,498 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1197206414] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:00,498 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:00,498 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:00,498 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [395080674] [2022-12-13 15:12:00,498 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:00,499 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:00,499 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:00,499 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:12:00,499 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:12:00,499 INFO L87 Difference]: Start difference. First operand 1788 states and 2640 transitions. cyclomatic complexity: 853 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:00,532 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:00,532 INFO L93 Difference]: Finished difference Result 1788 states and 2635 transitions. [2022-12-13 15:12:00,532 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1788 states and 2635 transitions. [2022-12-13 15:12:00,540 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-12-13 15:12:00,546 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1788 states to 1788 states and 2635 transitions. [2022-12-13 15:12:00,546 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1788 [2022-12-13 15:12:00,548 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1788 [2022-12-13 15:12:00,548 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1788 states and 2635 transitions. [2022-12-13 15:12:00,551 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:12:00,551 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2635 transitions. [2022-12-13 15:12:00,553 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1788 states and 2635 transitions. [2022-12-13 15:12:00,565 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1788 to 1788. [2022-12-13 15:12:00,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1788 states, 1788 states have (on average 1.4737136465324385) internal successors, (2635), 1787 states have internal predecessors, (2635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:00,570 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1788 states to 1788 states and 2635 transitions. [2022-12-13 15:12:00,570 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1788 states and 2635 transitions. [2022-12-13 15:12:00,570 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:12:00,571 INFO L428 stractBuchiCegarLoop]: Abstraction has 1788 states and 2635 transitions. [2022-12-13 15:12:00,571 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-12-13 15:12:00,571 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1788 states and 2635 transitions. [2022-12-13 15:12:00,577 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1625 [2022-12-13 15:12:00,577 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:00,577 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:00,579 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:00,579 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:00,579 INFO L748 eck$LassoCheckResult]: Stem: 46881#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 46882#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 47705#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 47706#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48301#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 48302#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47389#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47184#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46595#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46596#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 47816#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 47923#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48364#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 48365#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47314#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47315#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 47844#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 47767#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47350#L1201 assume !(0 == ~M_E~0); 47351#L1201-2 assume !(0 == ~T1_E~0); 48211#L1206-1 assume !(0 == ~T2_E~0); 48194#L1211-1 assume !(0 == ~T3_E~0); 48195#L1216-1 assume !(0 == ~T4_E~0); 47166#L1221-1 assume !(0 == ~T5_E~0); 47167#L1226-1 assume !(0 == ~T6_E~0); 46807#L1231-1 assume !(0 == ~T7_E~0); 46808#L1236-1 assume !(0 == ~T8_E~0); 48235#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 47206#L1246-1 assume !(0 == ~T10_E~0); 47207#L1251-1 assume !(0 == ~T11_E~0); 47348#L1256-1 assume !(0 == ~T12_E~0); 46604#L1261-1 assume !(0 == ~E_M~0); 46605#L1266-1 assume !(0 == ~E_1~0); 48349#L1271-1 assume !(0 == ~E_2~0); 47906#L1276-1 assume !(0 == ~E_3~0); 47907#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 47856#L1286-1 assume !(0 == ~E_5~0); 47062#L1291-1 assume !(0 == ~E_6~0); 47063#L1296-1 assume !(0 == ~E_7~0); 47640#L1301-1 assume !(0 == ~E_8~0); 47641#L1306-1 assume !(0 == ~E_9~0); 48128#L1311-1 assume !(0 == ~E_10~0); 47016#L1316-1 assume !(0 == ~E_11~0); 47017#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 47659#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47660#L593 assume 1 == ~m_pc~0; 47809#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 46906#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47551#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47552#L1492 assume !(0 != activate_threads_~tmp~1#1); 47866#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48163#L612 assume !(1 == ~t1_pc~0); 48164#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 48297#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48002#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46909#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46910#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47330#L631 assume 1 == ~t2_pc~0; 47261#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46685#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46686#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47030#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 47516#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46979#L650 assume !(1 == ~t3_pc~0); 46980#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 47682#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47982#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46642#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 46643#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47837#L669 assume 1 == ~t4_pc~0; 47838#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 48203#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46727#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46728#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 46844#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47072#L688 assume !(1 == ~t5_pc~0); 46863#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 46864#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48330#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47726#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 47727#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47854#L707 assume 1 == ~t6_pc~0; 48268#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47485#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47018#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47019#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 47797#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47349#L726 assume 1 == ~t7_pc~0; 47251#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46946#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47994#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 48273#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 46713#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46714#L745 assume !(1 == ~t8_pc~0); 47158#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 47178#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48217#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47560#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47561#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48083#L764 assume 1 == ~t9_pc~0; 47347#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47186#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47088#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47089#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 46739#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46740#L783 assume !(1 == ~t10_pc~0); 46794#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 46795#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 46984#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47309#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 47310#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48204#L802 assume 1 == ~t11_pc~0; 48186#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46682#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46683#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 47168#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 47169#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47281#L821 assume !(1 == ~t12_pc~0); 47529#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 47632#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46691#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46692#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 48245#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47876#L1339 assume !(1 == ~M_E~0); 47877#L1339-2 assume !(1 == ~T1_E~0); 48275#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48276#L1349-1 assume !(1 == ~T3_E~0); 47653#L1354-1 assume !(1 == ~T4_E~0); 47654#L1359-1 assume !(1 == ~T5_E~0); 48062#L1364-1 assume !(1 == ~T6_E~0); 47119#L1369-1 assume !(1 == ~T7_E~0); 47120#L1374-1 assume !(1 == ~T8_E~0); 47657#L1379-1 assume !(1 == ~T9_E~0); 47658#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47764#L1389-1 assume !(1 == ~T11_E~0); 48240#L1394-1 assume !(1 == ~T12_E~0); 48241#L1399-1 assume !(1 == ~E_M~0); 48322#L1404-1 assume !(1 == ~E_1~0); 47210#L1409-1 assume !(1 == ~E_2~0); 47211#L1414-1 assume !(1 == ~E_3~0); 47942#L1419-1 assume !(1 == ~E_4~0); 46853#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 46854#L1429-1 assume !(1 == ~E_6~0); 47667#L1434-1 assume !(1 == ~E_7~0); 48257#L1439-1 assume !(1 == ~E_8~0); 46895#L1444-1 assume !(1 == ~E_9~0); 46896#L1449-1 assume !(1 == ~E_10~0); 47268#L1454-1 assume !(1 == ~E_11~0); 47269#L1459-1 assume !(1 == ~E_12~0); 47794#L1464-1 assume { :end_inline_reset_delta_events } true; 47029#L1810-2 [2022-12-13 15:12:00,580 INFO L750 eck$LassoCheckResult]: Loop: 47029#L1810-2 assume !false; 47469#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48006#L1176 assume !false; 47952#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47515#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 46721#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 48004#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 48183#L1003 assume !(0 != eval_~tmp~0#1); 47476#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 47212#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 47213#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 47896#L1201-5 assume !(0 == ~T1_E~0); 47897#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 47793#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46972#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46973#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47441#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47048#L1231-3 assume !(0 == ~T7_E~0); 47049#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47293#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 48288#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 48189#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 47884#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 46992#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 46993#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 47040#L1271-3 assume !(0 == ~E_2~0); 47041#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47416#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 47417#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47939#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47940#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 48361#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 48319#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 47521#L1311-3 assume !(0 == ~E_10~0); 46918#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 46919#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 46994#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47631#L593-42 assume !(1 == ~m_pc~0); 47795#L593-44 is_master_triggered_~__retres1~0#1 := 0; 47796#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47316#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47317#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46814#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46815#L612-42 assume !(1 == ~t1_pc~0); 47751#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 48141#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48370#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46907#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46908#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47595#L631-42 assume 1 == ~t2_pc~0; 46669#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46670#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47580#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47467#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 47468#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47067#L650-42 assume 1 == ~t3_pc~0; 46634#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46635#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47972#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47259#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47260#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48259#L669-42 assume !(1 == ~t4_pc~0); 46632#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 46633#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48042#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47950#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 47849#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47850#L688-42 assume 1 == ~t5_pc~0; 47937#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 48144#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47643#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46839#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46840#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46662#L707-42 assume !(1 == ~t6_pc~0); 46663#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 48325#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46986#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46987#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 47818#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47819#L726-42 assume 1 == ~t7_pc~0; 48092#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 48125#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47670#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47524#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 47525#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47635#L745-42 assume 1 == ~t8_pc~0; 47673#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 47675#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47840#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46650#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 46651#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47375#L764-42 assume 1 == ~t9_pc~0; 47504#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47863#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47864#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46928#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 46929#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46985#L783-42 assume !(1 == ~t10_pc~0); 46608#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 46607#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47195#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47832#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 48352#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48032#L802-42 assume 1 == ~t11_pc~0; 47128#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46746#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46747#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46695#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 46696#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47872#L821-42 assume 1 == ~t12_pc~0; 47873#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 47236#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 47628#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 47629#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 47566#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47558#L1339-3 assume !(1 == ~M_E~0); 47559#L1339-5 assume !(1 == ~T1_E~0); 47728#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47836#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47245#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47246#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47846#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 48346#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 48255#L1374-3 assume !(1 == ~T8_E~0); 47068#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 47069#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47243#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 47244#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47455#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 48264#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 48233#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 48234#L1414-3 assume !(1 == ~E_3~0); 48287#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 48035#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46950#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46951#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 47845#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 46883#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 46884#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 46997#L1454-3 assume !(1 == ~E_11~0); 47841#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 47842#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47486#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 46786#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 46977#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 46978#L1829 assume !(0 == start_simulation_~tmp~3#1); 46768#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 46769#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47564#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 46675#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 46676#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 47857#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 48239#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 47028#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 47029#L1810-2 [2022-12-13 15:12:00,580 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:00,580 INFO L85 PathProgramCache]: Analyzing trace with hash -2089382286, now seen corresponding path program 1 times [2022-12-13 15:12:00,581 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:00,581 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [966378012] [2022-12-13 15:12:00,581 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:00,581 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:00,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:00,662 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:00,662 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:00,662 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [966378012] [2022-12-13 15:12:00,662 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [966378012] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:00,662 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:00,662 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:00,662 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [683536969] [2022-12-13 15:12:00,663 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:00,663 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:00,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:00,663 INFO L85 PathProgramCache]: Analyzing trace with hash -1433116652, now seen corresponding path program 1 times [2022-12-13 15:12:00,664 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:00,664 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [126457481] [2022-12-13 15:12:00,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:00,664 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:00,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:00,718 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:00,719 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:00,719 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [126457481] [2022-12-13 15:12:00,719 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [126457481] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:00,719 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:00,719 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:00,719 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [757515075] [2022-12-13 15:12:00,719 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:00,720 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:00,720 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:00,720 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 15:12:00,720 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 15:12:00,720 INFO L87 Difference]: Start difference. First operand 1788 states and 2635 transitions. cyclomatic complexity: 848 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:00,847 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:00,848 INFO L93 Difference]: Finished difference Result 3437 states and 5058 transitions. [2022-12-13 15:12:00,848 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3437 states and 5058 transitions. [2022-12-13 15:12:00,862 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3250 [2022-12-13 15:12:00,877 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3437 states to 3437 states and 5058 transitions. [2022-12-13 15:12:00,878 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3437 [2022-12-13 15:12:00,879 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3437 [2022-12-13 15:12:00,879 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3437 states and 5058 transitions. [2022-12-13 15:12:00,882 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:12:00,882 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3437 states and 5058 transitions. [2022-12-13 15:12:00,886 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3437 states and 5058 transitions. [2022-12-13 15:12:00,927 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3437 to 3437. [2022-12-13 15:12:00,932 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3437 states, 3437 states have (on average 1.4716322374163515) internal successors, (5058), 3436 states have internal predecessors, (5058), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:00,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3437 states to 3437 states and 5058 transitions. [2022-12-13 15:12:00,940 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3437 states and 5058 transitions. [2022-12-13 15:12:00,940 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 15:12:00,940 INFO L428 stractBuchiCegarLoop]: Abstraction has 3437 states and 5058 transitions. [2022-12-13 15:12:00,941 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-12-13 15:12:00,941 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3437 states and 5058 transitions. [2022-12-13 15:12:00,953 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3250 [2022-12-13 15:12:00,953 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:00,953 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:00,955 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:00,955 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:00,956 INFO L748 eck$LassoCheckResult]: Stem: 52116#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 52117#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 52949#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 52950#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 53593#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 53594#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 52628#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 52421#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 51830#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 51831#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53064#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 53173#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 53674#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 53675#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 52553#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 52554#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 53092#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 53013#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 52589#L1201 assume !(0 == ~M_E~0); 52590#L1201-2 assume !(0 == ~T1_E~0); 53487#L1206-1 assume !(0 == ~T2_E~0); 53469#L1211-1 assume !(0 == ~T3_E~0); 53470#L1216-1 assume !(0 == ~T4_E~0); 52403#L1221-1 assume !(0 == ~T5_E~0); 52404#L1226-1 assume !(0 == ~T6_E~0); 52042#L1231-1 assume !(0 == ~T7_E~0); 52043#L1236-1 assume !(0 == ~T8_E~0); 53512#L1241-1 assume !(0 == ~T9_E~0); 52444#L1246-1 assume !(0 == ~T10_E~0); 52445#L1251-1 assume !(0 == ~T11_E~0); 52587#L1256-1 assume !(0 == ~T12_E~0); 51839#L1261-1 assume !(0 == ~E_M~0); 51840#L1266-1 assume !(0 == ~E_1~0); 53655#L1271-1 assume !(0 == ~E_2~0); 53156#L1276-1 assume !(0 == ~E_3~0); 53157#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 53104#L1286-1 assume !(0 == ~E_5~0); 52297#L1291-1 assume !(0 == ~E_6~0); 52298#L1296-1 assume !(0 == ~E_7~0); 52882#L1301-1 assume !(0 == ~E_8~0); 52883#L1306-1 assume !(0 == ~E_9~0); 53400#L1311-1 assume !(0 == ~E_10~0); 52251#L1316-1 assume !(0 == ~E_11~0); 52252#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 52902#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52903#L593 assume 1 == ~m_pc~0; 53057#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 52141#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52791#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 52792#L1492 assume !(0 != activate_threads_~tmp~1#1); 53114#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53437#L612 assume !(1 == ~t1_pc~0); 53438#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 53589#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53257#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 52144#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52145#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52569#L631 assume 1 == ~t2_pc~0; 52499#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 51920#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51921#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52265#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 52756#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52214#L650 assume !(1 == ~t3_pc~0); 52215#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 52926#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53235#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51877#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 51878#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53085#L669 assume 1 == ~t4_pc~0; 53086#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53478#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51962#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51963#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 52079#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 52307#L688 assume !(1 == ~t5_pc~0); 52098#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 52099#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53629#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 52968#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 52969#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53102#L707 assume 1 == ~t6_pc~0; 53552#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 52724#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52253#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 52254#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 53044#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 52588#L726 assume 1 == ~t7_pc~0; 52489#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 52181#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53248#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53558#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 51948#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 51949#L745 assume !(1 == ~t8_pc~0); 52395#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 52415#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53493#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 52800#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 52801#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53346#L764 assume 1 == ~t9_pc~0; 52586#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52423#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 52325#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 52326#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 51974#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51975#L783 assume !(1 == ~t10_pc~0); 52029#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 52030#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52219#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 52548#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 52549#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53479#L802 assume 1 == ~t11_pc~0; 53461#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 51917#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 51918#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 52405#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 52406#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 52519#L821 assume !(1 == ~t12_pc~0); 52769#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 52874#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 51926#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 51927#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 53524#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53125#L1339 assume !(1 == ~M_E~0); 53126#L1339-2 assume !(1 == ~T1_E~0); 53563#L1344-1 assume !(1 == ~T2_E~0); 53564#L1349-1 assume !(1 == ~T3_E~0); 52895#L1354-1 assume !(1 == ~T4_E~0); 52896#L1359-1 assume !(1 == ~T5_E~0); 53324#L1364-1 assume !(1 == ~T6_E~0); 52356#L1369-1 assume !(1 == ~T7_E~0); 52357#L1374-1 assume !(1 == ~T8_E~0); 52899#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 52900#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 54927#L1389-1 assume !(1 == ~T11_E~0); 54926#L1394-1 assume !(1 == ~T12_E~0); 54925#L1399-1 assume !(1 == ~E_M~0); 54924#L1404-1 assume !(1 == ~E_1~0); 54923#L1409-1 assume !(1 == ~E_2~0); 54922#L1414-1 assume !(1 == ~E_3~0); 54921#L1419-1 assume !(1 == ~E_4~0); 54920#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 52910#L1429-1 assume !(1 == ~E_6~0); 52911#L1434-1 assume !(1 == ~E_7~0); 53686#L1439-1 assume !(1 == ~E_8~0); 52130#L1444-1 assume !(1 == ~E_9~0); 52131#L1449-1 assume !(1 == ~E_10~0); 53742#L1454-1 assume !(1 == ~E_11~0); 53556#L1459-1 assume !(1 == ~E_12~0); 53557#L1464-1 assume { :end_inline_reset_delta_events } true; 53729#L1810-2 [2022-12-13 15:12:00,956 INFO L750 eck$LassoCheckResult]: Loop: 53729#L1810-2 assume !false; 53579#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53264#L1176 assume !false; 53710#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 53724#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 53259#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 53260#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 53542#L1003 assume !(0 != eval_~tmp~0#1); 52715#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 52450#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 52451#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 53146#L1201-5 assume !(0 == ~T1_E~0); 53147#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 53040#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 52207#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 52208#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 52680#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 52285#L1231-3 assume !(0 == ~T7_E~0); 52286#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 52532#L1241-3 assume !(0 == ~T9_E~0); 53577#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 53578#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 54973#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 54971#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 54969#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 54966#L1271-3 assume !(0 == ~E_2~0); 54964#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54962#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 53500#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 53192#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 53193#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 53668#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 53616#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 53617#L1311-3 assume !(0 == ~E_10~0); 54888#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 54887#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 52872#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52873#L593-42 assume !(1 == ~m_pc~0); 53042#L593-44 is_master_triggered_~__retres1~0#1 := 0; 53043#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52555#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 52556#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 52046#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52047#L612-42 assume !(1 == ~t1_pc~0); 52995#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 53415#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53680#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 52142#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52143#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52836#L631-42 assume 1 == ~t2_pc~0; 51904#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 51905#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52820#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52706#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 52707#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52302#L650-42 assume 1 == ~t3_pc~0; 51869#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 51870#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53225#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 52497#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 52498#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53539#L669-42 assume 1 == ~t4_pc~0; 52774#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 51868#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53301#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53203#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 53097#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53098#L688-42 assume 1 == ~t5_pc~0; 53190#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 53418#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 52885#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 52074#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 52075#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 51897#L707-42 assume !(1 == ~t6_pc~0); 51898#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 53624#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52221#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 52222#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 53066#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53067#L726-42 assume 1 == ~t7_pc~0; 53356#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 53397#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 52914#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 52764#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 52765#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52877#L745-42 assume 1 == ~t8_pc~0; 52916#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 52918#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53088#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 51885#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 51886#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 52614#L764-42 assume 1 == ~t9_pc~0; 52743#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 53111#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53112#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 52163#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 52164#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 52220#L783-42 assume 1 == ~t10_pc~0; 51841#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 51842#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52432#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53080#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53658#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53291#L802-42 assume 1 == ~t11_pc~0; 52365#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 51981#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 51982#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 51930#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 51931#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53120#L821-42 assume 1 == ~t12_pc~0; 53121#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 52474#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 52869#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 52870#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 52806#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52798#L1339-3 assume !(1 == ~M_E~0); 52799#L1339-5 assume !(1 == ~T1_E~0); 52972#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 53084#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 52483#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 52484#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 53094#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 53650#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 53534#L1374-3 assume !(1 == ~T8_E~0); 52303#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 52304#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 52481#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 52482#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 52694#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 53545#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 53510#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 53511#L1414-3 assume !(1 == ~E_3~0); 53576#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53294#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 52185#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 52186#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 53093#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 52118#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 52119#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 52232#L1454-3 assume !(1 == ~E_11~0); 53089#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 53090#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 52725#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 52021#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 52212#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 52213#L1829 assume !(0 == start_simulation_~tmp~3#1); 52003#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 52004#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 53741#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 53740#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 53739#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 53738#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 53737#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 53733#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 53729#L1810-2 [2022-12-13 15:12:00,956 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:00,957 INFO L85 PathProgramCache]: Analyzing trace with hash 907144632, now seen corresponding path program 1 times [2022-12-13 15:12:00,957 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:00,957 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [350487219] [2022-12-13 15:12:00,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:00,957 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:00,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:01,032 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:01,032 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:01,033 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [350487219] [2022-12-13 15:12:01,033 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [350487219] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:01,033 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:01,033 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:01,033 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1060434365] [2022-12-13 15:12:01,033 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:01,034 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:01,034 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:01,034 INFO L85 PathProgramCache]: Analyzing trace with hash -1391615340, now seen corresponding path program 1 times [2022-12-13 15:12:01,034 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:01,034 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [713236313] [2022-12-13 15:12:01,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:01,035 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:01,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:01,086 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:01,086 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:01,086 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [713236313] [2022-12-13 15:12:01,086 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [713236313] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:01,086 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:01,086 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:01,087 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2038208017] [2022-12-13 15:12:01,087 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:01,087 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:01,087 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:01,087 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 15:12:01,087 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 15:12:01,088 INFO L87 Difference]: Start difference. First operand 3437 states and 5058 transitions. cyclomatic complexity: 1623 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:01,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:01,266 INFO L93 Difference]: Finished difference Result 6529 states and 9599 transitions. [2022-12-13 15:12:01,266 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6529 states and 9599 transitions. [2022-12-13 15:12:01,295 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6314 [2022-12-13 15:12:01,317 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6529 states to 6529 states and 9599 transitions. [2022-12-13 15:12:01,317 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6529 [2022-12-13 15:12:01,323 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6529 [2022-12-13 15:12:01,323 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6529 states and 9599 transitions. [2022-12-13 15:12:01,331 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:12:01,332 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6529 states and 9599 transitions. [2022-12-13 15:12:01,339 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6529 states and 9599 transitions. [2022-12-13 15:12:01,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6529 to 6527. [2022-12-13 15:12:01,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6527 states, 6527 states have (on average 1.4703539145089628) internal successors, (9597), 6526 states have internal predecessors, (9597), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:01,437 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6527 states to 6527 states and 9597 transitions. [2022-12-13 15:12:01,438 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6527 states and 9597 transitions. [2022-12-13 15:12:01,438 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 15:12:01,438 INFO L428 stractBuchiCegarLoop]: Abstraction has 6527 states and 9597 transitions. [2022-12-13 15:12:01,439 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-12-13 15:12:01,439 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6527 states and 9597 transitions. [2022-12-13 15:12:01,460 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6314 [2022-12-13 15:12:01,461 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:01,461 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:01,462 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:01,462 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:01,463 INFO L748 eck$LassoCheckResult]: Stem: 62092#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 62093#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 62937#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 62938#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 63591#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 63592#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 62613#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 62405#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 61806#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 61807#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 63052#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 63164#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 63673#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 63674#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 62536#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 62537#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 63080#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 63001#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 62573#L1201 assume !(0 == ~M_E~0); 62574#L1201-2 assume !(0 == ~T1_E~0); 63477#L1206-1 assume !(0 == ~T2_E~0); 63457#L1211-1 assume !(0 == ~T3_E~0); 63458#L1216-1 assume !(0 == ~T4_E~0); 62386#L1221-1 assume !(0 == ~T5_E~0); 62387#L1226-1 assume !(0 == ~T6_E~0); 62018#L1231-1 assume !(0 == ~T7_E~0); 62019#L1236-1 assume !(0 == ~T8_E~0); 63513#L1241-1 assume !(0 == ~T9_E~0); 62424#L1246-1 assume !(0 == ~T10_E~0); 62425#L1251-1 assume !(0 == ~T11_E~0); 62571#L1256-1 assume !(0 == ~T12_E~0); 61815#L1261-1 assume !(0 == ~E_M~0); 61816#L1266-1 assume !(0 == ~E_1~0); 63652#L1271-1 assume !(0 == ~E_2~0); 63146#L1276-1 assume !(0 == ~E_3~0); 63147#L1281-1 assume !(0 == ~E_4~0); 63093#L1286-1 assume !(0 == ~E_5~0); 62278#L1291-1 assume !(0 == ~E_6~0); 62279#L1296-1 assume !(0 == ~E_7~0); 62871#L1301-1 assume !(0 == ~E_8~0); 62872#L1306-1 assume !(0 == ~E_9~0); 63388#L1311-1 assume !(0 == ~E_10~0); 62230#L1316-1 assume !(0 == ~E_11~0); 62231#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 62891#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62892#L593 assume 1 == ~m_pc~0; 63045#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 62117#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62780#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 62781#L1492 assume !(0 != activate_threads_~tmp~1#1); 63103#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63423#L612 assume !(1 == ~t1_pc~0); 63424#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 63587#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63252#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62120#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62121#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62553#L631 assume 1 == ~t2_pc~0; 62482#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 61896#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61897#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62244#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 62744#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62189#L650 assume !(1 == ~t3_pc~0); 62190#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 62915#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63230#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 61853#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 61854#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63073#L669 assume 1 == ~t4_pc~0; 63074#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 63465#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61934#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 61935#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 62055#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62289#L688 assume !(1 == ~t5_pc~0); 62074#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 62075#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63629#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 62957#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 62958#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63087#L707 assume 1 == ~t6_pc~0; 63551#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 62712#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62232#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 62233#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 63031#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62572#L726 assume 1 == ~t7_pc~0; 62470#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 62158#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 63242#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 63558#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 61924#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 61925#L745 assume !(1 == ~t8_pc~0); 62379#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 62399#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 63487#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 62789#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 62790#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 63339#L764 assume 1 == ~t9_pc~0; 62570#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 62407#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 62306#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 62307#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 61950#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 61951#L783 assume !(1 == ~t10_pc~0); 62005#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 62006#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 62196#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 62525#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 62526#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 63467#L802 assume 1 == ~t11_pc~0; 63447#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 61893#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 61894#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 62388#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 62389#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 62502#L821 assume !(1 == ~t12_pc~0); 62757#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 62863#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 61900#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 61901#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 63523#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 63113#L1339 assume !(1 == ~M_E~0); 63114#L1339-2 assume !(1 == ~T1_E~0); 63561#L1344-1 assume !(1 == ~T2_E~0); 63562#L1349-1 assume !(1 == ~T3_E~0); 62883#L1354-1 assume !(1 == ~T4_E~0); 62884#L1359-1 assume !(1 == ~T5_E~0); 63315#L1364-1 assume !(1 == ~T6_E~0); 62337#L1369-1 assume !(1 == ~T7_E~0); 62338#L1374-1 assume !(1 == ~T8_E~0); 62886#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 62887#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 62998#L1389-1 assume !(1 == ~T11_E~0); 63518#L1394-1 assume !(1 == ~T12_E~0); 63519#L1399-1 assume !(1 == ~E_M~0); 63902#L1404-1 assume !(1 == ~E_1~0); 63900#L1409-1 assume !(1 == ~E_2~0); 63899#L1414-1 assume !(1 == ~E_3~0); 63872#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 63870#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 63868#L1429-1 assume !(1 == ~E_6~0); 63823#L1434-1 assume !(1 == ~E_7~0); 63821#L1439-1 assume !(1 == ~E_8~0); 63820#L1444-1 assume !(1 == ~E_9~0); 63782#L1449-1 assume !(1 == ~E_10~0); 63772#L1454-1 assume !(1 == ~E_11~0); 63761#L1459-1 assume !(1 == ~E_12~0); 63751#L1464-1 assume { :end_inline_reset_delta_events } true; 63744#L1810-2 [2022-12-13 15:12:01,463 INFO L750 eck$LassoCheckResult]: Loop: 63744#L1810-2 assume !false; 63741#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 63737#L1176 assume !false; 63736#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 63733#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 63722#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 63721#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 63719#L1003 assume !(0 != eval_~tmp~0#1); 63718#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 63717#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 63716#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 63715#L1201-5 assume !(0 == ~T1_E~0); 63713#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 63714#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 66700#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 66699#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 66698#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 66697#L1231-3 assume !(0 == ~T7_E~0); 66696#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 66695#L1241-3 assume !(0 == ~T9_E~0); 66694#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 66693#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 66692#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 66691#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 62736#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 62254#L1271-3 assume !(0 == ~E_2~0); 62255#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 62642#L1281-3 assume !(0 == ~E_4~0); 62643#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 63181#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 63182#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 63665#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 63616#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 62749#L1311-3 assume !(0 == ~E_10~0); 62129#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 62130#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 62206#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62862#L593-42 assume !(1 == ~m_pc~0); 63032#L593-44 is_master_triggered_~__retres1~0#1 := 0; 63033#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62538#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 62539#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 62025#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 62026#L612-42 assume !(1 == ~t1_pc~0); 62985#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 63401#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63680#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62118#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62119#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62824#L631-42 assume 1 == ~t2_pc~0; 61880#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 61881#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62809#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62693#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 62694#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62283#L650-42 assume 1 == ~t3_pc~0; 61845#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 61846#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63217#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 62480#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 62481#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63538#L669-42 assume !(1 == ~t4_pc~0); 61843#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 61844#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 65665#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 65662#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 65601#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65599#L688-42 assume 1 == ~t5_pc~0; 65537#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 65535#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 65533#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 65531#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 65529#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 65527#L707-42 assume 1 == ~t6_pc~0; 65523#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 65521#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 65519#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 65518#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 65517#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 65516#L726-42 assume 1 == ~t7_pc~0; 65512#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 65510#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 65508#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 65506#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 65504#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 65502#L745-42 assume !(1 == ~t8_pc~0); 65412#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 65410#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65407#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 65405#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 65355#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 65282#L764-42 assume !(1 == ~t9_pc~0); 65280#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 65277#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 65275#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 65208#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 65205#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 65203#L783-42 assume !(1 == ~t10_pc~0); 65200#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 65197#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 65195#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 65193#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 65191#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 65189#L802-42 assume 1 == ~t11_pc~0; 65068#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 65066#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 65064#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 64928#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 64813#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 64707#L821-42 assume !(1 == ~t12_pc~0); 64598#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 64596#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 64594#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 64592#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 64590#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64588#L1339-3 assume !(1 == ~M_E~0); 64586#L1339-5 assume !(1 == ~T1_E~0); 64584#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 63125#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 64485#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 64482#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 64479#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 64477#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 64475#L1374-3 assume !(1 == ~T8_E~0); 64473#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 62286#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 64470#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 64398#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 64278#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 64222#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 64172#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 64170#L1414-3 assume !(1 == ~E_3~0); 64123#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 64074#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 64034#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 63985#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 63957#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 63955#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 63953#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 63952#L1454-3 assume !(1 == ~E_11~0); 63951#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 63898#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 63860#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 63851#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 63849#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 63843#L1829 assume !(0 == start_simulation_~tmp~3#1); 63842#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 63809#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 63803#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 63801#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 63781#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 63771#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 63760#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 63750#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 63744#L1810-2 [2022-12-13 15:12:01,463 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:01,464 INFO L85 PathProgramCache]: Analyzing trace with hash -1065863428, now seen corresponding path program 1 times [2022-12-13 15:12:01,464 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:01,464 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [912063560] [2022-12-13 15:12:01,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:01,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:01,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:01,510 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:01,511 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:01,511 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [912063560] [2022-12-13 15:12:01,511 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [912063560] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:01,511 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:01,511 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:01,511 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1810189988] [2022-12-13 15:12:01,511 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:01,512 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:01,512 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:01,512 INFO L85 PathProgramCache]: Analyzing trace with hash -1087582758, now seen corresponding path program 1 times [2022-12-13 15:12:01,512 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:01,512 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [932876202] [2022-12-13 15:12:01,512 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:01,512 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:01,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:01,547 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:01,547 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:01,547 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [932876202] [2022-12-13 15:12:01,547 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [932876202] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:01,547 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:01,547 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:01,547 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2084884452] [2022-12-13 15:12:01,548 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:01,548 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:01,548 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:01,548 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 15:12:01,548 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 15:12:01,549 INFO L87 Difference]: Start difference. First operand 6527 states and 9597 transitions. cyclomatic complexity: 3074 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:01,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:01,767 INFO L93 Difference]: Finished difference Result 12485 states and 18332 transitions. [2022-12-13 15:12:01,767 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12485 states and 18332 transitions. [2022-12-13 15:12:01,813 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 12256 [2022-12-13 15:12:01,844 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12485 states to 12485 states and 18332 transitions. [2022-12-13 15:12:01,844 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12485 [2022-12-13 15:12:01,851 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12485 [2022-12-13 15:12:01,851 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12485 states and 18332 transitions. [2022-12-13 15:12:01,863 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:12:01,863 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12485 states and 18332 transitions. [2022-12-13 15:12:01,872 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12485 states and 18332 transitions. [2022-12-13 15:12:01,998 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12485 to 12481. [2022-12-13 15:12:02,010 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12481 states, 12481 states have (on average 1.468472077557888) internal successors, (18328), 12480 states have internal predecessors, (18328), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:02,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12481 states to 12481 states and 18328 transitions. [2022-12-13 15:12:02,033 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12481 states and 18328 transitions. [2022-12-13 15:12:02,033 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 15:12:02,033 INFO L428 stractBuchiCegarLoop]: Abstraction has 12481 states and 18328 transitions. [2022-12-13 15:12:02,034 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-12-13 15:12:02,034 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12481 states and 18328 transitions. [2022-12-13 15:12:02,066 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 12256 [2022-12-13 15:12:02,066 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:02,066 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:02,090 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:02,090 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:02,091 INFO L748 eck$LassoCheckResult]: Stem: 81114#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 81115#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 81945#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 81946#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 82581#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 82582#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 81625#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 81420#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 80828#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 80829#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 82058#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 82167#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 82661#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 82662#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 81550#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 81551#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 82086#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 82008#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 81586#L1201 assume !(0 == ~M_E~0); 81587#L1201-2 assume !(0 == ~T1_E~0); 82477#L1206-1 assume !(0 == ~T2_E~0); 82459#L1211-1 assume !(0 == ~T3_E~0); 82460#L1216-1 assume !(0 == ~T4_E~0); 81401#L1221-1 assume !(0 == ~T5_E~0); 81402#L1226-1 assume !(0 == ~T6_E~0); 81040#L1231-1 assume !(0 == ~T7_E~0); 81041#L1236-1 assume !(0 == ~T8_E~0); 82505#L1241-1 assume !(0 == ~T9_E~0); 81439#L1246-1 assume !(0 == ~T10_E~0); 81440#L1251-1 assume !(0 == ~T11_E~0); 81584#L1256-1 assume !(0 == ~T12_E~0); 80837#L1261-1 assume !(0 == ~E_M~0); 80838#L1266-1 assume !(0 == ~E_1~0); 82644#L1271-1 assume !(0 == ~E_2~0); 82151#L1276-1 assume !(0 == ~E_3~0); 82152#L1281-1 assume !(0 == ~E_4~0); 82098#L1286-1 assume !(0 == ~E_5~0); 81295#L1291-1 assume !(0 == ~E_6~0); 81296#L1296-1 assume !(0 == ~E_7~0); 81881#L1301-1 assume !(0 == ~E_8~0); 81882#L1306-1 assume !(0 == ~E_9~0); 82388#L1311-1 assume !(0 == ~E_10~0); 81249#L1316-1 assume !(0 == ~E_11~0); 81250#L1321-1 assume !(0 == ~E_12~0); 81900#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 81901#L593 assume 1 == ~m_pc~0; 82051#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 81139#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 81792#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 81793#L1492 assume !(0 != activate_threads_~tmp~1#1); 82108#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 82424#L612 assume !(1 == ~t1_pc~0); 82425#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 82577#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82255#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 81142#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 81143#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81566#L631 assume 1 == ~t2_pc~0; 81497#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 80918#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 80919#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 81263#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 81757#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81210#L650 assume !(1 == ~t3_pc~0); 81211#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 81923#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82232#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 80875#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 80876#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82079#L669 assume 1 == ~t4_pc~0; 82080#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 82467#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 80956#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 80957#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 81077#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 81308#L688 assume !(1 == ~t5_pc~0); 81096#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 81097#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 82619#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 81965#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 81966#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 82093#L707 assume 1 == ~t6_pc~0; 82538#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 81725#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 81251#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 81252#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 82036#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 81585#L726 assume 1 == ~t7_pc~0; 81485#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 81179#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 82245#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 82545#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 80946#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 80947#L745 assume !(1 == ~t8_pc~0); 81394#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 81414#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 82486#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 81801#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 81802#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 82343#L764 assume 1 == ~t9_pc~0; 81583#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 81422#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 81324#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 81325#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 80972#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 80973#L783 assume !(1 == ~t10_pc~0); 81027#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 81028#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 81217#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 81540#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 81541#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 82469#L802 assume 1 == ~t11_pc~0; 82449#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 80915#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 80916#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 81403#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 81404#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 81517#L821 assume !(1 == ~t12_pc~0); 81770#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 81873#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 80922#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 80923#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 82515#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82118#L1339 assume !(1 == ~M_E~0); 82119#L1339-2 assume !(1 == ~T1_E~0); 82549#L1344-1 assume !(1 == ~T2_E~0); 82550#L1349-1 assume !(1 == ~T3_E~0); 81893#L1354-1 assume !(1 == ~T4_E~0); 81894#L1359-1 assume !(1 == ~T5_E~0); 82658#L1364-1 assume !(1 == ~T6_E~0); 82659#L1369-1 assume !(1 == ~T7_E~0); 83032#L1374-1 assume !(1 == ~T8_E~0); 83027#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 83026#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 83025#L1389-1 assume !(1 == ~T11_E~0); 82510#L1394-1 assume !(1 == ~T12_E~0); 82511#L1399-1 assume !(1 == ~E_M~0); 82932#L1404-1 assume !(1 == ~E_1~0); 82930#L1409-1 assume !(1 == ~E_2~0); 82928#L1414-1 assume !(1 == ~E_3~0); 82926#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 82857#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 82855#L1429-1 assume !(1 == ~E_6~0); 82804#L1434-1 assume !(1 == ~E_7~0); 82790#L1439-1 assume !(1 == ~E_8~0); 82788#L1444-1 assume !(1 == ~E_9~0); 82770#L1449-1 assume !(1 == ~E_10~0); 82757#L1454-1 assume !(1 == ~E_11~0); 82746#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 82736#L1464-1 assume { :end_inline_reset_delta_events } true; 82729#L1810-2 [2022-12-13 15:12:02,091 INFO L750 eck$LassoCheckResult]: Loop: 82729#L1810-2 assume !false; 82726#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 82722#L1176 assume !false; 82721#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 82718#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 82707#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 82706#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 82704#L1003 assume !(0 != eval_~tmp~0#1); 82703#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 82702#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 82701#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 82700#L1201-5 assume !(0 == ~T1_E~0); 82698#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 82699#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 90510#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 90507#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 90505#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 90503#L1231-3 assume !(0 == ~T7_E~0); 90501#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 90499#L1241-3 assume !(0 == ~T9_E~0); 90497#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 90494#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 90492#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 90490#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 90488#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 90486#L1271-3 assume !(0 == ~E_2~0); 90484#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 90481#L1281-3 assume !(0 == ~E_4~0); 90479#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 90477#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 90475#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 90473#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 90471#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 90468#L1311-3 assume !(0 == ~E_10~0); 90466#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 90464#L1321-3 assume !(0 == ~E_12~0); 90462#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 90460#L593-42 assume 1 == ~m_pc~0; 90457#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 90454#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 90452#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 90450#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 90221#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 89592#L612-42 assume 1 == ~t1_pc~0; 89529#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 89514#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 89504#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 89496#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 89216#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 89211#L631-42 assume 1 == ~t2_pc~0; 89157#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 89155#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 89144#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 89134#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 89125#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 89121#L650-42 assume 1 == ~t3_pc~0; 89115#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 89110#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 89107#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 89105#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 89103#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 89101#L669-42 assume !(1 == ~t4_pc~0); 89099#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 87384#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 87378#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 87363#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 87359#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 87356#L688-42 assume 1 == ~t5_pc~0; 87351#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 87348#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 87345#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 87342#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 87338#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 87335#L707-42 assume 1 == ~t6_pc~0; 87331#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 87328#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 87325#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 87322#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 87320#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 83581#L726-42 assume !(1 == ~t7_pc~0); 83577#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 83574#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 83572#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 83570#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 83568#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 83565#L745-42 assume 1 == ~t8_pc~0; 83563#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 83560#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 83558#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 83556#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 83554#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 83551#L764-42 assume !(1 == ~t9_pc~0); 83549#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 83546#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 83545#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 83544#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 83543#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 83542#L783-42 assume 1 == ~t10_pc~0; 83541#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 83539#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 83538#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 83537#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 83536#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 83399#L802-42 assume !(1 == ~t11_pc~0); 83397#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 83394#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 83392#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 83390#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 83388#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 83387#L821-42 assume !(1 == ~t12_pc~0); 83383#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 83381#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 83379#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 83377#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 83375#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83373#L1339-3 assume !(1 == ~M_E~0); 83235#L1339-5 assume !(1 == ~T1_E~0); 83119#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 82131#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 83115#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 83113#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 83111#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 83109#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 83107#L1374-3 assume !(1 == ~T8_E~0); 83105#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 83101#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 83099#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 83097#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 83095#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 83093#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 83001#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 82999#L1414-3 assume !(1 == ~E_3~0); 82997#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 82993#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 82991#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 82989#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 82986#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 82984#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 82982#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 82906#L1454-3 assume !(1 == ~E_11~0); 82904#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 82901#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 82848#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 82841#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 82840#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 82829#L1829 assume !(0 == start_simulation_~tmp~3#1); 82827#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 82794#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 82789#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 82787#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 82769#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 82756#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 82745#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 82735#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 82729#L1810-2 [2022-12-13 15:12:02,091 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:02,092 INFO L85 PathProgramCache]: Analyzing trace with hash 1087243328, now seen corresponding path program 1 times [2022-12-13 15:12:02,092 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:02,092 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1996119625] [2022-12-13 15:12:02,092 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:02,092 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:02,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:02,131 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:02,132 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:02,132 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1996119625] [2022-12-13 15:12:02,132 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1996119625] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:02,132 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:02,132 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 15:12:02,132 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1471745676] [2022-12-13 15:12:02,132 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:02,133 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:02,133 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:02,133 INFO L85 PathProgramCache]: Analyzing trace with hash -1555017190, now seen corresponding path program 1 times [2022-12-13 15:12:02,133 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:02,133 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1404460722] [2022-12-13 15:12:02,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:02,134 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:02,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:02,182 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:02,182 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:02,182 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1404460722] [2022-12-13 15:12:02,182 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1404460722] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:02,182 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:02,183 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:02,183 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1732789304] [2022-12-13 15:12:02,183 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:02,183 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:02,183 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:02,183 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:12:02,184 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:12:02,184 INFO L87 Difference]: Start difference. First operand 12481 states and 18328 transitions. cyclomatic complexity: 5855 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:02,359 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:02,359 INFO L93 Difference]: Finished difference Result 24576 states and 35870 transitions. [2022-12-13 15:12:02,359 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24576 states and 35870 transitions. [2022-12-13 15:12:02,429 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24344 [2022-12-13 15:12:02,508 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24576 states to 24576 states and 35870 transitions. [2022-12-13 15:12:02,508 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24576 [2022-12-13 15:12:02,518 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24576 [2022-12-13 15:12:02,518 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24576 states and 35870 transitions. [2022-12-13 15:12:02,528 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:12:02,529 INFO L218 hiAutomatonCegarLoop]: Abstraction has 24576 states and 35870 transitions. [2022-12-13 15:12:02,541 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24576 states and 35870 transitions. [2022-12-13 15:12:02,767 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24576 to 23856. [2022-12-13 15:12:02,781 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23856 states, 23856 states have (on average 1.461016096579477) internal successors, (34854), 23855 states have internal predecessors, (34854), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:02,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23856 states to 23856 states and 34854 transitions. [2022-12-13 15:12:02,807 INFO L240 hiAutomatonCegarLoop]: Abstraction has 23856 states and 34854 transitions. [2022-12-13 15:12:02,808 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:12:02,808 INFO L428 stractBuchiCegarLoop]: Abstraction has 23856 states and 34854 transitions. [2022-12-13 15:12:02,808 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-12-13 15:12:02,808 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23856 states and 34854 transitions. [2022-12-13 15:12:02,854 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 23624 [2022-12-13 15:12:02,854 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:02,855 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:02,856 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:02,856 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:02,856 INFO L748 eck$LassoCheckResult]: Stem: 118176#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 118177#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 119048#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 119049#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 119802#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 119803#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 118706#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 118488#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 117892#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 117893#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 119178#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 119293#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 119935#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 119936#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 118626#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 118627#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 119207#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 119120#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 118663#L1201 assume !(0 == ~M_E~0); 118664#L1201-2 assume !(0 == ~T1_E~0); 119645#L1206-1 assume !(0 == ~T2_E~0); 119614#L1211-1 assume !(0 == ~T3_E~0); 119615#L1216-1 assume !(0 == ~T4_E~0); 118469#L1221-1 assume !(0 == ~T5_E~0); 118470#L1226-1 assume !(0 == ~T6_E~0); 118102#L1231-1 assume !(0 == ~T7_E~0); 118103#L1236-1 assume !(0 == ~T8_E~0); 119687#L1241-1 assume !(0 == ~T9_E~0); 118512#L1246-1 assume !(0 == ~T10_E~0); 118513#L1251-1 assume !(0 == ~T11_E~0); 118661#L1256-1 assume !(0 == ~T12_E~0); 117900#L1261-1 assume !(0 == ~E_M~0); 117901#L1266-1 assume !(0 == ~E_1~0); 119903#L1271-1 assume !(0 == ~E_2~0); 119273#L1276-1 assume !(0 == ~E_3~0); 119274#L1281-1 assume !(0 == ~E_4~0); 119220#L1286-1 assume !(0 == ~E_5~0); 118360#L1291-1 assume !(0 == ~E_6~0); 118361#L1296-1 assume !(0 == ~E_7~0); 118974#L1301-1 assume !(0 == ~E_8~0); 118975#L1306-1 assume !(0 == ~E_9~0); 119534#L1311-1 assume !(0 == ~E_10~0); 118314#L1316-1 assume !(0 == ~E_11~0); 118315#L1321-1 assume !(0 == ~E_12~0); 118995#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 118996#L593 assume !(1 == ~m_pc~0); 118200#L593-2 is_master_triggered_~__retres1~0#1 := 0; 118201#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 118878#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 118879#L1492 assume !(0 != activate_threads_~tmp~1#1); 119230#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 119577#L612 assume !(1 == ~t1_pc~0); 119578#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 119798#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 119388#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 118204#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 118205#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 118643#L631 assume 1 == ~t2_pc~0; 118568#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 117981#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 117982#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 118328#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 118842#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 118275#L650 assume !(1 == ~t3_pc~0); 118276#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 119022#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 119365#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 117938#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 117939#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 119199#L669 assume 1 == ~t4_pc~0; 119200#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 119630#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 118023#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 118024#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 118139#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 118372#L688 assume !(1 == ~t5_pc~0); 118158#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 118159#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 119860#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 119070#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 119071#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 119218#L707 assume 1 == ~t6_pc~0; 119742#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 118810#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 118316#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 118317#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 119156#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 118662#L726 assume 1 == ~t7_pc~0; 118558#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 118241#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 119379#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 119753#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 118009#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 118010#L745 assume !(1 == ~t8_pc~0); 118460#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 118481#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 119659#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 118887#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 118888#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 119484#L764 assume 1 == ~t9_pc~0; 118660#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 118490#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 118390#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 118391#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 118035#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 118036#L783 assume !(1 == ~t10_pc~0); 118090#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 118091#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 118280#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 118620#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 118621#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 119631#L802 assume 1 == ~t11_pc~0; 119604#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 117978#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 117979#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 118471#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 118472#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 118590#L821 assume !(1 == ~t12_pc~0); 118855#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 118964#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 117987#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 117988#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 119701#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 119241#L1339 assume !(1 == ~M_E~0); 119242#L1339-2 assume !(1 == ~T1_E~0); 119755#L1344-1 assume !(1 == ~T2_E~0); 119756#L1349-1 assume !(1 == ~T3_E~0); 119995#L1354-1 assume !(1 == ~T4_E~0); 119458#L1359-1 assume !(1 == ~T5_E~0); 119459#L1364-1 assume !(1 == ~T6_E~0); 118421#L1369-1 assume !(1 == ~T7_E~0); 118422#L1374-1 assume !(1 == ~T8_E~0); 118992#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 118993#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 119117#L1389-1 assume !(1 == ~T11_E~0); 120008#L1394-1 assume !(1 == ~T12_E~0); 121722#L1399-1 assume !(1 == ~E_M~0); 121719#L1404-1 assume !(1 == ~E_1~0); 121716#L1409-1 assume !(1 == ~E_2~0); 121712#L1414-1 assume !(1 == ~E_3~0); 121708#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 121705#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 121702#L1429-1 assume !(1 == ~E_6~0); 121699#L1434-1 assume !(1 == ~E_7~0); 121696#L1439-1 assume !(1 == ~E_8~0); 121692#L1444-1 assume !(1 == ~E_9~0); 121611#L1449-1 assume !(1 == ~E_10~0); 121609#L1454-1 assume !(1 == ~E_11~0); 121599#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 121589#L1464-1 assume { :end_inline_reset_delta_events } true; 121582#L1810-2 [2022-12-13 15:12:02,856 INFO L750 eck$LassoCheckResult]: Loop: 121582#L1810-2 assume !false; 121579#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 121575#L1176 assume !false; 121574#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 121571#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 121560#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 121559#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 121557#L1003 assume !(0 != eval_~tmp~0#1); 121556#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 121555#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 121554#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 121553#L1201-5 assume !(0 == ~T1_E~0); 121549#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 121550#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 131224#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 131223#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 131222#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 121542#L1231-3 assume !(0 == ~T7_E~0); 121541#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 121540#L1241-3 assume !(0 == ~T9_E~0); 121539#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 121538#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 121537#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 121536#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 121535#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 121534#L1271-3 assume !(0 == ~E_2~0); 121533#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 118735#L1281-3 assume !(0 == ~E_4~0); 118736#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 121336#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 121335#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 121334#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 121333#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 118847#L1311-3 assume !(0 == ~E_10~0); 118213#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 118214#L1321-3 assume !(0 == ~E_12~0); 118290#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 118963#L593-42 assume !(1 == ~m_pc~0); 119680#L593-44 is_master_triggered_~__retres1~0#1 := 0; 131213#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 131211#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 131209#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 131207#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 131205#L612-42 assume !(1 == ~t1_pc~0); 131202#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 131200#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 131198#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 131196#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 131194#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 131192#L631-42 assume !(1 == ~t2_pc~0); 131190#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 131187#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 131185#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 131183#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 131181#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 131179#L650-42 assume !(1 == ~t3_pc~0); 131176#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 131174#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 131171#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 131169#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 131059#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 119722#L669-42 assume !(1 == ~t4_pc~0); 119723#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 131061#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 131060#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 131019#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 119212#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 119213#L688-42 assume 1 == ~t5_pc~0; 119309#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 119789#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 118977#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 118134#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 118135#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 117956#L707-42 assume !(1 == ~t6_pc~0); 117957#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 119853#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 118282#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 118283#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 130882#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 130881#L726-42 assume !(1 == ~t7_pc~0); 130880#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 130878#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 130877#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 130876#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 130875#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 130874#L745-42 assume 1 == ~t8_pc~0; 130873#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 130871#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 130870#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 130869#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 130868#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 130867#L764-42 assume 1 == ~t9_pc~0; 130865#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 130864#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 130863#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 130862#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 130861#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 130860#L783-42 assume !(1 == ~t10_pc~0); 121349#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 121350#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 121346#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 121345#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 121344#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 121343#L802-42 assume 1 == ~t11_pc~0; 121341#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 121340#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 121339#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 121337#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 121338#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 130778#L821-42 assume 1 == ~t12_pc~0; 130775#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 121256#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 121255#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 121254#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 121253#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 120986#L1339-3 assume !(1 == ~M_E~0); 120985#L1339-5 assume !(1 == ~T1_E~0); 120984#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 120982#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 120983#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 122586#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 122583#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 122581#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 122579#L1374-3 assume !(1 == ~T8_E~0); 122577#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 120971#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 122549#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 122542#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 122534#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 122527#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 122520#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 122513#L1414-3 assume !(1 == ~E_3~0); 122506#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 122497#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 122491#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 122486#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 122480#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 122475#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 122469#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 122464#L1454-3 assume !(1 == ~E_11~0); 122458#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 122455#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 122444#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 122434#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 122430#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 122011#L1829 assume !(0 == start_simulation_~tmp~3#1); 122009#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 121734#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 121724#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 121612#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 121610#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 121608#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 121598#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 121588#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 121582#L1810-2 [2022-12-13 15:12:02,857 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:02,857 INFO L85 PathProgramCache]: Analyzing trace with hash 1374703233, now seen corresponding path program 1 times [2022-12-13 15:12:02,857 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:02,857 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1607028552] [2022-12-13 15:12:02,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:02,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:02,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:02,904 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:02,904 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:02,904 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1607028552] [2022-12-13 15:12:02,904 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1607028552] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:02,904 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:02,904 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 15:12:02,904 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1752702658] [2022-12-13 15:12:02,904 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:02,905 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:02,905 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:02,905 INFO L85 PathProgramCache]: Analyzing trace with hash 862119133, now seen corresponding path program 1 times [2022-12-13 15:12:02,905 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:02,905 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2042988141] [2022-12-13 15:12:02,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:02,906 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:02,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:02,992 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:02,992 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:02,992 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2042988141] [2022-12-13 15:12:02,993 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2042988141] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:02,993 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:02,993 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:02,993 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1581027649] [2022-12-13 15:12:02,993 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:02,993 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:02,994 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:02,994 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 15:12:02,994 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 15:12:02,994 INFO L87 Difference]: Start difference. First operand 23856 states and 34854 transitions. cyclomatic complexity: 11014 Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:03,464 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:03,465 INFO L93 Difference]: Finished difference Result 68097 states and 99301 transitions. [2022-12-13 15:12:03,465 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 68097 states and 99301 transitions. [2022-12-13 15:12:03,705 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 67512 [2022-12-13 15:12:03,822 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 68097 states to 68097 states and 99301 transitions. [2022-12-13 15:12:03,822 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 68097 [2022-12-13 15:12:03,846 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 68097 [2022-12-13 15:12:03,846 INFO L73 IsDeterministic]: Start isDeterministic. Operand 68097 states and 99301 transitions. [2022-12-13 15:12:03,874 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:12:03,874 INFO L218 hiAutomatonCegarLoop]: Abstraction has 68097 states and 99301 transitions. [2022-12-13 15:12:03,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68097 states and 99301 transitions. [2022-12-13 15:12:04,231 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68097 to 24507. [2022-12-13 15:12:04,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24507 states, 24507 states have (on average 1.448769739258171) internal successors, (35505), 24506 states have internal predecessors, (35505), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:04,279 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24507 states to 24507 states and 35505 transitions. [2022-12-13 15:12:04,279 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24507 states and 35505 transitions. [2022-12-13 15:12:04,280 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 15:12:04,280 INFO L428 stractBuchiCegarLoop]: Abstraction has 24507 states and 35505 transitions. [2022-12-13 15:12:04,280 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-12-13 15:12:04,280 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24507 states and 35505 transitions. [2022-12-13 15:12:04,331 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24272 [2022-12-13 15:12:04,331 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:04,331 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:04,332 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:04,333 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:04,333 INFO L748 eck$LassoCheckResult]: Stem: 210142#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 210143#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 211004#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 211005#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 211746#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 211747#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 210666#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 210454#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 209858#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 209859#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 211138#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 211255#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 211877#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 211878#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 210589#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 210590#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 211167#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 211082#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 210626#L1201 assume !(0 == ~M_E~0); 210627#L1201-2 assume !(0 == ~T1_E~0); 211616#L1206-1 assume !(0 == ~T2_E~0); 211590#L1211-1 assume !(0 == ~T3_E~0); 211591#L1216-1 assume !(0 == ~T4_E~0); 210432#L1221-1 assume !(0 == ~T5_E~0); 210433#L1226-1 assume !(0 == ~T6_E~0); 210068#L1231-1 assume !(0 == ~T7_E~0); 210069#L1236-1 assume !(0 == ~T8_E~0); 211650#L1241-1 assume !(0 == ~T9_E~0); 210473#L1246-1 assume !(0 == ~T10_E~0); 210474#L1251-1 assume !(0 == ~T11_E~0); 210624#L1256-1 assume !(0 == ~T12_E~0); 209866#L1261-1 assume !(0 == ~E_M~0); 209867#L1266-1 assume !(0 == ~E_1~0); 211838#L1271-1 assume !(0 == ~E_2~0); 211236#L1276-1 assume !(0 == ~E_3~0); 211237#L1281-1 assume !(0 == ~E_4~0); 211181#L1286-1 assume !(0 == ~E_5~0); 210326#L1291-1 assume !(0 == ~E_6~0); 210327#L1296-1 assume !(0 == ~E_7~0); 210936#L1301-1 assume !(0 == ~E_8~0); 210937#L1306-1 assume !(0 == ~E_9~0); 211499#L1311-1 assume !(0 == ~E_10~0); 210280#L1316-1 assume !(0 == ~E_11~0); 210281#L1321-1 assume !(0 == ~E_12~0); 210956#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 210957#L593 assume !(1 == ~m_pc~0); 210166#L593-2 is_master_triggered_~__retres1~0#1 := 0; 210167#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 210841#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 210842#L1492 assume !(0 != activate_threads_~tmp~1#1); 211192#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 211551#L612 assume !(1 == ~t1_pc~0); 211552#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 211860#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 211861#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 210170#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 210171#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 210606#L631 assume 1 == ~t2_pc~0; 210532#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 209947#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 209948#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 210294#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 210802#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 210239#L650 assume !(1 == ~t3_pc~0); 210240#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 210981#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 211325#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 209904#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 209905#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 211160#L669 assume 1 == ~t4_pc~0; 211161#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 211603#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 209985#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 209986#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 210105#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 210337#L688 assume !(1 == ~t5_pc~0); 210124#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 210125#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 211806#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 211028#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 211029#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 211174#L707 assume 1 == ~t6_pc~0; 211694#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 210769#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 210282#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 210283#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 211113#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 210625#L726 assume 1 == ~t7_pc~0; 210520#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 210208#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 211337#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 211703#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 209975#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 209976#L745 assume !(1 == ~t8_pc~0); 210425#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 210447#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 211626#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 210850#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 210851#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 211449#L764 assume 1 == ~t9_pc~0; 210623#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 210456#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 210355#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 210356#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 210001#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 210002#L783 assume !(1 == ~t10_pc~0); 210056#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 210057#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 210246#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 210578#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 210579#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 211606#L802 assume 1 == ~t11_pc~0; 211580#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 209944#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 209945#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 210434#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 210435#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 210553#L821 assume !(1 == ~t12_pc~0); 210817#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 210928#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 209951#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 209952#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 211663#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 211203#L1339 assume !(1 == ~M_E~0); 211204#L1339-2 assume !(1 == ~T1_E~0); 211706#L1344-1 assume !(1 == ~T2_E~0); 211707#L1349-1 assume !(1 == ~T3_E~0); 219499#L1354-1 assume !(1 == ~T4_E~0); 219498#L1359-1 assume !(1 == ~T5_E~0); 219497#L1364-1 assume !(1 == ~T6_E~0); 219496#L1369-1 assume !(1 == ~T7_E~0); 219495#L1374-1 assume !(1 == ~T8_E~0); 219494#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 219493#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 219489#L1389-1 assume !(1 == ~T11_E~0); 219487#L1394-1 assume !(1 == ~T12_E~0); 219485#L1399-1 assume !(1 == ~E_M~0); 219480#L1404-1 assume !(1 == ~E_1~0); 219474#L1409-1 assume !(1 == ~E_2~0); 219472#L1414-1 assume !(1 == ~E_3~0); 219469#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 219470#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 227108#L1429-1 assume !(1 == ~E_6~0); 227092#L1434-1 assume !(1 == ~E_7~0); 227090#L1439-1 assume !(1 == ~E_8~0); 227088#L1444-1 assume !(1 == ~E_9~0); 227085#L1449-1 assume !(1 == ~E_10~0); 227083#L1454-1 assume !(1 == ~E_11~0); 220158#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 220156#L1464-1 assume { :end_inline_reset_delta_events } true; 220153#L1810-2 [2022-12-13 15:12:04,333 INFO L750 eck$LassoCheckResult]: Loop: 220153#L1810-2 assume !false; 219478#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 219473#L1176 assume !false; 219471#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 218880#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 218142#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 218140#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 218138#L1003 assume !(0 != eval_~tmp~0#1); 218139#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 225691#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 225689#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 225686#L1201-5 assume !(0 == ~T1_E~0); 225684#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 225682#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 225680#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 225678#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 225676#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 225673#L1231-3 assume !(0 == ~T7_E~0); 225671#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 225669#L1241-3 assume !(0 == ~T9_E~0); 225667#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 225665#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 225663#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 225660#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 225658#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 225656#L1271-3 assume !(0 == ~E_2~0); 225654#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 225652#L1281-3 assume !(0 == ~E_4~0); 225650#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 225647#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 225645#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 225643#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 225641#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 225639#L1311-3 assume !(0 == ~E_10~0); 225637#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 225636#L1321-3 assume !(0 == ~E_12~0); 225635#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 225634#L593-42 assume !(1 == ~m_pc~0); 225633#L593-44 is_master_triggered_~__retres1~0#1 := 0; 225632#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 225631#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 225630#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 225629#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 225628#L612-42 assume !(1 == ~t1_pc~0); 225627#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 225625#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 225623#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 225621#L1500-42 assume !(0 != activate_threads_~tmp___0~0#1); 225618#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 225616#L631-42 assume !(1 == ~t2_pc~0); 225614#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 225611#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 225609#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 225534#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 225530#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 225526#L650-42 assume 1 == ~t3_pc~0; 225521#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 225500#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 225496#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 225492#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 225488#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 225470#L669-42 assume !(1 == ~t4_pc~0); 225466#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 225460#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 225455#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 225451#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 225446#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 225442#L688-42 assume !(1 == ~t5_pc~0); 225438#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 225432#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 225427#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 225423#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 225418#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 225414#L707-42 assume !(1 == ~t6_pc~0); 225410#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 225404#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 225399#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 225395#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 225390#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 225386#L726-42 assume !(1 == ~t7_pc~0); 225382#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 225376#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 225371#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 225367#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 225362#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 225358#L745-42 assume 1 == ~t8_pc~0; 225354#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 225348#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 225343#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 225339#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 225334#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 225330#L764-42 assume !(1 == ~t9_pc~0); 225326#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 225320#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 225315#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 225311#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 225306#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 225302#L783-42 assume 1 == ~t10_pc~0; 225298#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 225292#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 225287#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 225283#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 225278#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 225274#L802-42 assume !(1 == ~t11_pc~0); 225270#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 225264#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 225259#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 225255#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 225250#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 225246#L821-42 assume 1 == ~t12_pc~0; 225242#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 225236#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 225231#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 225227#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 225222#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 225218#L1339-3 assume !(1 == ~M_E~0); 225214#L1339-5 assume !(1 == ~T1_E~0); 225210#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 213220#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 225202#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 225197#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 225193#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 225189#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 225185#L1374-3 assume !(1 == ~T8_E~0); 225180#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 213211#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 225172#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 225168#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 225164#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 225160#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 225156#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 225152#L1414-3 assume !(1 == ~E_3~0); 225149#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 222560#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 225144#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 225125#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 225121#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 225117#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 225111#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 225107#L1454-3 assume !(1 == ~E_11~0); 225103#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 225100#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 225067#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 225058#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 225053#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 225049#L1829 assume !(0 == start_simulation_~tmp~3#1); 225048#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 225037#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 225032#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 225030#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 225028#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 225025#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 225023#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 220155#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 220153#L1810-2 [2022-12-13 15:12:04,334 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:04,334 INFO L85 PathProgramCache]: Analyzing trace with hash -1568878845, now seen corresponding path program 1 times [2022-12-13 15:12:04,334 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:04,334 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1257988083] [2022-12-13 15:12:04,334 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:04,334 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:04,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:04,422 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:04,422 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:04,422 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1257988083] [2022-12-13 15:12:04,422 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1257988083] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:04,422 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:04,422 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:04,423 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2057403069] [2022-12-13 15:12:04,423 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:04,423 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:04,423 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:04,424 INFO L85 PathProgramCache]: Analyzing trace with hash 1876372512, now seen corresponding path program 1 times [2022-12-13 15:12:04,424 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:04,424 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [749919907] [2022-12-13 15:12:04,424 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:04,424 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:04,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:04,454 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:04,454 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:04,455 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [749919907] [2022-12-13 15:12:04,455 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [749919907] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:04,455 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:04,455 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:04,455 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1207830] [2022-12-13 15:12:04,455 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:04,455 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:04,456 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:04,456 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 15:12:04,456 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 15:12:04,456 INFO L87 Difference]: Start difference. First operand 24507 states and 35505 transitions. cyclomatic complexity: 11014 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:04,835 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:04,835 INFO L93 Difference]: Finished difference Result 59818 states and 86081 transitions. [2022-12-13 15:12:04,835 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 59818 states and 86081 transitions. [2022-12-13 15:12:05,039 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 58776 [2022-12-13 15:12:05,167 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 59818 states to 59818 states and 86081 transitions. [2022-12-13 15:12:05,167 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 59818 [2022-12-13 15:12:05,192 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 59818 [2022-12-13 15:12:05,192 INFO L73 IsDeterministic]: Start isDeterministic. Operand 59818 states and 86081 transitions. [2022-12-13 15:12:05,225 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:12:05,225 INFO L218 hiAutomatonCegarLoop]: Abstraction has 59818 states and 86081 transitions. [2022-12-13 15:12:05,252 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59818 states and 86081 transitions. [2022-12-13 15:12:05,720 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59818 to 47010. [2022-12-13 15:12:05,745 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47010 states, 47010 states have (on average 1.4430972133588598) internal successors, (67840), 47009 states have internal predecessors, (67840), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:05,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47010 states to 47010 states and 67840 transitions. [2022-12-13 15:12:05,795 INFO L240 hiAutomatonCegarLoop]: Abstraction has 47010 states and 67840 transitions. [2022-12-13 15:12:05,796 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 15:12:05,796 INFO L428 stractBuchiCegarLoop]: Abstraction has 47010 states and 67840 transitions. [2022-12-13 15:12:05,796 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-12-13 15:12:05,796 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47010 states and 67840 transitions. [2022-12-13 15:12:05,958 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 46768 [2022-12-13 15:12:05,958 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:05,958 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:05,960 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:05,960 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:05,960 INFO L748 eck$LassoCheckResult]: Stem: 294479#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 294480#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 295336#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 295337#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 296028#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 296029#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 295002#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 294793#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 294193#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 294194#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 295457#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 295576#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 296137#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 296138#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 294923#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 294924#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 295488#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 295403#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 294961#L1201 assume !(0 == ~M_E~0); 294962#L1201-2 assume !(0 == ~T1_E~0); 295915#L1206-1 assume !(0 == ~T2_E~0); 295894#L1211-1 assume !(0 == ~T3_E~0); 295895#L1216-1 assume !(0 == ~T4_E~0); 294775#L1221-1 assume !(0 == ~T5_E~0); 294776#L1226-1 assume !(0 == ~T6_E~0); 294405#L1231-1 assume !(0 == ~T7_E~0); 294406#L1236-1 assume !(0 == ~T8_E~0); 295945#L1241-1 assume !(0 == ~T9_E~0); 294815#L1246-1 assume !(0 == ~T10_E~0); 294816#L1251-1 assume !(0 == ~T11_E~0); 294959#L1256-1 assume !(0 == ~T12_E~0); 294202#L1261-1 assume !(0 == ~E_M~0); 294203#L1266-1 assume !(0 == ~E_1~0); 296115#L1271-1 assume !(0 == ~E_2~0); 295557#L1276-1 assume !(0 == ~E_3~0); 295558#L1281-1 assume !(0 == ~E_4~0); 295500#L1286-1 assume !(0 == ~E_5~0); 294663#L1291-1 assume !(0 == ~E_6~0); 294664#L1296-1 assume !(0 == ~E_7~0); 295271#L1301-1 assume !(0 == ~E_8~0); 295272#L1306-1 assume !(0 == ~E_9~0); 295818#L1311-1 assume !(0 == ~E_10~0); 294617#L1316-1 assume !(0 == ~E_11~0); 294618#L1321-1 assume !(0 == ~E_12~0); 295290#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 295291#L593 assume !(1 == ~m_pc~0); 294503#L593-2 is_master_triggered_~__retres1~0#1 := 0; 294504#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 295169#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 295170#L1492 assume !(0 != activate_threads_~tmp~1#1); 295511#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 295858#L612 assume !(1 == ~t1_pc~0); 295859#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 296131#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 295664#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 294507#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 294508#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 294940#L631 assume !(1 == ~t2_pc~0); 294941#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 294282#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 294283#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 294631#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 295132#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 294579#L650 assume !(1 == ~t3_pc~0); 294580#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 295315#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 295641#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 294240#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 294241#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 295481#L669 assume 1 == ~t4_pc~0; 295482#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 295905#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 294325#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 294326#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 294442#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 294675#L688 assume !(1 == ~t5_pc~0); 294461#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 294462#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 296080#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 295358#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 295359#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 295498#L707 assume 1 == ~t6_pc~0; 295987#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 295101#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 294619#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 294620#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 295438#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 294960#L726 assume 1 == ~t7_pc~0; 294860#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 294545#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 295654#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 295995#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 294311#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 294312#L745 assume !(1 == ~t8_pc~0); 294767#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 294787#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 295922#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 295178#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 295179#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 295763#L764 assume 1 == ~t9_pc~0; 294958#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 294795#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 294694#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 294695#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 294337#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 294338#L783 assume !(1 == ~t10_pc~0); 294392#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 294393#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 294584#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 294917#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 294918#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 295906#L802 assume 1 == ~t11_pc~0; 295884#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 294279#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 294280#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 294777#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 294778#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 294889#L821 assume !(1 == ~t12_pc~0); 295147#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 295261#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 294288#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 294289#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 295956#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 295521#L1339 assume !(1 == ~M_E~0); 295522#L1339-2 assume !(1 == ~T1_E~0); 295997#L1344-1 assume !(1 == ~T2_E~0); 295998#L1349-1 assume !(1 == ~T3_E~0); 295284#L1354-1 assume !(1 == ~T4_E~0); 295285#L1359-1 assume !(1 == ~T5_E~0); 296133#L1364-1 assume !(1 == ~T6_E~0); 296134#L1369-1 assume !(1 == ~T7_E~0); 295704#L1374-1 assume !(1 == ~T8_E~0); 295705#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 308295#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 308294#L1389-1 assume !(1 == ~T11_E~0); 308293#L1394-1 assume !(1 == ~T12_E~0); 308292#L1399-1 assume !(1 == ~E_M~0); 308291#L1404-1 assume !(1 == ~E_1~0); 308290#L1409-1 assume !(1 == ~E_2~0); 308289#L1414-1 assume !(1 == ~E_3~0); 308287#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 308288#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 295299#L1429-1 assume !(1 == ~E_6~0); 295300#L1434-1 assume !(1 == ~E_7~0); 296150#L1439-1 assume !(1 == ~E_8~0); 296151#L1444-1 assume !(1 == ~E_9~0); 295541#L1449-1 assume !(1 == ~E_10~0); 295542#L1454-1 assume !(1 == ~E_11~0); 295992#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 295993#L1464-1 assume { :end_inline_reset_delta_events } true; 314537#L1810-2 [2022-12-13 15:12:05,961 INFO L750 eck$LassoCheckResult]: Loop: 314537#L1810-2 assume !false; 314269#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 314264#L1176 assume !false; 314263#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 313853#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 313839#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 313833#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 313825#L1003 assume !(0 != eval_~tmp~0#1); 313826#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 319523#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 319519#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 319515#L1201-5 assume !(0 == ~T1_E~0); 319512#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 319509#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 319506#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 319503#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 319499#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 319478#L1231-3 assume !(0 == ~T7_E~0); 319474#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 319470#L1241-3 assume !(0 == ~T9_E~0); 319466#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 319462#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 319457#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 319451#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 319447#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 319443#L1271-3 assume !(0 == ~E_2~0); 319439#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 319435#L1281-3 assume !(0 == ~E_4~0); 319430#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 319424#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 319420#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 319416#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 319412#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 319408#L1311-3 assume !(0 == ~E_10~0); 319404#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 319400#L1321-3 assume !(0 == ~E_12~0); 318713#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 318709#L593-42 assume !(1 == ~m_pc~0); 318644#L593-44 is_master_triggered_~__retres1~0#1 := 0; 318640#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 318633#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 318632#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 318631#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 318630#L612-42 assume 1 == ~t1_pc~0; 318628#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 318626#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 318624#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 318408#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 317965#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 295217#L631-42 assume !(1 == ~t2_pc~0); 295218#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 316837#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 316829#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 316822#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 316798#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 316795#L650-42 assume !(1 == ~t3_pc~0); 316792#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 316790#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 316788#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 316786#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 316784#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 316781#L669-42 assume 1 == ~t4_pc~0; 316778#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 316769#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 316760#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 316750#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 316741#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 316733#L688-42 assume 1 == ~t5_pc~0; 316725#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 316718#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 316711#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 316703#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 316696#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 316689#L707-42 assume 1 == ~t6_pc~0; 316681#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 316679#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 316677#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 316674#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 316672#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 316661#L726-42 assume 1 == ~t7_pc~0; 316653#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 316646#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 316640#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 316632#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 316626#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 316617#L745-42 assume !(1 == ~t8_pc~0); 316610#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 316604#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 316598#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 316590#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 316584#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 316575#L764-42 assume 1 == ~t9_pc~0; 316569#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 316563#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 316556#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 316549#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 316543#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 316534#L783-42 assume 1 == ~t10_pc~0; 316528#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 316336#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 316334#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 316204#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 316200#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 316198#L802-42 assume 1 == ~t11_pc~0; 316192#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 316185#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 316157#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 314673#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 314670#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 314668#L821-42 assume !(1 == ~t12_pc~0); 314665#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 314663#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 314661#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 314659#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 314656#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 314654#L1339-3 assume !(1 == ~M_E~0); 314652#L1339-5 assume !(1 == ~T1_E~0); 314650#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 309092#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 314645#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 314642#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 314640#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 314638#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 314636#L1374-3 assume !(1 == ~T8_E~0); 314634#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 314631#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 314627#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 314625#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 314623#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 314619#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 314618#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 314616#L1414-3 assume !(1 == ~E_3~0); 314614#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 311942#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 314611#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 314609#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 314605#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 314603#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 314601#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 314599#L1454-3 assume !(1 == ~E_11~0); 314597#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 314593#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 314579#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 314571#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 314569#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 314564#L1829 assume !(0 == start_simulation_~tmp~3#1); 314563#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 314553#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 314549#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 314545#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 314543#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 314541#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 314540#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 314539#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 314537#L1810-2 [2022-12-13 15:12:05,961 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:05,961 INFO L85 PathProgramCache]: Analyzing trace with hash -451693884, now seen corresponding path program 1 times [2022-12-13 15:12:05,961 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:05,961 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1388494682] [2022-12-13 15:12:05,962 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:05,962 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:05,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:06,014 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:06,014 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:06,014 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1388494682] [2022-12-13 15:12:06,014 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1388494682] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:06,014 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:06,015 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 15:12:06,015 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1393516064] [2022-12-13 15:12:06,015 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:06,015 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:06,015 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:06,016 INFO L85 PathProgramCache]: Analyzing trace with hash 1737612442, now seen corresponding path program 1 times [2022-12-13 15:12:06,016 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:06,016 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1355784604] [2022-12-13 15:12:06,016 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:06,016 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:06,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:06,059 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:06,059 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:06,060 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1355784604] [2022-12-13 15:12:06,060 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1355784604] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:06,060 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:06,060 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:06,060 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1339213066] [2022-12-13 15:12:06,060 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:06,060 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:06,061 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:06,061 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:12:06,061 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:12:06,061 INFO L87 Difference]: Start difference. First operand 47010 states and 67840 transitions. cyclomatic complexity: 20846 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:06,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:06,324 INFO L93 Difference]: Finished difference Result 90337 states and 129873 transitions. [2022-12-13 15:12:06,324 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 90337 states and 129873 transitions. [2022-12-13 15:12:06,606 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 90016 [2022-12-13 15:12:06,847 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 90337 states to 90337 states and 129873 transitions. [2022-12-13 15:12:06,847 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 90337 [2022-12-13 15:12:06,881 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 90337 [2022-12-13 15:12:06,881 INFO L73 IsDeterministic]: Start isDeterministic. Operand 90337 states and 129873 transitions. [2022-12-13 15:12:06,931 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:12:06,931 INFO L218 hiAutomatonCegarLoop]: Abstraction has 90337 states and 129873 transitions. [2022-12-13 15:12:06,963 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90337 states and 129873 transitions. [2022-12-13 15:12:07,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90337 to 90273. [2022-12-13 15:12:07,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 90273 states, 90273 states have (on average 1.4379604089816447) internal successors, (129809), 90272 states have internal predecessors, (129809), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:07,853 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90273 states to 90273 states and 129809 transitions. [2022-12-13 15:12:07,853 INFO L240 hiAutomatonCegarLoop]: Abstraction has 90273 states and 129809 transitions. [2022-12-13 15:12:07,853 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:12:07,854 INFO L428 stractBuchiCegarLoop]: Abstraction has 90273 states and 129809 transitions. [2022-12-13 15:12:07,854 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-12-13 15:12:07,854 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 90273 states and 129809 transitions. [2022-12-13 15:12:08,107 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 89952 [2022-12-13 15:12:08,107 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:08,107 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:08,109 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:08,109 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:08,110 INFO L748 eck$LassoCheckResult]: Stem: 431830#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 431831#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 432680#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 432681#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 433393#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 433394#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 432351#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 432141#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 431547#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 431548#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 432808#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 432934#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 433489#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 433490#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 432273#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 432274#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 432840#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 432754#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 432311#L1201 assume !(0 == ~M_E~0); 432312#L1201-2 assume !(0 == ~T1_E~0); 433268#L1206-1 assume !(0 == ~T2_E~0); 433246#L1211-1 assume !(0 == ~T3_E~0); 433247#L1216-1 assume !(0 == ~T4_E~0); 432122#L1221-1 assume !(0 == ~T5_E~0); 432123#L1226-1 assume !(0 == ~T6_E~0); 431756#L1231-1 assume !(0 == ~T7_E~0); 431757#L1236-1 assume !(0 == ~T8_E~0); 433303#L1241-1 assume !(0 == ~T9_E~0); 432164#L1246-1 assume !(0 == ~T10_E~0); 432165#L1251-1 assume !(0 == ~T11_E~0); 432309#L1256-1 assume !(0 == ~T12_E~0); 431556#L1261-1 assume !(0 == ~E_M~0); 431557#L1266-1 assume !(0 == ~E_1~0); 433466#L1271-1 assume !(0 == ~E_2~0); 432916#L1276-1 assume !(0 == ~E_3~0); 432917#L1281-1 assume !(0 == ~E_4~0); 432853#L1286-1 assume !(0 == ~E_5~0); 432014#L1291-1 assume !(0 == ~E_6~0); 432015#L1296-1 assume !(0 == ~E_7~0); 432616#L1301-1 assume !(0 == ~E_8~0); 432617#L1306-1 assume !(0 == ~E_9~0); 433166#L1311-1 assume !(0 == ~E_10~0); 431966#L1316-1 assume !(0 == ~E_11~0); 431967#L1321-1 assume !(0 == ~E_12~0); 432636#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 432637#L593 assume !(1 == ~m_pc~0); 431854#L593-2 is_master_triggered_~__retres1~0#1 := 0; 431855#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 432521#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 432522#L1492 assume !(0 != activate_threads_~tmp~1#1); 432867#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 433211#L612 assume !(1 == ~t1_pc~0); 433212#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 433483#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 433021#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 431858#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 431859#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 432290#L631 assume !(1 == ~t2_pc~0); 432291#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 431635#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 431636#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 431980#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 432483#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 431928#L650 assume !(1 == ~t3_pc~0); 431929#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 432660#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 432999#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 431594#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 431595#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 432833#L669 assume !(1 == ~t4_pc~0); 432834#L669-2 is_transmit4_triggered_~__retres1~4#1 := 0; 433258#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 431677#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 431678#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 431793#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 432025#L688 assume !(1 == ~t5_pc~0); 431812#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 431813#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 433436#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 432705#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 432706#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 432850#L707 assume 1 == ~t6_pc~0; 433342#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 432452#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 431968#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 431969#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 432785#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 432310#L726 assume 1 == ~t7_pc~0; 432209#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 431895#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 433011#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 433347#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 431663#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 431664#L745 assume !(1 == ~t8_pc~0); 432115#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 432135#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 433278#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 432530#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 432531#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 433117#L764 assume 1 == ~t9_pc~0; 432308#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 432143#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 432043#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 432044#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 431689#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 431690#L783 assume !(1 == ~t10_pc~0); 431744#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 431745#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 431933#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 432268#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 432269#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 433259#L802 assume 1 == ~t11_pc~0; 433236#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 431632#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 431633#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 432124#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 432125#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 432239#L821 assume !(1 == ~t12_pc~0); 432498#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 432607#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 431641#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 431642#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 433314#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 432877#L1339 assume !(1 == ~M_E~0); 432878#L1339-2 assume !(1 == ~T1_E~0); 433351#L1344-1 assume !(1 == ~T2_E~0); 433352#L1349-1 assume !(1 == ~T3_E~0); 448754#L1354-1 assume !(1 == ~T4_E~0); 448752#L1359-1 assume !(1 == ~T5_E~0); 448750#L1364-1 assume !(1 == ~T6_E~0); 448748#L1369-1 assume !(1 == ~T7_E~0); 448745#L1374-1 assume !(1 == ~T8_E~0); 448743#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 432748#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 432749#L1389-1 assume !(1 == ~T11_E~0); 433308#L1394-1 assume !(1 == ~T12_E~0); 433309#L1399-1 assume !(1 == ~E_M~0); 433428#L1404-1 assume !(1 == ~E_1~0); 432168#L1409-1 assume !(1 == ~E_2~0); 432169#L1414-1 assume !(1 == ~E_3~0); 462749#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 462747#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 462745#L1429-1 assume !(1 == ~E_6~0); 462743#L1434-1 assume !(1 == ~E_7~0); 462741#L1439-1 assume !(1 == ~E_8~0); 462739#L1444-1 assume !(1 == ~E_9~0); 462738#L1449-1 assume !(1 == ~E_10~0); 462737#L1454-1 assume !(1 == ~E_11~0); 462734#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 432781#L1464-1 assume { :end_inline_reset_delta_events } true; 432782#L1810-2 [2022-12-13 15:12:08,110 INFO L750 eck$LassoCheckResult]: Loop: 432782#L1810-2 assume !false; 472078#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 472071#L1176 assume !false; 471584#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 460015#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 460003#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 460001#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 459998#L1003 assume !(0 != eval_~tmp~0#1); 459999#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 475900#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 475899#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 475898#L1201-5 assume !(0 == ~T1_E~0); 475897#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 475896#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 475895#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 475894#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 475893#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 475892#L1231-3 assume !(0 == ~T7_E~0); 475891#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 475890#L1241-3 assume !(0 == ~T9_E~0); 475889#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 475888#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 475887#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 475886#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 475885#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 475884#L1271-3 assume !(0 == ~E_2~0); 475883#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 475882#L1281-3 assume !(0 == ~E_4~0); 475881#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 475880#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 475879#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 475878#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 475877#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 475876#L1311-3 assume !(0 == ~E_10~0); 475875#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 475874#L1321-3 assume !(0 == ~E_12~0); 475873#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 475872#L593-42 assume !(1 == ~m_pc~0); 475871#L593-44 is_master_triggered_~__retres1~0#1 := 0; 475870#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 475869#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 475868#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 475867#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 475866#L612-42 assume !(1 == ~t1_pc~0); 475865#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 475863#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 475861#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 475859#L1500-42 assume !(0 != activate_threads_~tmp___0~0#1); 475857#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 473321#L631-42 assume !(1 == ~t2_pc~0); 473316#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 473310#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 473292#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 473267#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 472744#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 472741#L650-42 assume 1 == ~t3_pc~0; 472739#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 472736#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 472734#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 472732#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 472730#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 472727#L669-42 assume !(1 == ~t4_pc~0); 472725#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 472723#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 472721#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 472719#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 472717#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 472716#L688-42 assume !(1 == ~t5_pc~0); 472715#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 472711#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 472709#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 472707#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 472705#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 472703#L707-42 assume !(1 == ~t6_pc~0); 472701#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 472697#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 472695#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 472693#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 472691#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 472689#L726-42 assume !(1 == ~t7_pc~0); 472684#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 472681#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 472679#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 472677#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 472675#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 472673#L745-42 assume 1 == ~t8_pc~0; 472670#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 472667#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 472665#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 472663#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 472661#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 472659#L764-42 assume !(1 == ~t9_pc~0); 472656#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 472653#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 472651#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 472649#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 472647#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 472644#L783-42 assume 1 == ~t10_pc~0; 472642#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 472639#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 472637#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 472635#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 472633#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 472632#L802-42 assume !(1 == ~t11_pc~0); 472631#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 472627#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 472625#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 472623#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 472621#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 472619#L821-42 assume 1 == ~t12_pc~0; 472617#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 472613#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 472611#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 472609#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 472607#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 472605#L1339-3 assume !(1 == ~M_E~0); 472603#L1339-5 assume !(1 == ~T1_E~0); 472600#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 444225#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 472597#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 472595#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 472593#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 472591#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 472588#L1374-3 assume !(1 == ~T8_E~0); 472586#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 444208#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 472583#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 472581#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 472579#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 472576#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 472574#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 472572#L1414-3 assume !(1 == ~E_3~0); 472570#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 468868#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 472567#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 472564#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 472562#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 472560#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 472558#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 472556#L1454-3 assume !(1 == ~E_11~0); 472554#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 462922#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 472528#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 472520#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 472518#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 472430#L1829 assume !(0 == start_simulation_~tmp~3#1); 472429#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 472209#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 472203#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 472201#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 472172#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 472155#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 472134#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 472114#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 432782#L1810-2 [2022-12-13 15:12:08,110 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:08,110 INFO L85 PathProgramCache]: Analyzing trace with hash 1008300037, now seen corresponding path program 1 times [2022-12-13 15:12:08,111 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:08,111 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1121327449] [2022-12-13 15:12:08,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:08,111 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:08,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:08,181 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:08,181 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:08,181 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1121327449] [2022-12-13 15:12:08,181 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1121327449] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:08,181 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:08,181 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:08,181 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1321554385] [2022-12-13 15:12:08,181 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:08,182 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:08,182 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:08,182 INFO L85 PathProgramCache]: Analyzing trace with hash 1876372512, now seen corresponding path program 2 times [2022-12-13 15:12:08,182 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:08,182 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [178176012] [2022-12-13 15:12:08,182 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:08,182 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:08,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:08,219 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:08,219 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:08,219 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [178176012] [2022-12-13 15:12:08,219 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [178176012] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:08,220 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:08,220 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:08,220 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1492886339] [2022-12-13 15:12:08,220 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:08,220 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:08,220 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:08,221 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 15:12:08,221 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 15:12:08,221 INFO L87 Difference]: Start difference. First operand 90273 states and 129809 transitions. cyclomatic complexity: 39568 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:09,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:09,116 INFO L93 Difference]: Finished difference Result 219312 states and 313482 transitions. [2022-12-13 15:12:09,116 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 219312 states and 313482 transitions. [2022-12-13 15:12:09,892 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 215696 [2022-12-13 15:12:10,345 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 219312 states to 219312 states and 313482 transitions. [2022-12-13 15:12:10,345 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 219312 [2022-12-13 15:12:10,427 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 219312 [2022-12-13 15:12:10,428 INFO L73 IsDeterministic]: Start isDeterministic. Operand 219312 states and 313482 transitions. [2022-12-13 15:12:10,518 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:12:10,518 INFO L218 hiAutomatonCegarLoop]: Abstraction has 219312 states and 313482 transitions. [2022-12-13 15:12:10,616 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 219312 states and 313482 transitions. [2022-12-13 15:12:11,826 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 219312 to 173344. [2022-12-13 15:12:11,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 173344 states, 173344 states have (on average 1.4332079564334503) internal successors, (248438), 173343 states have internal predecessors, (248438), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:12,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 173344 states to 173344 states and 248438 transitions. [2022-12-13 15:12:12,343 INFO L240 hiAutomatonCegarLoop]: Abstraction has 173344 states and 248438 transitions. [2022-12-13 15:12:12,344 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 15:12:12,344 INFO L428 stractBuchiCegarLoop]: Abstraction has 173344 states and 248438 transitions. [2022-12-13 15:12:12,344 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-12-13 15:12:12,344 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 173344 states and 248438 transitions. [2022-12-13 15:12:12,790 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 172928 [2022-12-13 15:12:12,790 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:12,790 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:12,792 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:12,792 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:12,792 INFO L748 eck$LassoCheckResult]: Stem: 741424#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 741425#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 742271#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 742272#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 742976#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 742977#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 741939#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 741729#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 741142#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 741143#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 742392#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 742508#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 743083#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 743084#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 741860#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 741861#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 742421#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 742338#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 741897#L1201 assume !(0 == ~M_E~0); 741898#L1201-2 assume !(0 == ~T1_E~0); 742855#L1206-1 assume !(0 == ~T2_E~0); 742831#L1211-1 assume !(0 == ~T3_E~0); 742832#L1216-1 assume !(0 == ~T4_E~0); 741711#L1221-1 assume !(0 == ~T5_E~0); 741712#L1226-1 assume !(0 == ~T6_E~0); 741350#L1231-1 assume !(0 == ~T7_E~0); 741351#L1236-1 assume !(0 == ~T8_E~0); 742887#L1241-1 assume !(0 == ~T9_E~0); 741751#L1246-1 assume !(0 == ~T10_E~0); 741752#L1251-1 assume !(0 == ~T11_E~0); 741895#L1256-1 assume !(0 == ~T12_E~0); 741150#L1261-1 assume !(0 == ~E_M~0); 741151#L1266-1 assume !(0 == ~E_1~0); 743057#L1271-1 assume !(0 == ~E_2~0); 742488#L1276-1 assume !(0 == ~E_3~0); 742489#L1281-1 assume !(0 == ~E_4~0); 742433#L1286-1 assume !(0 == ~E_5~0); 741606#L1291-1 assume !(0 == ~E_6~0); 741607#L1296-1 assume !(0 == ~E_7~0); 742205#L1301-1 assume !(0 == ~E_8~0); 742206#L1306-1 assume !(0 == ~E_9~0); 742754#L1311-1 assume !(0 == ~E_10~0); 741559#L1316-1 assume !(0 == ~E_11~0); 741560#L1321-1 assume !(0 == ~E_12~0); 742224#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 742225#L593 assume !(1 == ~m_pc~0); 741448#L593-2 is_master_triggered_~__retres1~0#1 := 0; 741449#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 742108#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 742109#L1492 assume !(0 != activate_threads_~tmp~1#1); 742444#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 742796#L612 assume !(1 == ~t1_pc~0); 742797#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 743075#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 742596#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 741452#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 741453#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 741876#L631 assume !(1 == ~t2_pc~0); 741877#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 741228#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 741229#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 741574#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 742071#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 741521#L650 assume !(1 == ~t3_pc~0); 741522#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 742249#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 742573#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 741188#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 741189#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 742415#L669 assume !(1 == ~t4_pc~0); 742416#L669-2 is_transmit4_triggered_~__retres1~4#1 := 0; 742841#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 741270#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 741271#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 741387#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 741617#L688 assume !(1 == ~t5_pc~0); 741406#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 741407#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 743024#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 742294#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 742295#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 742431#L707 assume !(1 == ~t6_pc~0); 742682#L707-2 is_transmit6_triggered_~__retres1~6#1 := 0; 742039#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 741561#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 741562#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 742372#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 741896#L726 assume 1 == ~t7_pc~0; 741798#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 741488#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 742587#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 742940#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 741256#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 741257#L745 assume !(1 == ~t8_pc~0); 741703#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 741723#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 742861#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 742118#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 742119#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 742702#L764 assume 1 == ~t9_pc~0; 741894#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 741731#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 741635#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 741636#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 741282#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 741283#L783 assume !(1 == ~t10_pc~0); 741337#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 741338#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 741526#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 741855#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 741856#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 742842#L802 assume 1 == ~t11_pc~0; 742820#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 741225#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 741226#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 741713#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 741714#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 741826#L821 assume !(1 == ~t12_pc~0); 742084#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 742196#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 741234#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 741235#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 742900#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 742454#L1339 assume !(1 == ~M_E~0); 742455#L1339-2 assume !(1 == ~T1_E~0); 742943#L1344-1 assume !(1 == ~T2_E~0); 742944#L1349-1 assume !(1 == ~T3_E~0); 742218#L1354-1 assume !(1 == ~T4_E~0); 742219#L1359-1 assume !(1 == ~T5_E~0); 743077#L1364-1 assume !(1 == ~T6_E~0); 743078#L1369-1 assume !(1 == ~T7_E~0); 742641#L1374-1 assume !(1 == ~T8_E~0); 742642#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 788934#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 788933#L1389-1 assume !(1 == ~T11_E~0); 788932#L1394-1 assume !(1 == ~T12_E~0); 788931#L1399-1 assume !(1 == ~E_M~0); 788930#L1404-1 assume !(1 == ~E_1~0); 788929#L1409-1 assume !(1 == ~E_2~0); 788928#L1414-1 assume !(1 == ~E_3~0); 788926#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 788927#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 742233#L1429-1 assume !(1 == ~E_6~0); 742234#L1434-1 assume !(1 == ~E_7~0); 743100#L1439-1 assume !(1 == ~E_8~0); 743101#L1444-1 assume !(1 == ~E_9~0); 742473#L1449-1 assume !(1 == ~E_10~0); 742474#L1454-1 assume !(1 == ~E_11~0); 742937#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 742366#L1464-1 assume { :end_inline_reset_delta_events } true; 742367#L1810-2 [2022-12-13 15:12:12,792 INFO L750 eck$LassoCheckResult]: Loop: 742367#L1810-2 assume !false; 828132#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 828127#L1176 assume !false; 826665#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 824147#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 824134#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 824132#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 824128#L1003 assume !(0 != eval_~tmp~0#1); 824129#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 829405#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 829404#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 829403#L1201-5 assume !(0 == ~T1_E~0); 829402#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 829401#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 829400#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 829399#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 829398#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 829397#L1231-3 assume !(0 == ~T7_E~0); 829396#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 829395#L1241-3 assume !(0 == ~T9_E~0); 829394#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 829393#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 829392#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 829391#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 829390#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 829389#L1271-3 assume !(0 == ~E_2~0); 829388#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 829387#L1281-3 assume !(0 == ~E_4~0); 829386#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 829385#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 829384#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 829383#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 829382#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 829381#L1311-3 assume !(0 == ~E_10~0); 829380#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 829379#L1321-3 assume !(0 == ~E_12~0); 829378#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 829377#L593-42 assume !(1 == ~m_pc~0); 829376#L593-44 is_master_triggered_~__retres1~0#1 := 0; 829375#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 829374#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 829373#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 829372#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 829371#L612-42 assume 1 == ~t1_pc~0; 829369#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 829367#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 829365#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 829363#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 829362#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 829361#L631-42 assume !(1 == ~t2_pc~0); 824627#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 829360#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 829359#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 829358#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 829357#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 829356#L650-42 assume !(1 == ~t3_pc~0); 829354#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 829353#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 829352#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 829351#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 829350#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 829349#L669-42 assume !(1 == ~t4_pc~0); 829348#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 829347#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 829346#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 829345#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 829344#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 829343#L688-42 assume 1 == ~t5_pc~0; 829341#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 829340#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 829339#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 829338#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 829337#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 829336#L707-42 assume !(1 == ~t6_pc~0); 768419#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 829335#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 829334#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 829333#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 829332#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 829331#L726-42 assume 1 == ~t7_pc~0; 829329#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 829328#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 829327#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 829326#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 829325#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 829324#L745-42 assume !(1 == ~t8_pc~0); 829322#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 829321#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 829320#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 829319#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 829318#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 829317#L764-42 assume !(1 == ~t9_pc~0); 829316#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 829314#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 829313#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 829312#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 829311#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 829310#L783-42 assume !(1 == ~t10_pc~0); 829308#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 829307#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 829306#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 829305#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 829304#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 829303#L802-42 assume 1 == ~t11_pc~0; 829301#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 829300#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 829299#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 829298#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 829296#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 829294#L821-42 assume 1 == ~t12_pc~0; 829292#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 829289#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 829287#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 829285#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 829283#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 829280#L1339-3 assume !(1 == ~M_E~0); 829277#L1339-5 assume !(1 == ~T1_E~0); 829269#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 790726#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 829265#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 829263#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 829260#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 829258#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 829256#L1374-3 assume !(1 == ~T8_E~0); 829254#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 804311#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 829251#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 829248#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 829246#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 829244#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 829241#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 829238#L1414-3 assume !(1 == ~E_3~0); 829235#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 790690#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 829230#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 829227#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 829224#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 829220#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 829215#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 829209#L1454-3 assume !(1 == ~E_11~0); 829204#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 810676#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 829122#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 829114#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 829112#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 829109#L1829 assume !(0 == start_simulation_~tmp~3#1); 829108#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 829042#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 829031#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 829021#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 829013#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 829003#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 828995#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 828986#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 742367#L1810-2 [2022-12-13 15:12:12,793 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:12,793 INFO L85 PathProgramCache]: Analyzing trace with hash 2145928902, now seen corresponding path program 1 times [2022-12-13 15:12:12,793 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:12,793 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1638957437] [2022-12-13 15:12:12,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:12,793 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:12,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:12,839 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:12,839 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:12,839 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1638957437] [2022-12-13 15:12:12,839 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1638957437] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:12,839 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:12,839 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:12,839 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [887017803] [2022-12-13 15:12:12,840 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:12,840 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:12,840 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:12,840 INFO L85 PathProgramCache]: Analyzing trace with hash 1710497693, now seen corresponding path program 1 times [2022-12-13 15:12:12,840 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:12,841 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1806638547] [2022-12-13 15:12:12,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:12,841 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:12,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:12,875 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:12,875 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:12,875 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1806638547] [2022-12-13 15:12:12,875 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1806638547] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:12,875 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:12,875 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:12,876 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [753740664] [2022-12-13 15:12:12,876 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:12,876 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:12,876 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:12,876 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 15:12:12,876 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 15:12:12,877 INFO L87 Difference]: Start difference. First operand 173344 states and 248438 transitions. cyclomatic complexity: 75126 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:14,326 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:14,326 INFO L93 Difference]: Finished difference Result 420255 states and 598859 transitions. [2022-12-13 15:12:14,326 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 420255 states and 598859 transitions. [2022-12-13 15:12:15,884 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 413280 [2022-12-13 15:12:16,717 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 420255 states to 420255 states and 598859 transitions. [2022-12-13 15:12:16,717 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 420255 [2022-12-13 15:12:16,838 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 420255 [2022-12-13 15:12:16,838 INFO L73 IsDeterministic]: Start isDeterministic. Operand 420255 states and 598859 transitions. [2022-12-13 15:12:16,946 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:12:16,946 INFO L218 hiAutomatonCegarLoop]: Abstraction has 420255 states and 598859 transitions. [2022-12-13 15:12:17,105 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 420255 states and 598859 transitions. [2022-12-13 15:12:19,638 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 420255 to 332639. [2022-12-13 15:12:19,790 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 332639 states, 332639 states have (on average 1.4287771427884284) internal successors, (475267), 332638 states have internal predecessors, (475267), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:20,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 332639 states to 332639 states and 475267 transitions. [2022-12-13 15:12:20,487 INFO L240 hiAutomatonCegarLoop]: Abstraction has 332639 states and 475267 transitions. [2022-12-13 15:12:20,487 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 15:12:20,488 INFO L428 stractBuchiCegarLoop]: Abstraction has 332639 states and 475267 transitions. [2022-12-13 15:12:20,488 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-12-13 15:12:20,488 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 332639 states and 475267 transitions. [2022-12-13 15:12:21,070 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 332032 [2022-12-13 15:12:21,070 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:21,070 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:21,072 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:21,072 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:21,072 INFO L748 eck$LassoCheckResult]: Stem: 1335034#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1335035#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1335908#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1335909#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1336703#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 1336704#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1335564#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1335347#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1334751#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1334752#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1336042#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1336167#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1336833#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1336834#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1335482#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1335483#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1336071#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1335979#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1335519#L1201 assume !(0 == ~M_E~0); 1335520#L1201-2 assume !(0 == ~T1_E~0); 1336556#L1206-1 assume !(0 == ~T2_E~0); 1336529#L1211-1 assume !(0 == ~T3_E~0); 1336530#L1216-1 assume !(0 == ~T4_E~0); 1335328#L1221-1 assume !(0 == ~T5_E~0); 1335329#L1226-1 assume !(0 == ~T6_E~0); 1334960#L1231-1 assume !(0 == ~T7_E~0); 1334961#L1236-1 assume !(0 == ~T8_E~0); 1336598#L1241-1 assume !(0 == ~T9_E~0); 1335369#L1246-1 assume !(0 == ~T10_E~0); 1335370#L1251-1 assume !(0 == ~T11_E~0); 1335517#L1256-1 assume !(0 == ~T12_E~0); 1334759#L1261-1 assume !(0 == ~E_M~0); 1334760#L1266-1 assume !(0 == ~E_1~0); 1336798#L1271-1 assume !(0 == ~E_2~0); 1336145#L1276-1 assume !(0 == ~E_3~0); 1336146#L1281-1 assume !(0 == ~E_4~0); 1336086#L1286-1 assume !(0 == ~E_5~0); 1335220#L1291-1 assume !(0 == ~E_6~0); 1335221#L1296-1 assume !(0 == ~E_7~0); 1335839#L1301-1 assume !(0 == ~E_8~0); 1335840#L1306-1 assume !(0 == ~E_9~0); 1336445#L1311-1 assume !(0 == ~E_10~0); 1335170#L1316-1 assume !(0 == ~E_11~0); 1335171#L1321-1 assume !(0 == ~E_12~0); 1335859#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1335860#L593 assume !(1 == ~m_pc~0); 1335058#L593-2 is_master_triggered_~__retres1~0#1 := 0; 1335059#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1335737#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1335738#L1492 assume !(0 != activate_threads_~tmp~1#1); 1336099#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1336490#L612 assume !(1 == ~t1_pc~0); 1336491#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1336816#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1336266#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1335062#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 1335063#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1335498#L631 assume !(1 == ~t2_pc~0); 1335499#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1334837#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1334838#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1335185#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 1335700#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1335132#L650 assume !(1 == ~t3_pc~0); 1335133#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1335882#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1336239#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1334796#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 1334797#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1336065#L669 assume !(1 == ~t4_pc~0); 1336066#L669-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1336540#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1334880#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1334881#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 1334997#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1335230#L688 assume !(1 == ~t5_pc~0); 1335016#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1335017#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1336762#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1335929#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 1335930#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1336083#L707 assume !(1 == ~t6_pc~0); 1336361#L707-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1335666#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1335172#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1335173#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 1336020#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1335518#L726 assume !(1 == ~t7_pc~0); 1335097#L726-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1335098#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1336255#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1336652#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 1334866#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1334867#L745 assume !(1 == ~t8_pc~0); 1335319#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1335341#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1336568#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1335745#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1335746#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1336382#L764 assume 1 == ~t9_pc~0; 1335516#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1335349#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1335248#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1335249#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 1334892#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1334893#L783 assume !(1 == ~t10_pc~0); 1334948#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1334949#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1335137#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1335477#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 1335478#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1336541#L802 assume 1 == ~t11_pc~0; 1336516#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1334834#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1334835#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1335330#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 1335331#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1335446#L821 assume !(1 == ~t12_pc~0); 1335713#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1335829#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1334843#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1334844#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 1336615#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1336109#L1339 assume !(1 == ~M_E~0); 1336110#L1339-2 assume !(1 == ~T1_E~0); 1336657#L1344-1 assume !(1 == ~T2_E~0); 1336658#L1349-1 assume !(1 == ~T3_E~0); 1335853#L1354-1 assume !(1 == ~T4_E~0); 1335854#L1359-1 assume !(1 == ~T5_E~0); 1336821#L1364-1 assume !(1 == ~T6_E~0); 1336822#L1369-1 assume !(1 == ~T7_E~0); 1336310#L1374-1 assume !(1 == ~T8_E~0); 1336311#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1421649#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1421648#L1389-1 assume !(1 == ~T11_E~0); 1421647#L1394-1 assume !(1 == ~T12_E~0); 1421646#L1399-1 assume !(1 == ~E_M~0); 1421645#L1404-1 assume !(1 == ~E_1~0); 1421644#L1409-1 assume !(1 == ~E_2~0); 1421643#L1414-1 assume !(1 == ~E_3~0); 1421641#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1421640#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1421639#L1429-1 assume !(1 == ~E_6~0); 1421638#L1434-1 assume !(1 == ~E_7~0); 1421637#L1439-1 assume !(1 == ~E_8~0); 1421636#L1444-1 assume !(1 == ~E_9~0); 1421635#L1449-1 assume !(1 == ~E_10~0); 1421634#L1454-1 assume !(1 == ~E_11~0); 1421633#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 1336016#L1464-1 assume { :end_inline_reset_delta_events } true; 1336017#L1810-2 [2022-12-13 15:12:21,072 INFO L750 eck$LassoCheckResult]: Loop: 1336017#L1810-2 assume !false; 1454291#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1454286#L1176 assume !false; 1454284#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1454030#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1454012#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1454004#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1453995#L1003 assume !(0 != eval_~tmp~0#1); 1453996#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1496637#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1496636#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1496635#L1201-5 assume !(0 == ~T1_E~0); 1496634#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1496633#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1496632#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1496631#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1496630#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1496629#L1231-3 assume !(0 == ~T7_E~0); 1496628#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1496627#L1241-3 assume !(0 == ~T9_E~0); 1496626#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1496625#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1496624#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1496623#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1496622#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1496621#L1271-3 assume !(0 == ~E_2~0); 1496620#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1496619#L1281-3 assume !(0 == ~E_4~0); 1496618#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1496617#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1496614#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1496606#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1496605#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1496602#L1311-3 assume !(0 == ~E_10~0); 1496601#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1496600#L1321-3 assume !(0 == ~E_12~0); 1496598#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1496597#L593-42 assume !(1 == ~m_pc~0); 1496596#L593-44 is_master_triggered_~__retres1~0#1 := 0; 1496594#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1496592#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1496590#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1496588#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1496580#L612-42 assume 1 == ~t1_pc~0; 1496581#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1496582#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1496604#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1496570#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1495447#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1456561#L631-42 assume !(1 == ~t2_pc~0); 1456558#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1456556#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1456554#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1456552#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1456550#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1456549#L650-42 assume 1 == ~t3_pc~0; 1456548#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1456543#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1456541#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1456527#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1456525#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1456523#L669-42 assume !(1 == ~t4_pc~0); 1456521#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1456519#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1456518#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1456385#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 1456381#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1456378#L688-42 assume 1 == ~t5_pc~0; 1456375#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1456373#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1456371#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1456369#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1456367#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1456355#L707-42 assume !(1 == ~t6_pc~0); 1417278#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 1456334#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1456328#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1456322#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1456318#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1456313#L726-42 assume !(1 == ~t7_pc~0); 1414636#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 1456307#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1456305#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1456304#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1456303#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1456302#L745-42 assume !(1 == ~t8_pc~0); 1456300#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 1456299#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1456298#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1456297#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1456296#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1456295#L764-42 assume !(1 == ~t9_pc~0); 1456292#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 1456289#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1456287#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1456285#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1456283#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1456281#L783-42 assume !(1 == ~t10_pc~0); 1456279#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 1456277#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1456275#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1456273#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1456271#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1456269#L802-42 assume !(1 == ~t11_pc~0); 1456268#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 1456265#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1456263#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1456261#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1456259#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1456257#L821-42 assume 1 == ~t12_pc~0; 1456254#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1456251#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1456249#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1456247#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1456245#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1456243#L1339-3 assume !(1 == ~M_E~0); 1456240#L1339-5 assume !(1 == ~T1_E~0); 1456238#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1430912#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1456235#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1456233#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1456231#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1456228#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1456226#L1374-3 assume !(1 == ~T8_E~0); 1456224#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1447404#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1456221#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1456219#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1456216#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1456214#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1456212#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1456210#L1414-3 assume !(1 == ~E_3~0); 1456208#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1431827#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1456204#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1456202#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1456200#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1456198#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1456196#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1456194#L1454-3 assume !(1 == ~E_11~0); 1456192#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1435370#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1456178#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1456170#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1456168#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1456143#L1829 assume !(0 == start_simulation_~tmp~3#1); 1456141#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1456068#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1456061#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1456059#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1455066#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1455063#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1454821#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1454790#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 1336017#L1810-2 [2022-12-13 15:12:21,072 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:21,073 INFO L85 PathProgramCache]: Analyzing trace with hash -1572109753, now seen corresponding path program 1 times [2022-12-13 15:12:21,073 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:21,073 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1149372221] [2022-12-13 15:12:21,073 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:21,073 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:21,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:21,124 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:21,124 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:21,124 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1149372221] [2022-12-13 15:12:21,124 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1149372221] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:21,124 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:21,124 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 15:12:21,124 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1233920951] [2022-12-13 15:12:21,125 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:21,125 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:21,125 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:21,125 INFO L85 PathProgramCache]: Analyzing trace with hash 1861322654, now seen corresponding path program 1 times [2022-12-13 15:12:21,125 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:21,125 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [963176645] [2022-12-13 15:12:21,125 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:21,125 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:21,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:21,304 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:21,304 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:21,304 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [963176645] [2022-12-13 15:12:21,304 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [963176645] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:21,304 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:21,304 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:21,304 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1344898001] [2022-12-13 15:12:21,305 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:21,305 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:21,305 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:21,305 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 15:12:21,306 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 15:12:21,306 INFO L87 Difference]: Start difference. First operand 332639 states and 475267 transitions. cyclomatic complexity: 142660 Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:23,709 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:23,710 INFO L93 Difference]: Finished difference Result 804430 states and 1157994 transitions. [2022-12-13 15:12:23,710 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 804430 states and 1157994 transitions. [2022-12-13 15:12:26,682 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 802816 [2022-12-13 15:12:28,364 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 804430 states to 804430 states and 1157994 transitions. [2022-12-13 15:12:28,364 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 804430 [2022-12-13 15:12:28,553 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 804430 [2022-12-13 15:12:28,553 INFO L73 IsDeterministic]: Start isDeterministic. Operand 804430 states and 1157994 transitions. [2022-12-13 15:12:28,719 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:12:28,719 INFO L218 hiAutomatonCegarLoop]: Abstraction has 804430 states and 1157994 transitions. [2022-12-13 15:12:28,984 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 804430 states and 1157994 transitions. [2022-12-13 15:12:32,906 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 804430 to 341474. [2022-12-13 15:12:33,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 341474 states, 341474 states have (on average 1.4176833375308222) internal successors, (484102), 341473 states have internal predecessors, (484102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:33,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 341474 states to 341474 states and 484102 transitions. [2022-12-13 15:12:33,863 INFO L240 hiAutomatonCegarLoop]: Abstraction has 341474 states and 484102 transitions. [2022-12-13 15:12:33,864 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 15:12:33,864 INFO L428 stractBuchiCegarLoop]: Abstraction has 341474 states and 484102 transitions. [2022-12-13 15:12:33,864 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-12-13 15:12:33,864 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 341474 states and 484102 transitions. [2022-12-13 15:12:34,797 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 340864 [2022-12-13 15:12:34,797 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:34,797 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:34,799 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:34,799 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:34,799 INFO L748 eck$LassoCheckResult]: Stem: 2472112#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 2472113#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 2472972#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2472973#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2473756#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 2473757#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2472633#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2472422#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2471833#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2471834#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2473103#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2473220#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2473878#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2473879#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2472554#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 2472555#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 2473132#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 2473045#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2472592#L1201 assume !(0 == ~M_E~0); 2472593#L1201-2 assume !(0 == ~T1_E~0); 2473599#L1206-1 assume !(0 == ~T2_E~0); 2473576#L1211-1 assume !(0 == ~T3_E~0); 2473577#L1216-1 assume !(0 == ~T4_E~0); 2472404#L1221-1 assume !(0 == ~T5_E~0); 2472405#L1226-1 assume !(0 == ~T6_E~0); 2472038#L1231-1 assume !(0 == ~T7_E~0); 2472039#L1236-1 assume !(0 == ~T8_E~0); 2473652#L1241-1 assume !(0 == ~T9_E~0); 2472444#L1246-1 assume !(0 == ~T10_E~0); 2472445#L1251-1 assume !(0 == ~T11_E~0); 2472590#L1256-1 assume !(0 == ~T12_E~0); 2471841#L1261-1 assume !(0 == ~E_M~0); 2471842#L1266-1 assume !(0 == ~E_1~0); 2473851#L1271-1 assume !(0 == ~E_2~0); 2473202#L1276-1 assume !(0 == ~E_3~0); 2473203#L1281-1 assume !(0 == ~E_4~0); 2473144#L1286-1 assume !(0 == ~E_5~0); 2472299#L1291-1 assume !(0 == ~E_6~0); 2472300#L1296-1 assume !(0 == ~E_7~0); 2472901#L1301-1 assume !(0 == ~E_8~0); 2472902#L1306-1 assume !(0 == ~E_9~0); 2473489#L1311-1 assume !(0 == ~E_10~0); 2472252#L1316-1 assume !(0 == ~E_11~0); 2472253#L1321-1 assume !(0 == ~E_12~0); 2472922#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2472923#L593 assume !(1 == ~m_pc~0); 2472136#L593-2 is_master_triggered_~__retres1~0#1 := 0; 2472137#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2472804#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2472805#L1492 assume !(0 != activate_threads_~tmp~1#1); 2473157#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2473541#L612 assume !(1 == ~t1_pc~0); 2473542#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2473869#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2473323#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2472140#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 2472141#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2472571#L631 assume !(1 == ~t2_pc~0); 2472572#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2471918#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2471919#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2472266#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 2472769#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2472210#L650 assume !(1 == ~t3_pc~0); 2472211#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2472948#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2473298#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2471878#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 2471879#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2473126#L669 assume !(1 == ~t4_pc~0); 2473127#L669-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2473589#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2471960#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2471961#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 2472075#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2472310#L688 assume !(1 == ~t5_pc~0); 2472094#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2472095#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2473818#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2472996#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 2472997#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2473142#L707 assume !(1 == ~t6_pc~0); 2473408#L707-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2472736#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2472254#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2472255#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 2473080#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2472591#L726 assume !(1 == ~t7_pc~0); 2472176#L726-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2472177#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2473313#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2473701#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 2471946#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2471947#L745 assume !(1 == ~t8_pc~0); 2472396#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2473521#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2473616#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2472812#L1556 assume !(0 != activate_threads_~tmp___7~0#1); 2472813#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2473428#L764 assume 1 == ~t9_pc~0; 2472589#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2472424#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2472328#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 2472329#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 2471972#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2471973#L783 assume !(1 == ~t10_pc~0); 2472026#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 2472027#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2472215#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 2472549#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 2472550#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2473590#L802 assume 1 == ~t11_pc~0; 2473565#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 2471915#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2471916#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 2472406#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 2472407#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 2472518#L821 assume !(1 == ~t12_pc~0); 2472782#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 2472892#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 2471924#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 2471925#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 2473664#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2473167#L1339 assume !(1 == ~M_E~0); 2473168#L1339-2 assume !(1 == ~T1_E~0); 2473706#L1344-1 assume !(1 == ~T2_E~0); 2473707#L1349-1 assume !(1 == ~T3_E~0); 2505823#L1354-1 assume !(1 == ~T4_E~0); 2505822#L1359-1 assume !(1 == ~T5_E~0); 2505821#L1364-1 assume !(1 == ~T6_E~0); 2505818#L1369-1 assume !(1 == ~T7_E~0); 2505816#L1374-1 assume !(1 == ~T8_E~0); 2505813#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2505814#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2511931#L1389-1 assume !(1 == ~T11_E~0); 2511929#L1394-1 assume !(1 == ~T12_E~0); 2511927#L1399-1 assume !(1 == ~E_M~0); 2511925#L1404-1 assume !(1 == ~E_1~0); 2511922#L1409-1 assume !(1 == ~E_2~0); 2511920#L1414-1 assume !(1 == ~E_3~0); 2511917#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2511918#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 2528514#L1429-1 assume !(1 == ~E_6~0); 2528510#L1434-1 assume !(1 == ~E_7~0); 2528496#L1439-1 assume !(1 == ~E_8~0); 2528494#L1444-1 assume !(1 == ~E_9~0); 2528492#L1449-1 assume !(1 == ~E_10~0); 2528479#L1454-1 assume !(1 == ~E_11~0); 2528469#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 2473076#L1464-1 assume { :end_inline_reset_delta_events } true; 2473077#L1810-2 [2022-12-13 15:12:34,800 INFO L750 eck$LassoCheckResult]: Loop: 2473077#L1810-2 assume !false; 2544187#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2544182#L1176 assume !false; 2544180#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 2544163#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 2544149#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 2544145#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2544136#L1003 assume !(0 != eval_~tmp~0#1); 2544137#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2552162#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2552159#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2552156#L1201-5 assume !(0 == ~T1_E~0); 2552153#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2552150#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2552147#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2552144#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2552141#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2552138#L1231-3 assume !(0 == ~T7_E~0); 2552135#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2552132#L1241-3 assume !(0 == ~T9_E~0); 2552108#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 2552104#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 2552100#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 2552095#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2552091#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2552087#L1271-3 assume !(0 == ~E_2~0); 2552083#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2552079#L1281-3 assume !(0 == ~E_4~0); 2552075#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2552070#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2552066#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2552062#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2552032#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2552030#L1311-3 assume !(0 == ~E_10~0); 2552012#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 2551994#L1321-3 assume !(0 == ~E_12~0); 2551948#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2551946#L593-42 assume !(1 == ~m_pc~0); 2551925#L593-44 is_master_triggered_~__retres1~0#1 := 0; 2551921#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2551920#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2551919#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2551918#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2551917#L612-42 assume 1 == ~t1_pc~0; 2551916#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2551914#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2551912#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2551909#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2551908#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2551907#L631-42 assume !(1 == ~t2_pc~0); 2551515#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 2551906#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2551905#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2551904#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2551903#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2551902#L650-42 assume !(1 == ~t3_pc~0); 2551900#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 2551899#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2551898#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2551897#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2551896#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2551895#L669-42 assume !(1 == ~t4_pc~0); 2551894#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 2551893#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2551892#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2551891#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 2551890#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2551889#L688-42 assume !(1 == ~t5_pc~0); 2551888#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 2547694#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2547695#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2547681#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2547682#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2547667#L707-42 assume !(1 == ~t6_pc~0); 2543321#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 2547651#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2547652#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2547633#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2547634#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2546292#L726-42 assume !(1 == ~t7_pc~0); 2546291#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 2546053#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2546052#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2546051#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2546050#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2546049#L745-42 assume !(1 == ~t8_pc~0); 2546048#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 2546046#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2546044#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2546042#L1556-42 assume !(0 != activate_threads_~tmp___7~0#1); 2546040#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2545395#L764-42 assume 1 == ~t9_pc~0; 2545392#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2545391#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2545390#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 2545389#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2545388#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2545276#L783-42 assume !(1 == ~t10_pc~0); 2545220#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 2545217#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2545213#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 2545209#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2545206#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2545203#L802-42 assume !(1 == ~t11_pc~0); 2545200#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 2545196#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2545147#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 2545142#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2545138#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 2545133#L821-42 assume !(1 == ~t12_pc~0); 2545128#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 2545124#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 2545119#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 2545114#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 2545110#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2545105#L1339-3 assume !(1 == ~M_E~0); 2545101#L1339-5 assume !(1 == ~T1_E~0); 2545097#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2509991#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2545072#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2545067#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2545060#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2545055#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2545048#L1374-3 assume !(1 == ~T8_E~0); 2544996#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2542183#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2544940#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 2544882#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 2544877#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2544826#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2544819#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2544813#L1414-3 assume !(1 == ~E_3~0); 2544806#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2512447#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2544749#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2544742#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2544736#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2544730#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2544725#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2544721#L1454-3 assume !(1 == ~E_11~0); 2544719#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 2528937#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 2544497#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 2544481#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 2544473#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 2544465#L1829 assume !(0 == start_simulation_~tmp~3#1); 2544450#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 2544264#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 2544249#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 2544242#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 2544227#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2544217#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2544208#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 2544198#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 2473077#L1810-2 [2022-12-13 15:12:34,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:34,800 INFO L85 PathProgramCache]: Analyzing trace with hash -1128209079, now seen corresponding path program 1 times [2022-12-13 15:12:34,800 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:34,800 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [310591301] [2022-12-13 15:12:34,800 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:34,801 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:34,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:34,846 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:34,846 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:34,846 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [310591301] [2022-12-13 15:12:34,846 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [310591301] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:34,846 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:34,847 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:34,847 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [895115162] [2022-12-13 15:12:34,847 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:34,847 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:34,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:34,848 INFO L85 PathProgramCache]: Analyzing trace with hash -576103070, now seen corresponding path program 1 times [2022-12-13 15:12:34,848 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:34,848 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1458813810] [2022-12-13 15:12:34,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:34,848 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:34,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:34,883 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:34,884 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:34,884 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1458813810] [2022-12-13 15:12:34,884 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1458813810] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:34,884 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:34,884 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:34,884 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [572227369] [2022-12-13 15:12:34,884 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:34,885 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:34,885 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:34,885 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 15:12:34,885 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 15:12:34,885 INFO L87 Difference]: Start difference. First operand 341474 states and 484102 transitions. cyclomatic complexity: 142660 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:37,356 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:37,356 INFO L93 Difference]: Finished difference Result 823649 states and 1161395 transitions. [2022-12-13 15:12:37,356 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 823649 states and 1161395 transitions. [2022-12-13 15:12:40,580 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 809600 [2022-12-13 15:12:42,245 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 823649 states to 823649 states and 1161395 transitions. [2022-12-13 15:12:42,245 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 823649 [2022-12-13 15:12:42,505 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 823649 [2022-12-13 15:12:42,505 INFO L73 IsDeterministic]: Start isDeterministic. Operand 823649 states and 1161395 transitions. [2022-12-13 15:12:42,732 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:12:42,732 INFO L218 hiAutomatonCegarLoop]: Abstraction has 823649 states and 1161395 transitions. [2022-12-13 15:12:43,177 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 823649 states and 1161395 transitions. [2022-12-13 15:12:48,084 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 823649 to 654561. [2022-12-13 15:12:48,357 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 654561 states, 654561 states have (on average 1.4136910081718892) internal successors, (925347), 654560 states have internal predecessors, (925347), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:49,715 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 654561 states to 654561 states and 925347 transitions. [2022-12-13 15:12:49,715 INFO L240 hiAutomatonCegarLoop]: Abstraction has 654561 states and 925347 transitions. [2022-12-13 15:12:49,716 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 15:12:49,716 INFO L428 stractBuchiCegarLoop]: Abstraction has 654561 states and 925347 transitions. [2022-12-13 15:12:49,716 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-12-13 15:12:49,716 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 654561 states and 925347 transitions. [2022-12-13 15:12:51,202 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 653568 [2022-12-13 15:12:51,202 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:51,202 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:51,205 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:51,205 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:51,205 INFO L748 eck$LassoCheckResult]: Stem: 3637246#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 3637247#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 3638107#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3638108#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3638891#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 3638892#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3637761#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3637554#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3636966#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3636967#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3638241#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3638361#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3639013#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3639014#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3637680#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3637681#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 3638271#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 3638179#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3637717#L1201 assume !(0 == ~M_E~0); 3637718#L1201-2 assume !(0 == ~T1_E~0); 3638745#L1206-1 assume !(0 == ~T2_E~0); 3638720#L1211-1 assume !(0 == ~T3_E~0); 3638721#L1216-1 assume !(0 == ~T4_E~0); 3637535#L1221-1 assume !(0 == ~T5_E~0); 3637536#L1226-1 assume !(0 == ~T6_E~0); 3637173#L1231-1 assume !(0 == ~T7_E~0); 3637174#L1236-1 assume !(0 == ~T8_E~0); 3638785#L1241-1 assume !(0 == ~T9_E~0); 3637572#L1246-1 assume !(0 == ~T10_E~0); 3637573#L1251-1 assume !(0 == ~T11_E~0); 3637715#L1256-1 assume !(0 == ~T12_E~0); 3636974#L1261-1 assume !(0 == ~E_M~0); 3636975#L1266-1 assume !(0 == ~E_1~0); 3638990#L1271-1 assume !(0 == ~E_2~0); 3638343#L1276-1 assume !(0 == ~E_3~0); 3638344#L1281-1 assume !(0 == ~E_4~0); 3638285#L1286-1 assume !(0 == ~E_5~0); 3637430#L1291-1 assume !(0 == ~E_6~0); 3637431#L1296-1 assume !(0 == ~E_7~0); 3638039#L1301-1 assume !(0 == ~E_8~0); 3638040#L1306-1 assume !(0 == ~E_9~0); 3638627#L1311-1 assume !(0 == ~E_10~0); 3637384#L1316-1 assume !(0 == ~E_11~0); 3637385#L1321-1 assume !(0 == ~E_12~0); 3638060#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3638061#L593 assume !(1 == ~m_pc~0); 3637270#L593-2 is_master_triggered_~__retres1~0#1 := 0; 3637271#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3637944#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3637945#L1492 assume !(0 != activate_threads_~tmp~1#1); 3638296#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3638681#L612 assume !(1 == ~t1_pc~0); 3638682#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3639006#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3638460#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3637274#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 3637275#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3637697#L631 assume !(1 == ~t2_pc~0); 3637698#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3637051#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3637052#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3637398#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 3637905#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3637342#L650 assume !(1 == ~t3_pc~0); 3637343#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3638085#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3638437#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3637011#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 3637012#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3638265#L669 assume !(1 == ~t4_pc~0); 3638266#L669-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3638729#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3637089#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3637090#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 3637209#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3637441#L688 assume !(1 == ~t5_pc~0); 3637228#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3637229#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3638950#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3638129#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 3638130#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3638278#L707 assume !(1 == ~t6_pc~0); 3638548#L707-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3637872#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3637386#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3637387#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 3638211#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3637716#L726 assume !(1 == ~t7_pc~0); 3637310#L726-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3637311#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3638449#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3638846#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 3637079#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3637080#L745 assume !(1 == ~t8_pc~0); 3637528#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3638659#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3638910#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3637952#L1556 assume !(0 != activate_threads_~tmp___7~0#1); 3637953#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3638570#L764 assume !(1 == ~t9_pc~0); 3637555#L764-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3637556#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3637459#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3637460#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 3637105#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3637106#L783 assume !(1 == ~t10_pc~0); 3637161#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3637162#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3637349#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3637671#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 3637672#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3638731#L802 assume 1 == ~t11_pc~0; 3638709#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3637048#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3637049#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3637537#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 3637538#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 3637648#L821 assume !(1 == ~t12_pc~0); 3637918#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 3638029#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3637055#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3637056#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 3638797#L1588-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3638306#L1339 assume !(1 == ~M_E~0); 3638307#L1339-2 assume !(1 == ~T1_E~0); 3638850#L1344-1 assume !(1 == ~T2_E~0); 3638851#L1349-1 assume !(1 == ~T3_E~0); 3931599#L1354-1 assume !(1 == ~T4_E~0); 3931597#L1359-1 assume !(1 == ~T5_E~0); 3931595#L1364-1 assume !(1 == ~T6_E~0); 3931593#L1369-1 assume !(1 == ~T7_E~0); 3931590#L1374-1 assume !(1 == ~T8_E~0); 3931588#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3931586#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3931584#L1389-1 assume !(1 == ~T11_E~0); 3931582#L1394-1 assume !(1 == ~T12_E~0); 3931580#L1399-1 assume !(1 == ~E_M~0); 3931577#L1404-1 assume !(1 == ~E_1~0); 3931575#L1409-1 assume !(1 == ~E_2~0); 3931573#L1414-1 assume !(1 == ~E_3~0); 3931570#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3931571#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 4101267#L1429-1 assume !(1 == ~E_6~0); 4101266#L1434-1 assume !(1 == ~E_7~0); 4101265#L1439-1 assume !(1 == ~E_8~0); 4101264#L1444-1 assume !(1 == ~E_9~0); 4101263#L1449-1 assume !(1 == ~E_10~0); 4101262#L1454-1 assume !(1 == ~E_11~0); 4101261#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 3638845#L1464-1 assume { :end_inline_reset_delta_events } true; 4249776#L1810-2 [2022-12-13 15:12:51,206 INFO L750 eck$LassoCheckResult]: Loop: 4249776#L1810-2 assume !false; 4249631#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4249626#L1176 assume !false; 4249623#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4249616#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4249602#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4249600#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4249597#L1003 assume !(0 != eval_~tmp~0#1); 4249598#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4284795#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4284792#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4284789#L1201-5 assume !(0 == ~T1_E~0); 4284781#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4284774#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4284767#L1216-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4284758#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4284749#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4284739#L1231-3 assume !(0 == ~T7_E~0); 4284730#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4284706#L1241-3 assume !(0 == ~T9_E~0); 4284698#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4284659#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4284652#L1256-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 3637357#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3637358#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3637406#L1271-3 assume !(0 == ~E_2~0); 3637407#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3637791#L1281-3 assume !(0 == ~E_4~0); 3637792#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3638384#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3638385#L1296-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3639007#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3638929#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3637910#L1311-3 assume !(0 == ~E_10~0); 3637284#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3637285#L1321-3 assume !(0 == ~E_12~0); 3637359#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3638028#L593-42 assume !(1 == ~m_pc~0); 3638212#L593-44 is_master_triggered_~__retres1~0#1 := 0; 3638213#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3637682#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3637683#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3637180#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3637181#L612-42 assume 1 == ~t1_pc~0; 3638159#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3639086#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4285651#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4285650#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3637273#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3639101#L631-42 assume !(1 == ~t2_pc~0); 4251724#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 4251203#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4251202#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4251201#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4251200#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4251199#L650-42 assume !(1 == ~t3_pc~0); 4251197#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 4251196#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4251194#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4251193#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4251192#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4251191#L669-42 assume !(1 == ~t4_pc~0); 4251190#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 4251188#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4251186#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4251185#L1524-42 assume !(0 != activate_threads_~tmp___3~0#1); 4251184#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4251183#L688-42 assume 1 == ~t5_pc~0; 4251180#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4251178#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4251176#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4251174#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4251172#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4251170#L707-42 assume !(1 == ~t6_pc~0); 4244782#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 4251166#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4251164#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4251162#L1540-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4251159#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4251157#L726-42 assume !(1 == ~t7_pc~0); 4152060#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 4251155#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4251153#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4251151#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4251149#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4251147#L745-42 assume !(1 == ~t8_pc~0); 4251143#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 4251140#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4251138#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4251136#L1556-42 assume !(0 != activate_threads_~tmp___7~0#1); 4251133#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4251131#L764-42 assume !(1 == ~t9_pc~0); 3963933#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 4251128#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4251126#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4251124#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4251122#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4251120#L783-42 assume !(1 == ~t10_pc~0); 4251117#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 4251114#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4251112#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4251110#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4251108#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4251106#L802-42 assume !(1 == ~t11_pc~0); 4251104#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 4251102#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4251100#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4251098#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4251096#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4251056#L821-42 assume !(1 == ~t12_pc~0); 4251047#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 4251038#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4251029#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4251021#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4251014#L1588-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4251005#L1339-3 assume !(1 == ~M_E~0); 4250998#L1339-5 assume !(1 == ~T1_E~0); 4250989#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3932271#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4250968#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4250957#L1359-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4250669#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4250662#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4250656#L1374-3 assume !(1 == ~T8_E~0); 4250578#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4250543#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4250533#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4250526#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4250517#L1399-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4250507#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4250438#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4250435#L1414-3 assume !(1 == ~E_3~0); 4250433#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4242271#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4250430#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4250428#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4250422#L1439-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4250418#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4250244#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4250140#L1454-3 assume !(1 == ~E_11~0); 4250138#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4101701#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4250032#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4250018#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4250010#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4250001#L1829 assume !(0 == start_simulation_~tmp~3#1); 4249992#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4249967#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4249954#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4249947#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 4249939#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4249834#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4249801#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 4249783#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 4249776#L1810-2 [2022-12-13 15:12:51,206 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:51,206 INFO L85 PathProgramCache]: Analyzing trace with hash 1065917002, now seen corresponding path program 1 times [2022-12-13 15:12:51,206 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:51,206 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [767826110] [2022-12-13 15:12:51,206 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:51,206 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:51,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:51,253 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:51,253 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:51,253 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [767826110] [2022-12-13 15:12:51,253 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [767826110] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:51,254 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:51,254 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:51,254 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [92349310] [2022-12-13 15:12:51,254 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:51,254 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:51,254 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:51,255 INFO L85 PathProgramCache]: Analyzing trace with hash 1486065762, now seen corresponding path program 1 times [2022-12-13 15:12:51,255 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:51,255 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [501397272] [2022-12-13 15:12:51,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:51,255 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:51,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:51,282 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:51,283 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:51,283 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [501397272] [2022-12-13 15:12:51,283 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [501397272] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:51,283 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:51,283 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:51,283 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [586618603] [2022-12-13 15:12:51,283 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:51,284 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:51,284 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:51,284 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 15:12:51,284 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 15:12:51,284 INFO L87 Difference]: Start difference. First operand 654561 states and 925347 transitions. cyclomatic complexity: 270818 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:56,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:56,557 INFO L93 Difference]: Finished difference Result 1602848 states and 2251584 transitions. [2022-12-13 15:12:56,557 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1602848 states and 2251584 transitions. [2022-12-13 15:13:02,161 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 1575104 [2022-12-13 15:13:05,495 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1602848 states to 1602848 states and 2251584 transitions. [2022-12-13 15:13:05,495 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1602848 [2022-12-13 15:13:06,043 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1602848 [2022-12-13 15:13:06,043 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1602848 states and 2251584 transitions. [2022-12-13 15:13:06,575 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:13:06,575 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1602848 states and 2251584 transitions. [2022-12-13 15:13:07,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1602848 states and 2251584 transitions. [2022-12-13 15:13:17,089 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1602848 to 1277408. [2022-12-13 15:13:17,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1277408 states, 1277408 states have (on average 1.4084270648062327) internal successors, (1799136), 1277407 states have internal predecessors, (1799136), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)