./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.01.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9ad4de3-194f-4f36-9fae-cbc11bfd65dd/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9ad4de3-194f-4f36-9fae-cbc11bfd65dd/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9ad4de3-194f-4f36-9fae-cbc11bfd65dd/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9ad4de3-194f-4f36-9fae-cbc11bfd65dd/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.01.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9ad4de3-194f-4f36-9fae-cbc11bfd65dd/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9ad4de3-194f-4f36-9fae-cbc11bfd65dd/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ea17b00cb6ed3e05e0ac7861fb220a62ceca6ba97bc4fe703ce3eb0d0ec5cbfe --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 20:45:30,152 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 20:45:30,154 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 20:45:30,172 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 20:45:30,172 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 20:45:30,173 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 20:45:30,175 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 20:45:30,176 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 20:45:30,178 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 20:45:30,178 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 20:45:30,179 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 20:45:30,180 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 20:45:30,181 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 20:45:30,182 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 20:45:30,183 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 20:45:30,184 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 20:45:30,185 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 20:45:30,186 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 20:45:30,188 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 20:45:30,189 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 20:45:30,191 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 20:45:30,192 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 20:45:30,193 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 20:45:30,194 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 20:45:30,197 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 20:45:30,198 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 20:45:30,198 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 20:45:30,199 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 20:45:30,199 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 20:45:30,200 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 20:45:30,201 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 20:45:30,201 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 20:45:30,202 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 20:45:30,203 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 20:45:30,203 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 20:45:30,204 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 20:45:30,204 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 20:45:30,204 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 20:45:30,204 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 20:45:30,205 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 20:45:30,205 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 20:45:30,206 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9ad4de3-194f-4f36-9fae-cbc11bfd65dd/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 20:45:30,228 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 20:45:30,228 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 20:45:30,235 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 20:45:30,235 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 20:45:30,236 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 20:45:30,237 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 20:45:30,237 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 20:45:30,237 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 20:45:30,237 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 20:45:30,237 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 20:45:30,237 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 20:45:30,238 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 20:45:30,238 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 20:45:30,238 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 20:45:30,238 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 20:45:30,238 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 20:45:30,238 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 20:45:30,238 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 20:45:30,239 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 20:45:30,239 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 20:45:30,239 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 20:45:30,239 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 20:45:30,239 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 20:45:30,239 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 20:45:30,239 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 20:45:30,240 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 20:45:30,240 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 20:45:30,240 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 20:45:30,240 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 20:45:30,240 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 20:45:30,241 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 20:45:30,241 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 20:45:30,242 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9ad4de3-194f-4f36-9fae-cbc11bfd65dd/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9ad4de3-194f-4f36-9fae-cbc11bfd65dd/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ea17b00cb6ed3e05e0ac7861fb220a62ceca6ba97bc4fe703ce3eb0d0ec5cbfe [2022-12-13 20:45:30,428 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 20:45:30,445 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 20:45:30,447 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 20:45:30,448 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 20:45:30,449 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 20:45:30,449 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9ad4de3-194f-4f36-9fae-cbc11bfd65dd/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/transmitter.01.cil.c [2022-12-13 20:45:33,043 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 20:45:33,198 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 20:45:33,198 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9ad4de3-194f-4f36-9fae-cbc11bfd65dd/sv-benchmarks/c/systemc/transmitter.01.cil.c [2022-12-13 20:45:33,204 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9ad4de3-194f-4f36-9fae-cbc11bfd65dd/bin/uautomizer-uyxdKDjOR8/data/ddb607d65/61fae886e8ca4ca1a72dc1e1a685fd93/FLAG978a4b93d [2022-12-13 20:45:33,615 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9ad4de3-194f-4f36-9fae-cbc11bfd65dd/bin/uautomizer-uyxdKDjOR8/data/ddb607d65/61fae886e8ca4ca1a72dc1e1a685fd93 [2022-12-13 20:45:33,617 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 20:45:33,619 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 20:45:33,620 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 20:45:33,620 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 20:45:33,623 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 20:45:33,623 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 08:45:33" (1/1) ... [2022-12-13 20:45:33,624 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5b985196 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:45:33, skipping insertion in model container [2022-12-13 20:45:33,624 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 08:45:33" (1/1) ... [2022-12-13 20:45:33,629 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 20:45:33,645 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 20:45:33,736 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9ad4de3-194f-4f36-9fae-cbc11bfd65dd/sv-benchmarks/c/systemc/transmitter.01.cil.c[706,719] [2022-12-13 20:45:33,763 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 20:45:33,772 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 20:45:33,780 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9ad4de3-194f-4f36-9fae-cbc11bfd65dd/sv-benchmarks/c/systemc/transmitter.01.cil.c[706,719] [2022-12-13 20:45:33,792 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 20:45:33,804 INFO L208 MainTranslator]: Completed translation [2022-12-13 20:45:33,804 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:45:33 WrapperNode [2022-12-13 20:45:33,804 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 20:45:33,805 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 20:45:33,805 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 20:45:33,805 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 20:45:33,810 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:45:33" (1/1) ... [2022-12-13 20:45:33,816 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:45:33" (1/1) ... [2022-12-13 20:45:33,833 INFO L138 Inliner]: procedures = 30, calls = 33, calls flagged for inlining = 28, calls inlined = 34, statements flattened = 357 [2022-12-13 20:45:33,834 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 20:45:33,834 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 20:45:33,834 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 20:45:33,834 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 20:45:33,840 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:45:33" (1/1) ... [2022-12-13 20:45:33,840 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:45:33" (1/1) ... [2022-12-13 20:45:33,842 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:45:33" (1/1) ... [2022-12-13 20:45:33,842 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:45:33" (1/1) ... [2022-12-13 20:45:33,846 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:45:33" (1/1) ... [2022-12-13 20:45:33,850 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:45:33" (1/1) ... [2022-12-13 20:45:33,851 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:45:33" (1/1) ... [2022-12-13 20:45:33,852 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:45:33" (1/1) ... [2022-12-13 20:45:33,854 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 20:45:33,855 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 20:45:33,855 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 20:45:33,855 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 20:45:33,856 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:45:33" (1/1) ... [2022-12-13 20:45:33,861 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 20:45:33,870 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9ad4de3-194f-4f36-9fae-cbc11bfd65dd/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 20:45:33,880 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9ad4de3-194f-4f36-9fae-cbc11bfd65dd/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 20:45:33,882 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9ad4de3-194f-4f36-9fae-cbc11bfd65dd/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 20:45:33,916 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 20:45:33,916 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 20:45:33,916 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 20:45:33,916 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 20:45:33,975 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 20:45:33,976 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 20:45:34,241 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 20:45:34,246 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 20:45:34,246 INFO L300 CfgBuilder]: Removed 5 assume(true) statements. [2022-12-13 20:45:34,248 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 08:45:34 BoogieIcfgContainer [2022-12-13 20:45:34,248 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 20:45:34,249 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 20:45:34,249 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 20:45:34,252 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 20:45:34,253 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 20:45:34,253 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 08:45:33" (1/3) ... [2022-12-13 20:45:34,253 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7a803e42 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 08:45:34, skipping insertion in model container [2022-12-13 20:45:34,253 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 20:45:34,254 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 08:45:33" (2/3) ... [2022-12-13 20:45:34,254 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7a803e42 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 08:45:34, skipping insertion in model container [2022-12-13 20:45:34,254 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 20:45:34,254 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 08:45:34" (3/3) ... [2022-12-13 20:45:34,255 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.01.cil.c [2022-12-13 20:45:34,296 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 20:45:34,297 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 20:45:34,297 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 20:45:34,297 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 20:45:34,297 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 20:45:34,297 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 20:45:34,297 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 20:45:34,297 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 20:45:34,300 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 133 states, 132 states have (on average 1.5227272727272727) internal successors, (201), 132 states have internal predecessors, (201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:45:34,317 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 100 [2022-12-13 20:45:34,317 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:45:34,317 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:45:34,323 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:45:34,323 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:45:34,323 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 20:45:34,323 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 133 states, 132 states have (on average 1.5227272727272727) internal successors, (201), 132 states have internal predecessors, (201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:45:34,328 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 100 [2022-12-13 20:45:34,328 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:45:34,328 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:45:34,329 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:45:34,329 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:45:34,335 INFO L748 eck$LassoCheckResult]: Stem: 30#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 48#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 131#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12#L161true assume !(1 == ~m_i~0);~m_st~0 := 2; 5#L161-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 78#L166-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 87#L250true assume !(0 == ~M_E~0); 106#L250-2true assume !(0 == ~T1_E~0); 38#L255-1true assume !(0 == ~E_1~0); 79#L260-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54#L115true assume !(1 == ~m_pc~0); 58#L115-2true is_master_triggered_~__retres1~0#1 := 0; 68#L126true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8#is_master_triggered_returnLabel#1true activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 65#L300true assume !(0 != activate_threads_~tmp~1#1); 105#L300-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 118#L134true assume 1 == ~t1_pc~0; 107#L135true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 56#L145true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10#L308true assume !(0 != activate_threads_~tmp___0~0#1); 61#L308-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59#L273true assume !(1 == ~M_E~0); 110#L273-2true assume !(1 == ~T1_E~0); 99#L278-1true assume !(1 == ~E_1~0); 71#L283-1true assume { :end_inline_reset_delta_events } true; 57#L404-2true [2022-12-13 20:45:34,336 INFO L750 eck$LassoCheckResult]: Loop: 57#L404-2true assume !false; 80#L405true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44#L225true assume !true; 83#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 114#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 117#L250-3true assume 0 == ~M_E~0;~M_E~0 := 1; 95#L250-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 101#L255-3true assume 0 == ~E_1~0;~E_1~0 := 1; 6#L260-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49#L115-6true assume 1 == ~m_pc~0; 113#L116-2true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 132#L126-2true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53#is_master_triggered_returnLabel#3true activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 73#L300-6true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 115#L300-8true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 130#L134-6true assume !(1 == ~t1_pc~0); 31#L134-8true is_transmit1_triggered_~__retres1~1#1 := 0; 52#L145-2true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 122#is_transmit1_triggered_returnLabel#3true activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 50#L308-6true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7#L308-8true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 127#L273-3true assume 1 == ~M_E~0;~M_E~0 := 2; 45#L273-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 32#L278-3true assume 1 == ~E_1~0;~E_1~0 := 2; 93#L283-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 75#L179-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 111#L191-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 97#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 18#L423true assume !(0 == start_simulation_~tmp~3#1); 17#L423-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 21#L179-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 72#L191-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 36#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 15#L378true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16#L385true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 133#stop_simulation_returnLabel#1true start_simulation_#t~ret11#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 43#L436true assume !(0 != start_simulation_~tmp___0~1#1); 57#L404-2true [2022-12-13 20:45:34,340 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:45:34,340 INFO L85 PathProgramCache]: Analyzing trace with hash 920294251, now seen corresponding path program 1 times [2022-12-13 20:45:34,347 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:45:34,347 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2073099925] [2022-12-13 20:45:34,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:45:34,348 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:45:34,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:45:34,484 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:45:34,485 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:45:34,485 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2073099925] [2022-12-13 20:45:34,486 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2073099925] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:45:34,486 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:45:34,486 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:45:34,488 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1665319363] [2022-12-13 20:45:34,488 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:45:34,492 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:45:34,493 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:45:34,493 INFO L85 PathProgramCache]: Analyzing trace with hash 478113713, now seen corresponding path program 1 times [2022-12-13 20:45:34,494 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:45:34,494 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [285519916] [2022-12-13 20:45:34,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:45:34,494 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:45:34,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:45:34,520 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:45:34,521 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:45:34,521 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [285519916] [2022-12-13 20:45:34,521 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [285519916] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:45:34,521 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:45:34,521 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 20:45:34,521 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [467619881] [2022-12-13 20:45:34,522 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:45:34,523 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:45:34,523 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:45:34,554 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:45:34,554 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:45:34,557 INFO L87 Difference]: Start difference. First operand has 133 states, 132 states have (on average 1.5227272727272727) internal successors, (201), 132 states have internal predecessors, (201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.0) internal successors, (27), 3 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:45:34,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:45:34,581 INFO L93 Difference]: Finished difference Result 132 states and 188 transitions. [2022-12-13 20:45:34,582 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 132 states and 188 transitions. [2022-12-13 20:45:34,585 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2022-12-13 20:45:34,590 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 132 states to 126 states and 182 transitions. [2022-12-13 20:45:34,591 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 126 [2022-12-13 20:45:34,592 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 126 [2022-12-13 20:45:34,592 INFO L73 IsDeterministic]: Start isDeterministic. Operand 126 states and 182 transitions. [2022-12-13 20:45:34,593 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:45:34,593 INFO L218 hiAutomatonCegarLoop]: Abstraction has 126 states and 182 transitions. [2022-12-13 20:45:34,607 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states and 182 transitions. [2022-12-13 20:45:34,618 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 126. [2022-12-13 20:45:34,619 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 126 states, 126 states have (on average 1.4444444444444444) internal successors, (182), 125 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:45:34,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126 states to 126 states and 182 transitions. [2022-12-13 20:45:34,621 INFO L240 hiAutomatonCegarLoop]: Abstraction has 126 states and 182 transitions. [2022-12-13 20:45:34,622 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:45:34,625 INFO L428 stractBuchiCegarLoop]: Abstraction has 126 states and 182 transitions. [2022-12-13 20:45:34,625 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 20:45:34,625 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 126 states and 182 transitions. [2022-12-13 20:45:34,627 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2022-12-13 20:45:34,627 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:45:34,627 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:45:34,628 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:45:34,628 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:45:34,629 INFO L748 eck$LassoCheckResult]: Stem: 322#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 323#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 347#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 341#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 291#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 278#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 279#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 374#L250 assume !(0 == ~M_E~0); 383#L250-2 assume !(0 == ~T1_E~0); 335#L255-1 assume !(0 == ~E_1~0); 336#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 354#L115 assume !(1 == ~m_pc~0); 318#L115-2 is_master_triggered_~__retres1~0#1 := 0; 319#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 284#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 285#L300 assume !(0 != activate_threads_~tmp~1#1); 363#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 393#L134 assume 1 == ~t1_pc~0; 394#L135 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 356#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 334#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 287#L308 assume !(0 != activate_threads_~tmp___0~0#1); 288#L308-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 358#L273 assume !(1 == ~M_E~0); 359#L273-2 assume !(1 == ~T1_E~0); 391#L278-1 assume !(1 == ~E_1~0); 367#L283-1 assume { :end_inline_reset_delta_events } true; 340#L404-2 [2022-12-13 20:45:34,629 INFO L750 eck$LassoCheckResult]: Loop: 340#L404-2 assume !false; 357#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 342#L225 assume !false; 343#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 380#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 321#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 292#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 293#L206 assume !(0 != eval_~tmp~0#1); 331#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 377#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 398#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 388#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 389#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 280#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 281#L115-6 assume 1 == ~m_pc~0; 348#L116-2 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 397#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 352#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 353#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 368#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 399#L134-6 assume !(1 == ~t1_pc~0); 324#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 325#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 351#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 350#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 282#L308-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 283#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 344#L273-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 326#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 327#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 370#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 371#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 390#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 302#L423 assume !(0 == start_simulation_~tmp~3#1); 300#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 301#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 306#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 333#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 297#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 298#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 299#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 339#L436 assume !(0 != start_simulation_~tmp___0~1#1); 340#L404-2 [2022-12-13 20:45:34,629 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:45:34,629 INFO L85 PathProgramCache]: Analyzing trace with hash -1569234711, now seen corresponding path program 1 times [2022-12-13 20:45:34,630 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:45:34,630 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [648284593] [2022-12-13 20:45:34,630 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:45:34,630 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:45:34,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:45:34,726 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:45:34,726 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:45:34,726 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [648284593] [2022-12-13 20:45:34,726 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [648284593] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:45:34,726 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:45:34,726 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:45:34,727 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [886152872] [2022-12-13 20:45:34,727 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:45:34,727 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:45:34,728 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:45:34,728 INFO L85 PathProgramCache]: Analyzing trace with hash -445215682, now seen corresponding path program 1 times [2022-12-13 20:45:34,728 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:45:34,728 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [495940813] [2022-12-13 20:45:34,728 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:45:34,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:45:34,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:45:34,794 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:45:34,794 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:45:34,794 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [495940813] [2022-12-13 20:45:34,794 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [495940813] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:45:34,794 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:45:34,794 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 20:45:34,794 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1920831681] [2022-12-13 20:45:34,795 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:45:34,795 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:45:34,795 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:45:34,795 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 20:45:34,796 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 20:45:34,796 INFO L87 Difference]: Start difference. First operand 126 states and 182 transitions. cyclomatic complexity: 57 Second operand has 4 states, 4 states have (on average 6.75) internal successors, (27), 3 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:45:34,877 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:45:34,877 INFO L93 Difference]: Finished difference Result 304 states and 423 transitions. [2022-12-13 20:45:34,877 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 304 states and 423 transitions. [2022-12-13 20:45:34,880 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 254 [2022-12-13 20:45:34,883 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 304 states to 304 states and 423 transitions. [2022-12-13 20:45:34,883 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 304 [2022-12-13 20:45:34,884 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 304 [2022-12-13 20:45:34,884 INFO L73 IsDeterministic]: Start isDeterministic. Operand 304 states and 423 transitions. [2022-12-13 20:45:34,885 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:45:34,886 INFO L218 hiAutomatonCegarLoop]: Abstraction has 304 states and 423 transitions. [2022-12-13 20:45:34,886 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 304 states and 423 transitions. [2022-12-13 20:45:34,897 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 304 to 284. [2022-12-13 20:45:34,898 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 284 states, 284 states have (on average 1.4049295774647887) internal successors, (399), 283 states have internal predecessors, (399), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:45:34,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 284 states to 284 states and 399 transitions. [2022-12-13 20:45:34,899 INFO L240 hiAutomatonCegarLoop]: Abstraction has 284 states and 399 transitions. [2022-12-13 20:45:34,900 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 20:45:34,900 INFO L428 stractBuchiCegarLoop]: Abstraction has 284 states and 399 transitions. [2022-12-13 20:45:34,900 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 20:45:34,900 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 284 states and 399 transitions. [2022-12-13 20:45:34,902 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 252 [2022-12-13 20:45:34,902 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:45:34,902 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:45:34,903 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:45:34,903 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:45:34,904 INFO L748 eck$LassoCheckResult]: Stem: 765#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 766#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 792#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 784#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 735#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 720#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 721#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 823#L250 assume !(0 == ~M_E~0); 839#L250-2 assume !(0 == ~T1_E~0); 778#L255-1 assume !(0 == ~E_1~0); 779#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 800#L115 assume !(1 == ~m_pc~0); 801#L115-2 is_master_triggered_~__retres1~0#1 := 0; 805#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 726#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 727#L300 assume !(0 != activate_threads_~tmp~1#1); 813#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 851#L134 assume !(1 == ~t1_pc~0); 811#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 802#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 777#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 731#L308 assume !(0 != activate_threads_~tmp___0~0#1); 732#L308-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 806#L273 assume !(1 == ~M_E~0); 807#L273-2 assume !(1 == ~T1_E~0); 847#L278-1 assume !(1 == ~E_1~0); 816#L283-1 assume { :end_inline_reset_delta_events } true; 783#L404-2 [2022-12-13 20:45:34,904 INFO L750 eck$LassoCheckResult]: Loop: 783#L404-2 assume !false; 824#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 786#L225 assume !false; 787#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 869#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 763#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 733#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 734#L206 assume !(0 != eval_~tmp~0#1); 774#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 990#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 989#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 988#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 932#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 930#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 929#L115-6 assume !(1 == ~m_pc~0); 865#L115-8 is_master_triggered_~__retres1~0#1 := 0; 866#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 798#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 799#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 817#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 859#L134-6 assume !(1 == ~t1_pc~0); 767#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 768#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 797#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 964#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 962#L308-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 868#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 785#L273-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 769#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 770#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 819#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 820#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 842#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 745#L423 assume !(0 == start_simulation_~tmp~3#1); 747#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 997#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 996#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 995#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 994#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 741#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 742#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 782#L436 assume !(0 != start_simulation_~tmp___0~1#1); 783#L404-2 [2022-12-13 20:45:34,904 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:45:34,904 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 1 times [2022-12-13 20:45:34,904 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:45:34,904 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [307412254] [2022-12-13 20:45:34,905 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:45:34,905 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:45:34,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:45:34,912 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:45:34,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:45:34,930 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:45:34,931 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:45:34,931 INFO L85 PathProgramCache]: Analyzing trace with hash -753654691, now seen corresponding path program 1 times [2022-12-13 20:45:34,931 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:45:34,931 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1077199406] [2022-12-13 20:45:34,931 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:45:34,931 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:45:34,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:45:34,981 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:45:34,981 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:45:34,981 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1077199406] [2022-12-13 20:45:34,981 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1077199406] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:45:34,981 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:45:34,981 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 20:45:34,982 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1770943146] [2022-12-13 20:45:34,982 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:45:34,982 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:45:34,982 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:45:34,982 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 20:45:34,982 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 20:45:34,983 INFO L87 Difference]: Start difference. First operand 284 states and 399 transitions. cyclomatic complexity: 117 Second operand has 5 states, 5 states have (on average 8.4) internal successors, (42), 5 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:45:35,039 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:45:35,039 INFO L93 Difference]: Finished difference Result 478 states and 654 transitions. [2022-12-13 20:45:35,039 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 478 states and 654 transitions. [2022-12-13 20:45:35,041 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 441 [2022-12-13 20:45:35,043 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 478 states to 478 states and 654 transitions. [2022-12-13 20:45:35,043 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 478 [2022-12-13 20:45:35,044 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 478 [2022-12-13 20:45:35,044 INFO L73 IsDeterministic]: Start isDeterministic. Operand 478 states and 654 transitions. [2022-12-13 20:45:35,045 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:45:35,045 INFO L218 hiAutomatonCegarLoop]: Abstraction has 478 states and 654 transitions. [2022-12-13 20:45:35,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 478 states and 654 transitions. [2022-12-13 20:45:35,062 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 478 to 293. [2022-12-13 20:45:35,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 293 states, 293 states have (on average 1.3924914675767919) internal successors, (408), 292 states have internal predecessors, (408), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:45:35,064 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 293 states to 293 states and 408 transitions. [2022-12-13 20:45:35,064 INFO L240 hiAutomatonCegarLoop]: Abstraction has 293 states and 408 transitions. [2022-12-13 20:45:35,064 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-12-13 20:45:35,065 INFO L428 stractBuchiCegarLoop]: Abstraction has 293 states and 408 transitions. [2022-12-13 20:45:35,065 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 20:45:35,065 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 293 states and 408 transitions. [2022-12-13 20:45:35,068 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 261 [2022-12-13 20:45:35,068 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:45:35,068 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:45:35,069 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:45:35,069 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:45:35,069 INFO L748 eck$LassoCheckResult]: Stem: 1542#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 1543#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 1569#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1561#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1513#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 1498#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1499#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1603#L250 assume !(0 == ~M_E~0); 1617#L250-2 assume !(0 == ~T1_E~0); 1555#L255-1 assume !(0 == ~E_1~0); 1556#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1578#L115 assume !(1 == ~m_pc~0); 1579#L115-2 is_master_triggered_~__retres1~0#1 := 0; 1582#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1504#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1505#L300 assume !(0 != activate_threads_~tmp~1#1); 1590#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1632#L134 assume !(1 == ~t1_pc~0); 1585#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1580#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1554#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1507#L308 assume !(0 != activate_threads_~tmp___0~0#1); 1508#L308-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1583#L273 assume !(1 == ~M_E~0); 1584#L273-2 assume !(1 == ~T1_E~0); 1627#L278-1 assume !(1 == ~E_1~0); 1593#L283-1 assume { :end_inline_reset_delta_events } true; 1594#L404-2 [2022-12-13 20:45:35,069 INFO L750 eck$LassoCheckResult]: Loop: 1594#L404-2 assume !false; 1745#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1741#L225 assume !false; 1734#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1733#L179 assume !(0 == ~m_st~0); 1723#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 1720#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1717#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1712#L206 assume !(0 != eval_~tmp~0#1); 1711#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1709#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1707#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1622#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1623#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1658#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1657#L115-6 assume !(1 == ~m_pc~0); 1646#L115-8 is_master_triggered_~__retres1~0#1 := 0; 1647#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1575#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1576#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1640#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1641#L134-6 assume !(1 == ~t1_pc~0); 1731#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 1730#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1729#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1572#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1573#L308-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1728#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1564#L273-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1546#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1547#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1598#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1599#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1624#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 1522#L423 assume !(0 == start_simulation_~tmp~3#1); 1520#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1521#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1758#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1756#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 1754#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1752#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1750#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 1748#L436 assume !(0 != start_simulation_~tmp___0~1#1); 1594#L404-2 [2022-12-13 20:45:35,070 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:45:35,070 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 2 times [2022-12-13 20:45:35,070 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:45:35,070 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [20328749] [2022-12-13 20:45:35,070 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:45:35,070 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:45:35,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:45:35,077 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:45:35,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:45:35,084 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:45:35,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:45:35,085 INFO L85 PathProgramCache]: Analyzing trace with hash -682345966, now seen corresponding path program 1 times [2022-12-13 20:45:35,085 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:45:35,085 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [368696783] [2022-12-13 20:45:35,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:45:35,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:45:35,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:45:35,154 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:45:35,154 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:45:35,155 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [368696783] [2022-12-13 20:45:35,155 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [368696783] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:45:35,155 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:45:35,155 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 20:45:35,155 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [203666165] [2022-12-13 20:45:35,155 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:45:35,156 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:45:35,156 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:45:35,156 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 20:45:35,157 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 20:45:35,157 INFO L87 Difference]: Start difference. First operand 293 states and 408 transitions. cyclomatic complexity: 117 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:45:35,232 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:45:35,232 INFO L93 Difference]: Finished difference Result 623 states and 857 transitions. [2022-12-13 20:45:35,233 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 623 states and 857 transitions. [2022-12-13 20:45:35,237 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 591 [2022-12-13 20:45:35,240 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 623 states to 623 states and 857 transitions. [2022-12-13 20:45:35,240 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 623 [2022-12-13 20:45:35,240 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 623 [2022-12-13 20:45:35,240 INFO L73 IsDeterministic]: Start isDeterministic. Operand 623 states and 857 transitions. [2022-12-13 20:45:35,241 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:45:35,241 INFO L218 hiAutomatonCegarLoop]: Abstraction has 623 states and 857 transitions. [2022-12-13 20:45:35,242 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 623 states and 857 transitions. [2022-12-13 20:45:35,248 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 623 to 311. [2022-12-13 20:45:35,249 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 311 states, 311 states have (on average 1.360128617363344) internal successors, (423), 310 states have internal predecessors, (423), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:45:35,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 311 states to 311 states and 423 transitions. [2022-12-13 20:45:35,250 INFO L240 hiAutomatonCegarLoop]: Abstraction has 311 states and 423 transitions. [2022-12-13 20:45:35,250 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 20:45:35,251 INFO L428 stractBuchiCegarLoop]: Abstraction has 311 states and 423 transitions. [2022-12-13 20:45:35,251 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 20:45:35,251 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 311 states and 423 transitions. [2022-12-13 20:45:35,252 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 279 [2022-12-13 20:45:35,252 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:45:35,252 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:45:35,253 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:45:35,253 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:45:35,253 INFO L748 eck$LassoCheckResult]: Stem: 2471#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 2472#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 2497#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2491#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2442#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 2427#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2428#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2531#L250 assume !(0 == ~M_E~0); 2545#L250-2 assume !(0 == ~T1_E~0); 2485#L255-1 assume !(0 == ~E_1~0); 2486#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2505#L115 assume !(1 == ~m_pc~0); 2506#L115-2 is_master_triggered_~__retres1~0#1 := 0; 2509#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2433#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2434#L300 assume !(0 != activate_threads_~tmp~1#1); 2515#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2556#L134 assume !(1 == ~t1_pc~0); 2514#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2507#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2483#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2436#L308 assume !(0 != activate_threads_~tmp___0~0#1); 2437#L308-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2510#L273 assume !(1 == ~M_E~0); 2511#L273-2 assume !(1 == ~T1_E~0); 2551#L278-1 assume !(1 == ~E_1~0); 2520#L283-1 assume { :end_inline_reset_delta_events } true; 2521#L404-2 [2022-12-13 20:45:35,254 INFO L750 eck$LassoCheckResult]: Loop: 2521#L404-2 assume !false; 2604#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2602#L225 assume !false; 2601#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2598#L179 assume !(0 == ~m_st~0); 2599#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 2600#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2593#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2594#L206 assume !(0 != eval_~tmp~0#1); 2535#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2536#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2563#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2548#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2549#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2429#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2430#L115-6 assume !(1 == ~m_pc~0); 2498#L115-8 is_master_triggered_~__retres1~0#1 := 0; 2646#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2645#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2644#L300-6 assume !(0 != activate_threads_~tmp~1#1); 2643#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2642#L134-6 assume !(1 == ~t1_pc~0); 2640#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 2638#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2636#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2634#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2632#L308-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2630#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2628#L273-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2626#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2624#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2621#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2619#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2617#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 2615#L423 assume !(0 == start_simulation_~tmp~3#1); 2613#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2611#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2610#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2609#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 2608#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2607#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2606#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 2605#L436 assume !(0 != start_simulation_~tmp___0~1#1); 2521#L404-2 [2022-12-13 20:45:35,254 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:45:35,254 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 3 times [2022-12-13 20:45:35,254 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:45:35,254 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1378918455] [2022-12-13 20:45:35,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:45:35,255 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:45:35,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:45:35,261 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:45:35,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:45:35,267 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:45:35,268 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:45:35,268 INFO L85 PathProgramCache]: Analyzing trace with hash -816359472, now seen corresponding path program 1 times [2022-12-13 20:45:35,268 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:45:35,268 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [225794953] [2022-12-13 20:45:35,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:45:35,268 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:45:35,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:45:35,292 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:45:35,293 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:45:35,293 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [225794953] [2022-12-13 20:45:35,293 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [225794953] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:45:35,293 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:45:35,293 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:45:35,293 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [228360899] [2022-12-13 20:45:35,293 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:45:35,294 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 20:45:35,294 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:45:35,294 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:45:35,294 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:45:35,294 INFO L87 Difference]: Start difference. First operand 311 states and 423 transitions. cyclomatic complexity: 114 Second operand has 3 states, 3 states have (on average 14.333333333333334) internal successors, (43), 3 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:45:35,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:45:35,316 INFO L93 Difference]: Finished difference Result 460 states and 611 transitions. [2022-12-13 20:45:35,316 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 460 states and 611 transitions. [2022-12-13 20:45:35,317 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 426 [2022-12-13 20:45:35,319 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 460 states to 460 states and 611 transitions. [2022-12-13 20:45:35,319 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 460 [2022-12-13 20:45:35,319 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 460 [2022-12-13 20:45:35,319 INFO L73 IsDeterministic]: Start isDeterministic. Operand 460 states and 611 transitions. [2022-12-13 20:45:35,320 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:45:35,320 INFO L218 hiAutomatonCegarLoop]: Abstraction has 460 states and 611 transitions. [2022-12-13 20:45:35,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 460 states and 611 transitions. [2022-12-13 20:45:35,325 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 460 to 439. [2022-12-13 20:45:35,325 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 439 states, 439 states have (on average 1.3348519362186788) internal successors, (586), 438 states have internal predecessors, (586), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:45:35,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 439 states to 439 states and 586 transitions. [2022-12-13 20:45:35,326 INFO L240 hiAutomatonCegarLoop]: Abstraction has 439 states and 586 transitions. [2022-12-13 20:45:35,326 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:45:35,327 INFO L428 stractBuchiCegarLoop]: Abstraction has 439 states and 586 transitions. [2022-12-13 20:45:35,327 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 20:45:35,327 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 439 states and 586 transitions. [2022-12-13 20:45:35,330 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 405 [2022-12-13 20:45:35,330 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:45:35,330 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:45:35,330 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:45:35,331 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:45:35,331 INFO L748 eck$LassoCheckResult]: Stem: 3249#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 3250#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 3276#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3268#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3220#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 3204#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3205#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3308#L250 assume !(0 == ~M_E~0); 3323#L250-2 assume !(0 == ~T1_E~0); 3261#L255-1 assume !(0 == ~E_1~0); 3262#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3283#L115 assume !(1 == ~m_pc~0); 3284#L115-2 is_master_triggered_~__retres1~0#1 := 0; 3287#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3210#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3211#L300 assume !(0 != activate_threads_~tmp~1#1); 3294#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3339#L134 assume !(1 == ~t1_pc~0); 3293#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3285#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3260#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3214#L308 assume !(0 != activate_threads_~tmp___0~0#1); 3215#L308-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3288#L273 assume !(1 == ~M_E~0); 3289#L273-2 assume !(1 == ~T1_E~0); 3331#L278-1 assume !(1 == ~E_1~0); 3299#L283-1 assume { :end_inline_reset_delta_events } true; 3300#L404-2 assume !false; 3569#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3319#L225 [2022-12-13 20:45:35,331 INFO L750 eck$LassoCheckResult]: Loop: 3319#L225 assume !false; 3566#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3564#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3562#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3560#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3558#L206 assume 0 != eval_~tmp~0#1; 3556#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 3355#L214 assume !(0 != eval_~tmp_ndt_1~0#1); 3356#L211 assume !(0 == ~t1_st~0); 3319#L225 [2022-12-13 20:45:35,331 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:45:35,331 INFO L85 PathProgramCache]: Analyzing trace with hash -1789227190, now seen corresponding path program 1 times [2022-12-13 20:45:35,332 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:45:35,332 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [626284571] [2022-12-13 20:45:35,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:45:35,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:45:35,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:45:35,339 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:45:35,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:45:35,347 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:45:35,348 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:45:35,348 INFO L85 PathProgramCache]: Analyzing trace with hash 438949112, now seen corresponding path program 1 times [2022-12-13 20:45:35,348 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:45:35,348 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1610287478] [2022-12-13 20:45:35,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:45:35,349 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:45:35,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:45:35,352 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:45:35,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:45:35,356 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:45:35,357 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:45:35,357 INFO L85 PathProgramCache]: Analyzing trace with hash -1724815409, now seen corresponding path program 1 times [2022-12-13 20:45:35,357 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:45:35,357 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1548036178] [2022-12-13 20:45:35,357 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:45:35,357 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:45:35,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:45:35,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:45:35,378 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:45:35,378 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1548036178] [2022-12-13 20:45:35,378 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1548036178] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:45:35,378 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:45:35,379 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 20:45:35,379 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [271078969] [2022-12-13 20:45:35,379 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:45:35,426 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:45:35,427 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:45:35,427 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:45:35,427 INFO L87 Difference]: Start difference. First operand 439 states and 586 transitions. cyclomatic complexity: 150 Second operand has 3 states, 2 states have (on average 19.0) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:45:35,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:45:35,458 INFO L93 Difference]: Finished difference Result 765 states and 1008 transitions. [2022-12-13 20:45:35,458 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 765 states and 1008 transitions. [2022-12-13 20:45:35,464 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 665 [2022-12-13 20:45:35,466 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 765 states to 765 states and 1008 transitions. [2022-12-13 20:45:35,466 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 765 [2022-12-13 20:45:35,467 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 765 [2022-12-13 20:45:35,467 INFO L73 IsDeterministic]: Start isDeterministic. Operand 765 states and 1008 transitions. [2022-12-13 20:45:35,467 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:45:35,468 INFO L218 hiAutomatonCegarLoop]: Abstraction has 765 states and 1008 transitions. [2022-12-13 20:45:35,468 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 765 states and 1008 transitions. [2022-12-13 20:45:35,474 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 765 to 690. [2022-12-13 20:45:35,474 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 690 states, 690 states have (on average 1.3333333333333333) internal successors, (920), 689 states have internal predecessors, (920), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:45:35,476 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 690 states to 690 states and 920 transitions. [2022-12-13 20:45:35,476 INFO L240 hiAutomatonCegarLoop]: Abstraction has 690 states and 920 transitions. [2022-12-13 20:45:35,476 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:45:35,477 INFO L428 stractBuchiCegarLoop]: Abstraction has 690 states and 920 transitions. [2022-12-13 20:45:35,477 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 20:45:35,477 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 690 states and 920 transitions. [2022-12-13 20:45:35,479 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 616 [2022-12-13 20:45:35,479 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:45:35,479 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:45:35,479 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:45:35,479 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:45:35,480 INFO L748 eck$LassoCheckResult]: Stem: 4460#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 4461#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 4488#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4479#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4434#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 4416#L161-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 4417#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4518#L250 assume !(0 == ~M_E~0); 4531#L250-2 assume !(0 == ~T1_E~0); 4472#L255-1 assume !(0 == ~E_1~0); 4473#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4496#L115 assume !(1 == ~m_pc~0); 4497#L115-2 is_master_triggered_~__retres1~0#1 := 0; 4500#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4423#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 4424#L300 assume !(0 != activate_threads_~tmp~1#1); 4506#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4550#L134 assume !(1 == ~t1_pc~0); 4505#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4498#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4471#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4427#L308 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4428#L308-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5045#L273 assume !(1 == ~M_E~0); 5044#L273-2 assume !(1 == ~T1_E~0); 5043#L278-1 assume !(1 == ~E_1~0); 4511#L283-1 assume { :end_inline_reset_delta_events } true; 4512#L404-2 assume !false; 5100#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4527#L225 [2022-12-13 20:45:35,480 INFO L750 eck$LassoCheckResult]: Loop: 4527#L225 assume !false; 5099#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5098#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5096#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5095#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4997#L206 assume 0 != eval_~tmp~0#1; 4986#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 4568#L214 assume !(0 != eval_~tmp_ndt_1~0#1); 4569#L211 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 4525#L228 assume !(0 != eval_~tmp_ndt_2~0#1); 4527#L225 [2022-12-13 20:45:35,480 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:45:35,480 INFO L85 PathProgramCache]: Analyzing trace with hash -1113894070, now seen corresponding path program 1 times [2022-12-13 20:45:35,480 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:45:35,480 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1016345772] [2022-12-13 20:45:35,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:45:35,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:45:35,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 20:45:35,502 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 20:45:35,502 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 20:45:35,502 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1016345772] [2022-12-13 20:45:35,502 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1016345772] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 20:45:35,502 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 20:45:35,502 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 20:45:35,503 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1258408934] [2022-12-13 20:45:35,503 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 20:45:35,503 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 20:45:35,503 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:45:35,503 INFO L85 PathProgramCache]: Analyzing trace with hash 722519635, now seen corresponding path program 1 times [2022-12-13 20:45:35,504 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:45:35,504 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [404865857] [2022-12-13 20:45:35,504 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:45:35,504 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:45:35,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:45:35,507 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:45:35,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:45:35,511 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:45:35,559 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 20:45:35,559 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 20:45:35,560 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 20:45:35,560 INFO L87 Difference]: Start difference. First operand 690 states and 920 transitions. cyclomatic complexity: 234 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:45:35,566 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 20:45:35,567 INFO L93 Difference]: Finished difference Result 577 states and 772 transitions. [2022-12-13 20:45:35,567 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 577 states and 772 transitions. [2022-12-13 20:45:35,570 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 543 [2022-12-13 20:45:35,573 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 577 states to 577 states and 772 transitions. [2022-12-13 20:45:35,573 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 577 [2022-12-13 20:45:35,573 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 577 [2022-12-13 20:45:35,573 INFO L73 IsDeterministic]: Start isDeterministic. Operand 577 states and 772 transitions. [2022-12-13 20:45:35,574 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 20:45:35,574 INFO L218 hiAutomatonCegarLoop]: Abstraction has 577 states and 772 transitions. [2022-12-13 20:45:35,575 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 577 states and 772 transitions. [2022-12-13 20:45:35,582 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 577 to 577. [2022-12-13 20:45:35,583 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 577 states, 577 states have (on average 1.3379549393414212) internal successors, (772), 576 states have internal predecessors, (772), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 20:45:35,585 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 577 states to 577 states and 772 transitions. [2022-12-13 20:45:35,585 INFO L240 hiAutomatonCegarLoop]: Abstraction has 577 states and 772 transitions. [2022-12-13 20:45:35,585 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 20:45:35,586 INFO L428 stractBuchiCegarLoop]: Abstraction has 577 states and 772 transitions. [2022-12-13 20:45:35,586 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 20:45:35,586 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 577 states and 772 transitions. [2022-12-13 20:45:35,589 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 543 [2022-12-13 20:45:35,589 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 20:45:35,589 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 20:45:35,589 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:45:35,589 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 20:45:35,590 INFO L748 eck$LassoCheckResult]: Stem: 5734#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 5735#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 5761#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5753#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5705#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 5689#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5690#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5797#L250 assume !(0 == ~M_E~0); 5816#L250-2 assume !(0 == ~T1_E~0); 5746#L255-1 assume !(0 == ~E_1~0); 5747#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5772#L115 assume !(1 == ~m_pc~0); 5773#L115-2 is_master_triggered_~__retres1~0#1 := 0; 5776#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5695#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5696#L300 assume !(0 != activate_threads_~tmp~1#1); 5783#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5830#L134 assume !(1 == ~t1_pc~0); 5779#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5774#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5745#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5699#L308 assume !(0 != activate_threads_~tmp___0~0#1); 5700#L308-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5777#L273 assume !(1 == ~M_E~0); 5778#L273-2 assume !(1 == ~T1_E~0); 5822#L278-1 assume !(1 == ~E_1~0); 5788#L283-1 assume { :end_inline_reset_delta_events } true; 5789#L404-2 assume !false; 6107#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5811#L225 [2022-12-13 20:45:35,590 INFO L750 eck$LassoCheckResult]: Loop: 5811#L225 assume !false; 6106#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6105#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5795#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5796#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6130#L206 assume 0 != eval_~tmp~0#1; 6128#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 5851#L214 assume !(0 != eval_~tmp_ndt_1~0#1); 5827#L211 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 5809#L228 assume !(0 != eval_~tmp_ndt_2~0#1); 5811#L225 [2022-12-13 20:45:35,590 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:45:35,590 INFO L85 PathProgramCache]: Analyzing trace with hash -1789227190, now seen corresponding path program 2 times [2022-12-13 20:45:35,590 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:45:35,590 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [280335570] [2022-12-13 20:45:35,590 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:45:35,591 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:45:35,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:45:35,596 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:45:35,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:45:35,603 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:45:35,604 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:45:35,604 INFO L85 PathProgramCache]: Analyzing trace with hash 722519635, now seen corresponding path program 2 times [2022-12-13 20:45:35,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:45:35,604 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [124176403] [2022-12-13 20:45:35,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:45:35,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:45:35,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:45:35,607 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:45:35,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:45:35,610 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:45:35,611 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 20:45:35,611 INFO L85 PathProgramCache]: Analyzing trace with hash -1929671076, now seen corresponding path program 1 times [2022-12-13 20:45:35,611 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 20:45:35,611 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1044193186] [2022-12-13 20:45:35,611 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 20:45:35,612 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 20:45:35,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:45:35,616 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:45:35,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:45:35,621 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 20:45:36,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:45:36,016 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 20:45:36,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 20:45:36,066 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 13.12 08:45:36 BoogieIcfgContainer [2022-12-13 20:45:36,066 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-12-13 20:45:36,067 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-12-13 20:45:36,067 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-12-13 20:45:36,067 INFO L275 PluginConnector]: Witness Printer initialized [2022-12-13 20:45:36,067 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 08:45:34" (3/4) ... [2022-12-13 20:45:36,069 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-12-13 20:45:36,105 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9ad4de3-194f-4f36-9fae-cbc11bfd65dd/bin/uautomizer-uyxdKDjOR8/witness.graphml [2022-12-13 20:45:36,105 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-12-13 20:45:36,106 INFO L158 Benchmark]: Toolchain (without parser) took 2487.23ms. Allocated memory was 125.8MB in the beginning and 163.6MB in the end (delta: 37.7MB). Free memory was 92.4MB in the beginning and 61.3MB in the end (delta: 31.1MB). Peak memory consumption was 70.0MB. Max. memory is 16.1GB. [2022-12-13 20:45:36,106 INFO L158 Benchmark]: CDTParser took 0.15ms. Allocated memory is still 125.8MB. Free memory is still 94.0MB. There was no memory consumed. Max. memory is 16.1GB. [2022-12-13 20:45:36,106 INFO L158 Benchmark]: CACSL2BoogieTranslator took 184.41ms. Allocated memory is still 125.8MB. Free memory was 92.4MB in the beginning and 79.8MB in the end (delta: 12.6MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2022-12-13 20:45:36,107 INFO L158 Benchmark]: Boogie Procedure Inliner took 28.84ms. Allocated memory is still 125.8MB. Free memory was 79.8MB in the beginning and 77.6MB in the end (delta: 2.2MB). There was no memory consumed. Max. memory is 16.1GB. [2022-12-13 20:45:36,107 INFO L158 Benchmark]: Boogie Preprocessor took 20.24ms. Allocated memory is still 125.8MB. Free memory was 77.6MB in the beginning and 75.6MB in the end (delta: 2.0MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-12-13 20:45:36,107 INFO L158 Benchmark]: RCFGBuilder took 393.15ms. Allocated memory is still 125.8MB. Free memory was 75.6MB in the beginning and 56.3MB in the end (delta: 19.3MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. [2022-12-13 20:45:36,107 INFO L158 Benchmark]: BuchiAutomizer took 1817.42ms. Allocated memory was 125.8MB in the beginning and 163.6MB in the end (delta: 37.7MB). Free memory was 55.9MB in the beginning and 64.4MB in the end (delta: -8.5MB). Peak memory consumption was 32.3MB. Max. memory is 16.1GB. [2022-12-13 20:45:36,108 INFO L158 Benchmark]: Witness Printer took 38.74ms. Allocated memory is still 163.6MB. Free memory was 64.4MB in the beginning and 61.3MB in the end (delta: 3.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-12-13 20:45:36,110 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15ms. Allocated memory is still 125.8MB. Free memory is still 94.0MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 184.41ms. Allocated memory is still 125.8MB. Free memory was 92.4MB in the beginning and 79.8MB in the end (delta: 12.6MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 28.84ms. Allocated memory is still 125.8MB. Free memory was 79.8MB in the beginning and 77.6MB in the end (delta: 2.2MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 20.24ms. Allocated memory is still 125.8MB. Free memory was 77.6MB in the beginning and 75.6MB in the end (delta: 2.0MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 393.15ms. Allocated memory is still 125.8MB. Free memory was 75.6MB in the beginning and 56.3MB in the end (delta: 19.3MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. * BuchiAutomizer took 1817.42ms. Allocated memory was 125.8MB in the beginning and 163.6MB in the end (delta: 37.7MB). Free memory was 55.9MB in the beginning and 64.4MB in the end (delta: -8.5MB). Peak memory consumption was 32.3MB. Max. memory is 16.1GB. * Witness Printer took 38.74ms. Allocated memory is still 163.6MB. Free memory was 64.4MB in the beginning and 61.3MB in the end (delta: 3.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 7 terminating modules (7 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.7 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 577 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 1.7s and 8 iterations. TraceHistogramMax:1. Analysis of lassos took 1.1s. Construction of modules took 0.1s. Büchi inclusion checks took 0.3s. Highest rank in rank-based complementation 0. Minimization of det autom 7. Minimization of nondet autom 0. Automata minimization 0.1s AutomataMinimizationTime, 7 MinimizatonAttempts, 613 StatesRemovedByMinimization, 5 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1700 SdHoareTripleChecker+Valid, 0.2s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1700 mSDsluCounter, 3003 SdHoareTripleChecker+Invalid, 0.1s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1724 mSDsCounter, 62 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 173 IncrementalHoareTripleChecker+Invalid, 235 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 62 mSolverCounterUnsat, 1279 mSDtfsCounter, 173 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc1 concLT0 SILN1 SILU0 SILI2 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 201]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int m_st ; [L28] int t1_st ; [L29] int m_i ; [L30] int t1_i ; [L31] int M_E = 2; [L32] int T1_E = 2; [L33] int E_1 = 2; VAL [E_1=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0] [L449] int __retres1 ; [L453] CALL init_model() [L364] m_i = 1 [L365] t1_i = 1 VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L453] RET init_model() [L454] CALL start_simulation() [L390] int kernel_st ; [L391] int tmp ; [L392] int tmp___0 ; [L396] kernel_st = 0 [L397] FCALL update_channels() [L398] CALL init_threads() [L161] COND TRUE m_i == 1 [L162] m_st = 0 VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L166] COND TRUE t1_i == 1 [L167] t1_st = 0 VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L398] RET init_threads() [L399] CALL fire_delta_events() [L250] COND FALSE !(M_E == 0) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L255] COND FALSE !(T1_E == 0) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L260] COND FALSE !(E_1 == 0) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L399] RET fire_delta_events() [L400] CALL activate_threads() [L293] int tmp ; [L294] int tmp___0 ; [L298] CALL, EXPR is_master_triggered() [L112] int __retres1 ; VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L115] COND FALSE !(m_pc == 1) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L125] __retres1 = 0 VAL [__retres1=0, E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L127] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L298] RET, EXPR is_master_triggered() [L298] tmp = is_master_triggered() [L300] COND FALSE !(\read(tmp)) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, tmp=0] [L306] CALL, EXPR is_transmit1_triggered() [L131] int __retres1 ; VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L134] COND FALSE !(t1_pc == 1) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L144] __retres1 = 0 VAL [__retres1=0, E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L146] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L306] RET, EXPR is_transmit1_triggered() [L306] tmp___0 = is_transmit1_triggered() [L308] COND FALSE !(\read(tmp___0)) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, tmp=0, tmp___0=0] [L400] RET activate_threads() [L401] CALL reset_delta_events() [L273] COND FALSE !(M_E == 1) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L278] COND FALSE !(T1_E == 1) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L283] COND FALSE !(E_1 == 1) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L401] RET reset_delta_events() [L404] COND TRUE 1 VAL [E_1=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L407] kernel_st = 1 [L408] CALL eval() [L197] int tmp ; VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] Loop: [L201] COND TRUE 1 [L204] CALL, EXPR exists_runnable_thread() [L176] int __retres1 ; [L179] COND TRUE m_st == 0 [L180] __retres1 = 1 [L192] return (__retres1); [L204] RET, EXPR exists_runnable_thread() [L204] tmp = exists_runnable_thread() [L206] COND TRUE \read(tmp) [L211] COND TRUE m_st == 0 [L212] int tmp_ndt_1; [L213] tmp_ndt_1 = __VERIFIER_nondet_int() [L214] COND FALSE !(\read(tmp_ndt_1)) [L225] COND TRUE t1_st == 0 [L226] int tmp_ndt_2; [L227] tmp_ndt_2 = __VERIFIER_nondet_int() [L228] COND FALSE !(\read(tmp_ndt_2)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 201]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int m_st ; [L28] int t1_st ; [L29] int m_i ; [L30] int t1_i ; [L31] int M_E = 2; [L32] int T1_E = 2; [L33] int E_1 = 2; VAL [E_1=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0] [L449] int __retres1 ; [L453] CALL init_model() [L364] m_i = 1 [L365] t1_i = 1 VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L453] RET init_model() [L454] CALL start_simulation() [L390] int kernel_st ; [L391] int tmp ; [L392] int tmp___0 ; [L396] kernel_st = 0 [L397] FCALL update_channels() [L398] CALL init_threads() [L161] COND TRUE m_i == 1 [L162] m_st = 0 VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L166] COND TRUE t1_i == 1 [L167] t1_st = 0 VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L398] RET init_threads() [L399] CALL fire_delta_events() [L250] COND FALSE !(M_E == 0) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L255] COND FALSE !(T1_E == 0) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L260] COND FALSE !(E_1 == 0) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L399] RET fire_delta_events() [L400] CALL activate_threads() [L293] int tmp ; [L294] int tmp___0 ; [L298] CALL, EXPR is_master_triggered() [L112] int __retres1 ; VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L115] COND FALSE !(m_pc == 1) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L125] __retres1 = 0 VAL [__retres1=0, E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L127] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L298] RET, EXPR is_master_triggered() [L298] tmp = is_master_triggered() [L300] COND FALSE !(\read(tmp)) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, tmp=0] [L306] CALL, EXPR is_transmit1_triggered() [L131] int __retres1 ; VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L134] COND FALSE !(t1_pc == 1) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L144] __retres1 = 0 VAL [__retres1=0, E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L146] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L306] RET, EXPR is_transmit1_triggered() [L306] tmp___0 = is_transmit1_triggered() [L308] COND FALSE !(\read(tmp___0)) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, tmp=0, tmp___0=0] [L400] RET activate_threads() [L401] CALL reset_delta_events() [L273] COND FALSE !(M_E == 1) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L278] COND FALSE !(T1_E == 1) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L283] COND FALSE !(E_1 == 1) VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L401] RET reset_delta_events() [L404] COND TRUE 1 VAL [E_1=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] [L407] kernel_st = 1 [L408] CALL eval() [L197] int tmp ; VAL [E_1=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0] Loop: [L201] COND TRUE 1 [L204] CALL, EXPR exists_runnable_thread() [L176] int __retres1 ; [L179] COND TRUE m_st == 0 [L180] __retres1 = 1 [L192] return (__retres1); [L204] RET, EXPR exists_runnable_thread() [L204] tmp = exists_runnable_thread() [L206] COND TRUE \read(tmp) [L211] COND TRUE m_st == 0 [L212] int tmp_ndt_1; [L213] tmp_ndt_1 = __VERIFIER_nondet_int() [L214] COND FALSE !(\read(tmp_ndt_1)) [L225] COND TRUE t1_st == 0 [L226] int tmp_ndt_2; [L227] tmp_ndt_2 = __VERIFIER_nondet_int() [L228] COND FALSE !(\read(tmp_ndt_2)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-12-13 20:45:36,147 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e9ad4de3-194f-4f36-9fae-cbc11bfd65dd/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)