./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.11.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eb70a5ac-b117-4444-8deb-9083d848649a/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eb70a5ac-b117-4444-8deb-9083d848649a/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eb70a5ac-b117-4444-8deb-9083d848649a/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eb70a5ac-b117-4444-8deb-9083d848649a/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.11.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eb70a5ac-b117-4444-8deb-9083d848649a/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eb70a5ac-b117-4444-8deb-9083d848649a/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 940a677bfde7dbbc79e036121bd0ec6fd3518c0f58a02d336e5d42fafb098792 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 12:06:59,322 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 12:06:59,324 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 12:06:59,343 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 12:06:59,343 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 12:06:59,344 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 12:06:59,346 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 12:06:59,347 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 12:06:59,349 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 12:06:59,350 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 12:06:59,351 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 12:06:59,352 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 12:06:59,352 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 12:06:59,353 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 12:06:59,354 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 12:06:59,355 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 12:06:59,356 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 12:06:59,357 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 12:06:59,359 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 12:06:59,360 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 12:06:59,362 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 12:06:59,363 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 12:06:59,364 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 12:06:59,365 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 12:06:59,369 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 12:06:59,369 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 12:06:59,369 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 12:06:59,370 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 12:06:59,371 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 12:06:59,372 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 12:06:59,372 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 12:06:59,373 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 12:06:59,373 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 12:06:59,374 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 12:06:59,375 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 12:06:59,375 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 12:06:59,376 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 12:06:59,376 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 12:06:59,376 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 12:06:59,377 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 12:06:59,378 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 12:06:59,378 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eb70a5ac-b117-4444-8deb-9083d848649a/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 12:06:59,393 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 12:06:59,394 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 12:06:59,394 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 12:06:59,394 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 12:06:59,395 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 12:06:59,395 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 12:06:59,395 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 12:06:59,395 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 12:06:59,395 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 12:06:59,395 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 12:06:59,396 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 12:06:59,396 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 12:06:59,396 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 12:06:59,396 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 12:06:59,396 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 12:06:59,396 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 12:06:59,396 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 12:06:59,396 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 12:06:59,396 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 12:06:59,397 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 12:06:59,397 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 12:06:59,397 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 12:06:59,397 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 12:06:59,397 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 12:06:59,397 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 12:06:59,397 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 12:06:59,397 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 12:06:59,398 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 12:06:59,398 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 12:06:59,398 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 12:06:59,398 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 12:06:59,399 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 12:06:59,399 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eb70a5ac-b117-4444-8deb-9083d848649a/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eb70a5ac-b117-4444-8deb-9083d848649a/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 940a677bfde7dbbc79e036121bd0ec6fd3518c0f58a02d336e5d42fafb098792 [2022-12-13 12:06:59,563 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 12:06:59,581 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 12:06:59,583 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 12:06:59,584 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 12:06:59,584 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 12:06:59,585 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eb70a5ac-b117-4444-8deb-9083d848649a/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/transmitter.11.cil.c [2022-12-13 12:07:02,123 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 12:07:02,329 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 12:07:02,330 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eb70a5ac-b117-4444-8deb-9083d848649a/sv-benchmarks/c/systemc/transmitter.11.cil.c [2022-12-13 12:07:02,340 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eb70a5ac-b117-4444-8deb-9083d848649a/bin/uautomizer-uyxdKDjOR8/data/5a4a1520e/7ac6978961f94d44a1e63d8208f10c41/FLAG75981abbf [2022-12-13 12:07:02,701 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eb70a5ac-b117-4444-8deb-9083d848649a/bin/uautomizer-uyxdKDjOR8/data/5a4a1520e/7ac6978961f94d44a1e63d8208f10c41 [2022-12-13 12:07:02,703 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 12:07:02,704 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 12:07:02,705 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 12:07:02,705 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 12:07:02,708 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 12:07:02,709 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 12:07:02" (1/1) ... [2022-12-13 12:07:02,709 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@73894c2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:07:02, skipping insertion in model container [2022-12-13 12:07:02,709 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 12:07:02" (1/1) ... [2022-12-13 12:07:02,715 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 12:07:02,745 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 12:07:02,843 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eb70a5ac-b117-4444-8deb-9083d848649a/sv-benchmarks/c/systemc/transmitter.11.cil.c[706,719] [2022-12-13 12:07:02,917 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 12:07:02,929 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 12:07:02,938 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eb70a5ac-b117-4444-8deb-9083d848649a/sv-benchmarks/c/systemc/transmitter.11.cil.c[706,719] [2022-12-13 12:07:02,986 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 12:07:03,006 INFO L208 MainTranslator]: Completed translation [2022-12-13 12:07:03,006 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:07:03 WrapperNode [2022-12-13 12:07:03,007 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 12:07:03,007 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 12:07:03,007 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 12:07:03,008 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 12:07:03,013 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:07:03" (1/1) ... [2022-12-13 12:07:03,023 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:07:03" (1/1) ... [2022-12-13 12:07:03,083 INFO L138 Inliner]: procedures = 50, calls = 63, calls flagged for inlining = 58, calls inlined = 224, statements flattened = 3437 [2022-12-13 12:07:03,083 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 12:07:03,083 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 12:07:03,083 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 12:07:03,084 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 12:07:03,090 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:07:03" (1/1) ... [2022-12-13 12:07:03,091 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:07:03" (1/1) ... [2022-12-13 12:07:03,097 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:07:03" (1/1) ... [2022-12-13 12:07:03,097 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:07:03" (1/1) ... [2022-12-13 12:07:03,118 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:07:03" (1/1) ... [2022-12-13 12:07:03,135 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:07:03" (1/1) ... [2022-12-13 12:07:03,139 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:07:03" (1/1) ... [2022-12-13 12:07:03,144 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:07:03" (1/1) ... [2022-12-13 12:07:03,153 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 12:07:03,153 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 12:07:03,154 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 12:07:03,154 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 12:07:03,154 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:07:03" (1/1) ... [2022-12-13 12:07:03,159 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 12:07:03,168 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eb70a5ac-b117-4444-8deb-9083d848649a/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 12:07:03,178 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eb70a5ac-b117-4444-8deb-9083d848649a/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 12:07:03,180 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_eb70a5ac-b117-4444-8deb-9083d848649a/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 12:07:03,215 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 12:07:03,215 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 12:07:03,215 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 12:07:03,215 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 12:07:03,307 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 12:07:03,308 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 12:07:04,560 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 12:07:04,574 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 12:07:04,574 INFO L300 CfgBuilder]: Removed 15 assume(true) statements. [2022-12-13 12:07:04,577 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 12:07:04 BoogieIcfgContainer [2022-12-13 12:07:04,577 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 12:07:04,577 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 12:07:04,578 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 12:07:04,580 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 12:07:04,581 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 12:07:04,581 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 12:07:02" (1/3) ... [2022-12-13 12:07:04,582 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@660e7214 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 12:07:04, skipping insertion in model container [2022-12-13 12:07:04,582 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 12:07:04,582 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:07:03" (2/3) ... [2022-12-13 12:07:04,582 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@660e7214 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 12:07:04, skipping insertion in model container [2022-12-13 12:07:04,582 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 12:07:04,582 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 12:07:04" (3/3) ... [2022-12-13 12:07:04,583 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.11.cil.c [2022-12-13 12:07:04,639 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 12:07:04,639 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 12:07:04,639 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 12:07:04,639 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 12:07:04,640 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 12:07:04,640 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 12:07:04,640 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 12:07:04,640 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 12:07:04,648 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1483 states, 1482 states have (on average 1.5053981106612686) internal successors, (2231), 1482 states have internal predecessors, (2231), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:04,699 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1330 [2022-12-13 12:07:04,699 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:04,699 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:04,710 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:04,710 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:04,710 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 12:07:04,713 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1483 states, 1482 states have (on average 1.5053981106612686) internal successors, (2231), 1482 states have internal predecessors, (2231), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:04,723 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1330 [2022-12-13 12:07:04,723 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:04,723 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:04,727 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:04,728 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:04,736 INFO L748 eck$LassoCheckResult]: Stem: 224#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1367#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1112#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1362#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 503#L761true assume !(1 == ~m_i~0);~m_st~0 := 2; 520#L761-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 419#L766-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 351#L771-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 195#L776-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 18#L781-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1466#L786-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 38#L791-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 647#L796-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 611#L801-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 655#L806-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1345#L811-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 251#L816-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1161#L1090true assume !(0 == ~M_E~0); 276#L1090-2true assume !(0 == ~T1_E~0); 1318#L1095-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 789#L1100-1true assume !(0 == ~T3_E~0); 816#L1105-1true assume !(0 == ~T4_E~0); 150#L1110-1true assume !(0 == ~T5_E~0); 371#L1115-1true assume !(0 == ~T6_E~0); 591#L1120-1true assume !(0 == ~T7_E~0); 1354#L1125-1true assume !(0 == ~T8_E~0); 1346#L1130-1true assume !(0 == ~T9_E~0); 814#L1135-1true assume 0 == ~T10_E~0;~T10_E~0 := 1; 254#L1140-1true assume !(0 == ~T11_E~0); 745#L1145-1true assume !(0 == ~E_1~0); 785#L1150-1true assume !(0 == ~E_2~0); 360#L1155-1true assume !(0 == ~E_3~0); 1329#L1160-1true assume !(0 == ~E_4~0); 424#L1165-1true assume !(0 == ~E_5~0); 1085#L1170-1true assume !(0 == ~E_6~0); 1270#L1175-1true assume 0 == ~E_7~0;~E_7~0 := 1; 475#L1180-1true assume !(0 == ~E_8~0); 902#L1185-1true assume !(0 == ~E_9~0); 252#L1190-1true assume !(0 == ~E_10~0); 485#L1195-1true assume !(0 == ~E_11~0); 1029#L1200-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 367#L525true assume !(1 == ~m_pc~0); 58#L525-2true is_master_triggered_~__retres1~0#1 := 0; 1023#L536true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 913#is_master_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 882#L1350true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 245#L1350-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 524#L544true assume 1 == ~t1_pc~0; 405#L545true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 742#L555true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 162#L1358true assume !(0 != activate_threads_~tmp___0~0#1); 569#L1358-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1018#L563true assume !(1 == ~t2_pc~0); 732#L563-2true is_transmit2_triggered_~__retres1~2#1 := 0; 67#L574true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 358#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 291#L1366true assume !(0 != activate_threads_~tmp___1~0#1); 633#L1366-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 743#L582true assume 1 == ~t3_pc~0; 135#L583true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1232#L593true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1096#L1374true assume !(0 != activate_threads_~tmp___2~0#1); 102#L1374-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1390#L601true assume !(1 == ~t4_pc~0); 835#L601-2true is_transmit4_triggered_~__retres1~4#1 := 0; 372#L612true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 108#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 753#L1382true assume !(0 != activate_threads_~tmp___3~0#1); 1396#L1382-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1204#L620true assume 1 == ~t5_pc~0; 81#L621true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 652#L631true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 920#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1465#L1390true assume !(0 != activate_threads_~tmp___4~0#1); 1260#L1390-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1358#L639true assume !(1 == ~t6_pc~0); 589#L639-2true is_transmit6_triggered_~__retres1~6#1 := 0; 311#L650true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 343#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1255#L1398true assume !(0 != activate_threads_~tmp___5~0#1); 375#L1398-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 949#L658true assume 1 == ~t7_pc~0; 590#L659true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1278#L669true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1382#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 693#L1406true assume !(0 != activate_threads_~tmp___6~0#1); 248#L1406-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 379#L677true assume 1 == ~t8_pc~0; 871#L678true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 142#L688true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 837#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 288#L1414true assume !(0 != activate_threads_~tmp___7~0#1); 872#L1414-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 984#L696true assume !(1 == ~t9_pc~0); 578#L696-2true is_transmit9_triggered_~__retres1~9#1 := 0; 662#L707true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 411#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 595#L1422true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 793#L1422-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1139#L715true assume 1 == ~t10_pc~0; 802#L716true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 679#L726true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 512#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 770#L1430true assume !(0 != activate_threads_~tmp___9~0#1); 471#L1430-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 140#L734true assume !(1 == ~t11_pc~0); 425#L734-2true is_transmit11_triggered_~__retres1~11#1 := 0; 477#L745true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 700#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12#L1438true assume !(0 != activate_threads_~tmp___10~0#1); 653#L1438-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1200#L1213true assume !(1 == ~M_E~0); 469#L1213-2true assume !(1 == ~T1_E~0); 969#L1218-1true assume !(1 == ~T2_E~0); 28#L1223-1true assume !(1 == ~T3_E~0); 453#L1228-1true assume !(1 == ~T4_E~0); 1261#L1233-1true assume !(1 == ~T5_E~0); 1446#L1238-1true assume !(1 == ~T6_E~0); 752#L1243-1true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1403#L1248-1true assume !(1 == ~T8_E~0); 799#L1253-1true assume !(1 == ~T9_E~0); 1100#L1258-1true assume !(1 == ~T10_E~0); 778#L1263-1true assume !(1 == ~T11_E~0); 1146#L1268-1true assume !(1 == ~E_1~0); 607#L1273-1true assume !(1 == ~E_2~0); 1242#L1278-1true assume !(1 == ~E_3~0); 310#L1283-1true assume 1 == ~E_4~0;~E_4~0 := 2; 1290#L1288-1true assume !(1 == ~E_5~0); 927#L1293-1true assume !(1 == ~E_6~0); 878#L1298-1true assume !(1 == ~E_7~0); 637#L1303-1true assume !(1 == ~E_8~0); 317#L1308-1true assume !(1 == ~E_9~0); 256#L1313-1true assume !(1 == ~E_10~0); 1372#L1318-1true assume !(1 == ~E_11~0); 261#L1323-1true assume { :end_inline_reset_delta_events } true; 1151#L1644-2true [2022-12-13 12:07:04,738 INFO L750 eck$LassoCheckResult]: Loop: 1151#L1644-2true assume !false; 691#L1645true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 769#L1065true assume !true; 845#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 535#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 954#L1090-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1042#L1090-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1375#L1095-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 987#L1100-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1253#L1105-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 191#L1110-3true assume !(0 == ~T5_E~0); 1090#L1115-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 352#L1120-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 750#L1125-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1127#L1130-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1289#L1135-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 304#L1140-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 42#L1145-3true assume 0 == ~E_1~0;~E_1~0 := 1; 490#L1150-3true assume !(0 == ~E_2~0); 103#L1155-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1425#L1160-3true assume 0 == ~E_4~0;~E_4~0 := 1; 295#L1165-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1480#L1170-3true assume 0 == ~E_6~0;~E_6~0 := 1; 564#L1175-3true assume 0 == ~E_7~0;~E_7~0 := 1; 247#L1180-3true assume 0 == ~E_8~0;~E_8~0 := 1; 117#L1185-3true assume 0 == ~E_9~0;~E_9~0 := 1; 1292#L1190-3true assume !(0 == ~E_10~0); 1105#L1195-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1478#L1200-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 441#L525-36true assume 1 == ~m_pc~0; 1109#L526-12true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 167#L536-12true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1115#is_master_triggered_returnLabel#13true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 325#L1350-36true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 563#L1350-38true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 278#L544-36true assume !(1 == ~t1_pc~0); 924#L544-38true is_transmit1_triggered_~__retres1~1#1 := 0; 669#L555-12true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1113#is_transmit1_triggered_returnLabel#13true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1271#L1358-36true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1082#L1358-38true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 915#L563-36true assume 1 == ~t2_pc~0; 161#L564-12true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 40#L574-12true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 892#is_transmit2_triggered_returnLabel#13true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1269#L1366-36true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 452#L1366-38true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1374#L582-36true assume 1 == ~t3_pc~0; 346#L583-12true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 502#L593-12true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 406#is_transmit3_triggered_returnLabel#13true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 660#L1374-36true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 476#L1374-38true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 438#L601-36true assume !(1 == ~t4_pc~0); 664#L601-38true is_transmit4_triggered_~__retres1~4#1 := 0; 1461#L612-12true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 549#is_transmit4_triggered_returnLabel#13true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1052#L1382-36true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1194#L1382-38true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 899#L620-36true assume 1 == ~t5_pc~0; 398#L621-12true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 735#L631-12true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1063#is_transmit5_triggered_returnLabel#13true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 378#L1390-36true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 173#L1390-38true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63#L639-36true assume !(1 == ~t6_pc~0); 1414#L639-38true is_transmit6_triggered_~__retres1~6#1 := 0; 83#L650-12true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 383#is_transmit6_triggered_returnLabel#13true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 202#L1398-36true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 593#L1398-38true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1193#L658-36true assume !(1 == ~t7_pc~0); 69#L658-38true is_transmit7_triggered_~__retres1~7#1 := 0; 1020#L669-12true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1026#is_transmit7_triggered_returnLabel#13true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59#L1406-36true assume !(0 != activate_threads_~tmp___6~0#1); 721#L1406-38true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 938#L677-36true assume 1 == ~t8_pc~0; 1098#L678-12true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 634#L688-12true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 635#is_transmit8_triggered_returnLabel#13true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1191#L1414-36true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 550#L1414-38true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1102#L696-36true assume !(1 == ~t9_pc~0); 1315#L696-38true is_transmit9_triggered_~__retres1~9#1 := 0; 834#L707-12true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 431#is_transmit9_triggered_returnLabel#13true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1021#L1422-36true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 565#L1422-38true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1266#L715-36true assume !(1 == ~t10_pc~0); 537#L715-38true is_transmit10_triggered_~__retres1~10#1 := 0; 13#L726-12true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 316#is_transmit10_triggered_returnLabel#13true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2#L1430-36true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1067#L1430-38true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 197#L734-36true assume !(1 == ~t11_pc~0); 47#L734-38true is_transmit11_triggered_~__retres1~11#1 := 0; 207#L745-12true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1316#is_transmit11_triggered_returnLabel#13true activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9#L1438-36true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 615#L1438-38true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1107#L1213-3true assume 1 == ~M_E~0;~M_E~0 := 2; 357#L1213-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 718#L1218-3true assume !(1 == ~T2_E~0); 222#L1223-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 758#L1228-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 328#L1233-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1279#L1238-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 500#L1243-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1051#L1248-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1408#L1253-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1058#L1258-3true assume !(1 == ~T10_E~0); 213#L1263-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1003#L1268-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1028#L1273-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1459#L1278-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1031#L1283-3true assume 1 == ~E_4~0;~E_4~0 := 2; 423#L1288-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1300#L1293-3true assume 1 == ~E_6~0;~E_6~0 := 2; 324#L1298-3true assume !(1 == ~E_7~0); 1153#L1303-3true assume 1 == ~E_8~0;~E_8~0 := 2; 688#L1308-3true assume 1 == ~E_9~0;~E_9~0 := 2; 322#L1313-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1054#L1318-3true assume 1 == ~E_11~0;~E_11~0 := 2; 214#L1323-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1435#L829-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 434#L891-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 312#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1436#L1663true assume !(0 == start_simulation_~tmp~3#1); 1340#L1663-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 592#L829-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 518#L891-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 44#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 74#L1618true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 250#L1625true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 552#stop_simulation_returnLabel#1true start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1180#L1676true assume !(0 != start_simulation_~tmp___0~1#1); 1151#L1644-2true [2022-12-13 12:07:04,745 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:04,745 INFO L85 PathProgramCache]: Analyzing trace with hash -92888918, now seen corresponding path program 1 times [2022-12-13 12:07:04,754 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:04,754 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [333379974] [2022-12-13 12:07:04,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:04,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:04,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:05,004 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:05,004 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:05,005 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [333379974] [2022-12-13 12:07:05,005 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [333379974] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:05,005 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:05,006 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:05,007 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1268755897] [2022-12-13 12:07:05,008 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:05,011 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:07:05,012 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:05,012 INFO L85 PathProgramCache]: Analyzing trace with hash -365321077, now seen corresponding path program 1 times [2022-12-13 12:07:05,012 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:05,013 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [55603318] [2022-12-13 12:07:05,013 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:05,013 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:05,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:05,075 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:05,075 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:05,076 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [55603318] [2022-12-13 12:07:05,076 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [55603318] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:05,076 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:05,076 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 12:07:05,076 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1592197653] [2022-12-13 12:07:05,076 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:05,078 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:07:05,079 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:07:05,103 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-12-13 12:07:05,103 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-12-13 12:07:05,106 INFO L87 Difference]: Start difference. First operand has 1483 states, 1482 states have (on average 1.5053981106612686) internal successors, (2231), 1482 states have internal predecessors, (2231), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 68.5) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:05,158 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:07:05,159 INFO L93 Difference]: Finished difference Result 1482 states and 2199 transitions. [2022-12-13 12:07:05,160 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1482 states and 2199 transitions. [2022-12-13 12:07:05,166 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-12-13 12:07:05,175 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1482 states to 1476 states and 2193 transitions. [2022-12-13 12:07:05,176 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2022-12-13 12:07:05,178 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2022-12-13 12:07:05,178 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2193 transitions. [2022-12-13 12:07:05,183 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:07:05,183 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2193 transitions. [2022-12-13 12:07:05,198 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2193 transitions. [2022-12-13 12:07:05,227 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2022-12-13 12:07:05,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4857723577235773) internal successors, (2193), 1475 states have internal predecessors, (2193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:05,232 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2193 transitions. [2022-12-13 12:07:05,233 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2193 transitions. [2022-12-13 12:07:05,233 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-12-13 12:07:05,236 INFO L428 stractBuchiCegarLoop]: Abstraction has 1476 states and 2193 transitions. [2022-12-13 12:07:05,236 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 12:07:05,236 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2193 transitions. [2022-12-13 12:07:05,253 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-12-13 12:07:05,253 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:05,253 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:05,255 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:05,256 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:05,256 INFO L748 eck$LassoCheckResult]: Stem: 3414#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 3415#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 4385#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4386#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3857#L761 assume !(1 == ~m_i~0);~m_st~0 := 2; 3858#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3728#L766-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3627#L771-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3358#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3008#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3009#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3051#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3052#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3983#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3984#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4028#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 3454#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3455#L1090 assume !(0 == ~M_E~0); 3499#L1090-2 assume !(0 == ~T1_E~0); 3500#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4174#L1100-1 assume !(0 == ~T3_E~0); 4175#L1105-1 assume !(0 == ~T4_E~0); 3281#L1110-1 assume !(0 == ~T5_E~0); 3282#L1115-1 assume !(0 == ~T6_E~0); 3663#L1120-1 assume !(0 == ~T7_E~0); 3962#L1125-1 assume !(0 == ~T8_E~0); 4435#L1130-1 assume !(0 == ~T9_E~0); 4195#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3459#L1140-1 assume !(0 == ~T11_E~0); 3460#L1145-1 assume !(0 == ~E_1~0); 4129#L1150-1 assume !(0 == ~E_2~0); 3640#L1155-1 assume !(0 == ~E_3~0); 3641#L1160-1 assume !(0 == ~E_4~0); 3733#L1165-1 assume !(0 == ~E_5~0); 3734#L1170-1 assume !(0 == ~E_6~0); 4368#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 3815#L1180-1 assume !(0 == ~E_8~0); 3816#L1185-1 assume !(0 == ~E_9~0); 3456#L1190-1 assume !(0 == ~E_10~0); 3457#L1195-1 assume !(0 == ~E_11~0); 3831#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3660#L525 assume !(1 == ~m_pc~0); 3093#L525-2 is_master_triggered_~__retres1~0#1 := 0; 3094#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4269#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4244#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3447#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3448#L544 assume 1 == ~t1_pc~0; 3710#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3662#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3072#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3073#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 3304#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3932#L563 assume !(1 == ~t2_pc~0); 4115#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3112#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3113#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3527#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 3528#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4009#L582 assume 1 == ~t3_pc~0; 3250#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3251#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3000#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3001#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 3184#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3185#L601 assume !(1 == ~t4_pc~0); 4141#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3664#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3201#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3202#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 4136#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4410#L620 assume 1 == ~t5_pc~0; 3144#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3145#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4025#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4275#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 4419#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4420#L639 assume !(1 == ~t6_pc~0); 3960#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3564#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3565#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3613#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 3670#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3671#L658 assume 1 == ~t7_pc~0; 3961#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3882#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4425#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4078#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 3450#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3451#L677 assume 1 == ~t8_pc~0; 3678#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3263#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3264#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3520#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 3521#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4236#L696 assume !(1 == ~t9_pc~0); 3945#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3946#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3720#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3721#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3967#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4178#L715 assume 1 == ~t10_pc~0; 4185#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4058#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3869#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3870#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 3809#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3257#L734 assume !(1 == ~t11_pc~0); 3258#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 3735#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3820#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2998#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 2999#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4026#L1213 assume !(1 == ~M_E~0); 3807#L1213-2 assume !(1 == ~T1_E~0); 3808#L1218-1 assume !(1 == ~T2_E~0); 3029#L1223-1 assume !(1 == ~T3_E~0); 3030#L1228-1 assume !(1 == ~T4_E~0); 3782#L1233-1 assume !(1 == ~T5_E~0); 4421#L1238-1 assume !(1 == ~T6_E~0); 4134#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4135#L1248-1 assume !(1 == ~T8_E~0); 4181#L1253-1 assume !(1 == ~T9_E~0); 4182#L1258-1 assume !(1 == ~T10_E~0); 4158#L1263-1 assume !(1 == ~T11_E~0); 4159#L1268-1 assume !(1 == ~E_1~0); 3980#L1273-1 assume !(1 == ~E_2~0); 3981#L1278-1 assume !(1 == ~E_3~0); 3560#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3561#L1288-1 assume !(1 == ~E_5~0); 4280#L1293-1 assume !(1 == ~E_6~0); 4240#L1298-1 assume !(1 == ~E_7~0); 4013#L1303-1 assume !(1 == ~E_8~0); 3570#L1308-1 assume !(1 == ~E_9~0); 3463#L1313-1 assume !(1 == ~E_10~0); 3464#L1318-1 assume !(1 == ~E_11~0); 3474#L1323-1 assume { :end_inline_reset_delta_events } true; 3475#L1644-2 [2022-12-13 12:07:05,257 INFO L750 eck$LassoCheckResult]: Loop: 3475#L1644-2 assume !false; 4074#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4075#L1065 assume !false; 4149#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4417#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3108#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3685#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3575#L906 assume !(0 != eval_~tmp~0#1); 3577#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3892#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3893#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4295#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4352#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4317#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4318#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3353#L1110-3 assume !(0 == ~T5_E~0); 3354#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3628#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3629#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4133#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4392#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3552#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 3063#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3064#L1150-3 assume !(0 == ~E_2~0); 3187#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3188#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3533#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3534#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3925#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3449#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3216#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3217#L1190-3 assume !(0 == ~E_10~0); 4379#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4380#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3764#L525-36 assume !(1 == ~m_pc~0); 3765#L525-38 is_master_triggered_~__retres1~0#1 := 0; 3318#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3319#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3585#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3586#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3496#L544-36 assume 1 == ~t1_pc~0; 3497#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4047#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4048#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4384#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4366#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4270#L563-36 assume 1 == ~t2_pc~0; 3302#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3059#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3060#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4251#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3780#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3781#L582-36 assume 1 == ~t3_pc~0; 3617#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3618#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3711#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3712#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3817#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3758#L601-36 assume 1 == ~t4_pc~0; 3648#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3649#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3909#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3910#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4356#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4257#L620-36 assume 1 == ~t5_pc~0; 3697#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3698#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4118#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3675#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3322#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3104#L639-36 assume 1 == ~t6_pc~0; 3105#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3142#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3143#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3372#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3373#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3965#L658-36 assume 1 == ~t7_pc~0; 3221#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3118#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4342#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3095#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 3096#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4107#L677-36 assume 1 == ~t8_pc~0; 4284#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3885#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4010#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4011#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3911#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3912#L696-36 assume 1 == ~t9_pc~0; 3803#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3805#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3746#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3747#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3926#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3927#L715-36 assume !(1 == ~t10_pc~0); 3891#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 2996#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2997#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2974#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2975#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3362#L734-36 assume 1 == ~t11_pc~0; 3363#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3071#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3382#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2990#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2991#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3989#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3634#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3635#L1218-3 assume !(1 == ~T2_E~0); 3411#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3412#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3589#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3590#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3854#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3855#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4355#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4357#L1258-3 assume !(1 == ~T10_E~0); 3394#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3395#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4330#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4345#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4347#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3731#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3732#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3583#L1298-3 assume !(1 == ~E_7~0); 3584#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4070#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3580#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3581#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 3396#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3397#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3337#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3562#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3563#L1663 assume !(0 == start_simulation_~tmp~3#1); 3238#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3963#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3182#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3065#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 3066#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3128#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3453#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 3913#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 3475#L1644-2 [2022-12-13 12:07:05,258 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:05,258 INFO L85 PathProgramCache]: Analyzing trace with hash -92888918, now seen corresponding path program 2 times [2022-12-13 12:07:05,258 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:05,258 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1804772799] [2022-12-13 12:07:05,258 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:05,258 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:05,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:05,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:05,320 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:05,320 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1804772799] [2022-12-13 12:07:05,320 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1804772799] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:05,321 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:05,321 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:05,321 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1365955792] [2022-12-13 12:07:05,321 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:05,322 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:07:05,322 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:05,322 INFO L85 PathProgramCache]: Analyzing trace with hash 1091788943, now seen corresponding path program 1 times [2022-12-13 12:07:05,322 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:05,323 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [910917840] [2022-12-13 12:07:05,323 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:05,323 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:05,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:05,407 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:05,407 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:05,407 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [910917840] [2022-12-13 12:07:05,408 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [910917840] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:05,408 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:05,408 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:05,408 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [571389901] [2022-12-13 12:07:05,408 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:05,409 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:07:05,409 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:07:05,409 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:07:05,409 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:07:05,410 INFO L87 Difference]: Start difference. First operand 1476 states and 2193 transitions. cyclomatic complexity: 718 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:05,443 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:07:05,443 INFO L93 Difference]: Finished difference Result 1476 states and 2192 transitions. [2022-12-13 12:07:05,443 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2192 transitions. [2022-12-13 12:07:05,449 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-12-13 12:07:05,454 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2192 transitions. [2022-12-13 12:07:05,454 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2022-12-13 12:07:05,455 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2022-12-13 12:07:05,455 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2192 transitions. [2022-12-13 12:07:05,457 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:07:05,457 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2192 transitions. [2022-12-13 12:07:05,459 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2192 transitions. [2022-12-13 12:07:05,470 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2022-12-13 12:07:05,471 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4850948509485096) internal successors, (2192), 1475 states have internal predecessors, (2192), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:05,474 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2192 transitions. [2022-12-13 12:07:05,474 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2192 transitions. [2022-12-13 12:07:05,474 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:07:05,475 INFO L428 stractBuchiCegarLoop]: Abstraction has 1476 states and 2192 transitions. [2022-12-13 12:07:05,475 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 12:07:05,475 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2192 transitions. [2022-12-13 12:07:05,482 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-12-13 12:07:05,482 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:05,482 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:05,483 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:05,484 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:05,484 INFO L748 eck$LassoCheckResult]: Stem: 6373#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 6374#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 7343#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7344#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6816#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 6817#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6687#L766-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 6586#L771-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 6317#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5967#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5968#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6010#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6011#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6942#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6943#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 6987#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 6413#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6414#L1090 assume !(0 == ~M_E~0); 6455#L1090-2 assume !(0 == ~T1_E~0); 6456#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7132#L1100-1 assume !(0 == ~T3_E~0); 7133#L1105-1 assume !(0 == ~T4_E~0); 6239#L1110-1 assume !(0 == ~T5_E~0); 6240#L1115-1 assume !(0 == ~T6_E~0); 6622#L1120-1 assume !(0 == ~T7_E~0); 6921#L1125-1 assume !(0 == ~T8_E~0); 7394#L1130-1 assume !(0 == ~T9_E~0); 7154#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6418#L1140-1 assume !(0 == ~T11_E~0); 6419#L1145-1 assume !(0 == ~E_1~0); 7088#L1150-1 assume !(0 == ~E_2~0); 6599#L1155-1 assume !(0 == ~E_3~0); 6600#L1160-1 assume !(0 == ~E_4~0); 6692#L1165-1 assume !(0 == ~E_5~0); 6693#L1170-1 assume !(0 == ~E_6~0); 7327#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 6774#L1180-1 assume !(0 == ~E_8~0); 6775#L1185-1 assume !(0 == ~E_9~0); 6415#L1190-1 assume !(0 == ~E_10~0); 6416#L1195-1 assume !(0 == ~E_11~0); 6790#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6614#L525 assume !(1 == ~m_pc~0); 6052#L525-2 is_master_triggered_~__retres1~0#1 := 0; 6053#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7228#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7201#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6406#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6407#L544 assume 1 == ~t1_pc~0; 6669#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6621#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6026#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6027#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 6263#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6891#L563 assume !(1 == ~t2_pc~0); 7074#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6071#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6072#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6483#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 6484#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6968#L582 assume 1 == ~t3_pc~0; 6207#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6208#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5959#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5960#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 6143#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6144#L601 assume !(1 == ~t4_pc~0); 7100#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6623#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6156#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6157#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 7095#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7369#L620 assume 1 == ~t5_pc~0; 6099#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6100#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6984#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7233#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 7378#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7379#L639 assume !(1 == ~t6_pc~0); 6919#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6521#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6522#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6572#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 6629#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6630#L658 assume 1 == ~t7_pc~0; 6920#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6840#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7384#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7036#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 6409#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6410#L677 assume 1 == ~t8_pc~0; 6635#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6222#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6223#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6479#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 6480#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7195#L696 assume !(1 == ~t9_pc~0); 6902#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 6903#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6679#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6680#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6926#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7137#L715 assume 1 == ~t10_pc~0; 7144#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7017#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6828#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6829#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 6768#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6216#L734 assume !(1 == ~t11_pc~0); 6217#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 6694#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 6777#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5955#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 5956#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6985#L1213 assume !(1 == ~M_E~0); 6765#L1213-2 assume !(1 == ~T1_E~0); 6766#L1218-1 assume !(1 == ~T2_E~0); 5988#L1223-1 assume !(1 == ~T3_E~0); 5989#L1228-1 assume !(1 == ~T4_E~0); 6741#L1233-1 assume !(1 == ~T5_E~0); 7380#L1238-1 assume !(1 == ~T6_E~0); 7093#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7094#L1248-1 assume !(1 == ~T8_E~0); 7140#L1253-1 assume !(1 == ~T9_E~0); 7141#L1258-1 assume !(1 == ~T10_E~0); 7117#L1263-1 assume !(1 == ~T11_E~0); 7118#L1268-1 assume !(1 == ~E_1~0); 6939#L1273-1 assume !(1 == ~E_2~0); 6940#L1278-1 assume !(1 == ~E_3~0); 6519#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6520#L1288-1 assume !(1 == ~E_5~0); 7239#L1293-1 assume !(1 == ~E_6~0); 7199#L1298-1 assume !(1 == ~E_7~0); 6972#L1303-1 assume !(1 == ~E_8~0); 6529#L1308-1 assume !(1 == ~E_9~0); 6422#L1313-1 assume !(1 == ~E_10~0); 6423#L1318-1 assume !(1 == ~E_11~0); 6430#L1323-1 assume { :end_inline_reset_delta_events } true; 6431#L1644-2 [2022-12-13 12:07:05,484 INFO L750 eck$LassoCheckResult]: Loop: 6431#L1644-2 assume !false; 7033#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7034#L1065 assume !false; 7108#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7376#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6067#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6644#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6534#L906 assume !(0 != eval_~tmp~0#1); 6536#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6850#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6851#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7254#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7311#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7276#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7277#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6312#L1110-3 assume !(0 == ~T5_E~0); 6313#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6587#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6588#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7092#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7351#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6509#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 6020#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6021#L1150-3 assume !(0 == ~E_2~0); 6145#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6146#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6492#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6493#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6884#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6408#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6172#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6173#L1190-3 assume !(0 == ~E_10~0); 7338#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7339#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6723#L525-36 assume !(1 == ~m_pc~0); 6724#L525-38 is_master_triggered_~__retres1~0#1 := 0; 6272#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6273#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6544#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6545#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6458#L544-36 assume 1 == ~t1_pc~0; 6459#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7006#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7007#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7345#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7325#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7229#L563-36 assume 1 == ~t2_pc~0; 6261#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6018#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6019#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7210#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6739#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6740#L582-36 assume 1 == ~t3_pc~0; 6576#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6577#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6670#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6671#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6776#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6717#L601-36 assume !(1 == ~t4_pc~0); 6609#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 6608#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6868#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6869#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7315#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7216#L620-36 assume 1 == ~t5_pc~0; 6658#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6659#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7077#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6634#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6281#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6063#L639-36 assume 1 == ~t6_pc~0; 6064#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6104#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6105#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6332#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6333#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6924#L658-36 assume 1 == ~t7_pc~0; 6182#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6077#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7301#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6054#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 6055#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7066#L677-36 assume 1 == ~t8_pc~0; 7243#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6844#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6969#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6970#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6870#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6871#L696-36 assume 1 == ~t9_pc~0; 6762#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6764#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6705#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6706#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6885#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6886#L715-36 assume 1 == ~t10_pc~0; 7028#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5957#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5958#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5933#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5934#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6321#L734-36 assume 1 == ~t11_pc~0; 6322#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 6032#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 6341#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5949#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 5950#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6948#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6595#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6596#L1218-3 assume !(1 == ~T2_E~0); 6370#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6371#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6548#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6549#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6813#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6814#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7314#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7317#L1258-3 assume !(1 == ~T10_E~0); 6353#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 6354#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7289#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7304#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7306#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6690#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6691#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6542#L1298-3 assume !(1 == ~E_7~0); 6543#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7029#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6539#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 6540#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 6355#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 6356#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6296#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6523#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 6524#L1663 assume !(0 == start_simulation_~tmp~3#1); 6197#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 6922#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6141#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6024#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 6025#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6087#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6412#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 6872#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 6431#L1644-2 [2022-12-13 12:07:05,485 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:05,485 INFO L85 PathProgramCache]: Analyzing trace with hash -456355416, now seen corresponding path program 1 times [2022-12-13 12:07:05,485 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:05,485 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [205034848] [2022-12-13 12:07:05,485 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:05,485 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:05,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:05,523 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:05,523 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:05,523 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [205034848] [2022-12-13 12:07:05,524 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [205034848] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:05,524 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:05,524 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:05,524 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [606470964] [2022-12-13 12:07:05,524 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:05,524 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:07:05,525 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:05,525 INFO L85 PathProgramCache]: Analyzing trace with hash -795951857, now seen corresponding path program 1 times [2022-12-13 12:07:05,525 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:05,526 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1627503351] [2022-12-13 12:07:05,526 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:05,526 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:05,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:05,586 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:05,587 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:05,587 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1627503351] [2022-12-13 12:07:05,587 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1627503351] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:05,587 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:05,587 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:05,588 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1164302637] [2022-12-13 12:07:05,588 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:05,588 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:07:05,588 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:07:05,589 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:07:05,589 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:07:05,589 INFO L87 Difference]: Start difference. First operand 1476 states and 2192 transitions. cyclomatic complexity: 717 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:05,614 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:07:05,614 INFO L93 Difference]: Finished difference Result 1476 states and 2191 transitions. [2022-12-13 12:07:05,614 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2191 transitions. [2022-12-13 12:07:05,620 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-12-13 12:07:05,624 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2191 transitions. [2022-12-13 12:07:05,624 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2022-12-13 12:07:05,625 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2022-12-13 12:07:05,625 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2191 transitions. [2022-12-13 12:07:05,626 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:07:05,627 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2191 transitions. [2022-12-13 12:07:05,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2191 transitions. [2022-12-13 12:07:05,639 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2022-12-13 12:07:05,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4844173441734418) internal successors, (2191), 1475 states have internal predecessors, (2191), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:05,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2191 transitions. [2022-12-13 12:07:05,644 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2191 transitions. [2022-12-13 12:07:05,644 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:07:05,645 INFO L428 stractBuchiCegarLoop]: Abstraction has 1476 states and 2191 transitions. [2022-12-13 12:07:05,645 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 12:07:05,645 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2191 transitions. [2022-12-13 12:07:05,651 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-12-13 12:07:05,651 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:05,651 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:05,653 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:05,653 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:05,653 INFO L748 eck$LassoCheckResult]: Stem: 9332#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 9333#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 10302#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10303#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9775#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 9776#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9646#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9545#L771-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 9276#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8926#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8927#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8969#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8970#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9901#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9902#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9946#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9372#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9373#L1090 assume !(0 == ~M_E~0); 9414#L1090-2 assume !(0 == ~T1_E~0); 9415#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10092#L1100-1 assume !(0 == ~T3_E~0); 10093#L1105-1 assume !(0 == ~T4_E~0); 9199#L1110-1 assume !(0 == ~T5_E~0); 9200#L1115-1 assume !(0 == ~T6_E~0); 9581#L1120-1 assume !(0 == ~T7_E~0); 9880#L1125-1 assume !(0 == ~T8_E~0); 10353#L1130-1 assume !(0 == ~T9_E~0); 10113#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9377#L1140-1 assume !(0 == ~T11_E~0); 9378#L1145-1 assume !(0 == ~E_1~0); 10047#L1150-1 assume !(0 == ~E_2~0); 9558#L1155-1 assume !(0 == ~E_3~0); 9559#L1160-1 assume !(0 == ~E_4~0); 9651#L1165-1 assume !(0 == ~E_5~0); 9652#L1170-1 assume !(0 == ~E_6~0); 10286#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 9733#L1180-1 assume !(0 == ~E_8~0); 9734#L1185-1 assume !(0 == ~E_9~0); 9374#L1190-1 assume !(0 == ~E_10~0); 9375#L1195-1 assume !(0 == ~E_11~0); 9749#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9578#L525 assume !(1 == ~m_pc~0); 9011#L525-2 is_master_triggered_~__retres1~0#1 := 0; 9012#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10187#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10162#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9365#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9366#L544 assume 1 == ~t1_pc~0; 9628#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9580#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8990#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8991#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 9222#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9850#L563 assume !(1 == ~t2_pc~0); 10033#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9030#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9031#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9442#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 9443#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9927#L582 assume 1 == ~t3_pc~0; 9168#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9169#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8918#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8919#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 9102#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9103#L601 assume !(1 == ~t4_pc~0); 10059#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9582#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9119#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9120#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 10054#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10328#L620 assume 1 == ~t5_pc~0; 9060#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9061#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9943#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10193#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 10337#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10338#L639 assume !(1 == ~t6_pc~0); 9878#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9482#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9483#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9531#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 9588#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9589#L658 assume 1 == ~t7_pc~0; 9879#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9800#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10343#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9996#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 9368#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9369#L677 assume 1 == ~t8_pc~0; 9596#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9181#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9182#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9438#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 9439#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10154#L696 assume !(1 == ~t9_pc~0); 9863#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 9864#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9638#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9639#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9885#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10096#L715 assume 1 == ~t10_pc~0; 10103#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 9976#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9787#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9788#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 9727#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9175#L734 assume !(1 == ~t11_pc~0); 9176#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 9653#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9736#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8916#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 8917#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9944#L1213 assume !(1 == ~M_E~0); 9725#L1213-2 assume !(1 == ~T1_E~0); 9726#L1218-1 assume !(1 == ~T2_E~0); 8947#L1223-1 assume !(1 == ~T3_E~0); 8948#L1228-1 assume !(1 == ~T4_E~0); 9700#L1233-1 assume !(1 == ~T5_E~0); 10339#L1238-1 assume !(1 == ~T6_E~0); 10052#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10053#L1248-1 assume !(1 == ~T8_E~0); 10099#L1253-1 assume !(1 == ~T9_E~0); 10100#L1258-1 assume !(1 == ~T10_E~0); 10076#L1263-1 assume !(1 == ~T11_E~0); 10077#L1268-1 assume !(1 == ~E_1~0); 9898#L1273-1 assume !(1 == ~E_2~0); 9899#L1278-1 assume !(1 == ~E_3~0); 9478#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 9479#L1288-1 assume !(1 == ~E_5~0); 10198#L1293-1 assume !(1 == ~E_6~0); 10158#L1298-1 assume !(1 == ~E_7~0); 9931#L1303-1 assume !(1 == ~E_8~0); 9488#L1308-1 assume !(1 == ~E_9~0); 9381#L1313-1 assume !(1 == ~E_10~0); 9382#L1318-1 assume !(1 == ~E_11~0); 9392#L1323-1 assume { :end_inline_reset_delta_events } true; 9393#L1644-2 [2022-12-13 12:07:05,654 INFO L750 eck$LassoCheckResult]: Loop: 9393#L1644-2 assume !false; 9992#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9993#L1065 assume !false; 10067#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10335#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9026#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9603#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9493#L906 assume !(0 != eval_~tmp~0#1); 9495#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9810#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9811#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10213#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10270#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10235#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10236#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9271#L1110-3 assume !(0 == ~T5_E~0); 9272#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9546#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9547#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10051#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10310#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9470#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 8981#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8982#L1150-3 assume !(0 == ~E_2~0); 9105#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9106#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9451#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9452#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9843#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9367#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9132#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9133#L1190-3 assume !(0 == ~E_10~0); 10297#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10298#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9682#L525-36 assume !(1 == ~m_pc~0); 9683#L525-38 is_master_triggered_~__retres1~0#1 := 0; 9236#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9237#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9503#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9504#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9417#L544-36 assume 1 == ~t1_pc~0; 9418#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9965#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9966#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10304#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10285#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10188#L563-36 assume 1 == ~t2_pc~0; 9220#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8977#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8978#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10169#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9698#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9699#L582-36 assume !(1 == ~t3_pc~0); 9537#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 9536#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9629#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9630#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9735#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9673#L601-36 assume !(1 == ~t4_pc~0); 9568#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 9567#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9827#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9828#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10274#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10173#L620-36 assume !(1 == ~t5_pc~0); 9617#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 9616#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10036#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9593#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9240#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9022#L639-36 assume !(1 == ~t6_pc~0); 9024#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 9058#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9059#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9290#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9291#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9883#L658-36 assume 1 == ~t7_pc~0; 9139#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9036#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10260#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9013#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 9014#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10025#L677-36 assume 1 == ~t8_pc~0; 10202#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9803#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9928#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9929#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9829#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9830#L696-36 assume 1 == ~t9_pc~0; 9721#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9723#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9664#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9665#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9844#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9845#L715-36 assume !(1 == ~t10_pc~0); 9809#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 8914#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8915#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8892#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8893#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9280#L734-36 assume 1 == ~t11_pc~0; 9281#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 8989#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9300#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8908#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8909#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9907#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9552#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9553#L1218-3 assume !(1 == ~T2_E~0); 9329#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9330#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9507#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9508#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9772#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9773#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10273#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10275#L1258-3 assume !(1 == ~T10_E~0); 9312#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9313#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10248#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10263#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10265#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9649#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9650#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9501#L1298-3 assume !(1 == ~E_7~0); 9502#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9988#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9498#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9499#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 9314#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 9315#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9255#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9480#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 9481#L1663 assume !(0 == start_simulation_~tmp~3#1); 9151#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 9881#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9100#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 8983#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 8984#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9043#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9371#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 9831#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 9393#L1644-2 [2022-12-13 12:07:05,654 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:05,654 INFO L85 PathProgramCache]: Analyzing trace with hash 88517158, now seen corresponding path program 1 times [2022-12-13 12:07:05,654 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:05,654 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1296697947] [2022-12-13 12:07:05,655 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:05,655 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:05,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:05,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:05,690 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:05,690 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1296697947] [2022-12-13 12:07:05,691 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1296697947] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:05,691 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:05,691 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:05,691 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1256782535] [2022-12-13 12:07:05,691 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:05,692 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:07:05,692 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:05,692 INFO L85 PathProgramCache]: Analyzing trace with hash -1163132021, now seen corresponding path program 1 times [2022-12-13 12:07:05,692 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:05,692 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1707017904] [2022-12-13 12:07:05,692 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:05,693 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:05,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:05,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:05,737 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:05,737 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1707017904] [2022-12-13 12:07:05,737 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1707017904] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:05,737 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:05,737 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:05,737 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [798474585] [2022-12-13 12:07:05,737 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:05,738 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:07:05,738 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:07:05,738 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:07:05,738 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:07:05,739 INFO L87 Difference]: Start difference. First operand 1476 states and 2191 transitions. cyclomatic complexity: 716 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:05,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:07:05,763 INFO L93 Difference]: Finished difference Result 1476 states and 2190 transitions. [2022-12-13 12:07:05,763 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2190 transitions. [2022-12-13 12:07:05,769 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-12-13 12:07:05,772 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2190 transitions. [2022-12-13 12:07:05,773 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2022-12-13 12:07:05,773 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2022-12-13 12:07:05,774 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2190 transitions. [2022-12-13 12:07:05,775 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:07:05,775 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2190 transitions. [2022-12-13 12:07:05,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2190 transitions. [2022-12-13 12:07:05,787 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2022-12-13 12:07:05,789 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.483739837398374) internal successors, (2190), 1475 states have internal predecessors, (2190), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:05,800 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2190 transitions. [2022-12-13 12:07:05,801 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2190 transitions. [2022-12-13 12:07:05,801 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:07:05,801 INFO L428 stractBuchiCegarLoop]: Abstraction has 1476 states and 2190 transitions. [2022-12-13 12:07:05,802 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 12:07:05,802 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2190 transitions. [2022-12-13 12:07:05,809 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-12-13 12:07:05,810 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:05,810 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:05,811 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:05,811 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:05,811 INFO L748 eck$LassoCheckResult]: Stem: 12291#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 12292#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 13261#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13262#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12734#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 12735#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12605#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12504#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12235#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 11885#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11886#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11928#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11929#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12860#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12861#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12905#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12331#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12332#L1090 assume !(0 == ~M_E~0); 12373#L1090-2 assume !(0 == ~T1_E~0); 12374#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13050#L1100-1 assume !(0 == ~T3_E~0); 13051#L1105-1 assume !(0 == ~T4_E~0); 12157#L1110-1 assume !(0 == ~T5_E~0); 12158#L1115-1 assume !(0 == ~T6_E~0); 12540#L1120-1 assume !(0 == ~T7_E~0); 12839#L1125-1 assume !(0 == ~T8_E~0); 13312#L1130-1 assume !(0 == ~T9_E~0); 13072#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12336#L1140-1 assume !(0 == ~T11_E~0); 12337#L1145-1 assume !(0 == ~E_1~0); 13006#L1150-1 assume !(0 == ~E_2~0); 12517#L1155-1 assume !(0 == ~E_3~0); 12518#L1160-1 assume !(0 == ~E_4~0); 12610#L1165-1 assume !(0 == ~E_5~0); 12611#L1170-1 assume !(0 == ~E_6~0); 13245#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 12692#L1180-1 assume !(0 == ~E_8~0); 12693#L1185-1 assume !(0 == ~E_9~0); 12333#L1190-1 assume !(0 == ~E_10~0); 12334#L1195-1 assume !(0 == ~E_11~0); 12708#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12532#L525 assume !(1 == ~m_pc~0); 11970#L525-2 is_master_triggered_~__retres1~0#1 := 0; 11971#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13146#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13119#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12324#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12325#L544 assume 1 == ~t1_pc~0; 12587#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12539#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11944#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11945#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 12181#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12809#L563 assume !(1 == ~t2_pc~0); 12992#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11989#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11990#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12401#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 12402#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12886#L582 assume 1 == ~t3_pc~0; 12125#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12126#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11877#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11878#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 12061#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12062#L601 assume !(1 == ~t4_pc~0); 13018#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12541#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12074#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12075#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 13013#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13287#L620 assume 1 == ~t5_pc~0; 12017#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12018#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12902#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13151#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 13296#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13297#L639 assume !(1 == ~t6_pc~0); 12837#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12439#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12440#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12490#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 12547#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12548#L658 assume 1 == ~t7_pc~0; 12838#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12758#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13302#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12954#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 12327#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12328#L677 assume 1 == ~t8_pc~0; 12553#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12140#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12141#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12397#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 12398#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13113#L696 assume !(1 == ~t9_pc~0); 12820#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 12821#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12597#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12598#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12844#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13055#L715 assume 1 == ~t10_pc~0; 13062#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12935#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12746#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12747#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 12686#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12134#L734 assume !(1 == ~t11_pc~0); 12135#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 12612#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12695#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11873#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 11874#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12903#L1213 assume !(1 == ~M_E~0); 12683#L1213-2 assume !(1 == ~T1_E~0); 12684#L1218-1 assume !(1 == ~T2_E~0); 11906#L1223-1 assume !(1 == ~T3_E~0); 11907#L1228-1 assume !(1 == ~T4_E~0); 12659#L1233-1 assume !(1 == ~T5_E~0); 13298#L1238-1 assume !(1 == ~T6_E~0); 13011#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13012#L1248-1 assume !(1 == ~T8_E~0); 13058#L1253-1 assume !(1 == ~T9_E~0); 13059#L1258-1 assume !(1 == ~T10_E~0); 13035#L1263-1 assume !(1 == ~T11_E~0); 13036#L1268-1 assume !(1 == ~E_1~0); 12857#L1273-1 assume !(1 == ~E_2~0); 12858#L1278-1 assume !(1 == ~E_3~0); 12437#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 12438#L1288-1 assume !(1 == ~E_5~0); 13157#L1293-1 assume !(1 == ~E_6~0); 13117#L1298-1 assume !(1 == ~E_7~0); 12890#L1303-1 assume !(1 == ~E_8~0); 12447#L1308-1 assume !(1 == ~E_9~0); 12340#L1313-1 assume !(1 == ~E_10~0); 12341#L1318-1 assume !(1 == ~E_11~0); 12348#L1323-1 assume { :end_inline_reset_delta_events } true; 12349#L1644-2 [2022-12-13 12:07:05,812 INFO L750 eck$LassoCheckResult]: Loop: 12349#L1644-2 assume !false; 12951#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12952#L1065 assume !false; 13026#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13294#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 11985#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12562#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12452#L906 assume !(0 != eval_~tmp~0#1); 12454#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12768#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12769#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13172#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13229#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13194#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13195#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12230#L1110-3 assume !(0 == ~T5_E~0); 12231#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12505#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12506#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13010#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13269#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12427#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 11938#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11939#L1150-3 assume !(0 == ~E_2~0); 12063#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12064#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12410#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12411#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12802#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12326#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12090#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12091#L1190-3 assume !(0 == ~E_10~0); 13256#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 13257#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12641#L525-36 assume !(1 == ~m_pc~0); 12642#L525-38 is_master_triggered_~__retres1~0#1 := 0; 12190#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12191#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12462#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12463#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12376#L544-36 assume 1 == ~t1_pc~0; 12377#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12924#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12925#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13263#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13243#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13147#L563-36 assume 1 == ~t2_pc~0; 12179#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11936#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11937#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13128#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12657#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12658#L582-36 assume !(1 == ~t3_pc~0); 12496#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 12495#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12588#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12589#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12694#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12635#L601-36 assume 1 == ~t4_pc~0; 12525#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12526#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12786#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12787#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13233#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13134#L620-36 assume 1 == ~t5_pc~0; 12576#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12577#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12995#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12552#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12199#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11981#L639-36 assume 1 == ~t6_pc~0; 11982#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12022#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12023#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12250#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12251#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12842#L658-36 assume 1 == ~t7_pc~0; 12100#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11995#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13219#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11972#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 11973#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12984#L677-36 assume 1 == ~t8_pc~0; 13161#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12762#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12887#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12888#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12788#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12789#L696-36 assume 1 == ~t9_pc~0; 12680#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12682#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12623#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12624#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12803#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12804#L715-36 assume 1 == ~t10_pc~0; 12946#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11875#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11876#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11851#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11852#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12239#L734-36 assume 1 == ~t11_pc~0; 12240#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11950#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12259#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11867#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11868#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12866#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12513#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12514#L1218-3 assume !(1 == ~T2_E~0); 12288#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12289#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12466#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12467#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12731#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12732#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13232#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13235#L1258-3 assume !(1 == ~T10_E~0); 12271#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12272#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13207#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13222#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13224#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12608#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12609#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12460#L1298-3 assume !(1 == ~E_7~0); 12461#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12947#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12457#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12458#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12273#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 12274#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12214#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12441#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 12442#L1663 assume !(0 == start_simulation_~tmp~3#1); 12115#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 12840#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12059#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 11942#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 11943#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12005#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12330#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 12790#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 12349#L1644-2 [2022-12-13 12:07:05,812 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:05,812 INFO L85 PathProgramCache]: Analyzing trace with hash -586642968, now seen corresponding path program 1 times [2022-12-13 12:07:05,812 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:05,813 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1201062656] [2022-12-13 12:07:05,813 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:05,813 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:05,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:05,845 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:05,845 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:05,845 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1201062656] [2022-12-13 12:07:05,846 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1201062656] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:05,846 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:05,846 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:05,846 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1254192343] [2022-12-13 12:07:05,846 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:05,846 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:07:05,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:05,847 INFO L85 PathProgramCache]: Analyzing trace with hash -378492465, now seen corresponding path program 1 times [2022-12-13 12:07:05,847 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:05,847 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1007500175] [2022-12-13 12:07:05,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:05,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:05,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:05,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:05,887 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:05,887 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1007500175] [2022-12-13 12:07:05,887 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1007500175] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:05,888 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:05,888 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:05,888 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [922602864] [2022-12-13 12:07:05,888 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:05,888 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:07:05,888 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:07:05,889 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:07:05,889 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:07:05,889 INFO L87 Difference]: Start difference. First operand 1476 states and 2190 transitions. cyclomatic complexity: 715 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:05,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:07:05,913 INFO L93 Difference]: Finished difference Result 1476 states and 2189 transitions. [2022-12-13 12:07:05,913 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2189 transitions. [2022-12-13 12:07:05,918 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-12-13 12:07:05,922 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2189 transitions. [2022-12-13 12:07:05,922 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2022-12-13 12:07:05,923 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2022-12-13 12:07:05,923 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2189 transitions. [2022-12-13 12:07:05,925 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:07:05,925 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2189 transitions. [2022-12-13 12:07:05,926 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2189 transitions. [2022-12-13 12:07:05,937 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2022-12-13 12:07:05,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4830623306233062) internal successors, (2189), 1475 states have internal predecessors, (2189), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:05,941 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2189 transitions. [2022-12-13 12:07:05,942 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2189 transitions. [2022-12-13 12:07:05,942 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:07:05,942 INFO L428 stractBuchiCegarLoop]: Abstraction has 1476 states and 2189 transitions. [2022-12-13 12:07:05,942 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 12:07:05,943 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2189 transitions. [2022-12-13 12:07:05,950 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-12-13 12:07:05,950 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:05,950 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:05,951 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:05,951 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:05,952 INFO L748 eck$LassoCheckResult]: Stem: 15250#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 15251#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 16220#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16221#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15693#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 15694#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15564#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15463#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15194#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14844#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 14845#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14887#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14888#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15819#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15820#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 15864#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 15290#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15291#L1090 assume !(0 == ~M_E~0); 15332#L1090-2 assume !(0 == ~T1_E~0); 15333#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16010#L1100-1 assume !(0 == ~T3_E~0); 16011#L1105-1 assume !(0 == ~T4_E~0); 15117#L1110-1 assume !(0 == ~T5_E~0); 15118#L1115-1 assume !(0 == ~T6_E~0); 15499#L1120-1 assume !(0 == ~T7_E~0); 15798#L1125-1 assume !(0 == ~T8_E~0); 16271#L1130-1 assume !(0 == ~T9_E~0); 16031#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15295#L1140-1 assume !(0 == ~T11_E~0); 15296#L1145-1 assume !(0 == ~E_1~0); 15965#L1150-1 assume !(0 == ~E_2~0); 15476#L1155-1 assume !(0 == ~E_3~0); 15477#L1160-1 assume !(0 == ~E_4~0); 15569#L1165-1 assume !(0 == ~E_5~0); 15570#L1170-1 assume !(0 == ~E_6~0); 16204#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 15651#L1180-1 assume !(0 == ~E_8~0); 15652#L1185-1 assume !(0 == ~E_9~0); 15292#L1190-1 assume !(0 == ~E_10~0); 15293#L1195-1 assume !(0 == ~E_11~0); 15667#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15496#L525 assume !(1 == ~m_pc~0); 14929#L525-2 is_master_triggered_~__retres1~0#1 := 0; 14930#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16105#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16078#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15283#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15284#L544 assume 1 == ~t1_pc~0; 15546#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15498#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14908#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14909#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 15140#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15768#L563 assume !(1 == ~t2_pc~0); 15951#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14948#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14949#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15360#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 15361#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15845#L582 assume 1 == ~t3_pc~0; 15086#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15087#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14836#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14837#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 15020#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15021#L601 assume !(1 == ~t4_pc~0); 15977#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 15500#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15037#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15038#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 15972#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16246#L620 assume 1 == ~t5_pc~0; 14978#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14979#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15861#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16111#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 16255#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16256#L639 assume !(1 == ~t6_pc~0); 15796#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 15400#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15401#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15449#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 15506#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15507#L658 assume 1 == ~t7_pc~0; 15797#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15717#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16261#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15913#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 15286#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15287#L677 assume 1 == ~t8_pc~0; 15512#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15099#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15100#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15356#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 15357#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16072#L696 assume !(1 == ~t9_pc~0); 15781#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 15782#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15556#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15557#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15803#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16014#L715 assume 1 == ~t10_pc~0; 16021#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 15894#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15705#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15706#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 15645#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15093#L734 assume !(1 == ~t11_pc~0); 15094#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 15571#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15654#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14834#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 14835#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15862#L1213 assume !(1 == ~M_E~0); 15643#L1213-2 assume !(1 == ~T1_E~0); 15644#L1218-1 assume !(1 == ~T2_E~0); 14865#L1223-1 assume !(1 == ~T3_E~0); 14866#L1228-1 assume !(1 == ~T4_E~0); 15618#L1233-1 assume !(1 == ~T5_E~0); 16257#L1238-1 assume !(1 == ~T6_E~0); 15970#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15971#L1248-1 assume !(1 == ~T8_E~0); 16017#L1253-1 assume !(1 == ~T9_E~0); 16018#L1258-1 assume !(1 == ~T10_E~0); 15994#L1263-1 assume !(1 == ~T11_E~0); 15995#L1268-1 assume !(1 == ~E_1~0); 15816#L1273-1 assume !(1 == ~E_2~0); 15817#L1278-1 assume !(1 == ~E_3~0); 15396#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15397#L1288-1 assume !(1 == ~E_5~0); 16116#L1293-1 assume !(1 == ~E_6~0); 16076#L1298-1 assume !(1 == ~E_7~0); 15849#L1303-1 assume !(1 == ~E_8~0); 15406#L1308-1 assume !(1 == ~E_9~0); 15299#L1313-1 assume !(1 == ~E_10~0); 15300#L1318-1 assume !(1 == ~E_11~0); 15310#L1323-1 assume { :end_inline_reset_delta_events } true; 15311#L1644-2 [2022-12-13 12:07:05,952 INFO L750 eck$LassoCheckResult]: Loop: 15311#L1644-2 assume !false; 15910#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15911#L1065 assume !false; 15985#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16253#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 14944#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 15521#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15411#L906 assume !(0 != eval_~tmp~0#1); 15413#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15728#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15729#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16131#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16188#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16153#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16154#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15189#L1110-3 assume !(0 == ~T5_E~0); 15190#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15464#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15465#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15969#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16228#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15386#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 14899#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14900#L1150-3 assume !(0 == ~E_2~0); 15023#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15024#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15369#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15370#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15761#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15285#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15050#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15051#L1190-3 assume !(0 == ~E_10~0); 16215#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16216#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15600#L525-36 assume !(1 == ~m_pc~0); 15601#L525-38 is_master_triggered_~__retres1~0#1 := 0; 15154#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15155#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15421#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15422#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15335#L544-36 assume 1 == ~t1_pc~0; 15336#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15883#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15884#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16222#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16203#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16106#L563-36 assume 1 == ~t2_pc~0; 15138#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14895#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14896#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16087#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15616#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15617#L582-36 assume 1 == ~t3_pc~0; 15453#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15454#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15547#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15548#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15653#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15594#L601-36 assume 1 == ~t4_pc~0; 15484#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15485#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15745#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15746#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16192#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16093#L620-36 assume 1 == ~t5_pc~0; 15537#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15538#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15958#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15511#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15158#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14937#L639-36 assume 1 == ~t6_pc~0; 14938#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14976#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14977#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15206#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15207#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15801#L658-36 assume 1 == ~t7_pc~0; 15057#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14951#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16178#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14931#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 14932#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15943#L677-36 assume 1 == ~t8_pc~0; 16119#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15720#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15846#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15847#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15747#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15748#L696-36 assume 1 == ~t9_pc~0; 15639#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15641#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15582#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15583#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15762#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15763#L715-36 assume 1 == ~t10_pc~0; 15905#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 14832#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14833#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14810#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14811#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15198#L734-36 assume !(1 == ~t11_pc~0); 14906#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 14907#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15218#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14826#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14827#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15825#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15470#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15471#L1218-3 assume !(1 == ~T2_E~0); 15247#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15248#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15425#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15426#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15690#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15691#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16191#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16193#L1258-3 assume !(1 == ~T10_E~0); 15230#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15231#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16166#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16181#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16183#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15567#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15568#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15418#L1298-3 assume !(1 == ~E_7~0); 15419#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15906#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15416#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15417#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 15232#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 15233#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15173#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 15398#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 15399#L1663 assume !(0 == start_simulation_~tmp~3#1); 15067#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 15799#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15018#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 14901#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 14902#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14961#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15289#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 15749#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 15311#L1644-2 [2022-12-13 12:07:05,952 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:05,952 INFO L85 PathProgramCache]: Analyzing trace with hash 361408998, now seen corresponding path program 1 times [2022-12-13 12:07:05,953 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:05,953 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [333022469] [2022-12-13 12:07:05,953 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:05,953 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:05,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:05,983 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:05,983 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:05,983 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [333022469] [2022-12-13 12:07:05,983 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [333022469] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:05,983 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:05,983 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:05,984 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [723204863] [2022-12-13 12:07:05,984 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:05,984 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:07:05,984 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:05,985 INFO L85 PathProgramCache]: Analyzing trace with hash 1798407119, now seen corresponding path program 1 times [2022-12-13 12:07:05,985 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:05,985 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1193626961] [2022-12-13 12:07:05,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:05,985 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:05,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:06,046 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:06,046 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:06,046 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1193626961] [2022-12-13 12:07:06,046 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1193626961] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:06,046 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:06,046 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:06,047 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [422255021] [2022-12-13 12:07:06,047 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:06,047 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:07:06,047 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:07:06,047 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:07:06,047 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:07:06,047 INFO L87 Difference]: Start difference. First operand 1476 states and 2189 transitions. cyclomatic complexity: 714 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:06,072 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:07:06,072 INFO L93 Difference]: Finished difference Result 1476 states and 2188 transitions. [2022-12-13 12:07:06,072 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2188 transitions. [2022-12-13 12:07:06,080 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-12-13 12:07:06,084 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2188 transitions. [2022-12-13 12:07:06,084 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2022-12-13 12:07:06,085 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2022-12-13 12:07:06,085 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2188 transitions. [2022-12-13 12:07:06,086 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:07:06,086 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2188 transitions. [2022-12-13 12:07:06,088 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2188 transitions. [2022-12-13 12:07:06,099 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2022-12-13 12:07:06,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4823848238482384) internal successors, (2188), 1475 states have internal predecessors, (2188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:06,103 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2188 transitions. [2022-12-13 12:07:06,103 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2188 transitions. [2022-12-13 12:07:06,104 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:07:06,104 INFO L428 stractBuchiCegarLoop]: Abstraction has 1476 states and 2188 transitions. [2022-12-13 12:07:06,105 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 12:07:06,105 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2188 transitions. [2022-12-13 12:07:06,110 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-12-13 12:07:06,111 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:06,111 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:06,113 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:06,113 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:06,113 INFO L748 eck$LassoCheckResult]: Stem: 18209#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 18210#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 19180#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19181#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18652#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 18653#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18523#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18422#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18153#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17803#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17804#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17846#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17847#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 18782#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18783#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18830#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 18249#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18250#L1090 assume !(0 == ~M_E~0); 18295#L1090-2 assume !(0 == ~T1_E~0); 18296#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18969#L1100-1 assume !(0 == ~T3_E~0); 18970#L1105-1 assume !(0 == ~T4_E~0); 18076#L1110-1 assume !(0 == ~T5_E~0); 18077#L1115-1 assume !(0 == ~T6_E~0); 18461#L1120-1 assume !(0 == ~T7_E~0); 18757#L1125-1 assume !(0 == ~T8_E~0); 19230#L1130-1 assume !(0 == ~T9_E~0); 18990#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 18254#L1140-1 assume !(0 == ~T11_E~0); 18255#L1145-1 assume !(0 == ~E_1~0); 18924#L1150-1 assume !(0 == ~E_2~0); 18435#L1155-1 assume !(0 == ~E_3~0); 18436#L1160-1 assume !(0 == ~E_4~0); 18528#L1165-1 assume !(0 == ~E_5~0); 18529#L1170-1 assume !(0 == ~E_6~0); 19163#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 18610#L1180-1 assume !(0 == ~E_8~0); 18611#L1185-1 assume !(0 == ~E_9~0); 18251#L1190-1 assume !(0 == ~E_10~0); 18252#L1195-1 assume !(0 == ~E_11~0); 18626#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18455#L525 assume !(1 == ~m_pc~0); 17888#L525-2 is_master_triggered_~__retres1~0#1 := 0; 17889#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19064#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19039#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18242#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18243#L544 assume 1 == ~t1_pc~0; 18505#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18457#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17867#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17868#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 18099#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18727#L563 assume !(1 == ~t2_pc~0); 18912#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 17907#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17908#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18322#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 18323#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18804#L582 assume 1 == ~t3_pc~0; 18045#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18046#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17795#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17796#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 17979#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17980#L601 assume !(1 == ~t4_pc~0); 18936#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18462#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17996#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17997#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 18931#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19205#L620 assume 1 == ~t5_pc~0; 17939#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17940#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18820#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19070#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 19214#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19215#L639 assume !(1 == ~t6_pc~0); 18756#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 18359#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18360#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18408#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 18467#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18468#L658 assume 1 == ~t7_pc~0; 18755#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18676#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19220#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18872#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 18245#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18246#L677 assume 1 == ~t8_pc~0; 18471#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18058#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18059#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18315#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 18316#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19031#L696 assume !(1 == ~t9_pc~0); 18738#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 18739#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18515#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18516#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18762#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18973#L715 assume 1 == ~t10_pc~0; 18980#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 18853#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18664#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18665#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 18604#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18052#L734 assume !(1 == ~t11_pc~0); 18053#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 18530#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18613#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17791#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 17792#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18821#L1213 assume !(1 == ~M_E~0); 18601#L1213-2 assume !(1 == ~T1_E~0); 18602#L1218-1 assume !(1 == ~T2_E~0); 17824#L1223-1 assume !(1 == ~T3_E~0); 17825#L1228-1 assume !(1 == ~T4_E~0); 18577#L1233-1 assume !(1 == ~T5_E~0); 19216#L1238-1 assume !(1 == ~T6_E~0); 18929#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18930#L1248-1 assume !(1 == ~T8_E~0); 18976#L1253-1 assume !(1 == ~T9_E~0); 18977#L1258-1 assume !(1 == ~T10_E~0); 18953#L1263-1 assume !(1 == ~T11_E~0); 18954#L1268-1 assume !(1 == ~E_1~0); 18775#L1273-1 assume !(1 == ~E_2~0); 18776#L1278-1 assume !(1 == ~E_3~0); 18355#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 18356#L1288-1 assume !(1 == ~E_5~0); 19075#L1293-1 assume !(1 == ~E_6~0); 19035#L1298-1 assume !(1 == ~E_7~0); 18808#L1303-1 assume !(1 == ~E_8~0); 18365#L1308-1 assume !(1 == ~E_9~0); 18258#L1313-1 assume !(1 == ~E_10~0); 18259#L1318-1 assume !(1 == ~E_11~0); 18266#L1323-1 assume { :end_inline_reset_delta_events } true; 18267#L1644-2 [2022-12-13 12:07:06,114 INFO L750 eck$LassoCheckResult]: Loop: 18267#L1644-2 assume !false; 18869#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18870#L1065 assume !false; 18944#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19212#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 17903#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 18480#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18370#L906 assume !(0 != eval_~tmp~0#1); 18372#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18686#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18687#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19090#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19147#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19112#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19113#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18148#L1110-3 assume !(0 == ~T5_E~0); 18149#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18423#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18424#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18928#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19187#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 18345#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 17856#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17857#L1150-3 assume !(0 == ~E_2~0); 17981#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17982#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18328#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18329#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18720#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18244#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18008#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18009#L1190-3 assume !(0 == ~E_10~0); 19174#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 19175#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18559#L525-36 assume !(1 == ~m_pc~0); 18560#L525-38 is_master_triggered_~__retres1~0#1 := 0; 18108#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18109#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18380#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18381#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18292#L544-36 assume 1 == ~t1_pc~0; 18293#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18842#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18843#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19179#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19161#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19065#L563-36 assume 1 == ~t2_pc~0; 18097#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17854#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17855#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19046#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18575#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18576#L582-36 assume 1 == ~t3_pc~0; 18412#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18413#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18506#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18507#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18612#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18553#L601-36 assume 1 == ~t4_pc~0; 18443#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18444#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18704#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18705#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19151#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19052#L620-36 assume !(1 == ~t5_pc~0); 18496#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 18495#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18913#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18470#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18117#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17899#L639-36 assume 1 == ~t6_pc~0; 17900#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17937#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17938#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18168#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18169#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18760#L658-36 assume 1 == ~t7_pc~0; 18018#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17913#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19137#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17890#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 17891#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18902#L677-36 assume 1 == ~t8_pc~0; 19079#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18680#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18805#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18806#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18706#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18707#L696-36 assume 1 == ~t9_pc~0; 18598#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18600#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18541#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18542#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18721#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18722#L715-36 assume 1 == ~t10_pc~0; 18864#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 17793#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17794#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17769#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17770#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18157#L734-36 assume !(1 == ~t11_pc~0); 17865#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 17866#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18177#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17785#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 17786#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18784#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18431#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18432#L1218-3 assume !(1 == ~T2_E~0); 18206#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18207#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18384#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18385#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18649#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18650#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19150#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19153#L1258-3 assume !(1 == ~T10_E~0); 18189#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18190#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19125#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19140#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19142#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18526#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18527#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18378#L1298-3 assume !(1 == ~E_7~0); 18379#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18865#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 18375#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 18376#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 18191#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 18192#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 18132#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 18357#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 18358#L1663 assume !(0 == start_simulation_~tmp~3#1); 18033#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 18758#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 17977#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 17860#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 17861#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17923#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18248#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 18708#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 18267#L1644-2 [2022-12-13 12:07:06,114 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:06,114 INFO L85 PathProgramCache]: Analyzing trace with hash 946180648, now seen corresponding path program 1 times [2022-12-13 12:07:06,114 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:06,114 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [943874290] [2022-12-13 12:07:06,115 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:06,115 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:06,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:06,151 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:06,151 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:06,151 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [943874290] [2022-12-13 12:07:06,151 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [943874290] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:06,151 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:06,151 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:06,151 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [646383390] [2022-12-13 12:07:06,151 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:06,151 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:07:06,152 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:06,152 INFO L85 PathProgramCache]: Analyzing trace with hash 521254446, now seen corresponding path program 1 times [2022-12-13 12:07:06,152 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:06,152 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [190192978] [2022-12-13 12:07:06,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:06,152 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:06,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:06,190 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:06,190 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:06,190 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [190192978] [2022-12-13 12:07:06,190 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [190192978] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:06,191 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:06,191 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:06,191 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [816849173] [2022-12-13 12:07:06,191 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:06,191 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:07:06,191 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:07:06,191 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:07:06,191 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:07:06,192 INFO L87 Difference]: Start difference. First operand 1476 states and 2188 transitions. cyclomatic complexity: 713 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:06,224 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:07:06,224 INFO L93 Difference]: Finished difference Result 1476 states and 2187 transitions. [2022-12-13 12:07:06,224 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2187 transitions. [2022-12-13 12:07:06,231 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-12-13 12:07:06,238 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2187 transitions. [2022-12-13 12:07:06,238 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2022-12-13 12:07:06,239 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2022-12-13 12:07:06,239 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2187 transitions. [2022-12-13 12:07:06,241 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:07:06,242 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2187 transitions. [2022-12-13 12:07:06,244 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2187 transitions. [2022-12-13 12:07:06,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2022-12-13 12:07:06,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4817073170731707) internal successors, (2187), 1475 states have internal predecessors, (2187), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:06,277 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2187 transitions. [2022-12-13 12:07:06,278 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2187 transitions. [2022-12-13 12:07:06,278 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:07:06,279 INFO L428 stractBuchiCegarLoop]: Abstraction has 1476 states and 2187 transitions. [2022-12-13 12:07:06,279 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 12:07:06,279 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2187 transitions. [2022-12-13 12:07:06,286 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-12-13 12:07:06,286 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:06,286 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:06,288 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:06,289 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:06,289 INFO L748 eck$LassoCheckResult]: Stem: 21168#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 21169#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 22138#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22139#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21611#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 21612#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21482#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21381#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21112#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20762#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20763#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20805#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20806#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21737#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21738#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21782#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21208#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21209#L1090 assume !(0 == ~M_E~0); 21250#L1090-2 assume !(0 == ~T1_E~0); 21251#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21927#L1100-1 assume !(0 == ~T3_E~0); 21928#L1105-1 assume !(0 == ~T4_E~0); 21034#L1110-1 assume !(0 == ~T5_E~0); 21035#L1115-1 assume !(0 == ~T6_E~0); 21417#L1120-1 assume !(0 == ~T7_E~0); 21716#L1125-1 assume !(0 == ~T8_E~0); 22189#L1130-1 assume !(0 == ~T9_E~0); 21949#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21213#L1140-1 assume !(0 == ~T11_E~0); 21214#L1145-1 assume !(0 == ~E_1~0); 21883#L1150-1 assume !(0 == ~E_2~0); 21394#L1155-1 assume !(0 == ~E_3~0); 21395#L1160-1 assume !(0 == ~E_4~0); 21487#L1165-1 assume !(0 == ~E_5~0); 21488#L1170-1 assume !(0 == ~E_6~0); 22122#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 21569#L1180-1 assume !(0 == ~E_8~0); 21570#L1185-1 assume !(0 == ~E_9~0); 21210#L1190-1 assume !(0 == ~E_10~0); 21211#L1195-1 assume !(0 == ~E_11~0); 21585#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21409#L525 assume !(1 == ~m_pc~0); 20847#L525-2 is_master_triggered_~__retres1~0#1 := 0; 20848#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22023#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21996#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21201#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21202#L544 assume 1 == ~t1_pc~0; 21464#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21416#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20826#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20827#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 21058#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21686#L563 assume !(1 == ~t2_pc~0); 21869#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20866#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20867#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21278#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 21279#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21763#L582 assume 1 == ~t3_pc~0; 21002#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21003#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20754#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20755#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 20938#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20939#L601 assume !(1 == ~t4_pc~0); 21895#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 21418#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20955#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20956#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 21890#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22164#L620 assume 1 == ~t5_pc~0; 20894#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20895#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21779#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22028#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 22173#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22174#L639 assume !(1 == ~t6_pc~0); 21714#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 21318#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21319#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21367#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 21424#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21425#L658 assume 1 == ~t7_pc~0; 21715#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21635#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22179#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21831#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 21204#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21205#L677 assume 1 == ~t8_pc~0; 21430#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21017#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21018#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21274#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 21275#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21990#L696 assume !(1 == ~t9_pc~0); 21697#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 21698#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21474#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21475#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21721#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21932#L715 assume 1 == ~t10_pc~0; 21939#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21812#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21623#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21624#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 21563#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21011#L734 assume !(1 == ~t11_pc~0); 21012#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 21489#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21572#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20752#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 20753#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21780#L1213 assume !(1 == ~M_E~0); 21560#L1213-2 assume !(1 == ~T1_E~0); 21561#L1218-1 assume !(1 == ~T2_E~0); 20783#L1223-1 assume !(1 == ~T3_E~0); 20784#L1228-1 assume !(1 == ~T4_E~0); 21536#L1233-1 assume !(1 == ~T5_E~0); 22175#L1238-1 assume !(1 == ~T6_E~0); 21888#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21889#L1248-1 assume !(1 == ~T8_E~0); 21935#L1253-1 assume !(1 == ~T9_E~0); 21936#L1258-1 assume !(1 == ~T10_E~0); 21912#L1263-1 assume !(1 == ~T11_E~0); 21913#L1268-1 assume !(1 == ~E_1~0); 21734#L1273-1 assume !(1 == ~E_2~0); 21735#L1278-1 assume !(1 == ~E_3~0); 21314#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 21315#L1288-1 assume !(1 == ~E_5~0); 22034#L1293-1 assume !(1 == ~E_6~0); 21994#L1298-1 assume !(1 == ~E_7~0); 21767#L1303-1 assume !(1 == ~E_8~0); 21324#L1308-1 assume !(1 == ~E_9~0); 21217#L1313-1 assume !(1 == ~E_10~0); 21218#L1318-1 assume !(1 == ~E_11~0); 21225#L1323-1 assume { :end_inline_reset_delta_events } true; 21226#L1644-2 [2022-12-13 12:07:06,289 INFO L750 eck$LassoCheckResult]: Loop: 21226#L1644-2 assume !false; 21828#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21829#L1065 assume !false; 21903#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 22171#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 20862#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 21439#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21329#L906 assume !(0 != eval_~tmp~0#1); 21331#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21646#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21647#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22049#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22106#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22071#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22072#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21107#L1110-3 assume !(0 == ~T5_E~0); 21108#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21382#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21383#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21887#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22146#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21304#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20815#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20816#L1150-3 assume !(0 == ~E_2~0); 20941#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20942#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21287#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21288#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21679#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21203#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20967#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 20968#L1190-3 assume !(0 == ~E_10~0); 22133#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22134#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21518#L525-36 assume 1 == ~m_pc~0; 21520#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 21067#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21068#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21339#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21340#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21253#L544-36 assume 1 == ~t1_pc~0; 21254#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21801#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21802#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22140#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22121#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22024#L563-36 assume 1 == ~t2_pc~0; 21056#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20813#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20814#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22005#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21534#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21535#L582-36 assume 1 == ~t3_pc~0; 21371#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21372#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21465#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21466#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21571#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21512#L601-36 assume 1 == ~t4_pc~0; 21402#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21403#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21663#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21664#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22110#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22011#L620-36 assume !(1 == ~t5_pc~0); 21457#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 21456#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21874#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21429#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21076#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20858#L639-36 assume 1 == ~t6_pc~0; 20859#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20899#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20900#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21127#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21128#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21719#L658-36 assume 1 == ~t7_pc~0; 20977#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20872#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22096#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20849#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 20850#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21861#L677-36 assume 1 == ~t8_pc~0; 22038#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21639#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21764#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21765#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21665#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21666#L696-36 assume 1 == ~t9_pc~0; 21557#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21559#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21497#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21498#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21680#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21681#L715-36 assume !(1 == ~t10_pc~0); 21645#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 20750#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20751#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20728#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20729#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21113#L734-36 assume !(1 == ~t11_pc~0); 20824#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 20825#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21136#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20744#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20745#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21743#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21388#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21389#L1218-3 assume !(1 == ~T2_E~0); 21165#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21166#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21343#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21344#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21608#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21609#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22109#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22111#L1258-3 assume !(1 == ~T10_E~0); 21148#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21149#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22084#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22099#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22100#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21485#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21486#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21336#L1298-3 assume !(1 == ~E_7~0); 21337#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21824#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21334#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 21335#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21150#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 21151#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 21091#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 21316#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 21317#L1663 assume !(0 == start_simulation_~tmp~3#1); 20985#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 21717#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 20936#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 20819#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 20820#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20879#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21207#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 21667#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 21226#L1644-2 [2022-12-13 12:07:06,290 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:06,290 INFO L85 PathProgramCache]: Analyzing trace with hash 1380686246, now seen corresponding path program 1 times [2022-12-13 12:07:06,290 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:06,290 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1811322166] [2022-12-13 12:07:06,291 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:06,291 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:06,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:06,346 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:06,347 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:06,347 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1811322166] [2022-12-13 12:07:06,347 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1811322166] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:06,347 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:06,347 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:06,347 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [753577409] [2022-12-13 12:07:06,348 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:06,348 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:07:06,348 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:06,348 INFO L85 PathProgramCache]: Analyzing trace with hash -1894119762, now seen corresponding path program 1 times [2022-12-13 12:07:06,349 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:06,349 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1649082822] [2022-12-13 12:07:06,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:06,349 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:06,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:06,419 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:06,419 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:06,419 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1649082822] [2022-12-13 12:07:06,420 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1649082822] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:06,420 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:06,420 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:06,420 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1340858666] [2022-12-13 12:07:06,420 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:06,420 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:07:06,420 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:07:06,421 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:07:06,421 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:07:06,421 INFO L87 Difference]: Start difference. First operand 1476 states and 2187 transitions. cyclomatic complexity: 712 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:06,448 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:07:06,449 INFO L93 Difference]: Finished difference Result 1476 states and 2186 transitions. [2022-12-13 12:07:06,449 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2186 transitions. [2022-12-13 12:07:06,455 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-12-13 12:07:06,461 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2186 transitions. [2022-12-13 12:07:06,461 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2022-12-13 12:07:06,462 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2022-12-13 12:07:06,463 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2186 transitions. [2022-12-13 12:07:06,465 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:07:06,465 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2186 transitions. [2022-12-13 12:07:06,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2186 transitions. [2022-12-13 12:07:06,483 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2022-12-13 12:07:06,485 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.481029810298103) internal successors, (2186), 1475 states have internal predecessors, (2186), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:06,489 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2186 transitions. [2022-12-13 12:07:06,489 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2186 transitions. [2022-12-13 12:07:06,490 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:07:06,490 INFO L428 stractBuchiCegarLoop]: Abstraction has 1476 states and 2186 transitions. [2022-12-13 12:07:06,490 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 12:07:06,490 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2186 transitions. [2022-12-13 12:07:06,496 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-12-13 12:07:06,496 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:06,496 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:06,498 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:06,498 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:06,498 INFO L748 eck$LassoCheckResult]: Stem: 24127#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 24128#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 25098#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25099#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24570#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 24571#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24441#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24340#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24071#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23721#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23722#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23764#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 23765#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24700#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24701#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24748#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24167#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24168#L1090 assume !(0 == ~M_E~0); 24213#L1090-2 assume !(0 == ~T1_E~0); 24214#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24887#L1100-1 assume !(0 == ~T3_E~0); 24888#L1105-1 assume !(0 == ~T4_E~0); 23994#L1110-1 assume !(0 == ~T5_E~0); 23995#L1115-1 assume !(0 == ~T6_E~0); 24379#L1120-1 assume !(0 == ~T7_E~0); 24675#L1125-1 assume !(0 == ~T8_E~0); 25148#L1130-1 assume !(0 == ~T9_E~0); 24908#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24172#L1140-1 assume !(0 == ~T11_E~0); 24173#L1145-1 assume !(0 == ~E_1~0); 24842#L1150-1 assume !(0 == ~E_2~0); 24353#L1155-1 assume !(0 == ~E_3~0); 24354#L1160-1 assume !(0 == ~E_4~0); 24446#L1165-1 assume !(0 == ~E_5~0); 24447#L1170-1 assume !(0 == ~E_6~0); 25081#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 24528#L1180-1 assume !(0 == ~E_8~0); 24529#L1185-1 assume !(0 == ~E_9~0); 24169#L1190-1 assume !(0 == ~E_10~0); 24170#L1195-1 assume !(0 == ~E_11~0); 24544#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24373#L525 assume !(1 == ~m_pc~0); 23806#L525-2 is_master_triggered_~__retres1~0#1 := 0; 23807#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24982#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24957#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24160#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24161#L544 assume 1 == ~t1_pc~0; 24423#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24375#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23785#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23786#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 24017#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24645#L563 assume !(1 == ~t2_pc~0); 24830#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23825#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23826#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24240#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 24241#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24722#L582 assume 1 == ~t3_pc~0; 23963#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23964#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23713#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23714#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 23897#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23898#L601 assume !(1 == ~t4_pc~0); 24854#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24380#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23914#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23915#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 24849#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25123#L620 assume 1 == ~t5_pc~0; 23857#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23858#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24738#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24988#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 25132#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25133#L639 assume !(1 == ~t6_pc~0); 24673#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24277#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24278#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24326#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 24385#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24386#L658 assume 1 == ~t7_pc~0; 24674#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24595#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25138#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24791#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 24163#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24164#L677 assume 1 == ~t8_pc~0; 24391#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 23979#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23980#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24233#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 24234#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24949#L696 assume !(1 == ~t9_pc~0); 24659#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 24660#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24433#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24434#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24682#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24892#L715 assume 1 == ~t10_pc~0; 24898#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24771#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24582#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24583#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 24522#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23970#L734 assume !(1 == ~t11_pc~0); 23971#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 24448#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24533#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23711#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 23712#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24739#L1213 assume !(1 == ~M_E~0); 24520#L1213-2 assume !(1 == ~T1_E~0); 24521#L1218-1 assume !(1 == ~T2_E~0); 23742#L1223-1 assume !(1 == ~T3_E~0); 23743#L1228-1 assume !(1 == ~T4_E~0); 24495#L1233-1 assume !(1 == ~T5_E~0); 25134#L1238-1 assume !(1 == ~T6_E~0); 24847#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24848#L1248-1 assume !(1 == ~T8_E~0); 24894#L1253-1 assume !(1 == ~T9_E~0); 24895#L1258-1 assume !(1 == ~T10_E~0); 24871#L1263-1 assume !(1 == ~T11_E~0); 24872#L1268-1 assume !(1 == ~E_1~0); 24693#L1273-1 assume !(1 == ~E_2~0); 24694#L1278-1 assume !(1 == ~E_3~0); 24273#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 24274#L1288-1 assume !(1 == ~E_5~0); 24993#L1293-1 assume !(1 == ~E_6~0); 24953#L1298-1 assume !(1 == ~E_7~0); 24726#L1303-1 assume !(1 == ~E_8~0); 24283#L1308-1 assume !(1 == ~E_9~0); 24176#L1313-1 assume !(1 == ~E_10~0); 24177#L1318-1 assume !(1 == ~E_11~0); 24187#L1323-1 assume { :end_inline_reset_delta_events } true; 24188#L1644-2 [2022-12-13 12:07:06,499 INFO L750 eck$LassoCheckResult]: Loop: 24188#L1644-2 assume !false; 24787#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24788#L1065 assume !false; 24862#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 25130#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 23821#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 24398#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24288#L906 assume !(0 != eval_~tmp~0#1); 24290#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24605#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24606#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25008#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25065#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25030#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25031#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24066#L1110-3 assume !(0 == ~T5_E~0); 24067#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24341#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24342#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24846#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25105#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24263#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 23774#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23775#L1150-3 assume !(0 == ~E_2~0); 23899#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23900#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24246#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 24247#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24638#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24162#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23926#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 23927#L1190-3 assume !(0 == ~E_10~0); 25092#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25093#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24474#L525-36 assume !(1 == ~m_pc~0); 24475#L525-38 is_master_triggered_~__retres1~0#1 := 0; 24026#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24027#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24298#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24299#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24210#L544-36 assume 1 == ~t1_pc~0; 24211#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24760#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24761#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25097#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25079#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24983#L563-36 assume !(1 == ~t2_pc~0); 24016#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 23772#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23773#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24964#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24493#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24494#L582-36 assume 1 == ~t3_pc~0; 24330#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24331#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24424#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24425#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24530#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24471#L601-36 assume 1 == ~t4_pc~0; 24361#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24362#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24622#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24623#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25069#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24970#L620-36 assume 1 == ~t5_pc~0; 24410#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24411#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24831#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24388#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 24035#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23817#L639-36 assume 1 == ~t6_pc~0; 23818#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23855#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23856#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24085#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 24086#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24678#L658-36 assume 1 == ~t7_pc~0; 23936#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23831#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25055#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23808#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 23809#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24820#L677-36 assume 1 == ~t8_pc~0; 24997#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24598#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24723#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24724#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24624#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24625#L696-36 assume 1 == ~t9_pc~0; 24516#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24518#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24459#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24460#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24639#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24640#L715-36 assume !(1 == ~t10_pc~0); 24604#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 23709#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23710#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23687#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23688#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24075#L734-36 assume !(1 == ~t11_pc~0); 23783#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 23784#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24095#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23703#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 23704#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24702#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24347#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24348#L1218-3 assume !(1 == ~T2_E~0); 24124#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24125#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24302#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24303#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24567#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24568#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25068#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25070#L1258-3 assume !(1 == ~T10_E~0); 24107#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 24108#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25043#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25058#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25060#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24444#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24445#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24296#L1298-3 assume !(1 == ~E_7~0); 24297#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24783#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24293#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24294#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24109#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 24110#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 24050#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 24275#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 24276#L1663 assume !(0 == start_simulation_~tmp~3#1); 23951#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 24676#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 23895#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 23778#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 23779#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23841#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24166#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 24626#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 24188#L1644-2 [2022-12-13 12:07:06,499 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:06,499 INFO L85 PathProgramCache]: Analyzing trace with hash 1810344552, now seen corresponding path program 1 times [2022-12-13 12:07:06,499 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:06,499 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1820827606] [2022-12-13 12:07:06,499 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:06,500 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:06,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:06,538 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:06,538 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:06,538 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1820827606] [2022-12-13 12:07:06,538 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1820827606] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:06,538 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:06,538 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:06,538 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1645673675] [2022-12-13 12:07:06,539 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:06,539 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:07:06,539 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:06,539 INFO L85 PathProgramCache]: Analyzing trace with hash -708129011, now seen corresponding path program 1 times [2022-12-13 12:07:06,539 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:06,539 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1614220961] [2022-12-13 12:07:06,539 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:06,539 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:06,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:06,576 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:06,576 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:06,576 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1614220961] [2022-12-13 12:07:06,576 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1614220961] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:06,576 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:06,576 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:06,576 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1950996057] [2022-12-13 12:07:06,576 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:06,576 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:07:06,577 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:07:06,577 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:07:06,577 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:07:06,577 INFO L87 Difference]: Start difference. First operand 1476 states and 2186 transitions. cyclomatic complexity: 711 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:06,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:07:06,608 INFO L93 Difference]: Finished difference Result 1476 states and 2185 transitions. [2022-12-13 12:07:06,608 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2185 transitions. [2022-12-13 12:07:06,613 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-12-13 12:07:06,616 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2185 transitions. [2022-12-13 12:07:06,616 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2022-12-13 12:07:06,617 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2022-12-13 12:07:06,617 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2185 transitions. [2022-12-13 12:07:06,618 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:07:06,618 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2185 transitions. [2022-12-13 12:07:06,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2185 transitions. [2022-12-13 12:07:06,629 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2022-12-13 12:07:06,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4803523035230353) internal successors, (2185), 1475 states have internal predecessors, (2185), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:06,633 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2185 transitions. [2022-12-13 12:07:06,633 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2185 transitions. [2022-12-13 12:07:06,634 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:07:06,634 INFO L428 stractBuchiCegarLoop]: Abstraction has 1476 states and 2185 transitions. [2022-12-13 12:07:06,634 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 12:07:06,634 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2185 transitions. [2022-12-13 12:07:06,638 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-12-13 12:07:06,638 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:06,638 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:06,639 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:06,639 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:06,639 INFO L748 eck$LassoCheckResult]: Stem: 27086#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 27087#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 28056#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28057#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27529#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 27530#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27400#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27299#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27030#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26680#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26681#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26723#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26724#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 27655#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27656#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 27700#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 27126#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27127#L1090 assume !(0 == ~M_E~0); 27168#L1090-2 assume !(0 == ~T1_E~0); 27169#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27845#L1100-1 assume !(0 == ~T3_E~0); 27846#L1105-1 assume !(0 == ~T4_E~0); 26952#L1110-1 assume !(0 == ~T5_E~0); 26953#L1115-1 assume !(0 == ~T6_E~0); 27335#L1120-1 assume !(0 == ~T7_E~0); 27634#L1125-1 assume !(0 == ~T8_E~0); 28107#L1130-1 assume !(0 == ~T9_E~0); 27867#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 27131#L1140-1 assume !(0 == ~T11_E~0); 27132#L1145-1 assume !(0 == ~E_1~0); 27801#L1150-1 assume !(0 == ~E_2~0); 27312#L1155-1 assume !(0 == ~E_3~0); 27313#L1160-1 assume !(0 == ~E_4~0); 27405#L1165-1 assume !(0 == ~E_5~0); 27406#L1170-1 assume !(0 == ~E_6~0); 28040#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 27487#L1180-1 assume !(0 == ~E_8~0); 27488#L1185-1 assume !(0 == ~E_9~0); 27128#L1190-1 assume !(0 == ~E_10~0); 27129#L1195-1 assume !(0 == ~E_11~0); 27503#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27327#L525 assume !(1 == ~m_pc~0); 26765#L525-2 is_master_triggered_~__retres1~0#1 := 0; 26766#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27941#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27914#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27119#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27120#L544 assume 1 == ~t1_pc~0; 27382#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27334#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26739#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26740#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 26976#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27604#L563 assume !(1 == ~t2_pc~0); 27787#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26784#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26785#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27196#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 27197#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27681#L582 assume 1 == ~t3_pc~0; 26920#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26921#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26672#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26673#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 26856#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26857#L601 assume !(1 == ~t4_pc~0); 27813#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 27336#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26869#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26870#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 27808#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28082#L620 assume 1 == ~t5_pc~0; 26812#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26813#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27697#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27946#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 28091#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28092#L639 assume !(1 == ~t6_pc~0); 27632#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27234#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27235#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27285#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 27342#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27343#L658 assume 1 == ~t7_pc~0; 27633#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27553#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28097#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27749#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 27122#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27123#L677 assume 1 == ~t8_pc~0; 27348#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26935#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26936#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27192#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 27193#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27908#L696 assume !(1 == ~t9_pc~0); 27615#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 27616#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27392#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27393#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 27639#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27850#L715 assume 1 == ~t10_pc~0; 27857#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 27730#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 27541#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27542#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 27481#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26929#L734 assume !(1 == ~t11_pc~0); 26930#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 27407#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27490#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26668#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 26669#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27698#L1213 assume !(1 == ~M_E~0); 27478#L1213-2 assume !(1 == ~T1_E~0); 27479#L1218-1 assume !(1 == ~T2_E~0); 26701#L1223-1 assume !(1 == ~T3_E~0); 26702#L1228-1 assume !(1 == ~T4_E~0); 27454#L1233-1 assume !(1 == ~T5_E~0); 28093#L1238-1 assume !(1 == ~T6_E~0); 27806#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27807#L1248-1 assume !(1 == ~T8_E~0); 27853#L1253-1 assume !(1 == ~T9_E~0); 27854#L1258-1 assume !(1 == ~T10_E~0); 27830#L1263-1 assume !(1 == ~T11_E~0); 27831#L1268-1 assume !(1 == ~E_1~0); 27652#L1273-1 assume !(1 == ~E_2~0); 27653#L1278-1 assume !(1 == ~E_3~0); 27232#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 27233#L1288-1 assume !(1 == ~E_5~0); 27952#L1293-1 assume !(1 == ~E_6~0); 27912#L1298-1 assume !(1 == ~E_7~0); 27685#L1303-1 assume !(1 == ~E_8~0); 27242#L1308-1 assume !(1 == ~E_9~0); 27135#L1313-1 assume !(1 == ~E_10~0); 27136#L1318-1 assume !(1 == ~E_11~0); 27143#L1323-1 assume { :end_inline_reset_delta_events } true; 27144#L1644-2 [2022-12-13 12:07:06,639 INFO L750 eck$LassoCheckResult]: Loop: 27144#L1644-2 assume !false; 27746#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27747#L1065 assume !false; 27821#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 28089#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 26780#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 27357#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 27247#L906 assume !(0 != eval_~tmp~0#1); 27249#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27563#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27564#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 27967#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28024#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27989#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 27990#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27025#L1110-3 assume !(0 == ~T5_E~0); 27026#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27300#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27301#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 27805#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28064#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 27222#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 26733#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26734#L1150-3 assume !(0 == ~E_2~0); 26858#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26859#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 27205#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 27206#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 27597#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 27121#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26885#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26886#L1190-3 assume !(0 == ~E_10~0); 28051#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28052#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27436#L525-36 assume !(1 == ~m_pc~0); 27437#L525-38 is_master_triggered_~__retres1~0#1 := 0; 26985#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26986#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27257#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27258#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27171#L544-36 assume 1 == ~t1_pc~0; 27172#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27719#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27720#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28058#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28038#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27942#L563-36 assume 1 == ~t2_pc~0; 26974#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26731#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26732#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27923#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27452#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27453#L582-36 assume 1 == ~t3_pc~0; 27289#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27290#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27383#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27384#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27489#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27430#L601-36 assume 1 == ~t4_pc~0; 27320#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27321#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27581#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27582#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28028#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27929#L620-36 assume 1 == ~t5_pc~0; 27371#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27372#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27790#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27347#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26994#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26776#L639-36 assume 1 == ~t6_pc~0; 26777#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26817#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26818#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27045#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27046#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27637#L658-36 assume !(1 == ~t7_pc~0); 26789#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 26790#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28014#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26767#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 26768#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27779#L677-36 assume 1 == ~t8_pc~0; 27956#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27557#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27682#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27683#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27583#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27584#L696-36 assume 1 == ~t9_pc~0; 27475#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27477#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27418#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27419#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 27598#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27599#L715-36 assume 1 == ~t10_pc~0; 27741#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 26670#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26671#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26646#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26647#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27034#L734-36 assume !(1 == ~t11_pc~0); 26744#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 26745#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27054#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26662#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 26663#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27661#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 27308#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27309#L1218-3 assume !(1 == ~T2_E~0); 27083#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27084#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27261#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27262#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27526#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27527#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28027#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28030#L1258-3 assume !(1 == ~T10_E~0); 27066#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 27067#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28002#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28017#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28019#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27403#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27404#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27255#L1298-3 assume !(1 == ~E_7~0); 27256#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27742#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 27252#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 27253#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 27068#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 27069#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 27009#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 27236#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 27237#L1663 assume !(0 == start_simulation_~tmp~3#1); 26903#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 27635#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 26854#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 26737#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 26738#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26800#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27125#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 27585#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 27144#L1644-2 [2022-12-13 12:07:06,640 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:06,640 INFO L85 PathProgramCache]: Analyzing trace with hash -1778026138, now seen corresponding path program 1 times [2022-12-13 12:07:06,640 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:06,640 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [52279275] [2022-12-13 12:07:06,640 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:06,640 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:06,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:06,668 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:06,668 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:06,669 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [52279275] [2022-12-13 12:07:06,669 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [52279275] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:06,669 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:06,669 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:06,669 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1231731103] [2022-12-13 12:07:06,669 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:06,669 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:07:06,669 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:06,669 INFO L85 PathProgramCache]: Analyzing trace with hash 620432558, now seen corresponding path program 1 times [2022-12-13 12:07:06,670 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:06,670 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [264902049] [2022-12-13 12:07:06,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:06,670 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:06,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:06,705 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:06,706 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:06,706 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [264902049] [2022-12-13 12:07:06,706 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [264902049] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:06,706 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:06,706 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:06,706 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [86460558] [2022-12-13 12:07:06,706 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:06,706 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:07:06,706 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:07:06,706 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:07:06,707 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:07:06,707 INFO L87 Difference]: Start difference. First operand 1476 states and 2185 transitions. cyclomatic complexity: 710 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:06,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:07:06,724 INFO L93 Difference]: Finished difference Result 1476 states and 2184 transitions. [2022-12-13 12:07:06,724 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2184 transitions. [2022-12-13 12:07:06,728 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-12-13 12:07:06,732 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2184 transitions. [2022-12-13 12:07:06,732 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2022-12-13 12:07:06,733 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2022-12-13 12:07:06,733 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2184 transitions. [2022-12-13 12:07:06,734 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:07:06,734 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2184 transitions. [2022-12-13 12:07:06,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2184 transitions. [2022-12-13 12:07:06,745 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2022-12-13 12:07:06,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4796747967479675) internal successors, (2184), 1475 states have internal predecessors, (2184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:06,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2184 transitions. [2022-12-13 12:07:06,749 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2184 transitions. [2022-12-13 12:07:06,750 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:07:06,750 INFO L428 stractBuchiCegarLoop]: Abstraction has 1476 states and 2184 transitions. [2022-12-13 12:07:06,750 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 12:07:06,750 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2184 transitions. [2022-12-13 12:07:06,753 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-12-13 12:07:06,753 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:06,753 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:06,754 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:06,755 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:06,755 INFO L748 eck$LassoCheckResult]: Stem: 30045#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 30046#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 31016#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31017#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30488#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 30489#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30359#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30258#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29989#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29639#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29640#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29682#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29683#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 30614#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 30615#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 30659#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 30085#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30086#L1090 assume !(0 == ~M_E~0); 30130#L1090-2 assume !(0 == ~T1_E~0); 30131#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30805#L1100-1 assume !(0 == ~T3_E~0); 30806#L1105-1 assume !(0 == ~T4_E~0); 29912#L1110-1 assume !(0 == ~T5_E~0); 29913#L1115-1 assume !(0 == ~T6_E~0); 30294#L1120-1 assume !(0 == ~T7_E~0); 30593#L1125-1 assume !(0 == ~T8_E~0); 31066#L1130-1 assume !(0 == ~T9_E~0); 30826#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30090#L1140-1 assume !(0 == ~T11_E~0); 30091#L1145-1 assume !(0 == ~E_1~0); 30760#L1150-1 assume !(0 == ~E_2~0); 30271#L1155-1 assume !(0 == ~E_3~0); 30272#L1160-1 assume !(0 == ~E_4~0); 30364#L1165-1 assume !(0 == ~E_5~0); 30365#L1170-1 assume !(0 == ~E_6~0); 30999#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 30446#L1180-1 assume !(0 == ~E_8~0); 30447#L1185-1 assume !(0 == ~E_9~0); 30087#L1190-1 assume !(0 == ~E_10~0); 30088#L1195-1 assume !(0 == ~E_11~0); 30462#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30291#L525 assume !(1 == ~m_pc~0); 29724#L525-2 is_master_triggered_~__retres1~0#1 := 0; 29725#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30900#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30875#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30078#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30079#L544 assume 1 == ~t1_pc~0; 30341#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30293#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29703#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29704#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 29935#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30563#L563 assume !(1 == ~t2_pc~0); 30746#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 29743#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29744#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30158#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 30159#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30640#L582 assume 1 == ~t3_pc~0; 29881#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29882#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29631#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29632#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 29815#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29816#L601 assume !(1 == ~t4_pc~0); 30772#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 30295#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29832#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29833#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 30767#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31041#L620 assume 1 == ~t5_pc~0; 29775#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29776#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30656#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30906#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 31050#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31051#L639 assume !(1 == ~t6_pc~0); 30591#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 30195#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30196#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30244#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 30301#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30302#L658 assume 1 == ~t7_pc~0; 30592#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30513#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31056#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30709#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 30081#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30082#L677 assume 1 == ~t8_pc~0; 30309#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29894#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29895#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30151#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 30152#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30867#L696 assume !(1 == ~t9_pc~0); 30576#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 30577#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30351#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30352#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30598#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30809#L715 assume 1 == ~t10_pc~0; 30816#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30689#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30500#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30501#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 30440#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29888#L734 assume !(1 == ~t11_pc~0); 29889#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 30366#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30451#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29629#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 29630#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30657#L1213 assume !(1 == ~M_E~0); 30438#L1213-2 assume !(1 == ~T1_E~0); 30439#L1218-1 assume !(1 == ~T2_E~0); 29660#L1223-1 assume !(1 == ~T3_E~0); 29661#L1228-1 assume !(1 == ~T4_E~0); 30413#L1233-1 assume !(1 == ~T5_E~0); 31052#L1238-1 assume !(1 == ~T6_E~0); 30765#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30766#L1248-1 assume !(1 == ~T8_E~0); 30812#L1253-1 assume !(1 == ~T9_E~0); 30813#L1258-1 assume !(1 == ~T10_E~0); 30789#L1263-1 assume !(1 == ~T11_E~0); 30790#L1268-1 assume !(1 == ~E_1~0); 30611#L1273-1 assume !(1 == ~E_2~0); 30612#L1278-1 assume !(1 == ~E_3~0); 30191#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 30192#L1288-1 assume !(1 == ~E_5~0); 30911#L1293-1 assume !(1 == ~E_6~0); 30871#L1298-1 assume !(1 == ~E_7~0); 30644#L1303-1 assume !(1 == ~E_8~0); 30201#L1308-1 assume !(1 == ~E_9~0); 30094#L1313-1 assume !(1 == ~E_10~0); 30095#L1318-1 assume !(1 == ~E_11~0); 30105#L1323-1 assume { :end_inline_reset_delta_events } true; 30106#L1644-2 [2022-12-13 12:07:06,755 INFO L750 eck$LassoCheckResult]: Loop: 30106#L1644-2 assume !false; 30705#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30706#L1065 assume !false; 30780#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 31048#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 29739#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 30316#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30206#L906 assume !(0 != eval_~tmp~0#1); 30208#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30523#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30524#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30926#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30983#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30948#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30949#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29984#L1110-3 assume !(0 == ~T5_E~0); 29985#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30259#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 30260#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 30764#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 31023#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30183#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29694#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29695#L1150-3 assume !(0 == ~E_2~0); 29818#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29819#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30164#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30165#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30556#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30080#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29847#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29848#L1190-3 assume !(0 == ~E_10~0); 31010#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 31011#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30395#L525-36 assume !(1 == ~m_pc~0); 30396#L525-38 is_master_triggered_~__retres1~0#1 := 0; 29949#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29950#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30216#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30217#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30127#L544-36 assume 1 == ~t1_pc~0; 30128#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30678#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30679#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31015#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30997#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30901#L563-36 assume 1 == ~t2_pc~0; 29933#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29690#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29691#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30882#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30411#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30412#L582-36 assume 1 == ~t3_pc~0; 30248#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30249#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30342#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30343#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30448#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30389#L601-36 assume 1 == ~t4_pc~0; 30279#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30280#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30540#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30541#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30987#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30888#L620-36 assume 1 == ~t5_pc~0; 30328#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30329#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30749#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30306#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29953#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29735#L639-36 assume 1 == ~t6_pc~0; 29736#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29773#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29774#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30003#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30004#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30596#L658-36 assume !(1 == ~t7_pc~0); 29748#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 29749#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30973#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29726#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 29727#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30738#L677-36 assume 1 == ~t8_pc~0; 30915#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30516#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30641#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30642#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 30542#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30543#L696-36 assume 1 == ~t9_pc~0; 30434#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30436#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30377#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30378#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30557#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30558#L715-36 assume !(1 == ~t10_pc~0); 30522#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 29627#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29628#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29605#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29606#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29993#L734-36 assume !(1 == ~t11_pc~0); 29701#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 29702#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30013#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29621#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 29622#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30620#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30265#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30266#L1218-3 assume !(1 == ~T2_E~0); 30042#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30043#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30220#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30221#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30485#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30486#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30986#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30988#L1258-3 assume !(1 == ~T10_E~0); 30025#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 30026#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30961#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30976#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30978#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30362#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30363#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30214#L1298-3 assume !(1 == ~E_7~0); 30215#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30701#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 30211#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 30212#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 30027#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 30028#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 29968#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 30193#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 30194#L1663 assume !(0 == start_simulation_~tmp~3#1); 29869#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 30594#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 29813#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 29696#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 29697#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29759#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30084#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 30544#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 30106#L1644-2 [2022-12-13 12:07:06,755 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:06,755 INFO L85 PathProgramCache]: Analyzing trace with hash 1655107556, now seen corresponding path program 1 times [2022-12-13 12:07:06,755 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:06,755 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1925720547] [2022-12-13 12:07:06,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:06,756 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:06,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:06,784 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:06,784 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:06,784 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1925720547] [2022-12-13 12:07:06,784 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1925720547] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:06,784 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:06,784 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:06,784 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [128502709] [2022-12-13 12:07:06,784 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:06,785 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:07:06,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:06,785 INFO L85 PathProgramCache]: Analyzing trace with hash 2053267277, now seen corresponding path program 1 times [2022-12-13 12:07:06,785 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:06,785 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [329300226] [2022-12-13 12:07:06,785 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:06,785 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:06,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:06,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:06,819 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:06,819 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [329300226] [2022-12-13 12:07:06,820 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [329300226] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:06,820 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:06,820 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:06,820 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1669963629] [2022-12-13 12:07:06,820 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:06,820 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:07:06,820 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:07:06,820 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:07:06,820 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:07:06,820 INFO L87 Difference]: Start difference. First operand 1476 states and 2184 transitions. cyclomatic complexity: 709 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:06,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:07:06,857 INFO L93 Difference]: Finished difference Result 1476 states and 2183 transitions. [2022-12-13 12:07:06,857 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2183 transitions. [2022-12-13 12:07:06,864 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-12-13 12:07:06,867 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2183 transitions. [2022-12-13 12:07:06,867 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2022-12-13 12:07:06,868 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2022-12-13 12:07:06,868 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2183 transitions. [2022-12-13 12:07:06,869 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:07:06,869 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2183 transitions. [2022-12-13 12:07:06,871 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2183 transitions. [2022-12-13 12:07:06,881 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2022-12-13 12:07:06,883 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4789972899728998) internal successors, (2183), 1475 states have internal predecessors, (2183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:06,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2183 transitions. [2022-12-13 12:07:06,885 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2183 transitions. [2022-12-13 12:07:06,885 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:07:06,886 INFO L428 stractBuchiCegarLoop]: Abstraction has 1476 states and 2183 transitions. [2022-12-13 12:07:06,886 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 12:07:06,886 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2183 transitions. [2022-12-13 12:07:06,891 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-12-13 12:07:06,891 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:06,891 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:06,893 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:06,893 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:06,894 INFO L748 eck$LassoCheckResult]: Stem: 33004#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 33005#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 33974#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33975#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33447#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 33448#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33318#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33217#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32948#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32598#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 32599#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32641#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32642#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33573#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33574#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 33618#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 33044#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33045#L1090 assume !(0 == ~M_E~0); 33086#L1090-2 assume !(0 == ~T1_E~0); 33087#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33763#L1100-1 assume !(0 == ~T3_E~0); 33764#L1105-1 assume !(0 == ~T4_E~0); 32870#L1110-1 assume !(0 == ~T5_E~0); 32871#L1115-1 assume !(0 == ~T6_E~0); 33253#L1120-1 assume !(0 == ~T7_E~0); 33552#L1125-1 assume !(0 == ~T8_E~0); 34025#L1130-1 assume !(0 == ~T9_E~0); 33785#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33049#L1140-1 assume !(0 == ~T11_E~0); 33050#L1145-1 assume !(0 == ~E_1~0); 33719#L1150-1 assume !(0 == ~E_2~0); 33230#L1155-1 assume !(0 == ~E_3~0); 33231#L1160-1 assume !(0 == ~E_4~0); 33323#L1165-1 assume !(0 == ~E_5~0); 33324#L1170-1 assume !(0 == ~E_6~0); 33958#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 33405#L1180-1 assume !(0 == ~E_8~0); 33406#L1185-1 assume !(0 == ~E_9~0); 33046#L1190-1 assume !(0 == ~E_10~0); 33047#L1195-1 assume !(0 == ~E_11~0); 33421#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33245#L525 assume !(1 == ~m_pc~0); 32683#L525-2 is_master_triggered_~__retres1~0#1 := 0; 32684#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33859#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33832#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33037#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33038#L544 assume 1 == ~t1_pc~0; 33300#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33252#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32657#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 32658#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 32894#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33522#L563 assume !(1 == ~t2_pc~0); 33705#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 32702#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32703#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33114#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 33115#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33599#L582 assume 1 == ~t3_pc~0; 32838#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 32839#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32590#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32591#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 32774#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32775#L601 assume !(1 == ~t4_pc~0); 33731#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 33254#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32787#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32788#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 33726#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34000#L620 assume 1 == ~t5_pc~0; 32730#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32731#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33615#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33864#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 34009#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34010#L639 assume !(1 == ~t6_pc~0); 33550#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 33152#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33153#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33203#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 33260#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33261#L658 assume 1 == ~t7_pc~0; 33551#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33471#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34015#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33667#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 33040#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33041#L677 assume 1 == ~t8_pc~0; 33266#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32853#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32854#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33110#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 33111#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33826#L696 assume !(1 == ~t9_pc~0); 33533#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 33534#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33310#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33311#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33557#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33768#L715 assume 1 == ~t10_pc~0; 33775#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 33648#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33459#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33460#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 33399#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32847#L734 assume !(1 == ~t11_pc~0); 32848#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 33325#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33408#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32586#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 32587#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33616#L1213 assume !(1 == ~M_E~0); 33396#L1213-2 assume !(1 == ~T1_E~0); 33397#L1218-1 assume !(1 == ~T2_E~0); 32619#L1223-1 assume !(1 == ~T3_E~0); 32620#L1228-1 assume !(1 == ~T4_E~0); 33372#L1233-1 assume !(1 == ~T5_E~0); 34011#L1238-1 assume !(1 == ~T6_E~0); 33724#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33725#L1248-1 assume !(1 == ~T8_E~0); 33771#L1253-1 assume !(1 == ~T9_E~0); 33772#L1258-1 assume !(1 == ~T10_E~0); 33748#L1263-1 assume !(1 == ~T11_E~0); 33749#L1268-1 assume !(1 == ~E_1~0); 33570#L1273-1 assume !(1 == ~E_2~0); 33571#L1278-1 assume !(1 == ~E_3~0); 33150#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 33151#L1288-1 assume !(1 == ~E_5~0); 33870#L1293-1 assume !(1 == ~E_6~0); 33830#L1298-1 assume !(1 == ~E_7~0); 33603#L1303-1 assume !(1 == ~E_8~0); 33160#L1308-1 assume !(1 == ~E_9~0); 33053#L1313-1 assume !(1 == ~E_10~0); 33054#L1318-1 assume !(1 == ~E_11~0); 33061#L1323-1 assume { :end_inline_reset_delta_events } true; 33062#L1644-2 [2022-12-13 12:07:06,894 INFO L750 eck$LassoCheckResult]: Loop: 33062#L1644-2 assume !false; 33664#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33665#L1065 assume !false; 33739#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 34007#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 32698#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 33275#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 33165#L906 assume !(0 != eval_~tmp~0#1); 33167#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33481#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33482#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33885#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33942#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33907#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33908#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32943#L1110-3 assume !(0 == ~T5_E~0); 32944#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 33218#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33219#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33723#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33982#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33140#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32651#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32652#L1150-3 assume !(0 == ~E_2~0); 32776#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32777#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33123#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33124#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33515#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 33039#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 32803#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32804#L1190-3 assume !(0 == ~E_10~0); 33969#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 33970#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33354#L525-36 assume !(1 == ~m_pc~0); 33355#L525-38 is_master_triggered_~__retres1~0#1 := 0; 32903#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32904#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33175#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33176#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33089#L544-36 assume 1 == ~t1_pc~0; 33090#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33637#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33638#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33976#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33956#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33860#L563-36 assume 1 == ~t2_pc~0; 32892#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32649#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32650#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33841#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33370#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33371#L582-36 assume 1 == ~t3_pc~0; 33207#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33208#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33301#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33302#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33407#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33348#L601-36 assume 1 == ~t4_pc~0; 33238#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33239#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33499#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33500#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33946#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33847#L620-36 assume 1 == ~t5_pc~0; 33289#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33290#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33708#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33265#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 32912#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32694#L639-36 assume 1 == ~t6_pc~0; 32695#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32735#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32736#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32963#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32964#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33555#L658-36 assume !(1 == ~t7_pc~0); 32707#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 32708#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33932#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32685#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 32686#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33697#L677-36 assume 1 == ~t8_pc~0; 33874#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33475#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33600#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33601#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33501#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33502#L696-36 assume 1 == ~t9_pc~0; 33393#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33395#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33336#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33337#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33516#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33517#L715-36 assume 1 == ~t10_pc~0; 33659#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 32588#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32589#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32564#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32565#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32952#L734-36 assume !(1 == ~t11_pc~0); 32662#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 32663#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32972#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32580#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32581#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33579#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33226#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33227#L1218-3 assume !(1 == ~T2_E~0); 33001#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33002#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33179#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33180#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33444#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33445#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33945#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 33948#L1258-3 assume !(1 == ~T10_E~0); 32984#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 32985#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33920#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33935#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33937#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33321#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33322#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33173#L1298-3 assume !(1 == ~E_7~0); 33174#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33660#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 33170#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 33171#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 32986#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 32987#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 32927#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 33154#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 33155#L1663 assume !(0 == start_simulation_~tmp~3#1); 32828#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 33553#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 32772#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 32655#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 32656#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32718#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33043#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 33503#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 33062#L1644-2 [2022-12-13 12:07:06,894 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:06,894 INFO L85 PathProgramCache]: Analyzing trace with hash -589450842, now seen corresponding path program 1 times [2022-12-13 12:07:06,895 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:06,895 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [517947072] [2022-12-13 12:07:06,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:06,895 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:06,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:06,948 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:06,948 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:06,949 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [517947072] [2022-12-13 12:07:06,949 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [517947072] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:06,949 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:06,949 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 12:07:06,949 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [257341126] [2022-12-13 12:07:06,949 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:06,949 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:07:06,950 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:06,950 INFO L85 PathProgramCache]: Analyzing trace with hash 620432558, now seen corresponding path program 2 times [2022-12-13 12:07:06,950 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:06,950 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1881712131] [2022-12-13 12:07:06,950 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:06,950 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:06,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:06,993 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:06,994 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:06,994 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1881712131] [2022-12-13 12:07:06,994 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1881712131] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:06,994 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:06,994 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:06,994 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1610820405] [2022-12-13 12:07:06,994 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:06,994 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:07:06,994 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:07:06,995 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:07:06,995 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:07:06,995 INFO L87 Difference]: Start difference. First operand 1476 states and 2183 transitions. cyclomatic complexity: 708 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:07,015 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:07:07,016 INFO L93 Difference]: Finished difference Result 1476 states and 2178 transitions. [2022-12-13 12:07:07,016 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2178 transitions. [2022-12-13 12:07:07,019 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-12-13 12:07:07,023 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2178 transitions. [2022-12-13 12:07:07,023 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2022-12-13 12:07:07,024 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2022-12-13 12:07:07,024 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2178 transitions. [2022-12-13 12:07:07,025 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:07:07,025 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2178 transitions. [2022-12-13 12:07:07,026 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2178 transitions. [2022-12-13 12:07:07,046 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2022-12-13 12:07:07,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.475609756097561) internal successors, (2178), 1475 states have internal predecessors, (2178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:07,050 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2178 transitions. [2022-12-13 12:07:07,051 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2178 transitions. [2022-12-13 12:07:07,051 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:07:07,051 INFO L428 stractBuchiCegarLoop]: Abstraction has 1476 states and 2178 transitions. [2022-12-13 12:07:07,051 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-12-13 12:07:07,051 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2178 transitions. [2022-12-13 12:07:07,055 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-12-13 12:07:07,055 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:07,055 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:07,056 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:07,056 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:07,056 INFO L748 eck$LassoCheckResult]: Stem: 35963#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 35964#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 36933#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 36934#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36406#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 36407#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36277#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36176#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35907#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35557#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35558#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35600#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35601#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36532#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36533#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36577#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 36003#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36004#L1090 assume !(0 == ~M_E~0); 36045#L1090-2 assume !(0 == ~T1_E~0); 36046#L1095-1 assume !(0 == ~T2_E~0); 36723#L1100-1 assume !(0 == ~T3_E~0); 36724#L1105-1 assume !(0 == ~T4_E~0); 35830#L1110-1 assume !(0 == ~T5_E~0); 35831#L1115-1 assume !(0 == ~T6_E~0); 36212#L1120-1 assume !(0 == ~T7_E~0); 36511#L1125-1 assume !(0 == ~T8_E~0); 36984#L1130-1 assume !(0 == ~T9_E~0); 36744#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36008#L1140-1 assume !(0 == ~T11_E~0); 36009#L1145-1 assume !(0 == ~E_1~0); 36678#L1150-1 assume !(0 == ~E_2~0); 36189#L1155-1 assume !(0 == ~E_3~0); 36190#L1160-1 assume !(0 == ~E_4~0); 36282#L1165-1 assume !(0 == ~E_5~0); 36283#L1170-1 assume !(0 == ~E_6~0); 36917#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 36364#L1180-1 assume !(0 == ~E_8~0); 36365#L1185-1 assume !(0 == ~E_9~0); 36005#L1190-1 assume !(0 == ~E_10~0); 36006#L1195-1 assume !(0 == ~E_11~0); 36380#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36209#L525 assume !(1 == ~m_pc~0); 35642#L525-2 is_master_triggered_~__retres1~0#1 := 0; 35643#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36818#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36793#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35996#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35997#L544 assume 1 == ~t1_pc~0; 36259#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36211#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35621#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35622#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 35853#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36481#L563 assume !(1 == ~t2_pc~0); 36664#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 35661#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35662#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36073#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 36074#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36558#L582 assume 1 == ~t3_pc~0; 35799#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 35800#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35549#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35550#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 35733#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35734#L601 assume !(1 == ~t4_pc~0); 36690#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 36213#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35750#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35751#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 36685#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36959#L620 assume 1 == ~t5_pc~0; 35691#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35692#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36574#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36824#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 36968#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36969#L639 assume !(1 == ~t6_pc~0); 36509#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36113#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36114#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36162#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 36219#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36220#L658 assume 1 == ~t7_pc~0; 36510#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36431#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36974#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36627#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 35999#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36000#L677 assume 1 == ~t8_pc~0; 36227#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35812#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35813#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36069#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 36070#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36785#L696 assume !(1 == ~t9_pc~0); 36494#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 36495#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36269#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36270#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36516#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36727#L715 assume 1 == ~t10_pc~0; 36734#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 36607#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36418#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36419#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 36358#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35806#L734 assume !(1 == ~t11_pc~0); 35807#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 36284#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36367#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35547#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 35548#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36575#L1213 assume !(1 == ~M_E~0); 36356#L1213-2 assume !(1 == ~T1_E~0); 36357#L1218-1 assume !(1 == ~T2_E~0); 35578#L1223-1 assume !(1 == ~T3_E~0); 35579#L1228-1 assume !(1 == ~T4_E~0); 36331#L1233-1 assume !(1 == ~T5_E~0); 36970#L1238-1 assume !(1 == ~T6_E~0); 36683#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36684#L1248-1 assume !(1 == ~T8_E~0); 36730#L1253-1 assume !(1 == ~T9_E~0); 36731#L1258-1 assume !(1 == ~T10_E~0); 36707#L1263-1 assume !(1 == ~T11_E~0); 36708#L1268-1 assume !(1 == ~E_1~0); 36529#L1273-1 assume !(1 == ~E_2~0); 36530#L1278-1 assume !(1 == ~E_3~0); 36109#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 36110#L1288-1 assume !(1 == ~E_5~0); 36829#L1293-1 assume !(1 == ~E_6~0); 36789#L1298-1 assume !(1 == ~E_7~0); 36562#L1303-1 assume !(1 == ~E_8~0); 36119#L1308-1 assume !(1 == ~E_9~0); 36012#L1313-1 assume !(1 == ~E_10~0); 36013#L1318-1 assume !(1 == ~E_11~0); 36023#L1323-1 assume { :end_inline_reset_delta_events } true; 36024#L1644-2 [2022-12-13 12:07:07,057 INFO L750 eck$LassoCheckResult]: Loop: 36024#L1644-2 assume !false; 36623#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36624#L1065 assume !false; 36698#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 36966#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 35657#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 36234#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 36124#L906 assume !(0 != eval_~tmp~0#1); 36126#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36441#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36442#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 36844#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36901#L1095-3 assume !(0 == ~T2_E~0); 36866#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36867#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35902#L1110-3 assume !(0 == ~T5_E~0); 35903#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36177#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36178#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36682#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36941#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36101#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 35612#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35613#L1150-3 assume !(0 == ~E_2~0); 35736#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35737#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36082#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36083#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36474#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 35998#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35763#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35764#L1190-3 assume !(0 == ~E_10~0); 36928#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36929#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36313#L525-36 assume !(1 == ~m_pc~0); 36314#L525-38 is_master_triggered_~__retres1~0#1 := 0; 35867#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35868#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36134#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36135#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36048#L544-36 assume 1 == ~t1_pc~0; 36049#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36596#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36597#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 36935#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36916#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36819#L563-36 assume 1 == ~t2_pc~0; 35851#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35608#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35609#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36800#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36329#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36330#L582-36 assume 1 == ~t3_pc~0; 36166#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36167#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36260#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36261#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36366#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36304#L601-36 assume 1 == ~t4_pc~0; 36197#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 36198#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36458#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36459#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36905#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36804#L620-36 assume 1 == ~t5_pc~0; 36246#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36247#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36667#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36224#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 35871#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35653#L639-36 assume 1 == ~t6_pc~0; 35654#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 35689#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35690#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35921#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35922#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36514#L658-36 assume !(1 == ~t7_pc~0); 35666#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 35667#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36891#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35644#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 35645#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36656#L677-36 assume 1 == ~t8_pc~0; 36833#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36434#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36559#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36560#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36460#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36461#L696-36 assume 1 == ~t9_pc~0; 36352#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36354#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36295#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36296#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36475#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36476#L715-36 assume !(1 == ~t10_pc~0); 36440#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 35545#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35546#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35523#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35524#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35911#L734-36 assume !(1 == ~t11_pc~0); 35619#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 35620#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35931#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35539#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35540#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36538#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36183#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36184#L1218-3 assume !(1 == ~T2_E~0); 35960#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35961#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36138#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36139#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36403#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36404#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36904#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36906#L1258-3 assume !(1 == ~T10_E~0); 35943#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35944#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36879#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 36894#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36896#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36280#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36281#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36132#L1298-3 assume !(1 == ~E_7~0); 36133#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36619#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 36129#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 36130#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 35945#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35946#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 35886#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 36111#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 36112#L1663 assume !(0 == start_simulation_~tmp~3#1); 35782#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 36512#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 35731#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 35614#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 35615#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35674#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36002#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 36462#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 36024#L1644-2 [2022-12-13 12:07:07,057 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:07,057 INFO L85 PathProgramCache]: Analyzing trace with hash 1863040740, now seen corresponding path program 1 times [2022-12-13 12:07:07,057 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:07,057 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [144576554] [2022-12-13 12:07:07,057 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:07,057 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:07,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:07,102 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:07,102 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:07,102 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [144576554] [2022-12-13 12:07:07,102 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [144576554] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:07,102 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:07,102 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:07,102 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2124395500] [2022-12-13 12:07:07,102 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:07,103 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:07:07,103 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:07,103 INFO L85 PathProgramCache]: Analyzing trace with hash -1566539893, now seen corresponding path program 1 times [2022-12-13 12:07:07,103 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:07,103 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [377904789] [2022-12-13 12:07:07,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:07,103 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:07,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:07,170 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:07,170 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:07,170 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [377904789] [2022-12-13 12:07:07,170 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [377904789] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:07,170 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:07,170 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:07,170 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1039777146] [2022-12-13 12:07:07,170 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:07,171 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:07:07,171 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:07:07,171 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:07:07,171 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:07:07,171 INFO L87 Difference]: Start difference. First operand 1476 states and 2178 transitions. cyclomatic complexity: 703 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:07,252 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:07:07,252 INFO L93 Difference]: Finished difference Result 2816 states and 4147 transitions. [2022-12-13 12:07:07,252 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2816 states and 4147 transitions. [2022-12-13 12:07:07,260 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2654 [2022-12-13 12:07:07,269 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2816 states to 2816 states and 4147 transitions. [2022-12-13 12:07:07,269 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2816 [2022-12-13 12:07:07,271 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2816 [2022-12-13 12:07:07,271 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2816 states and 4147 transitions. [2022-12-13 12:07:07,273 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:07:07,274 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2816 states and 4147 transitions. [2022-12-13 12:07:07,276 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2816 states and 4147 transitions. [2022-12-13 12:07:07,290 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2816 to 1476. [2022-12-13 12:07:07,292 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4742547425474255) internal successors, (2176), 1475 states have internal predecessors, (2176), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:07,295 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2176 transitions. [2022-12-13 12:07:07,296 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2176 transitions. [2022-12-13 12:07:07,296 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:07:07,296 INFO L428 stractBuchiCegarLoop]: Abstraction has 1476 states and 2176 transitions. [2022-12-13 12:07:07,296 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-12-13 12:07:07,297 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2176 transitions. [2022-12-13 12:07:07,301 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-12-13 12:07:07,301 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:07,301 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:07,302 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:07,302 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:07,303 INFO L748 eck$LassoCheckResult]: Stem: 40265#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 40266#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 41235#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41236#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 40708#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 40709#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40579#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40478#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40209#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39859#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39860#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 39902#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 39903#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 40834#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 40835#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 40879#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 40305#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40306#L1090 assume !(0 == ~M_E~0); 40347#L1090-2 assume !(0 == ~T1_E~0); 40348#L1095-1 assume !(0 == ~T2_E~0); 41024#L1100-1 assume !(0 == ~T3_E~0); 41025#L1105-1 assume !(0 == ~T4_E~0); 40131#L1110-1 assume !(0 == ~T5_E~0); 40132#L1115-1 assume !(0 == ~T6_E~0); 40514#L1120-1 assume !(0 == ~T7_E~0); 40813#L1125-1 assume !(0 == ~T8_E~0); 41286#L1130-1 assume !(0 == ~T9_E~0); 41046#L1135-1 assume !(0 == ~T10_E~0); 40310#L1140-1 assume !(0 == ~T11_E~0); 40311#L1145-1 assume !(0 == ~E_1~0); 40980#L1150-1 assume !(0 == ~E_2~0); 40491#L1155-1 assume !(0 == ~E_3~0); 40492#L1160-1 assume !(0 == ~E_4~0); 40584#L1165-1 assume !(0 == ~E_5~0); 40585#L1170-1 assume !(0 == ~E_6~0); 41219#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 40666#L1180-1 assume !(0 == ~E_8~0); 40667#L1185-1 assume !(0 == ~E_9~0); 40307#L1190-1 assume !(0 == ~E_10~0); 40308#L1195-1 assume !(0 == ~E_11~0); 40682#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40506#L525 assume !(1 == ~m_pc~0); 39944#L525-2 is_master_triggered_~__retres1~0#1 := 0; 39945#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41120#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 41093#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40298#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40299#L544 assume 1 == ~t1_pc~0; 40561#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40513#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39918#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39919#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 40155#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40783#L563 assume !(1 == ~t2_pc~0); 40966#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 39963#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39964#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40375#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 40376#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40860#L582 assume 1 == ~t3_pc~0; 40099#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40100#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39851#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39852#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 40035#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40036#L601 assume !(1 == ~t4_pc~0); 40992#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 40515#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40048#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40049#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 40987#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41261#L620 assume 1 == ~t5_pc~0; 39991#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39992#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40876#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41125#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 41270#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41271#L639 assume !(1 == ~t6_pc~0); 40811#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 40413#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40414#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40464#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 40521#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40522#L658 assume 1 == ~t7_pc~0; 40812#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 40732#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41276#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40928#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 40301#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40302#L677 assume 1 == ~t8_pc~0; 40527#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40114#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40115#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40371#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 40372#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41087#L696 assume !(1 == ~t9_pc~0); 40794#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 40795#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40571#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40572#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 40818#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41029#L715 assume 1 == ~t10_pc~0; 41036#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 40909#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40720#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40721#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 40660#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40108#L734 assume !(1 == ~t11_pc~0); 40109#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 40586#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40669#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39847#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 39848#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40877#L1213 assume !(1 == ~M_E~0); 40657#L1213-2 assume !(1 == ~T1_E~0); 40658#L1218-1 assume !(1 == ~T2_E~0); 39880#L1223-1 assume !(1 == ~T3_E~0); 39881#L1228-1 assume !(1 == ~T4_E~0); 40633#L1233-1 assume !(1 == ~T5_E~0); 41272#L1238-1 assume !(1 == ~T6_E~0); 40985#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 40986#L1248-1 assume !(1 == ~T8_E~0); 41032#L1253-1 assume !(1 == ~T9_E~0); 41033#L1258-1 assume !(1 == ~T10_E~0); 41009#L1263-1 assume !(1 == ~T11_E~0); 41010#L1268-1 assume !(1 == ~E_1~0); 40831#L1273-1 assume !(1 == ~E_2~0); 40832#L1278-1 assume !(1 == ~E_3~0); 40411#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 40412#L1288-1 assume !(1 == ~E_5~0); 41131#L1293-1 assume !(1 == ~E_6~0); 41091#L1298-1 assume !(1 == ~E_7~0); 40864#L1303-1 assume !(1 == ~E_8~0); 40421#L1308-1 assume !(1 == ~E_9~0); 40314#L1313-1 assume !(1 == ~E_10~0); 40315#L1318-1 assume !(1 == ~E_11~0); 40322#L1323-1 assume { :end_inline_reset_delta_events } true; 40323#L1644-2 [2022-12-13 12:07:07,303 INFO L750 eck$LassoCheckResult]: Loop: 40323#L1644-2 assume !false; 40925#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40926#L1065 assume !false; 41000#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41268#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 39959#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 40536#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 40426#L906 assume !(0 != eval_~tmp~0#1); 40428#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40742#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40743#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 41146#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41203#L1095-3 assume !(0 == ~T2_E~0); 41168#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41169#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40204#L1110-3 assume !(0 == ~T5_E~0); 40205#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40479#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40480#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40984#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41243#L1135-3 assume !(0 == ~T10_E~0); 40401#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 39912#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 39913#L1150-3 assume !(0 == ~E_2~0); 40037#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40038#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40384#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40385#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 40776#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40300#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 40064#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 40065#L1190-3 assume !(0 == ~E_10~0); 41230#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 41231#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40615#L525-36 assume !(1 == ~m_pc~0); 40616#L525-38 is_master_triggered_~__retres1~0#1 := 0; 40164#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40165#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 40436#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40437#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40350#L544-36 assume !(1 == ~t1_pc~0); 40352#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 40898#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40899#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41237#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41217#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41121#L563-36 assume 1 == ~t2_pc~0; 40153#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39910#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39911#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41102#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 40631#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40632#L582-36 assume 1 == ~t3_pc~0; 40468#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40469#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40562#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40563#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40668#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40609#L601-36 assume 1 == ~t4_pc~0; 40499#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 40500#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40760#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40761#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41207#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41108#L620-36 assume 1 == ~t5_pc~0; 40550#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40551#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40969#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40526#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 40173#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39955#L639-36 assume 1 == ~t6_pc~0; 39956#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 39996#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39997#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40224#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40225#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40816#L658-36 assume !(1 == ~t7_pc~0); 39968#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 39969#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41193#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39946#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 39947#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40958#L677-36 assume 1 == ~t8_pc~0; 41135#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40736#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40861#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40862#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40762#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40763#L696-36 assume 1 == ~t9_pc~0; 40654#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40656#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40597#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40598#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 40777#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40778#L715-36 assume 1 == ~t10_pc~0; 40920#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 39849#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39850#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39825#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 39826#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40213#L734-36 assume !(1 == ~t11_pc~0); 39923#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 39924#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40233#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39841#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39842#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40840#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 40487#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40488#L1218-3 assume !(1 == ~T2_E~0); 40262#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40263#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40440#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40441#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 40705#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 40706#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41206#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41209#L1258-3 assume !(1 == ~T10_E~0); 40245#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40246#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41181#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41196#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41198#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 40582#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40583#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 40434#L1298-3 assume !(1 == ~E_7~0); 40435#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 40921#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 40431#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 40432#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 40247#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 40248#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 40188#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 40415#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 40416#L1663 assume !(0 == start_simulation_~tmp~3#1); 40089#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 40814#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 40033#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 39916#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 39917#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 39979#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40304#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 40764#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 40323#L1644-2 [2022-12-13 12:07:07,303 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:07,303 INFO L85 PathProgramCache]: Analyzing trace with hash -268309982, now seen corresponding path program 1 times [2022-12-13 12:07:07,303 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:07,303 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [654376224] [2022-12-13 12:07:07,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:07,304 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:07,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:07,347 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:07,347 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:07,347 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [654376224] [2022-12-13 12:07:07,347 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [654376224] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:07,347 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:07,347 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 12:07:07,347 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [820176966] [2022-12-13 12:07:07,347 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:07,348 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:07:07,348 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:07,348 INFO L85 PathProgramCache]: Analyzing trace with hash 1675178121, now seen corresponding path program 1 times [2022-12-13 12:07:07,348 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:07,348 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [909184219] [2022-12-13 12:07:07,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:07,349 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:07,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:07,382 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:07,382 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:07,382 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [909184219] [2022-12-13 12:07:07,382 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [909184219] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:07,382 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:07,382 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:07,382 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [689525547] [2022-12-13 12:07:07,382 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:07,383 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:07:07,383 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:07:07,383 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:07:07,383 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:07:07,383 INFO L87 Difference]: Start difference. First operand 1476 states and 2176 transitions. cyclomatic complexity: 701 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:07,432 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:07:07,432 INFO L93 Difference]: Finished difference Result 1476 states and 2158 transitions. [2022-12-13 12:07:07,432 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2158 transitions. [2022-12-13 12:07:07,435 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-12-13 12:07:07,440 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2158 transitions. [2022-12-13 12:07:07,441 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2022-12-13 12:07:07,441 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2022-12-13 12:07:07,441 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2158 transitions. [2022-12-13 12:07:07,443 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:07:07,443 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2158 transitions. [2022-12-13 12:07:07,444 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2158 transitions. [2022-12-13 12:07:07,483 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2022-12-13 12:07:07,485 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.462059620596206) internal successors, (2158), 1475 states have internal predecessors, (2158), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:07,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2158 transitions. [2022-12-13 12:07:07,490 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2158 transitions. [2022-12-13 12:07:07,491 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:07:07,491 INFO L428 stractBuchiCegarLoop]: Abstraction has 1476 states and 2158 transitions. [2022-12-13 12:07:07,491 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-12-13 12:07:07,491 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2158 transitions. [2022-12-13 12:07:07,497 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2022-12-13 12:07:07,497 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:07,497 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:07,500 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:07,500 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:07,500 INFO L748 eck$LassoCheckResult]: Stem: 43224#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 43225#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 44194#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 44195#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43666#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 43667#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43538#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43437#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43168#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42818#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42819#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 42861#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42862#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 43793#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 43794#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 43838#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 43264#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43265#L1090 assume !(0 == ~M_E~0); 43306#L1090-2 assume !(0 == ~T1_E~0); 43307#L1095-1 assume !(0 == ~T2_E~0); 43983#L1100-1 assume !(0 == ~T3_E~0); 43984#L1105-1 assume !(0 == ~T4_E~0); 43090#L1110-1 assume !(0 == ~T5_E~0); 43091#L1115-1 assume !(0 == ~T6_E~0); 43473#L1120-1 assume !(0 == ~T7_E~0); 43771#L1125-1 assume !(0 == ~T8_E~0); 44245#L1130-1 assume !(0 == ~T9_E~0); 44005#L1135-1 assume !(0 == ~T10_E~0); 43269#L1140-1 assume !(0 == ~T11_E~0); 43270#L1145-1 assume !(0 == ~E_1~0); 43939#L1150-1 assume !(0 == ~E_2~0); 43450#L1155-1 assume !(0 == ~E_3~0); 43451#L1160-1 assume !(0 == ~E_4~0); 43543#L1165-1 assume !(0 == ~E_5~0); 43544#L1170-1 assume !(0 == ~E_6~0); 44178#L1175-1 assume !(0 == ~E_7~0); 43624#L1180-1 assume !(0 == ~E_8~0); 43625#L1185-1 assume !(0 == ~E_9~0); 43266#L1190-1 assume !(0 == ~E_10~0); 43267#L1195-1 assume !(0 == ~E_11~0); 43640#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43465#L525 assume !(1 == ~m_pc~0); 42903#L525-2 is_master_triggered_~__retres1~0#1 := 0; 42904#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44079#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 44052#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43257#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43258#L544 assume 1 == ~t1_pc~0; 43520#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 43472#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42877#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 42878#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 43114#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43741#L563 assume !(1 == ~t2_pc~0); 43925#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 42922#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42923#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43334#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 43335#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43819#L582 assume 1 == ~t3_pc~0; 43058#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43059#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42810#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 42811#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 42994#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42995#L601 assume !(1 == ~t4_pc~0); 43951#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 43474#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43007#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43008#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 43946#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44220#L620 assume 1 == ~t5_pc~0; 42950#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 42951#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43835#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44084#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 44229#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44230#L639 assume !(1 == ~t6_pc~0); 43769#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 43372#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43373#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43423#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 43480#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43481#L658 assume !(1 == ~t7_pc~0); 43689#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 43690#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44235#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43887#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 43260#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43261#L677 assume 1 == ~t8_pc~0; 43486#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 43073#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43074#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43330#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 43331#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44046#L696 assume !(1 == ~t9_pc~0); 43752#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 43753#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43530#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43531#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 43776#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43988#L715 assume 1 == ~t10_pc~0; 43995#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 43868#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43678#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43679#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 43618#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43067#L734 assume !(1 == ~t11_pc~0); 43068#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 43545#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43627#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42806#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 42807#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43836#L1213 assume !(1 == ~M_E~0); 43615#L1213-2 assume !(1 == ~T1_E~0); 43616#L1218-1 assume !(1 == ~T2_E~0); 42839#L1223-1 assume !(1 == ~T3_E~0); 42840#L1228-1 assume !(1 == ~T4_E~0); 43591#L1233-1 assume !(1 == ~T5_E~0); 44231#L1238-1 assume !(1 == ~T6_E~0); 43944#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 43945#L1248-1 assume !(1 == ~T8_E~0); 43991#L1253-1 assume !(1 == ~T9_E~0); 43992#L1258-1 assume !(1 == ~T10_E~0); 43968#L1263-1 assume !(1 == ~T11_E~0); 43969#L1268-1 assume !(1 == ~E_1~0); 43790#L1273-1 assume !(1 == ~E_2~0); 43791#L1278-1 assume !(1 == ~E_3~0); 43370#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 43371#L1288-1 assume !(1 == ~E_5~0); 44090#L1293-1 assume !(1 == ~E_6~0); 44050#L1298-1 assume !(1 == ~E_7~0); 43823#L1303-1 assume !(1 == ~E_8~0); 43380#L1308-1 assume !(1 == ~E_9~0); 43273#L1313-1 assume !(1 == ~E_10~0); 43274#L1318-1 assume !(1 == ~E_11~0); 43281#L1323-1 assume { :end_inline_reset_delta_events } true; 43282#L1644-2 [2022-12-13 12:07:07,501 INFO L750 eck$LassoCheckResult]: Loop: 43282#L1644-2 assume !false; 43884#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 43885#L1065 assume !false; 43959#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 44227#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 42918#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 43495#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 43385#L906 assume !(0 != eval_~tmp~0#1); 43387#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 43700#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43701#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44105#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44162#L1095-3 assume !(0 == ~T2_E~0); 44127#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44128#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 43163#L1110-3 assume !(0 == ~T5_E~0); 43164#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43438#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 43439#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 43943#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 44202#L1135-3 assume !(0 == ~T10_E~0); 43360#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 42871#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 42872#L1150-3 assume !(0 == ~E_2~0); 42996#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42997#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 43343#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 43344#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 43734#L1175-3 assume !(0 == ~E_7~0); 43259#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 43023#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 43024#L1190-3 assume !(0 == ~E_10~0); 44189#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 44190#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43573#L525-36 assume !(1 == ~m_pc~0); 43574#L525-38 is_master_triggered_~__retres1~0#1 := 0; 43123#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43124#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 43395#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43396#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43309#L544-36 assume 1 == ~t1_pc~0; 43310#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 43857#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43858#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 44196#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44176#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44080#L563-36 assume 1 == ~t2_pc~0; 43112#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42869#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42870#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 44061#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 43589#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43590#L582-36 assume 1 == ~t3_pc~0; 43427#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43428#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43521#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43522#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43626#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43567#L601-36 assume 1 == ~t4_pc~0; 43458#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43459#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43718#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43719#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44166#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44067#L620-36 assume 1 == ~t5_pc~0; 43509#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43510#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43928#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43485#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 43132#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42914#L639-36 assume 1 == ~t6_pc~0; 42915#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 42955#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42956#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43183#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 43184#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43774#L658-36 assume !(1 == ~t7_pc~0); 42927#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 42928#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44152#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 42905#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 42906#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43917#L677-36 assume !(1 == ~t8_pc~0); 43693#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 43694#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43820#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43821#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43720#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43721#L696-36 assume 1 == ~t9_pc~0; 43612#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43614#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43556#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43557#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 43735#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43736#L715-36 assume !(1 == ~t10_pc~0); 43702#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 42808#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 42809#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 42784#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 42785#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43172#L734-36 assume !(1 == ~t11_pc~0); 42882#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 42883#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43192#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42800#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 42801#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43799#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 43446#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 43447#L1218-3 assume !(1 == ~T2_E~0); 43221#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43222#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43399#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 43400#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 43663#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 43664#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 44165#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 44168#L1258-3 assume !(1 == ~T10_E~0); 43204#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43205#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44140#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44155#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44157#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43541#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43542#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43393#L1298-3 assume !(1 == ~E_7~0); 43394#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 43880#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43390#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 43391#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 43206#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 43207#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 43147#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 43374#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 43375#L1663 assume !(0 == start_simulation_~tmp~3#1); 43048#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 43772#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 42992#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 42875#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 42876#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42938#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43263#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 43722#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 43282#L1644-2 [2022-12-13 12:07:07,501 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:07,501 INFO L85 PathProgramCache]: Analyzing trace with hash -2032217409, now seen corresponding path program 1 times [2022-12-13 12:07:07,502 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:07,502 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2029218714] [2022-12-13 12:07:07,502 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:07,502 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:07,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:07,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:07,579 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:07,580 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2029218714] [2022-12-13 12:07:07,580 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2029218714] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:07,580 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:07,580 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:07:07,580 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [293114837] [2022-12-13 12:07:07,580 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:07,581 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:07:07,581 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:07,581 INFO L85 PathProgramCache]: Analyzing trace with hash 773420582, now seen corresponding path program 1 times [2022-12-13 12:07:07,581 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:07,581 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1628863005] [2022-12-13 12:07:07,581 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:07,582 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:07,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:07,641 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:07,641 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:07,641 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1628863005] [2022-12-13 12:07:07,641 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1628863005] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:07,641 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:07,641 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:07:07,642 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [965402089] [2022-12-13 12:07:07,642 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:07,642 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:07:07,642 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:07:07,642 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 12:07:07,642 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 12:07:07,642 INFO L87 Difference]: Start difference. First operand 1476 states and 2158 transitions. cyclomatic complexity: 683 Second operand has 5 states, 5 states have (on average 27.4) internal successors, (137), 5 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:07,883 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:07:07,883 INFO L93 Difference]: Finished difference Result 4220 states and 6138 transitions. [2022-12-13 12:07:07,884 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4220 states and 6138 transitions. [2022-12-13 12:07:07,904 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3864 [2022-12-13 12:07:07,914 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4220 states to 4220 states and 6138 transitions. [2022-12-13 12:07:07,914 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4220 [2022-12-13 12:07:07,917 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4220 [2022-12-13 12:07:07,917 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4220 states and 6138 transitions. [2022-12-13 12:07:07,921 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:07:07,921 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4220 states and 6138 transitions. [2022-12-13 12:07:07,924 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4220 states and 6138 transitions. [2022-12-13 12:07:07,943 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4220 to 1518. [2022-12-13 12:07:07,945 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1518 states, 1518 states have (on average 1.4492753623188406) internal successors, (2200), 1517 states have internal predecessors, (2200), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:07,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1518 states to 1518 states and 2200 transitions. [2022-12-13 12:07:07,947 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1518 states and 2200 transitions. [2022-12-13 12:07:07,947 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 12:07:07,948 INFO L428 stractBuchiCegarLoop]: Abstraction has 1518 states and 2200 transitions. [2022-12-13 12:07:07,948 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-12-13 12:07:07,948 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1518 states and 2200 transitions. [2022-12-13 12:07:07,953 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1366 [2022-12-13 12:07:07,953 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:07,953 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:07,954 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:07,954 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:07,954 INFO L748 eck$LassoCheckResult]: Stem: 48936#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 48937#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 49932#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 49933#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49384#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 49385#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49255#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49152#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 48880#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48529#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48530#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48572#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48573#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49513#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49514#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49558#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 48978#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 48979#L1090 assume !(0 == ~M_E~0); 49020#L1090-2 assume !(0 == ~T1_E~0); 49021#L1095-1 assume !(0 == ~T2_E~0); 49707#L1100-1 assume !(0 == ~T3_E~0); 49708#L1105-1 assume !(0 == ~T4_E~0); 48801#L1110-1 assume !(0 == ~T5_E~0); 48802#L1115-1 assume !(0 == ~T6_E~0); 49188#L1120-1 assume !(0 == ~T7_E~0); 49491#L1125-1 assume !(0 == ~T8_E~0); 49993#L1130-1 assume !(0 == ~T9_E~0); 49730#L1135-1 assume !(0 == ~T10_E~0); 48983#L1140-1 assume !(0 == ~T11_E~0); 48984#L1145-1 assume !(0 == ~E_1~0); 49662#L1150-1 assume !(0 == ~E_2~0); 49165#L1155-1 assume !(0 == ~E_3~0); 49166#L1160-1 assume !(0 == ~E_4~0); 49260#L1165-1 assume !(0 == ~E_5~0); 49261#L1170-1 assume !(0 == ~E_6~0); 49915#L1175-1 assume !(0 == ~E_7~0); 49342#L1180-1 assume !(0 == ~E_8~0); 49343#L1185-1 assume !(0 == ~E_9~0); 48980#L1190-1 assume !(0 == ~E_10~0); 48981#L1195-1 assume !(0 == ~E_11~0); 49358#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49180#L525 assume !(1 == ~m_pc~0); 48614#L525-2 is_master_triggered_~__retres1~0#1 := 0; 48615#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49886#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49779#L1350 assume !(0 != activate_threads_~tmp~1#1); 48970#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48971#L544 assume 1 == ~t1_pc~0; 49235#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49187#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48588#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 48589#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 48825#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49460#L563 assume !(1 == ~t2_pc~0); 49648#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 48633#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48634#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49048#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 49049#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49539#L582 assume 1 == ~t3_pc~0; 48769#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 48770#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48521#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48522#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 48705#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48706#L601 assume !(1 == ~t4_pc~0); 49674#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49189#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48718#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48719#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 49669#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49964#L620 assume 1 == ~t5_pc~0; 48661#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 48662#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49555#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49813#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 49976#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49977#L639 assume !(1 == ~t6_pc~0); 49489#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 49087#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49088#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49138#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 49195#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49196#L658 assume !(1 == ~t7_pc~0); 49407#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 49408#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49982#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49609#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 48974#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 48975#L677 assume 1 == ~t8_pc~0; 49201#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 48784#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48785#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49044#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 49045#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49773#L696 assume !(1 == ~t9_pc~0); 49471#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 49472#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49245#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49246#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 49496#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49712#L715 assume 1 == ~t10_pc~0; 49720#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 49588#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49396#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49397#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 49336#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48778#L734 assume !(1 == ~t11_pc~0); 48779#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 49262#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49345#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48517#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 48518#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49556#L1213 assume !(1 == ~M_E~0); 49333#L1213-2 assume !(1 == ~T1_E~0); 49334#L1218-1 assume !(1 == ~T2_E~0); 48550#L1223-1 assume !(1 == ~T3_E~0); 48551#L1228-1 assume !(1 == ~T4_E~0); 49308#L1233-1 assume !(1 == ~T5_E~0); 49978#L1238-1 assume !(1 == ~T6_E~0); 49667#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 49668#L1248-1 assume !(1 == ~T8_E~0); 49716#L1253-1 assume !(1 == ~T9_E~0); 49717#L1258-1 assume !(1 == ~T10_E~0); 49691#L1263-1 assume !(1 == ~T11_E~0); 49692#L1268-1 assume !(1 == ~E_1~0); 49510#L1273-1 assume !(1 == ~E_2~0); 49511#L1278-1 assume !(1 == ~E_3~0); 49085#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 49086#L1288-1 assume !(1 == ~E_5~0); 49819#L1293-1 assume !(1 == ~E_6~0); 49777#L1298-1 assume !(1 == ~E_7~0); 49543#L1303-1 assume !(1 == ~E_8~0); 49095#L1308-1 assume !(1 == ~E_9~0); 48987#L1313-1 assume !(1 == ~E_10~0); 48988#L1318-1 assume !(1 == ~E_11~0); 48995#L1323-1 assume { :end_inline_reset_delta_events } true; 48996#L1644-2 [2022-12-13 12:07:07,955 INFO L750 eck$LassoCheckResult]: Loop: 48996#L1644-2 assume !false; 49606#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49607#L1065 assume !false; 49682#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49974#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 48629#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49210#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 49100#L906 assume !(0 != eval_~tmp~0#1); 49102#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49418#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49419#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 49835#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 49896#L1095-3 assume !(0 == ~T2_E~0); 49859#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 49860#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 48875#L1110-3 assume !(0 == ~T5_E~0); 48876#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 49153#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49154#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49666#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 49942#L1135-3 assume !(0 == ~T10_E~0); 49074#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 48582#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 48583#L1150-3 assume !(0 == ~E_2~0); 48707#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 48708#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 49057#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 49058#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 49453#L1175-3 assume !(0 == ~E_7~0); 48973#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 48734#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 48735#L1190-3 assume !(0 == ~E_10~0); 49926#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 49927#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49290#L525-36 assume !(1 == ~m_pc~0); 49291#L525-38 is_master_triggered_~__retres1~0#1 := 0; 48835#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48836#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49110#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 49111#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49023#L544-36 assume 1 == ~t1_pc~0; 49024#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49577#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49578#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49934#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49913#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49809#L563-36 assume 1 == ~t2_pc~0; 48823#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 48580#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48581#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49788#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49306#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49307#L582-36 assume 1 == ~t3_pc~0; 49142#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49143#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49236#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49237#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49344#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49284#L601-36 assume 1 == ~t4_pc~0; 49173#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49174#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49436#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49437#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49901#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49795#L620-36 assume 1 == ~t5_pc~0; 49224#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49225#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49651#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49200#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 48844#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48625#L639-36 assume 1 == ~t6_pc~0; 48626#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 48666#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48667#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48895#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 48896#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49494#L658-36 assume !(1 == ~t7_pc~0); 48638#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 48639#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49885#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48616#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 48617#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49640#L677-36 assume 1 == ~t8_pc~0; 49824#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49412#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49540#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49541#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49438#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49439#L696-36 assume 1 == ~t9_pc~0; 49330#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49332#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49273#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49274#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 49454#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49455#L715-36 assume 1 == ~t10_pc~0; 49600#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 48519#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48520#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 48495#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 48496#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48884#L734-36 assume !(1 == ~t11_pc~0); 48593#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 48594#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48904#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48511#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 48512#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49519#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 49161#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49162#L1218-3 assume !(1 == ~T2_E~0); 48933#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48934#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49114#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 49115#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49381#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 49382#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49900#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49903#L1258-3 assume !(1 == ~T10_E~0); 48916#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 48917#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 49872#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 49889#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 49891#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49258#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49259#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 49108#L1298-3 assume !(1 == ~E_7~0); 49109#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49601#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 49105#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 49106#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 48918#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 48919#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 48859#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49089#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 49090#L1663 assume !(0 == start_simulation_~tmp~3#1); 48759#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49492#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 48703#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 48586#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 48587#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48649#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 48977#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 49441#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 48996#L1644-2 [2022-12-13 12:07:07,955 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:07,955 INFO L85 PathProgramCache]: Analyzing trace with hash -2060717699, now seen corresponding path program 1 times [2022-12-13 12:07:07,955 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:07,955 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [168591387] [2022-12-13 12:07:07,955 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:07,955 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:07,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:08,009 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:08,009 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:08,009 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [168591387] [2022-12-13 12:07:08,009 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [168591387] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:08,009 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:08,009 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:08,010 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [700693275] [2022-12-13 12:07:08,010 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:08,010 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:07:08,010 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:08,010 INFO L85 PathProgramCache]: Analyzing trace with hash -1658603226, now seen corresponding path program 1 times [2022-12-13 12:07:08,010 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:08,011 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1253931216] [2022-12-13 12:07:08,011 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:08,011 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:08,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:08,059 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:08,060 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:08,060 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1253931216] [2022-12-13 12:07:08,060 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1253931216] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:08,060 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:08,060 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:07:08,060 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [583769791] [2022-12-13 12:07:08,060 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:08,061 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:07:08,061 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:07:08,061 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:07:08,061 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:07:08,062 INFO L87 Difference]: Start difference. First operand 1518 states and 2200 transitions. cyclomatic complexity: 683 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:08,289 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:07:08,289 INFO L93 Difference]: Finished difference Result 4068 states and 5826 transitions. [2022-12-13 12:07:08,289 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4068 states and 5826 transitions. [2022-12-13 12:07:08,304 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3828 [2022-12-13 12:07:08,316 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4068 states to 4068 states and 5826 transitions. [2022-12-13 12:07:08,316 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4068 [2022-12-13 12:07:08,320 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4068 [2022-12-13 12:07:08,320 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4068 states and 5826 transitions. [2022-12-13 12:07:08,326 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:07:08,326 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4068 states and 5826 transitions. [2022-12-13 12:07:08,331 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4068 states and 5826 transitions. [2022-12-13 12:07:08,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4068 to 3902. [2022-12-13 12:07:08,378 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3902 states, 3902 states have (on average 1.4349051768323937) internal successors, (5599), 3901 states have internal predecessors, (5599), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:08,387 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3902 states to 3902 states and 5599 transitions. [2022-12-13 12:07:08,387 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3902 states and 5599 transitions. [2022-12-13 12:07:08,387 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:07:08,388 INFO L428 stractBuchiCegarLoop]: Abstraction has 3902 states and 5599 transitions. [2022-12-13 12:07:08,388 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-12-13 12:07:08,388 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3902 states and 5599 transitions. [2022-12-13 12:07:08,400 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3750 [2022-12-13 12:07:08,401 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:08,401 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:08,403 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:08,403 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:08,403 INFO L748 eck$LassoCheckResult]: Stem: 54535#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 54536#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 55536#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 55537#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54980#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 54981#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 54852#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 54748#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 54478#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 54127#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54128#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54170#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 54171#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 55110#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 55111#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 55156#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 54577#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54578#L1090 assume !(0 == ~M_E~0); 54619#L1090-2 assume !(0 == ~T1_E~0); 54620#L1095-1 assume !(0 == ~T2_E~0); 55306#L1100-1 assume !(0 == ~T3_E~0); 55307#L1105-1 assume !(0 == ~T4_E~0); 54400#L1110-1 assume !(0 == ~T5_E~0); 54401#L1115-1 assume !(0 == ~T6_E~0); 54787#L1120-1 assume !(0 == ~T7_E~0); 55088#L1125-1 assume !(0 == ~T8_E~0); 55607#L1130-1 assume !(0 == ~T9_E~0); 55331#L1135-1 assume !(0 == ~T10_E~0); 54582#L1140-1 assume !(0 == ~T11_E~0); 54583#L1145-1 assume !(0 == ~E_1~0); 55261#L1150-1 assume !(0 == ~E_2~0); 54762#L1155-1 assume !(0 == ~E_3~0); 54763#L1160-1 assume !(0 == ~E_4~0); 54857#L1165-1 assume !(0 == ~E_5~0); 54858#L1170-1 assume !(0 == ~E_6~0); 55517#L1175-1 assume !(0 == ~E_7~0); 54938#L1180-1 assume !(0 == ~E_8~0); 54939#L1185-1 assume !(0 == ~E_9~0); 54579#L1190-1 assume !(0 == ~E_10~0); 54580#L1195-1 assume !(0 == ~E_11~0); 54954#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54779#L525 assume !(1 == ~m_pc~0); 54212#L525-2 is_master_triggered_~__retres1~0#1 := 0; 54213#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55409#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 55382#L1350 assume !(0 != activate_threads_~tmp~1#1); 54570#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54571#L544 assume !(1 == ~t1_pc~0); 54785#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 54786#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54186#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 54187#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 54423#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55058#L563 assume !(1 == ~t2_pc~0); 55247#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 54231#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54232#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 54647#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 54648#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55136#L582 assume 1 == ~t3_pc~0; 54368#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 54369#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54119#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 54120#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 54304#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54305#L601 assume !(1 == ~t4_pc~0); 55274#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 54788#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54317#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 54318#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 55269#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55573#L620 assume 1 == ~t5_pc~0; 54259#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 54260#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55152#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 55414#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 55589#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55590#L639 assume !(1 == ~t6_pc~0); 55086#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 54683#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54684#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54734#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 54793#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54794#L658 assume !(1 == ~t7_pc~0); 55003#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 55004#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55595#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 55207#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 54573#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54574#L677 assume 1 == ~t8_pc~0; 54800#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 54383#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54384#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54643#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 54644#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 55372#L696 assume !(1 == ~t9_pc~0); 55069#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 55070#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54843#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54844#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 55093#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 55311#L715 assume 1 == ~t10_pc~0; 55321#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 55186#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54992#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 54993#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 54931#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54377#L734 assume !(1 == ~t11_pc~0); 54378#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 54859#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 54941#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54115#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 54116#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55153#L1213 assume !(1 == ~M_E~0); 54928#L1213-2 assume !(1 == ~T1_E~0); 54929#L1218-1 assume !(1 == ~T2_E~0); 54148#L1223-1 assume !(1 == ~T3_E~0); 54149#L1228-1 assume !(1 == ~T4_E~0); 54904#L1233-1 assume !(1 == ~T5_E~0); 55591#L1238-1 assume !(1 == ~T6_E~0); 55267#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 55268#L1248-1 assume !(1 == ~T8_E~0); 55317#L1253-1 assume !(1 == ~T9_E~0); 55318#L1258-1 assume !(1 == ~T10_E~0); 55291#L1263-1 assume !(1 == ~T11_E~0); 55292#L1268-1 assume !(1 == ~E_1~0); 55107#L1273-1 assume !(1 == ~E_2~0); 55108#L1278-1 assume !(1 == ~E_3~0); 54681#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 54682#L1288-1 assume !(1 == ~E_5~0); 55422#L1293-1 assume !(1 == ~E_6~0); 55377#L1298-1 assume !(1 == ~E_7~0); 55140#L1303-1 assume !(1 == ~E_8~0); 54691#L1308-1 assume !(1 == ~E_9~0); 54586#L1313-1 assume !(1 == ~E_10~0); 54587#L1318-1 assume !(1 == ~E_11~0); 54594#L1323-1 assume { :end_inline_reset_delta_events } true; 54595#L1644-2 [2022-12-13 12:07:08,403 INFO L750 eck$LassoCheckResult]: Loop: 54595#L1644-2 assume !false; 55204#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 55205#L1065 assume !false; 55282#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 55587#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 54227#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 54809#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 54696#L906 assume !(0 != eval_~tmp~0#1); 54698#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 55015#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 55016#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 55440#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 55499#L1095-3 assume !(0 == ~T2_E~0); 55462#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 55463#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 54473#L1110-3 assume !(0 == ~T5_E~0); 54474#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 54749#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 54750#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 55265#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 55548#L1135-3 assume !(0 == ~T10_E~0); 54672#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 54180#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 54181#L1150-3 assume !(0 == ~E_2~0); 54306#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54307#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 54656#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54657#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 55051#L1175-3 assume !(0 == ~E_7~0); 54572#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 54333#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 54334#L1190-3 assume !(0 == ~E_10~0); 55528#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 55529#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54887#L525-36 assume !(1 == ~m_pc~0); 54888#L525-38 is_master_triggered_~__retres1~0#1 := 0; 54432#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54433#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 54706#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 54707#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54624#L544-36 assume !(1 == ~t1_pc~0); 54625#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 55175#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55176#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 55538#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 55515#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55410#L563-36 assume 1 == ~t2_pc~0; 54421#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54178#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54179#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 55391#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54902#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54903#L582-36 assume 1 == ~t3_pc~0; 54738#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 54739#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54834#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 54835#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54940#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54881#L601-36 assume 1 == ~t4_pc~0; 54772#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 54773#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55033#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 55034#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 55503#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55397#L620-36 assume 1 == ~t5_pc~0; 54823#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 54824#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55250#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54799#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 54441#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54223#L639-36 assume 1 == ~t6_pc~0; 54224#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 54264#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54265#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54491#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54492#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 55091#L658-36 assume !(1 == ~t7_pc~0); 54236#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 54237#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55488#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54214#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 54215#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 55239#L677-36 assume 1 == ~t8_pc~0; 55429#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 55008#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 55137#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 55138#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 55035#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 55036#L696-36 assume 1 == ~t9_pc~0; 54925#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54927#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54870#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54871#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 55052#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 55053#L715-36 assume !(1 == ~t10_pc~0); 55017#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 54117#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54118#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 54093#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 54094#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54482#L734-36 assume 1 == ~t11_pc~0; 54483#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 54192#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 54502#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54109#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 54110#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55116#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 54758#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54759#L1218-3 assume !(1 == ~T2_E~0); 54532#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54533#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54710#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54711#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 54977#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54978#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 55502#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 55505#L1258-3 assume !(1 == ~T10_E~0); 54514#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 54515#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 55476#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 55491#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 55493#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 54855#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 54856#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 54704#L1298-3 assume !(1 == ~E_7~0); 54705#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 55199#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 54701#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 54702#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 54516#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 54517#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 54456#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 54685#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 54686#L1663 assume !(0 == start_simulation_~tmp~3#1); 54358#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 55089#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 54302#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 54184#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 54185#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54247#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54576#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 55038#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 54595#L1644-2 [2022-12-13 12:07:08,404 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:08,404 INFO L85 PathProgramCache]: Analyzing trace with hash -2098164388, now seen corresponding path program 1 times [2022-12-13 12:07:08,404 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:08,404 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [130273261] [2022-12-13 12:07:08,404 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:08,404 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:08,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:08,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:08,472 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:08,472 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [130273261] [2022-12-13 12:07:08,472 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [130273261] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:08,472 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:08,472 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:08,473 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [47350411] [2022-12-13 12:07:08,473 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:08,473 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:07:08,473 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:08,473 INFO L85 PathProgramCache]: Analyzing trace with hash 64772933, now seen corresponding path program 1 times [2022-12-13 12:07:08,473 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:08,474 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1392828761] [2022-12-13 12:07:08,474 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:08,474 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:08,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:08,547 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:08,547 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:08,547 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1392828761] [2022-12-13 12:07:08,547 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1392828761] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:08,548 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:08,548 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:07:08,548 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1434037699] [2022-12-13 12:07:08,548 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:08,548 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:07:08,548 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:07:08,548 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:07:08,549 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:07:08,549 INFO L87 Difference]: Start difference. First operand 3902 states and 5599 transitions. cyclomatic complexity: 1699 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:08,737 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:07:08,737 INFO L93 Difference]: Finished difference Result 10909 states and 15519 transitions. [2022-12-13 12:07:08,737 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10909 states and 15519 transitions. [2022-12-13 12:07:08,769 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10559 [2022-12-13 12:07:08,791 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10909 states to 10909 states and 15519 transitions. [2022-12-13 12:07:08,791 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10909 [2022-12-13 12:07:08,797 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10909 [2022-12-13 12:07:08,798 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10909 states and 15519 transitions. [2022-12-13 12:07:08,806 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:07:08,806 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10909 states and 15519 transitions. [2022-12-13 12:07:08,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10909 states and 15519 transitions. [2022-12-13 12:07:08,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10909 to 10528. [2022-12-13 12:07:08,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10528 states, 10528 states have (on average 1.425056990881459) internal successors, (15003), 10527 states have internal predecessors, (15003), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:08,955 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10528 states to 10528 states and 15003 transitions. [2022-12-13 12:07:08,956 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10528 states and 15003 transitions. [2022-12-13 12:07:08,956 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:07:08,956 INFO L428 stractBuchiCegarLoop]: Abstraction has 10528 states and 15003 transitions. [2022-12-13 12:07:08,956 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-12-13 12:07:08,956 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10528 states and 15003 transitions. [2022-12-13 12:07:08,977 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10367 [2022-12-13 12:07:08,977 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:08,977 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:08,978 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:08,978 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:08,979 INFO L748 eck$LassoCheckResult]: Stem: 69365#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 69366#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 70608#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 70609#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 69850#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 69851#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 69708#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 69594#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 69308#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 68950#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 68951#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 68993#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 68994#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 70005#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 70006#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 70066#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 69414#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 69415#L1090 assume !(0 == ~M_E~0); 69465#L1090-2 assume !(0 == ~T1_E~0); 69466#L1095-1 assume !(0 == ~T2_E~0); 70245#L1100-1 assume !(0 == ~T3_E~0); 70246#L1105-1 assume !(0 == ~T4_E~0); 69222#L1110-1 assume !(0 == ~T5_E~0); 69223#L1115-1 assume !(0 == ~T6_E~0); 69634#L1120-1 assume !(0 == ~T7_E~0); 69975#L1125-1 assume !(0 == ~T8_E~0); 70793#L1130-1 assume !(0 == ~T9_E~0); 70274#L1135-1 assume !(0 == ~T10_E~0); 69421#L1140-1 assume !(0 == ~T11_E~0); 69422#L1145-1 assume !(0 == ~E_1~0); 70184#L1150-1 assume !(0 == ~E_2~0); 69608#L1155-1 assume !(0 == ~E_3~0); 69609#L1160-1 assume !(0 == ~E_4~0); 69713#L1165-1 assume !(0 == ~E_5~0); 69714#L1170-1 assume !(0 == ~E_6~0); 70574#L1175-1 assume !(0 == ~E_7~0); 69804#L1180-1 assume !(0 == ~E_8~0); 69805#L1185-1 assume !(0 == ~E_9~0); 69416#L1190-1 assume !(0 == ~E_10~0); 69417#L1195-1 assume !(0 == ~E_11~0); 69822#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69627#L525 assume !(1 == ~m_pc~0); 69034#L525-2 is_master_triggered_~__retres1~0#1 := 0; 69035#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 70392#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 70349#L1350 assume !(0 != activate_threads_~tmp~1#1); 69405#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69406#L544 assume !(1 == ~t1_pc~0); 69630#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 69631#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69011#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 69012#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 69246#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69940#L563 assume !(1 == ~t2_pc~0); 70169#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 69053#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69054#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 69488#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 69489#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 70034#L582 assume !(1 == ~t3_pc~0); 70183#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 70714#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68942#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 68943#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 69128#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69129#L601 assume !(1 == ~t4_pc~0); 70207#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 69635#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69143#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 69144#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 70198#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 70696#L620 assume 1 == ~t5_pc~0; 69083#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 69084#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 70055#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 70399#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 70732#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 70733#L639 assume !(1 == ~t6_pc~0); 69973#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 69526#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 69527#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 69578#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 69640#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 69641#L658 assume !(1 == ~t7_pc~0); 69877#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 69878#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 70749#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 70114#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 69409#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 69410#L677 assume 1 == ~t8_pc~0; 69646#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 69211#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 69212#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 69484#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 69485#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 70336#L696 assume !(1 == ~t9_pc~0); 69956#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 69957#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 69695#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 69696#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 69983#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 70251#L715 assume 1 == ~t10_pc~0; 70262#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 70093#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 69865#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 69866#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 69797#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69199#L734 assume !(1 == ~t11_pc~0); 69200#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 69718#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 69808#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 68940#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 68941#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70056#L1213 assume !(1 == ~M_E~0); 69795#L1213-2 assume !(1 == ~T1_E~0); 69796#L1218-1 assume !(1 == ~T2_E~0); 68971#L1223-1 assume !(1 == ~T3_E~0); 68972#L1228-1 assume !(1 == ~T4_E~0); 69769#L1233-1 assume !(1 == ~T5_E~0); 70734#L1238-1 assume !(1 == ~T6_E~0); 70196#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 70197#L1248-1 assume !(1 == ~T8_E~0); 70256#L1253-1 assume !(1 == ~T9_E~0); 70257#L1258-1 assume !(1 == ~T10_E~0); 70228#L1263-1 assume !(1 == ~T11_E~0); 70229#L1268-1 assume !(1 == ~E_1~0); 69999#L1273-1 assume !(1 == ~E_2~0); 70000#L1278-1 assume !(1 == ~E_3~0); 69522#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 69523#L1288-1 assume !(1 == ~E_5~0); 70409#L1293-1 assume !(1 == ~E_6~0); 70345#L1298-1 assume !(1 == ~E_7~0); 70040#L1303-1 assume !(1 == ~E_8~0); 69533#L1308-1 assume !(1 == ~E_9~0); 69425#L1313-1 assume !(1 == ~E_10~0); 69426#L1318-1 assume !(1 == ~E_11~0); 69433#L1323-1 assume { :end_inline_reset_delta_events } true; 69434#L1644-2 [2022-12-13 12:07:08,979 INFO L750 eck$LassoCheckResult]: Loop: 69434#L1644-2 assume !false; 78731#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 70216#L1065 assume !false; 70217#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 70778#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 69049#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 69659#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 69660#L906 assume !(0 != eval_~tmp~0#1); 78718#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 79231#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 79230#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 79229#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 78694#L1095-3 assume !(0 == ~T2_E~0); 78695#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 78654#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 78655#L1110-3 assume !(0 == ~T5_E~0); 70579#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 70580#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 70193#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 70194#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 78595#L1135-3 assume !(0 == ~T10_E~0); 78596#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 78591#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 78592#L1150-3 assume !(0 == ~E_2~0); 78587#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 78588#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 78583#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 78584#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 69931#L1175-3 assume !(0 == ~E_7~0); 69932#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 69157#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 69158#L1190-3 assume !(0 == ~E_10~0); 70598#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 70599#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69745#L525-36 assume !(1 == ~m_pc~0); 69746#L525-38 is_master_triggered_~__retres1~0#1 := 0; 69259#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69260#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 69549#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 69550#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69463#L544-36 assume !(1 == ~t1_pc~0); 69464#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 70080#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 70081#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 70743#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 70744#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 70393#L563-36 assume 1 == ~t2_pc~0; 70395#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 68998#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68999#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 70741#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 70742#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 70805#L582-36 assume !(1 == ~t3_pc~0); 70806#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 69848#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69849#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 70068#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 70069#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69739#L601-36 assume 1 == ~t4_pc~0; 69741#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 70855#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70856#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 70542#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 70543#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 70373#L620-36 assume !(1 == ~t5_pc~0); 70375#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 70174#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 70175#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 69644#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 69645#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69045#L639-36 assume !(1 == ~t6_pc~0); 69047#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 69088#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 69089#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 69320#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 69321#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 70683#L658-36 assume !(1 == ~t7_pc~0); 69166#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 70515#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 70516#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 69036#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 69037#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 70419#L677-36 assume !(1 == ~t8_pc~0); 70421#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 70035#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 70036#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 70681#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 70682#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 70591#L696-36 assume 1 == ~t9_pc~0; 70593#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 70293#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 70294#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 70517#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 70518#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 70738#L715-36 assume 1 == ~t10_pc~0; 70739#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 79227#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 79226#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 79225#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 79224#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 79223#L734-36 assume !(1 == ~t11_pc~0); 79221#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 79220#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 79219#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 79218#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 79217#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 79216#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 79215#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 79214#L1218-3 assume !(1 == ~T2_E~0); 79213#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 79212#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 79211#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 79210#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 79209#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 79208#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 79207#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 79206#L1258-3 assume !(1 == ~T10_E~0); 79205#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 79204#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 79203#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 79202#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 79201#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 79200#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 79199#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 79198#L1298-3 assume !(1 == ~E_7~0); 79197#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 79196#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 79195#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 79194#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 79193#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 79192#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 79180#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 79179#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 79178#L1663 assume !(0 == start_simulation_~tmp~3#1); 70787#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 70788#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 78737#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 78736#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 78735#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 78734#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 78733#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 78732#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 69434#L1644-2 [2022-12-13 12:07:08,979 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:08,979 INFO L85 PathProgramCache]: Analyzing trace with hash 919650235, now seen corresponding path program 1 times [2022-12-13 12:07:08,979 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:08,979 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2100669841] [2022-12-13 12:07:08,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:08,980 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:08,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:09,021 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:09,021 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:09,021 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2100669841] [2022-12-13 12:07:09,021 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2100669841] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:09,021 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:09,022 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 12:07:09,022 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [534467456] [2022-12-13 12:07:09,022 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:09,022 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:07:09,022 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:09,022 INFO L85 PathProgramCache]: Analyzing trace with hash 1359859329, now seen corresponding path program 1 times [2022-12-13 12:07:09,023 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:09,023 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [133601136] [2022-12-13 12:07:09,023 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:09,023 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:09,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:09,087 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:09,087 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:09,087 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [133601136] [2022-12-13 12:07:09,087 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [133601136] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:09,087 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:09,087 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:07:09,087 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [904737478] [2022-12-13 12:07:09,088 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:09,088 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:07:09,088 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:07:09,088 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:07:09,088 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:07:09,088 INFO L87 Difference]: Start difference. First operand 10528 states and 15003 transitions. cyclomatic complexity: 4479 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:09,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:07:09,223 INFO L93 Difference]: Finished difference Result 20040 states and 28450 transitions. [2022-12-13 12:07:09,223 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20040 states and 28450 transitions. [2022-12-13 12:07:09,298 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 19847 [2022-12-13 12:07:09,344 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20040 states to 20040 states and 28450 transitions. [2022-12-13 12:07:09,345 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20040 [2022-12-13 12:07:09,355 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20040 [2022-12-13 12:07:09,355 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20040 states and 28450 transitions. [2022-12-13 12:07:09,368 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:07:09,368 INFO L218 hiAutomatonCegarLoop]: Abstraction has 20040 states and 28450 transitions. [2022-12-13 12:07:09,383 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20040 states and 28450 transitions. [2022-12-13 12:07:09,577 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20040 to 20022. [2022-12-13 12:07:09,591 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20022 states, 20022 states have (on average 1.4200379582459295) internal successors, (28432), 20021 states have internal predecessors, (28432), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:09,618 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20022 states to 20022 states and 28432 transitions. [2022-12-13 12:07:09,619 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20022 states and 28432 transitions. [2022-12-13 12:07:09,619 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:07:09,619 INFO L428 stractBuchiCegarLoop]: Abstraction has 20022 states and 28432 transitions. [2022-12-13 12:07:09,620 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-12-13 12:07:09,620 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20022 states and 28432 transitions. [2022-12-13 12:07:09,661 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 19829 [2022-12-13 12:07:09,661 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:09,661 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:09,662 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:09,663 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:09,663 INFO L748 eck$LassoCheckResult]: Stem: 99934#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 99935#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 100974#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 100975#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 100385#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 100386#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 100255#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 100150#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 99876#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 99527#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 99528#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 99570#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 99571#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 100522#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 100523#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 100567#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 99978#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 99979#L1090 assume !(0 == ~M_E~0); 100021#L1090-2 assume !(0 == ~T1_E~0); 100022#L1095-1 assume !(0 == ~T2_E~0); 100727#L1100-1 assume !(0 == ~T3_E~0); 100728#L1105-1 assume !(0 == ~T4_E~0); 99798#L1110-1 assume !(0 == ~T5_E~0); 99799#L1115-1 assume !(0 == ~T6_E~0); 100188#L1120-1 assume !(0 == ~T7_E~0); 100496#L1125-1 assume !(0 == ~T8_E~0); 101075#L1130-1 assume !(0 == ~T9_E~0); 100753#L1135-1 assume !(0 == ~T10_E~0); 99983#L1140-1 assume !(0 == ~T11_E~0); 99984#L1145-1 assume !(0 == ~E_1~0); 100678#L1150-1 assume !(0 == ~E_2~0); 100164#L1155-1 assume !(0 == ~E_3~0); 100165#L1160-1 assume !(0 == ~E_4~0); 100260#L1165-1 assume !(0 == ~E_5~0); 100261#L1170-1 assume !(0 == ~E_6~0); 100955#L1175-1 assume !(0 == ~E_7~0); 100342#L1180-1 assume !(0 == ~E_8~0); 100343#L1185-1 assume !(0 == ~E_9~0); 99980#L1190-1 assume !(0 == ~E_10~0); 99981#L1195-1 assume !(0 == ~E_11~0); 100358#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 100180#L525 assume !(1 == ~m_pc~0); 99610#L525-2 is_master_triggered_~__retres1~0#1 := 0; 99611#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 100840#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 100808#L1350 assume !(0 != activate_threads_~tmp~1#1); 99971#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 99972#L544 assume !(1 == ~t1_pc~0); 100186#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 100187#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 99585#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 99586#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 99821#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 100465#L563 assume !(1 == ~t2_pc~0); 100661#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 99632#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 99633#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 100048#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 100049#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 100548#L582 assume !(1 == ~t3_pc~0); 100676#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 101032#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 99519#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 99520#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 99703#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 99704#L601 assume !(1 == ~t4_pc~0); 100692#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 100189#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 99718#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 99719#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 100687#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 101026#L620 assume !(1 == ~t5_pc~0); 100512#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 100513#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 100564#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 100845#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 101042#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 101043#L639 assume !(1 == ~t6_pc~0); 100494#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 100084#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 100085#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 100135#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 100194#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 100195#L658 assume !(1 == ~t7_pc~0); 100411#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 100412#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 101054#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 100617#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 99974#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 99975#L677 assume 1 == ~t8_pc~0; 100201#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 99781#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 99782#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 100044#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 100045#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 100798#L696 assume !(1 == ~t9_pc~0); 100476#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 100477#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 100246#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 100247#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 100501#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 100732#L715 assume 1 == ~t10_pc~0; 100742#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 100596#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 100397#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 100398#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 100335#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 99775#L734 assume !(1 == ~t11_pc~0); 99776#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 100262#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 100345#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 99515#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 99516#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 100565#L1213 assume !(1 == ~M_E~0); 100332#L1213-2 assume !(1 == ~T1_E~0); 100333#L1218-1 assume !(1 == ~T2_E~0); 99548#L1223-1 assume !(1 == ~T3_E~0); 99549#L1228-1 assume !(1 == ~T4_E~0); 100309#L1233-1 assume !(1 == ~T5_E~0); 101044#L1238-1 assume !(1 == ~T6_E~0); 100685#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 100686#L1248-1 assume !(1 == ~T8_E~0); 100738#L1253-1 assume !(1 == ~T9_E~0); 100739#L1258-1 assume !(1 == ~T10_E~0); 100711#L1263-1 assume !(1 == ~T11_E~0); 100712#L1268-1 assume !(1 == ~E_1~0); 100519#L1273-1 assume !(1 == ~E_2~0); 100520#L1278-1 assume !(1 == ~E_3~0); 100082#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 100083#L1288-1 assume !(1 == ~E_5~0); 100853#L1293-1 assume !(1 == ~E_6~0); 100803#L1298-1 assume !(1 == ~E_7~0); 100552#L1303-1 assume !(1 == ~E_8~0); 100092#L1308-1 assume !(1 == ~E_9~0); 99987#L1313-1 assume !(1 == ~E_10~0); 99988#L1318-1 assume !(1 == ~E_11~0); 99995#L1323-1 assume { :end_inline_reset_delta_events } true; 99996#L1644-2 [2022-12-13 12:07:09,663 INFO L750 eck$LassoCheckResult]: Loop: 99996#L1644-2 assume !false; 115895#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 115887#L1065 assume !false; 115883#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 115855#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 115841#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 115837#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 115830#L906 assume !(0 != eval_~tmp~0#1); 115831#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 116393#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 116391#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 116389#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 116387#L1095-3 assume !(0 == ~T2_E~0); 116385#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 116383#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 116381#L1110-3 assume !(0 == ~T5_E~0); 116379#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 116377#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 116375#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 116373#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 116371#L1135-3 assume !(0 == ~T10_E~0); 116368#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 116366#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 116364#L1150-3 assume !(0 == ~E_2~0); 116362#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 116360#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 116358#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 116356#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 116354#L1175-3 assume !(0 == ~E_7~0); 116352#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 116350#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 116348#L1190-3 assume !(0 == ~E_10~0); 116346#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 116343#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 116341#L525-36 assume !(1 == ~m_pc~0); 116339#L525-38 is_master_triggered_~__retres1~0#1 := 0; 116337#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 116335#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 116332#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 116330#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 116328#L544-36 assume !(1 == ~t1_pc~0); 116326#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 116324#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 116322#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 116320#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 116317#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 116315#L563-36 assume 1 == ~t2_pc~0; 116313#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 116310#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 116308#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 116306#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 116303#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 116301#L582-36 assume !(1 == ~t3_pc~0); 116299#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 116297#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 116295#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 116293#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 116290#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 116288#L601-36 assume !(1 == ~t4_pc~0); 116285#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 116283#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 116281#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 116279#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 116276#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 116274#L620-36 assume !(1 == ~t5_pc~0); 116272#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 116270#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 116268#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 116266#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 116264#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 116262#L639-36 assume !(1 == ~t6_pc~0); 116259#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 116257#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 116255#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 116253#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 116251#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 116249#L658-36 assume !(1 == ~t7_pc~0); 116246#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 116244#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 116242#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 116240#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 116238#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 116236#L677-36 assume 1 == ~t8_pc~0; 116233#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 116231#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 116229#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 116227#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 116225#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 116223#L696-36 assume 1 == ~t9_pc~0; 116221#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 116218#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 116217#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 116216#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 116215#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 116214#L715-36 assume !(1 == ~t10_pc~0); 116213#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 116211#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 116210#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 116209#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 116208#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 116207#L734-36 assume !(1 == ~t11_pc~0); 116205#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 116204#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 116203#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 116202#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 116201#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 116200#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 116199#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 116197#L1218-3 assume !(1 == ~T2_E~0); 116195#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 116193#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 116191#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 116189#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 116187#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 116185#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 116183#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 116181#L1258-3 assume !(1 == ~T10_E~0); 116179#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 116177#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 116175#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 116173#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 116170#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 116168#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 116166#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 116164#L1298-3 assume !(1 == ~E_7~0); 116162#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 116160#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 116158#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 116156#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 116154#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 116152#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 116139#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 116137#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 116133#L1663 assume !(0 == start_simulation_~tmp~3#1); 116130#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 116113#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 116107#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 116104#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 116102#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 115934#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 115929#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 115912#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 99996#L1644-2 [2022-12-13 12:07:09,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:09,663 INFO L85 PathProgramCache]: Analyzing trace with hash -258324326, now seen corresponding path program 1 times [2022-12-13 12:07:09,663 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:09,664 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2138021668] [2022-12-13 12:07:09,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:09,664 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:09,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:09,704 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:09,704 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:09,704 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2138021668] [2022-12-13 12:07:09,704 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2138021668] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:09,704 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:09,704 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 12:07:09,705 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1171332696] [2022-12-13 12:07:09,705 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:09,705 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:07:09,705 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:09,705 INFO L85 PathProgramCache]: Analyzing trace with hash -50695136, now seen corresponding path program 1 times [2022-12-13 12:07:09,705 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:09,706 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1570621504] [2022-12-13 12:07:09,706 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:09,706 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:09,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:09,748 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:09,748 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:09,748 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1570621504] [2022-12-13 12:07:09,749 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1570621504] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:09,749 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:09,749 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:07:09,749 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1054204724] [2022-12-13 12:07:09,749 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:09,749 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:07:09,749 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:07:09,750 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:07:09,750 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:07:09,750 INFO L87 Difference]: Start difference. First operand 20022 states and 28432 transitions. cyclomatic complexity: 8418 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:09,962 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:07:09,962 INFO L93 Difference]: Finished difference Result 38178 states and 54029 transitions. [2022-12-13 12:07:09,962 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38178 states and 54029 transitions. [2022-12-13 12:07:10,107 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 37902 [2022-12-13 12:07:10,229 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38178 states to 38178 states and 54029 transitions. [2022-12-13 12:07:10,229 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38178 [2022-12-13 12:07:10,248 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38178 [2022-12-13 12:07:10,248 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38178 states and 54029 transitions. [2022-12-13 12:07:10,269 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:07:10,269 INFO L218 hiAutomatonCegarLoop]: Abstraction has 38178 states and 54029 transitions. [2022-12-13 12:07:10,296 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38178 states and 54029 transitions. [2022-12-13 12:07:10,630 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38178 to 38142. [2022-12-13 12:07:10,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38142 states, 38142 states have (on average 1.415578627235069) internal successors, (53993), 38141 states have internal predecessors, (53993), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:10,719 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38142 states to 38142 states and 53993 transitions. [2022-12-13 12:07:10,719 INFO L240 hiAutomatonCegarLoop]: Abstraction has 38142 states and 53993 transitions. [2022-12-13 12:07:10,720 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:07:10,720 INFO L428 stractBuchiCegarLoop]: Abstraction has 38142 states and 53993 transitions. [2022-12-13 12:07:10,720 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-12-13 12:07:10,721 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38142 states and 53993 transitions. [2022-12-13 12:07:10,824 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 37866 [2022-12-13 12:07:10,825 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:10,825 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:10,827 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:10,827 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:10,827 INFO L748 eck$LassoCheckResult]: Stem: 158143#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 158144#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 159225#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 159226#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 158598#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 158599#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 158466#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 158364#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 158086#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 157736#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 157737#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 157779#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 157780#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 158742#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 158743#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 158791#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 158188#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 158189#L1090 assume !(0 == ~M_E~0); 158237#L1090-2 assume !(0 == ~T1_E~0); 158238#L1095-1 assume !(0 == ~T2_E~0); 158950#L1100-1 assume !(0 == ~T3_E~0); 158951#L1105-1 assume !(0 == ~T4_E~0); 158005#L1110-1 assume !(0 == ~T5_E~0); 158006#L1115-1 assume !(0 == ~T6_E~0); 158402#L1120-1 assume !(0 == ~T7_E~0); 158713#L1125-1 assume !(0 == ~T8_E~0); 159339#L1130-1 assume !(0 == ~T9_E~0); 158978#L1135-1 assume !(0 == ~T10_E~0); 158194#L1140-1 assume !(0 == ~T11_E~0); 158195#L1145-1 assume !(0 == ~E_1~0); 158897#L1150-1 assume !(0 == ~E_2~0); 158378#L1155-1 assume !(0 == ~E_3~0); 158379#L1160-1 assume !(0 == ~E_4~0); 158471#L1165-1 assume !(0 == ~E_5~0); 158472#L1170-1 assume !(0 == ~E_6~0); 159202#L1175-1 assume !(0 == ~E_7~0); 158555#L1180-1 assume !(0 == ~E_8~0); 158556#L1185-1 assume !(0 == ~E_9~0); 158190#L1190-1 assume !(0 == ~E_10~0); 158191#L1195-1 assume !(0 == ~E_11~0); 158572#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 158397#L525 assume !(1 == ~m_pc~0); 157821#L525-2 is_master_triggered_~__retres1~0#1 := 0; 157822#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 159072#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 159043#L1350 assume !(0 != activate_threads_~tmp~1#1); 158180#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 158181#L544 assume !(1 == ~t1_pc~0); 158398#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 158399#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 157800#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 157801#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 158028#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 158682#L563 assume !(1 == ~t2_pc~0); 158882#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 157840#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 157841#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 158262#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 158263#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 158766#L582 assume !(1 == ~t3_pc~0); 158896#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 159292#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 157728#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 157729#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 157911#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 157912#L601 assume !(1 == ~t4_pc~0); 158913#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 158403#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 157928#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 157929#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 158908#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 159282#L620 assume !(1 == ~t5_pc~0); 158732#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 158733#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 158782#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 159079#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 159308#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 159309#L639 assume !(1 == ~t6_pc~0); 158711#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 158298#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 158299#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 158349#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 158408#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 158409#L658 assume !(1 == ~t7_pc~0); 158625#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 158626#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 159318#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 158839#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 158183#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 158184#L677 assume !(1 == ~t8_pc~0); 158207#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 157993#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 157994#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 158255#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 158256#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 159028#L696 assume !(1 == ~t9_pc~0); 158696#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 158697#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 158457#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 158458#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 158719#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 158956#L715 assume 1 == ~t10_pc~0; 158966#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 158817#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 158612#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 158613#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 158548#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 157981#L734 assume !(1 == ~t11_pc~0); 157982#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 158476#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 158560#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 157726#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 157727#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 158783#L1213 assume !(1 == ~M_E~0); 158546#L1213-2 assume !(1 == ~T1_E~0); 158547#L1218-1 assume !(1 == ~T2_E~0); 157757#L1223-1 assume !(1 == ~T3_E~0); 157758#L1228-1 assume !(1 == ~T4_E~0); 158520#L1233-1 assume !(1 == ~T5_E~0); 159310#L1238-1 assume !(1 == ~T6_E~0); 158906#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 158907#L1248-1 assume !(1 == ~T8_E~0); 158962#L1253-1 assume !(1 == ~T9_E~0); 158963#L1258-1 assume !(1 == ~T10_E~0); 158934#L1263-1 assume !(1 == ~T11_E~0); 158935#L1268-1 assume !(1 == ~E_1~0); 158737#L1273-1 assume !(1 == ~E_2~0); 158738#L1278-1 assume !(1 == ~E_3~0); 158294#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 158295#L1288-1 assume !(1 == ~E_5~0); 159086#L1293-1 assume !(1 == ~E_6~0); 159037#L1298-1 assume !(1 == ~E_7~0); 158770#L1303-1 assume !(1 == ~E_8~0); 158305#L1308-1 assume !(1 == ~E_9~0); 158198#L1313-1 assume !(1 == ~E_10~0); 158199#L1318-1 assume !(1 == ~E_11~0); 158208#L1323-1 assume { :end_inline_reset_delta_events } true; 158209#L1644-2 [2022-12-13 12:07:10,827 INFO L750 eck$LassoCheckResult]: Loop: 158209#L1644-2 assume !false; 189267#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 189260#L1065 assume !false; 189258#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 189231#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 189219#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 189216#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 189210#L906 assume !(0 != eval_~tmp~0#1); 189211#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 189836#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 189835#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 189834#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 189833#L1095-3 assume !(0 == ~T2_E~0); 189832#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 189831#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 189830#L1110-3 assume !(0 == ~T5_E~0); 189829#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 189828#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 189827#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 189826#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 189825#L1135-3 assume !(0 == ~T10_E~0); 189824#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 189823#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 189822#L1150-3 assume !(0 == ~E_2~0); 189821#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 189820#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 189819#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 189818#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 189817#L1175-3 assume !(0 == ~E_7~0); 189816#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 189815#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 189814#L1190-3 assume !(0 == ~E_10~0); 189813#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 189812#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 189811#L525-36 assume !(1 == ~m_pc~0); 189810#L525-38 is_master_triggered_~__retres1~0#1 := 0; 189809#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 189808#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 189807#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 189806#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 189805#L544-36 assume !(1 == ~t1_pc~0); 189804#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 189803#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 189802#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 189801#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 189800#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 189799#L563-36 assume 1 == ~t2_pc~0; 189798#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 189796#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 189795#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 189794#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 189793#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 189792#L582-36 assume !(1 == ~t3_pc~0); 189791#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 189790#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 189789#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 189787#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 189785#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 189783#L601-36 assume !(1 == ~t4_pc~0); 189780#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 189778#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 189776#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 189774#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 189772#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 189770#L620-36 assume !(1 == ~t5_pc~0); 189768#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 189766#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 189764#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 189762#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 189759#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 189757#L639-36 assume !(1 == ~t6_pc~0); 189754#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 189752#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 189750#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 189748#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 189746#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 189744#L658-36 assume !(1 == ~t7_pc~0); 189741#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 189738#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 189735#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 189732#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 189728#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 189725#L677-36 assume !(1 == ~t8_pc~0); 189722#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 189719#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 189716#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 189713#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 189710#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 189706#L696-36 assume 1 == ~t9_pc~0; 189702#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 189697#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 189692#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 189687#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 189681#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 189675#L715-36 assume 1 == ~t10_pc~0; 189668#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 189662#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 189656#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 189649#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 189643#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 189637#L734-36 assume 1 == ~t11_pc~0; 189630#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 189623#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 189616#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 189610#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 189603#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 189597#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 189590#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 189584#L1218-3 assume !(1 == ~T2_E~0); 189578#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 189572#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 189565#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 189559#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 189552#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 189546#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 189539#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 189533#L1258-3 assume !(1 == ~T10_E~0); 189525#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 189519#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 189512#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 189505#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 189499#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 189493#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 189486#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 189480#L1298-3 assume !(1 == ~E_7~0); 189473#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 189467#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 189461#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 189455#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 189448#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 189394#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 189376#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 189370#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 189362#L1663 assume !(0 == start_simulation_~tmp~3#1); 189359#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 189323#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 189314#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 189309#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 189304#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 189297#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 189289#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 189283#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 158209#L1644-2 [2022-12-13 12:07:10,828 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:10,828 INFO L85 PathProgramCache]: Analyzing trace with hash 1174510393, now seen corresponding path program 1 times [2022-12-13 12:07:10,828 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:10,828 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [503600353] [2022-12-13 12:07:10,828 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:10,828 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:10,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:10,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:10,927 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:10,927 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [503600353] [2022-12-13 12:07:10,927 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [503600353] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:10,927 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:10,927 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:07:10,927 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1186304] [2022-12-13 12:07:10,928 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:10,928 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:07:10,928 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:10,928 INFO L85 PathProgramCache]: Analyzing trace with hash -1234499647, now seen corresponding path program 1 times [2022-12-13 12:07:10,928 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:10,928 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1242263635] [2022-12-13 12:07:10,928 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:10,928 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:10,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:10,968 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:10,968 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:10,968 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1242263635] [2022-12-13 12:07:10,968 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1242263635] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:10,968 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:10,968 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:07:10,969 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2111590858] [2022-12-13 12:07:10,969 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:10,969 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:07:10,969 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:07:10,969 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 12:07:10,969 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 12:07:10,969 INFO L87 Difference]: Start difference. First operand 38142 states and 53993 transitions. cyclomatic complexity: 15867 Second operand has 5 states, 5 states have (on average 27.4) internal successors, (137), 5 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:11,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:07:11,323 INFO L93 Difference]: Finished difference Result 88469 states and 126442 transitions. [2022-12-13 12:07:11,323 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 88469 states and 126442 transitions. [2022-12-13 12:07:11,651 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 87860 [2022-12-13 12:07:11,870 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 88469 states to 88469 states and 126442 transitions. [2022-12-13 12:07:11,870 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 88469 [2022-12-13 12:07:11,896 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 88469 [2022-12-13 12:07:11,896 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88469 states and 126442 transitions. [2022-12-13 12:07:11,935 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:07:11,935 INFO L218 hiAutomatonCegarLoop]: Abstraction has 88469 states and 126442 transitions. [2022-12-13 12:07:11,966 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88469 states and 126442 transitions. [2022-12-13 12:07:12,351 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88469 to 39237. [2022-12-13 12:07:12,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39237 states, 39237 states have (on average 1.4039809363610878) internal successors, (55088), 39236 states have internal predecessors, (55088), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:12,454 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39237 states to 39237 states and 55088 transitions. [2022-12-13 12:07:12,455 INFO L240 hiAutomatonCegarLoop]: Abstraction has 39237 states and 55088 transitions. [2022-12-13 12:07:12,455 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 12:07:12,455 INFO L428 stractBuchiCegarLoop]: Abstraction has 39237 states and 55088 transitions. [2022-12-13 12:07:12,455 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-12-13 12:07:12,455 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39237 states and 55088 transitions. [2022-12-13 12:07:12,553 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 38958 [2022-12-13 12:07:12,553 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:12,553 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:12,555 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:12,555 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:12,555 INFO L748 eck$LassoCheckResult]: Stem: 284766#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 284767#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 285875#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 285876#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 285222#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 285223#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 285089#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 284985#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 284709#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 284362#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 284363#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 284405#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 284406#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 285366#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 285367#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 285417#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 284811#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 284812#L1090 assume !(0 == ~M_E~0); 284860#L1090-2 assume !(0 == ~T1_E~0); 284861#L1095-1 assume !(0 == ~T2_E~0); 285581#L1100-1 assume !(0 == ~T3_E~0); 285582#L1105-1 assume !(0 == ~T4_E~0); 284628#L1110-1 assume !(0 == ~T5_E~0); 284629#L1115-1 assume !(0 == ~T6_E~0); 285025#L1120-1 assume !(0 == ~T7_E~0); 285335#L1125-1 assume !(0 == ~T8_E~0); 286002#L1130-1 assume !(0 == ~T9_E~0); 285608#L1135-1 assume !(0 == ~T10_E~0); 284817#L1140-1 assume !(0 == ~T11_E~0); 284818#L1145-1 assume !(0 == ~E_1~0); 285531#L1150-1 assume !(0 == ~E_2~0); 284999#L1155-1 assume !(0 == ~E_3~0); 285000#L1160-1 assume !(0 == ~E_4~0); 285094#L1165-1 assume !(0 == ~E_5~0); 285095#L1170-1 assume !(0 == ~E_6~0); 285845#L1175-1 assume !(0 == ~E_7~0); 285179#L1180-1 assume !(0 == ~E_8~0); 285180#L1185-1 assume !(0 == ~E_9~0); 284813#L1190-1 assume !(0 == ~E_10~0); 284814#L1195-1 assume !(0 == ~E_11~0); 285196#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 285015#L525 assume !(1 == ~m_pc~0); 284446#L525-2 is_master_triggered_~__retres1~0#1 := 0; 284447#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 285709#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 285675#L1350 assume !(0 != activate_threads_~tmp~1#1); 284804#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 284805#L544 assume !(1 == ~t1_pc~0); 285021#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 285022#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 284423#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 284424#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 284652#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 285305#L563 assume !(1 == ~t2_pc~0); 285515#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 284465#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 284466#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 284882#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 284883#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 285391#L582 assume !(1 == ~t3_pc~0); 285530#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 285944#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 284354#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 284355#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 284534#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 284535#L601 assume !(1 == ~t4_pc~0); 285547#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 285026#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 284549#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 284550#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 285542#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 285934#L620 assume !(1 == ~t5_pc~0); 285356#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 285357#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 285408#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 285717#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 285959#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 285960#L639 assume !(1 == ~t6_pc~0); 285333#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 284920#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 284921#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 284969#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 285029#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 285030#L658 assume !(1 == ~t7_pc~0); 285245#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 285246#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 285968#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 285464#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 284807#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 284808#L677 assume !(1 == ~t8_pc~0); 284829#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 284614#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 284615#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 284878#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 284879#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 285663#L696 assume !(1 == ~t9_pc~0); 285316#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 285317#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 285423#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 285342#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 285343#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 285587#L715 assume 1 == ~t10_pc~0; 285597#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 285443#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 285234#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 285235#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 285172#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 284605#L734 assume !(1 == ~t11_pc~0); 284606#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 285096#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 285183#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 284352#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 284353#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 285409#L1213 assume !(1 == ~M_E~0); 285169#L1213-2 assume !(1 == ~T1_E~0); 285170#L1218-1 assume !(1 == ~T2_E~0); 284383#L1223-1 assume !(1 == ~T3_E~0); 284384#L1228-1 assume !(1 == ~T4_E~0); 285146#L1233-1 assume !(1 == ~T5_E~0); 285961#L1238-1 assume !(1 == ~T6_E~0); 285540#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 285541#L1248-1 assume !(1 == ~T8_E~0); 285593#L1253-1 assume !(1 == ~T9_E~0); 285594#L1258-1 assume !(1 == ~T10_E~0); 285565#L1263-1 assume !(1 == ~T11_E~0); 285566#L1268-1 assume !(1 == ~E_1~0); 285361#L1273-1 assume !(1 == ~E_2~0); 285362#L1278-1 assume !(1 == ~E_3~0); 284916#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 284917#L1288-1 assume !(1 == ~E_5~0); 285725#L1293-1 assume !(1 == ~E_6~0); 285672#L1298-1 assume !(1 == ~E_7~0); 285395#L1303-1 assume !(1 == ~E_8~0); 284926#L1308-1 assume !(1 == ~E_9~0); 284821#L1313-1 assume !(1 == ~E_10~0); 284822#L1318-1 assume !(1 == ~E_11~0); 284830#L1323-1 assume { :end_inline_reset_delta_events } true; 284831#L1644-2 [2022-12-13 12:07:12,556 INFO L750 eck$LassoCheckResult]: Loop: 284831#L1644-2 assume !false; 304232#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 304227#L1065 assume !false; 304226#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 304223#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 304213#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 304212#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 304210#L906 assume !(0 != eval_~tmp~0#1); 304211#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 306754#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 306752#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 306750#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 306748#L1095-3 assume !(0 == ~T2_E~0); 306746#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 306744#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 306742#L1110-3 assume !(0 == ~T5_E~0); 306740#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 306738#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 306737#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 306721#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 306716#L1135-3 assume !(0 == ~T10_E~0); 306711#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 306706#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 306701#L1150-3 assume !(0 == ~E_2~0); 306697#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 306693#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 306628#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 306623#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 306479#L1175-3 assume !(0 == ~E_7~0); 306473#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 306468#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 306461#L1190-3 assume !(0 == ~E_10~0); 306389#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 306385#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 306384#L525-36 assume !(1 == ~m_pc~0); 306383#L525-38 is_master_triggered_~__retres1~0#1 := 0; 306382#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 306381#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 306380#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 306379#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 306378#L544-36 assume !(1 == ~t1_pc~0); 306377#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 306376#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 306375#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 306374#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 306373#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 306372#L563-36 assume !(1 == ~t2_pc~0); 306370#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 306369#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 306368#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 306367#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 306366#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 306365#L582-36 assume !(1 == ~t3_pc~0); 306364#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 306363#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 306362#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 306361#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 306360#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 306359#L601-36 assume !(1 == ~t4_pc~0); 306357#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 306356#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 306355#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 306354#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 306353#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 306352#L620-36 assume !(1 == ~t5_pc~0); 306351#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 306350#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 306349#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 306348#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 306347#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 306346#L639-36 assume !(1 == ~t6_pc~0); 306344#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 306343#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 306342#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 306341#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 306340#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 306339#L658-36 assume !(1 == ~t7_pc~0); 306337#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 306336#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 306335#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 306334#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 306333#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 306332#L677-36 assume !(1 == ~t8_pc~0); 306331#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 306330#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 306329#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 306328#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 306327#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 306326#L696-36 assume 1 == ~t9_pc~0; 306324#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 306322#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 306320#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 306318#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 306313#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 306306#L715-36 assume 1 == ~t10_pc~0; 306300#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 306294#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 306289#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 306284#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 306279#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 306273#L734-36 assume 1 == ~t11_pc~0; 306268#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 306262#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 306257#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 306252#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 306247#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 306242#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 306238#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 306167#L1218-3 assume !(1 == ~T2_E~0); 306162#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 306157#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 306151#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 306146#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 306141#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 306136#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 306131#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 306126#L1258-3 assume !(1 == ~T10_E~0); 306054#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 306049#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 306044#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 306038#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 306033#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 306028#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 306023#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 306019#L1298-3 assume !(1 == ~E_7~0); 306015#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 305944#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 305939#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 305934#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 305929#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 305756#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 305739#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 305732#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 305725#L1663 assume !(0 == start_simulation_~tmp~3#1); 305721#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 305632#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 305622#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 305615#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 305610#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 304246#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 304242#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 304237#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 284831#L1644-2 [2022-12-13 12:07:12,556 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:12,556 INFO L85 PathProgramCache]: Analyzing trace with hash 145151095, now seen corresponding path program 1 times [2022-12-13 12:07:12,556 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:12,556 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1509003451] [2022-12-13 12:07:12,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:12,557 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:12,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:12,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:12,614 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:12,614 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1509003451] [2022-12-13 12:07:12,614 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1509003451] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:12,614 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:12,614 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:12,614 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1995992394] [2022-12-13 12:07:12,615 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:12,615 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:07:12,615 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:12,615 INFO L85 PathProgramCache]: Analyzing trace with hash -878903200, now seen corresponding path program 1 times [2022-12-13 12:07:12,616 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:12,616 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [711647230] [2022-12-13 12:07:12,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:12,616 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:12,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:12,667 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:12,668 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:12,668 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [711647230] [2022-12-13 12:07:12,668 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [711647230] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:12,668 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:12,668 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:07:12,668 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1535600718] [2022-12-13 12:07:12,668 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:12,669 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:07:12,669 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:07:12,669 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:07:12,669 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:07:12,670 INFO L87 Difference]: Start difference. First operand 39237 states and 55088 transitions. cyclomatic complexity: 15867 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:13,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:07:13,184 INFO L93 Difference]: Finished difference Result 110204 states and 153821 transitions. [2022-12-13 12:07:13,184 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 110204 states and 153821 transitions. [2022-12-13 12:07:13,541 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 108078 [2022-12-13 12:07:13,754 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 110204 states to 110204 states and 153821 transitions. [2022-12-13 12:07:13,754 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 110204 [2022-12-13 12:07:13,812 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 110204 [2022-12-13 12:07:13,812 INFO L73 IsDeterministic]: Start isDeterministic. Operand 110204 states and 153821 transitions. [2022-12-13 12:07:13,866 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:07:13,866 INFO L218 hiAutomatonCegarLoop]: Abstraction has 110204 states and 153821 transitions. [2022-12-13 12:07:13,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110204 states and 153821 transitions. [2022-12-13 12:07:14,767 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110204 to 108040. [2022-12-13 12:07:14,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108040 states, 108040 states have (on average 1.397972972972973) internal successors, (151037), 108039 states have internal predecessors, (151037), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:15,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108040 states to 108040 states and 151037 transitions. [2022-12-13 12:07:15,093 INFO L240 hiAutomatonCegarLoop]: Abstraction has 108040 states and 151037 transitions. [2022-12-13 12:07:15,093 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:07:15,094 INFO L428 stractBuchiCegarLoop]: Abstraction has 108040 states and 151037 transitions. [2022-12-13 12:07:15,094 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-12-13 12:07:15,094 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108040 states and 151037 transitions. [2022-12-13 12:07:15,340 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 107538 [2022-12-13 12:07:15,340 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:15,340 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:15,342 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:15,342 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:15,343 INFO L748 eck$LassoCheckResult]: Stem: 434219#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 434220#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 435315#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 435316#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 434680#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 434681#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 434547#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 434440#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 434162#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 433815#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 433816#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 433859#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 433860#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 434828#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 434829#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 434876#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 434263#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 434264#L1090 assume !(0 == ~M_E~0); 434306#L1090-2 assume !(0 == ~T1_E~0); 434307#L1095-1 assume !(0 == ~T2_E~0); 435040#L1100-1 assume !(0 == ~T3_E~0); 435041#L1105-1 assume !(0 == ~T4_E~0); 434082#L1110-1 assume !(0 == ~T5_E~0); 434083#L1115-1 assume !(0 == ~T6_E~0); 434480#L1120-1 assume !(0 == ~T7_E~0); 434799#L1125-1 assume !(0 == ~T8_E~0); 435433#L1130-1 assume !(0 == ~T9_E~0); 435063#L1135-1 assume !(0 == ~T10_E~0); 434268#L1140-1 assume !(0 == ~T11_E~0); 434269#L1145-1 assume !(0 == ~E_1~0); 434991#L1150-1 assume !(0 == ~E_2~0); 434456#L1155-1 assume !(0 == ~E_3~0); 434457#L1160-1 assume !(0 == ~E_4~0); 434553#L1165-1 assume !(0 == ~E_5~0); 434554#L1170-1 assume !(0 == ~E_6~0); 435292#L1175-1 assume !(0 == ~E_7~0); 434638#L1180-1 assume !(0 == ~E_8~0); 434639#L1185-1 assume !(0 == ~E_9~0); 434265#L1190-1 assume !(0 == ~E_10~0); 434266#L1195-1 assume !(0 == ~E_11~0); 434654#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 434472#L525 assume !(1 == ~m_pc~0); 433900#L525-2 is_master_triggered_~__retres1~0#1 := 0; 433901#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 435159#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 435128#L1350 assume !(0 != activate_threads_~tmp~1#1); 434255#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 434256#L544 assume !(1 == ~t1_pc~0); 434478#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 434479#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 433875#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 433876#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 434107#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 434764#L563 assume !(1 == ~t2_pc~0); 434976#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 433919#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 433920#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 434333#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 434334#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 434855#L582 assume !(1 == ~t3_pc~0); 434990#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 435380#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 433807#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 433808#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 433988#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 433989#L601 assume !(1 == ~t4_pc~0); 435005#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 434481#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 434001#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 434002#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 435000#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 435374#L620 assume !(1 == ~t5_pc~0); 434817#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 434818#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 434873#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 435164#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 435396#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 435397#L639 assume !(1 == ~t6_pc~0); 434797#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 434372#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 434373#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 434424#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 434486#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 434487#L658 assume !(1 == ~t7_pc~0); 434705#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 434706#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 435405#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 434931#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 434259#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 434260#L677 assume !(1 == ~t8_pc~0); 434279#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 434065#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 434066#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 434329#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 434330#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 435118#L696 assume !(1 == ~t9_pc~0); 434775#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 434776#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 435492#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 434804#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 434805#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 435045#L715 assume !(1 == ~t10_pc~0); 435336#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 434908#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 434692#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 434693#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 434631#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 434059#L734 assume !(1 == ~t11_pc~0); 434060#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 434555#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 434641#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 433803#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 433804#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 434874#L1213 assume !(1 == ~M_E~0); 434628#L1213-2 assume !(1 == ~T1_E~0); 434629#L1218-1 assume !(1 == ~T2_E~0); 433836#L1223-1 assume !(1 == ~T3_E~0); 433837#L1228-1 assume !(1 == ~T4_E~0); 434602#L1233-1 assume !(1 == ~T5_E~0); 435398#L1238-1 assume !(1 == ~T6_E~0); 434998#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 434999#L1248-1 assume !(1 == ~T8_E~0); 435051#L1253-1 assume !(1 == ~T9_E~0); 435052#L1258-1 assume !(1 == ~T10_E~0); 435025#L1263-1 assume !(1 == ~T11_E~0); 435026#L1268-1 assume !(1 == ~E_1~0); 434824#L1273-1 assume !(1 == ~E_2~0); 434825#L1278-1 assume !(1 == ~E_3~0); 434370#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 434371#L1288-1 assume !(1 == ~E_5~0); 435171#L1293-1 assume !(1 == ~E_6~0); 435123#L1298-1 assume !(1 == ~E_7~0); 434859#L1303-1 assume !(1 == ~E_8~0); 434381#L1308-1 assume !(1 == ~E_9~0); 434272#L1313-1 assume !(1 == ~E_10~0); 434273#L1318-1 assume !(1 == ~E_11~0); 434280#L1323-1 assume { :end_inline_reset_delta_events } true; 434281#L1644-2 [2022-12-13 12:07:15,343 INFO L750 eck$LassoCheckResult]: Loop: 434281#L1644-2 assume !false; 524754#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 524745#L1065 assume !false; 524742#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 524728#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 524714#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 524709#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 524700#L906 assume !(0 != eval_~tmp~0#1); 524701#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 525404#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 525403#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 525402#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 525401#L1095-3 assume !(0 == ~T2_E~0); 525400#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 525399#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 525398#L1110-3 assume !(0 == ~T5_E~0); 525397#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 525396#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 525395#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 525394#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 525393#L1135-3 assume !(0 == ~T10_E~0); 525392#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 525391#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 525390#L1150-3 assume !(0 == ~E_2~0); 525389#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 525388#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 525387#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 525386#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 525385#L1175-3 assume !(0 == ~E_7~0); 525384#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 525383#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 525382#L1190-3 assume !(0 == ~E_10~0); 525381#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 525380#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 525379#L525-36 assume !(1 == ~m_pc~0); 525378#L525-38 is_master_triggered_~__retres1~0#1 := 0; 525377#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 525376#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 525375#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 525374#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 525373#L544-36 assume !(1 == ~t1_pc~0); 525372#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 525371#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 525370#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 525369#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 525368#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 525367#L563-36 assume !(1 == ~t2_pc~0); 525365#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 525364#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 525363#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 525362#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 525361#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 525360#L582-36 assume !(1 == ~t3_pc~0); 525359#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 525358#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 525357#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 525356#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 525355#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 525354#L601-36 assume !(1 == ~t4_pc~0); 525352#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 525351#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 525350#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 525349#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 525348#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 525347#L620-36 assume !(1 == ~t5_pc~0); 525346#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 525345#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 525344#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 525343#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 525342#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 525341#L639-36 assume !(1 == ~t6_pc~0); 525339#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 525338#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 525337#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 525335#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 525333#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 525331#L658-36 assume !(1 == ~t7_pc~0); 525328#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 525325#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 525321#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 525317#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 525313#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 525308#L677-36 assume !(1 == ~t8_pc~0); 525303#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 525298#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 525293#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 525288#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 525281#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 525273#L696-36 assume 1 == ~t9_pc~0; 525272#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 525271#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 525269#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 525245#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 525243#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 525241#L715-36 assume !(1 == ~t10_pc~0); 525239#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 525237#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 525235#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 525233#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 525228#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 525223#L734-36 assume !(1 == ~t11_pc~0); 525216#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 525210#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 525203#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 525197#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 525190#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 525184#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 525178#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 525172#L1218-3 assume !(1 == ~T2_E~0); 525166#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 525160#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 525154#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 525148#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 525141#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 525134#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 525127#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 525120#L1258-3 assume !(1 == ~T10_E~0); 525113#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 525107#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 525101#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 525094#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 525088#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 525081#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 525075#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 525069#L1298-3 assume !(1 == ~E_7~0); 525062#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 525055#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 525049#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 525042#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 525036#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 524932#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 524915#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 524909#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 524902#L1663 assume !(0 == start_simulation_~tmp~3#1); 524900#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 524830#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 524817#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 524810#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 524796#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 524785#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 524777#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 524770#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 434281#L1644-2 [2022-12-13 12:07:15,343 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:15,343 INFO L85 PathProgramCache]: Analyzing trace with hash -1619665514, now seen corresponding path program 1 times [2022-12-13 12:07:15,344 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:15,344 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2049259085] [2022-12-13 12:07:15,344 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:15,344 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:15,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:15,403 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:15,403 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:15,404 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2049259085] [2022-12-13 12:07:15,404 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2049259085] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:15,404 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:15,404 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:15,404 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1288649643] [2022-12-13 12:07:15,404 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:15,405 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:07:15,405 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:15,405 INFO L85 PathProgramCache]: Analyzing trace with hash -1601582882, now seen corresponding path program 1 times [2022-12-13 12:07:15,405 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:15,405 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [162720065] [2022-12-13 12:07:15,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:15,406 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:15,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:15,456 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:15,456 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:15,456 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [162720065] [2022-12-13 12:07:15,456 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [162720065] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:15,456 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:15,456 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:07:15,457 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1695665016] [2022-12-13 12:07:15,457 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:15,457 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:07:15,457 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:07:15,457 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:07:15,458 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:07:15,458 INFO L87 Difference]: Start difference. First operand 108040 states and 151037 transitions. cyclomatic complexity: 43029 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:16,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:07:16,121 INFO L93 Difference]: Finished difference Result 227739 states and 318355 transitions. [2022-12-13 12:07:16,121 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 227739 states and 318355 transitions. [2022-12-13 12:07:16,908 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 226760 [2022-12-13 12:07:17,442 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 227739 states to 227739 states and 318355 transitions. [2022-12-13 12:07:17,442 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 227739 [2022-12-13 12:07:17,526 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 227739 [2022-12-13 12:07:17,526 INFO L73 IsDeterministic]: Start isDeterministic. Operand 227739 states and 318355 transitions. [2022-12-13 12:07:17,597 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:07:17,597 INFO L218 hiAutomatonCegarLoop]: Abstraction has 227739 states and 318355 transitions. [2022-12-13 12:07:17,688 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 227739 states and 318355 transitions. [2022-12-13 12:07:18,648 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 227739 to 119829. [2022-12-13 12:07:18,718 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 119829 states, 119829 states have (on average 1.3996194577272614) internal successors, (167715), 119828 states have internal predecessors, (167715), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:19,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119829 states to 119829 states and 167715 transitions. [2022-12-13 12:07:19,038 INFO L240 hiAutomatonCegarLoop]: Abstraction has 119829 states and 167715 transitions. [2022-12-13 12:07:19,039 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:07:19,039 INFO L428 stractBuchiCegarLoop]: Abstraction has 119829 states and 167715 transitions. [2022-12-13 12:07:19,039 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-12-13 12:07:19,039 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 119829 states and 167715 transitions. [2022-12-13 12:07:19,341 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 119222 [2022-12-13 12:07:19,341 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:19,341 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:19,342 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:19,342 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:19,343 INFO L748 eck$LassoCheckResult]: Stem: 770008#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 770009#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 771109#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 771110#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 770474#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 770475#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 770339#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 770230#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 769951#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 769606#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 769607#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 769650#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 769651#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 770627#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 770628#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 770676#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 770053#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 770054#L1090 assume !(0 == ~M_E~0); 770097#L1090-2 assume !(0 == ~T1_E~0); 770098#L1095-1 assume !(0 == ~T2_E~0); 770844#L1100-1 assume !(0 == ~T3_E~0); 770845#L1105-1 assume !(0 == ~T4_E~0); 769871#L1110-1 assume !(0 == ~T5_E~0); 769872#L1115-1 assume !(0 == ~T6_E~0); 770273#L1120-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 770596#L1125-1 assume !(0 == ~T8_E~0); 771226#L1130-1 assume !(0 == ~T9_E~0); 771334#L1135-1 assume !(0 == ~T10_E~0); 771333#L1140-1 assume !(0 == ~T11_E~0); 770794#L1145-1 assume !(0 == ~E_1~0); 770795#L1150-1 assume !(0 == ~E_2~0); 770839#L1155-1 assume !(0 == ~E_3~0); 771213#L1160-1 assume !(0 == ~E_4~0); 770345#L1165-1 assume !(0 == ~E_5~0); 770346#L1170-1 assume !(0 == ~E_6~0); 771191#L1175-1 assume !(0 == ~E_7~0); 770430#L1180-1 assume !(0 == ~E_8~0); 770431#L1185-1 assume !(0 == ~E_9~0); 770055#L1190-1 assume !(0 == ~E_10~0); 770056#L1195-1 assume !(0 == ~E_11~0); 770446#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 771057#L525 assume !(1 == ~m_pc~0); 771325#L525-2 is_master_triggered_~__retres1~0#1 := 0; 771324#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 771323#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 771322#L1350 assume !(0 != activate_threads_~tmp~1#1); 771321#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 770503#L544 assume !(1 == ~t1_pc~0); 770504#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 770790#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 770791#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 769895#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 769896#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 771320#L563 assume !(1 == ~t2_pc~0); 770775#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 770776#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 770245#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 770246#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 770653#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 770654#L582 assume !(1 == ~t3_pc~0); 771223#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 771224#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 771319#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 771096#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 769778#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 769779#L601 assume !(1 == ~t4_pc~0); 771316#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 770274#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 769791#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 769792#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 770803#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 771163#L620 assume !(1 == ~t5_pc~0); 771164#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 770671#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 770672#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 770963#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 771183#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 771184#L639 assume !(1 == ~t6_pc~0); 770594#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 770595#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 770214#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 770215#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 771311#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 771310#L658 assume !(1 == ~t7_pc~0); 770500#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 770501#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 771240#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 771241#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 771308#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 771307#L677 assume !(1 == ~t8_pc~0); 770069#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 770070#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 771306#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 770120#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 770121#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 770919#L696 assume !(1 == ~t9_pc~0); 771009#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 771301#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 771300#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 771297#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 771296#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 771129#L715 assume !(1 == ~t10_pc~0); 771130#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 770707#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 770488#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 770489#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 770422#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 770423#L734 assume !(1 == ~t11_pc~0); 771291#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 771290#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 770740#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 770741#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 770673#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 770674#L1213 assume !(1 == ~M_E~0); 771289#L1213-2 assume !(1 == ~T1_E~0); 771288#L1218-1 assume !(1 == ~T2_E~0); 771287#L1223-1 assume !(1 == ~T3_E~0); 771286#L1228-1 assume !(1 == ~T4_E~0); 771185#L1233-1 assume !(1 == ~T5_E~0); 771186#L1238-1 assume !(1 == ~T6_E~0); 771285#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 770802#L1248-1 assume !(1 == ~T8_E~0); 770855#L1253-1 assume !(1 == ~T9_E~0); 770856#L1258-1 assume !(1 == ~T10_E~0); 770828#L1263-1 assume !(1 == ~T11_E~0); 770829#L1268-1 assume !(1 == ~E_1~0); 770623#L1273-1 assume !(1 == ~E_2~0); 770624#L1278-1 assume !(1 == ~E_3~0); 770160#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 770161#L1288-1 assume !(1 == ~E_5~0); 770972#L1293-1 assume !(1 == ~E_6~0); 770924#L1298-1 assume !(1 == ~E_7~0); 770658#L1303-1 assume !(1 == ~E_8~0); 770170#L1308-1 assume !(1 == ~E_9~0); 770062#L1313-1 assume !(1 == ~E_10~0); 770063#L1318-1 assume !(1 == ~E_11~0); 770071#L1323-1 assume { :end_inline_reset_delta_events } true; 770072#L1644-2 [2022-12-13 12:07:19,343 INFO L750 eck$LassoCheckResult]: Loop: 770072#L1644-2 assume !false; 852532#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 852526#L1065 assume !false; 852524#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 852515#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 852504#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 852502#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 852499#L906 assume !(0 != eval_~tmp~0#1); 852500#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 852744#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 852743#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 852742#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 852741#L1095-3 assume !(0 == ~T2_E~0); 852740#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 852739#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 852738#L1110-3 assume !(0 == ~T5_E~0); 852737#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 852735#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 852734#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 852733#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 852732#L1135-3 assume !(0 == ~T10_E~0); 852731#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 852730#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 852729#L1150-3 assume !(0 == ~E_2~0); 852728#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 852727#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 852726#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 852725#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 852724#L1175-3 assume !(0 == ~E_7~0); 852723#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 852722#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 852721#L1190-3 assume !(0 == ~E_10~0); 852720#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 852719#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 852718#L525-36 assume !(1 == ~m_pc~0); 852717#L525-38 is_master_triggered_~__retres1~0#1 := 0; 852716#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 852715#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 852714#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 852713#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 852712#L544-36 assume !(1 == ~t1_pc~0); 852711#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 852710#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 852709#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 852708#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 852707#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 852706#L563-36 assume 1 == ~t2_pc~0; 852705#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 852703#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 852702#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 852701#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 852700#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 852699#L582-36 assume !(1 == ~t3_pc~0); 852698#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 852697#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 852696#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 852695#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 852694#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 852693#L601-36 assume 1 == ~t4_pc~0; 852692#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 852690#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 852689#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 852688#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 852687#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 852686#L620-36 assume !(1 == ~t5_pc~0); 852685#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 852684#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 852683#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 852682#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 852681#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 852680#L639-36 assume 1 == ~t6_pc~0; 852679#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 852677#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 852676#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 852675#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 852674#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 852673#L658-36 assume !(1 == ~t7_pc~0); 852671#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 852670#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 852669#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 852668#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 852667#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 852666#L677-36 assume !(1 == ~t8_pc~0); 852665#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 852664#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 852663#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 852662#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 852661#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 852660#L696-36 assume !(1 == ~t9_pc~0); 852659#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 852657#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 852655#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 852653#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 852651#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 852650#L715-36 assume !(1 == ~t10_pc~0); 852649#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 852648#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 852647#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 852646#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 852645#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 852644#L734-36 assume 1 == ~t11_pc~0; 852643#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 852641#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 852640#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 852639#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 852638#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 852637#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 852636#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 852635#L1218-3 assume !(1 == ~T2_E~0); 852634#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 852633#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 852632#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 852631#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 852629#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 852627#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 852624#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 852622#L1258-3 assume !(1 == ~T10_E~0); 852620#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 852618#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 852616#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 852614#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 852612#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 852610#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 852608#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 852606#L1298-3 assume !(1 == ~E_7~0); 852604#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 852602#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 852599#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 852597#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 852595#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 852593#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 852580#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 852577#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 852574#L1663 assume !(0 == start_simulation_~tmp~3#1); 852571#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 852554#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 852546#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 852544#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 852542#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 852540#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 852537#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 852535#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 770072#L1644-2 [2022-12-13 12:07:19,343 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:19,344 INFO L85 PathProgramCache]: Analyzing trace with hash 948156820, now seen corresponding path program 1 times [2022-12-13 12:07:19,344 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:19,344 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [741761680] [2022-12-13 12:07:19,344 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:19,344 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:19,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:19,407 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:19,407 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:19,407 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [741761680] [2022-12-13 12:07:19,407 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [741761680] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:19,407 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:19,408 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:19,408 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1283446687] [2022-12-13 12:07:19,408 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:19,408 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:07:19,409 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:19,409 INFO L85 PathProgramCache]: Analyzing trace with hash 760377663, now seen corresponding path program 1 times [2022-12-13 12:07:19,409 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:19,409 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1454071797] [2022-12-13 12:07:19,409 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:19,409 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:19,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:19,471 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:19,472 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:19,472 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1454071797] [2022-12-13 12:07:19,472 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1454071797] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:19,472 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:19,472 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:07:19,472 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [444972783] [2022-12-13 12:07:19,472 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:19,473 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:07:19,473 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:07:19,473 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:07:19,473 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:07:19,473 INFO L87 Difference]: Start difference. First operand 119829 states and 167715 transitions. cyclomatic complexity: 47918 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:19,872 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:07:19,872 INFO L93 Difference]: Finished difference Result 108040 states and 150711 transitions. [2022-12-13 12:07:19,872 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 108040 states and 150711 transitions. [2022-12-13 12:07:20,220 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 107538 [2022-12-13 12:07:20,451 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 108040 states to 108040 states and 150711 transitions. [2022-12-13 12:07:20,452 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 108040 [2022-12-13 12:07:20,505 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 108040 [2022-12-13 12:07:20,505 INFO L73 IsDeterministic]: Start isDeterministic. Operand 108040 states and 150711 transitions. [2022-12-13 12:07:20,557 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:07:20,557 INFO L218 hiAutomatonCegarLoop]: Abstraction has 108040 states and 150711 transitions. [2022-12-13 12:07:20,611 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108040 states and 150711 transitions. [2022-12-13 12:07:21,391 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108040 to 108040. [2022-12-13 12:07:21,463 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108040 states, 108040 states have (on average 1.3949555720103666) internal successors, (150711), 108039 states have internal predecessors, (150711), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:21,768 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108040 states to 108040 states and 150711 transitions. [2022-12-13 12:07:21,768 INFO L240 hiAutomatonCegarLoop]: Abstraction has 108040 states and 150711 transitions. [2022-12-13 12:07:21,768 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:07:21,769 INFO L428 stractBuchiCegarLoop]: Abstraction has 108040 states and 150711 transitions. [2022-12-13 12:07:21,769 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2022-12-13 12:07:21,769 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108040 states and 150711 transitions. [2022-12-13 12:07:21,958 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 107538 [2022-12-13 12:07:21,958 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:21,958 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:21,959 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:21,960 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:21,960 INFO L748 eck$LassoCheckResult]: Stem: 997891#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 997892#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 998982#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 998983#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 998349#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 998350#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 998216#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 998109#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 997833#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 997487#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 997488#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 997531#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 997532#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 998500#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 998501#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 998549#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 997935#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 997936#L1090 assume !(0 == ~M_E~0); 997977#L1090-2 assume !(0 == ~T1_E~0); 997978#L1095-1 assume !(0 == ~T2_E~0); 998710#L1100-1 assume !(0 == ~T3_E~0); 998711#L1105-1 assume !(0 == ~T4_E~0); 997754#L1110-1 assume !(0 == ~T5_E~0); 997755#L1115-1 assume !(0 == ~T6_E~0); 998149#L1120-1 assume !(0 == ~T7_E~0); 998469#L1125-1 assume !(0 == ~T8_E~0); 999100#L1130-1 assume !(0 == ~T9_E~0); 998733#L1135-1 assume !(0 == ~T10_E~0); 997940#L1140-1 assume !(0 == ~T11_E~0); 997941#L1145-1 assume !(0 == ~E_1~0); 998662#L1150-1 assume !(0 == ~E_2~0); 998125#L1155-1 assume !(0 == ~E_3~0); 998126#L1160-1 assume !(0 == ~E_4~0); 998221#L1165-1 assume !(0 == ~E_5~0); 998222#L1170-1 assume !(0 == ~E_6~0); 998958#L1175-1 assume !(0 == ~E_7~0); 998305#L1180-1 assume !(0 == ~E_8~0); 998306#L1185-1 assume !(0 == ~E_9~0); 997937#L1190-1 assume !(0 == ~E_10~0); 997938#L1195-1 assume !(0 == ~E_11~0); 998321#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 998141#L525 assume !(1 == ~m_pc~0); 997571#L525-2 is_master_triggered_~__retres1~0#1 := 0; 997572#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 998832#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 998797#L1350 assume !(0 != activate_threads_~tmp~1#1); 997928#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 997929#L544 assume !(1 == ~t1_pc~0); 998147#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 998148#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 997546#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 997547#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 997779#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 998434#L563 assume !(1 == ~t2_pc~0); 998647#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 997593#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 997594#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 998004#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 998005#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 998527#L582 assume !(1 == ~t3_pc~0); 998661#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 999043#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 997479#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 997480#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 997661#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 997662#L601 assume !(1 == ~t4_pc~0); 998675#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 998150#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 997674#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 997675#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 998670#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 999034#L620 assume !(1 == ~t5_pc~0); 998487#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 998488#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 998546#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 998837#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 999057#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 999058#L639 assume !(1 == ~t6_pc~0); 998468#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 998042#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 998043#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 998094#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 998155#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 998156#L658 assume !(1 == ~t7_pc~0); 998376#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 998377#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 999071#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 998603#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 997931#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 997932#L677 assume !(1 == ~t8_pc~0); 997951#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 997737#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 997738#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 998000#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 998001#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 998787#L696 assume !(1 == ~t9_pc~0); 998447#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 998448#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 999150#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 998474#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 998475#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 998715#L715 assume !(1 == ~t10_pc~0); 999000#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 998580#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 998363#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 998364#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 998298#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 997731#L734 assume !(1 == ~t11_pc~0); 997732#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 998223#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 998308#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 997475#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 997476#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 998547#L1213 assume !(1 == ~M_E~0); 998295#L1213-2 assume !(1 == ~T1_E~0); 998296#L1218-1 assume !(1 == ~T2_E~0); 997508#L1223-1 assume !(1 == ~T3_E~0); 997509#L1228-1 assume !(1 == ~T4_E~0); 998269#L1233-1 assume !(1 == ~T5_E~0); 999059#L1238-1 assume !(1 == ~T6_E~0); 998668#L1243-1 assume !(1 == ~T7_E~0); 998669#L1248-1 assume !(1 == ~T8_E~0); 998721#L1253-1 assume !(1 == ~T9_E~0); 998722#L1258-1 assume !(1 == ~T10_E~0); 998695#L1263-1 assume !(1 == ~T11_E~0); 998696#L1268-1 assume !(1 == ~E_1~0); 998495#L1273-1 assume !(1 == ~E_2~0); 998496#L1278-1 assume !(1 == ~E_3~0); 998040#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 998041#L1288-1 assume !(1 == ~E_5~0); 998844#L1293-1 assume !(1 == ~E_6~0); 998792#L1298-1 assume !(1 == ~E_7~0); 998531#L1303-1 assume !(1 == ~E_8~0); 998050#L1308-1 assume !(1 == ~E_9~0); 997944#L1313-1 assume !(1 == ~E_10~0); 997945#L1318-1 assume !(1 == ~E_11~0); 997952#L1323-1 assume { :end_inline_reset_delta_events } true; 997953#L1644-2 [2022-12-13 12:07:21,960 INFO L750 eck$LassoCheckResult]: Loop: 997953#L1644-2 assume !false; 1053513#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1053507#L1065 assume !false; 1053504#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1048937#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1048926#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1048923#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1048919#L906 assume !(0 != eval_~tmp~0#1); 1048920#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1053816#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1053814#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1053812#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1053810#L1095-3 assume !(0 == ~T2_E~0); 1053808#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1053806#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1053804#L1110-3 assume !(0 == ~T5_E~0); 1053802#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1053800#L1120-3 assume !(0 == ~T7_E~0); 1053798#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1053796#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1053794#L1135-3 assume !(0 == ~T10_E~0); 1053791#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1053789#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1053787#L1150-3 assume !(0 == ~E_2~0); 1053785#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1053783#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1053781#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1053779#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1053777#L1175-3 assume !(0 == ~E_7~0); 1053775#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1053773#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1053771#L1190-3 assume !(0 == ~E_10~0); 1053769#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1053766#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1053764#L525-36 assume !(1 == ~m_pc~0); 1053762#L525-38 is_master_triggered_~__retres1~0#1 := 0; 1053760#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1053758#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1053756#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 1053754#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1053752#L544-36 assume !(1 == ~t1_pc~0); 1053750#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1053748#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1053746#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1053744#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1053741#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1053739#L563-36 assume !(1 == ~t2_pc~0); 1053736#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1053734#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1053732#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1053729#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1053727#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1053725#L582-36 assume !(1 == ~t3_pc~0); 1053723#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1053721#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1053719#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1053717#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1053715#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1053713#L601-36 assume !(1 == ~t4_pc~0); 1053710#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1053708#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1053706#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1053702#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1053700#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1053698#L620-36 assume !(1 == ~t5_pc~0); 1053696#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1053693#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1053691#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1053689#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1053687#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1053685#L639-36 assume !(1 == ~t6_pc~0); 1053682#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 1053680#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1053678#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1053676#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1053673#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1053671#L658-36 assume !(1 == ~t7_pc~0); 1053668#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1053666#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1053664#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1053662#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 1053660#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1053658#L677-36 assume !(1 == ~t8_pc~0); 1053656#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1053654#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1053652#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1053650#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1053648#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1053646#L696-36 assume !(1 == ~t9_pc~0); 1053642#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 1053640#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1053638#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1053636#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 1053633#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1053631#L715-36 assume !(1 == ~t10_pc~0); 1053629#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1053627#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1053625#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1053623#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1053621#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1053619#L734-36 assume !(1 == ~t11_pc~0); 1053616#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 1053614#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1053613#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1053612#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1053611#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1053610#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1053609#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1053608#L1218-3 assume !(1 == ~T2_E~0); 1053607#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1053606#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1053605#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1053604#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1053603#L1243-3 assume !(1 == ~T7_E~0); 1053602#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1053601#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1053600#L1258-3 assume !(1 == ~T10_E~0); 1053598#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1053596#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1053594#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1053592#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1053590#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1053588#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1053586#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1053585#L1298-3 assume !(1 == ~E_7~0); 1053583#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1053581#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1053579#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1053577#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1053575#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1053572#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1053559#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1053557#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1053554#L1663 assume !(0 == start_simulation_~tmp~3#1); 1053551#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1053532#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1053526#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1053524#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1053522#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1053520#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1053518#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1053516#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 997953#L1644-2 [2022-12-13 12:07:21,961 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:21,961 INFO L85 PathProgramCache]: Analyzing trace with hash 1086953880, now seen corresponding path program 1 times [2022-12-13 12:07:21,961 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:21,961 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [501463071] [2022-12-13 12:07:21,961 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:21,961 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:21,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:22,019 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:22,019 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:22,019 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [501463071] [2022-12-13 12:07:22,019 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [501463071] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:22,019 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:22,019 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:22,019 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [765397412] [2022-12-13 12:07:22,019 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:22,020 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:07:22,020 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:22,020 INFO L85 PathProgramCache]: Analyzing trace with hash -1300255105, now seen corresponding path program 1 times [2022-12-13 12:07:22,020 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:22,020 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [49548721] [2022-12-13 12:07:22,020 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:22,021 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:22,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:22,065 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:22,066 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:22,066 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [49548721] [2022-12-13 12:07:22,066 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [49548721] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:22,066 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:22,066 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:07:22,066 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [266237002] [2022-12-13 12:07:22,066 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:22,066 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:07:22,066 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:07:22,067 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:07:22,067 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:07:22,067 INFO L87 Difference]: Start difference. First operand 108040 states and 150711 transitions. cyclomatic complexity: 42703 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:22,784 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:07:22,784 INFO L93 Difference]: Finished difference Result 226717 states and 314370 transitions. [2022-12-13 12:07:22,784 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 226717 states and 314370 transitions. [2022-12-13 12:07:23,626 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 225640 [2022-12-13 12:07:24,172 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 226717 states to 226717 states and 314370 transitions. [2022-12-13 12:07:24,172 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 226717 [2022-12-13 12:07:24,257 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 226717 [2022-12-13 12:07:24,258 INFO L73 IsDeterministic]: Start isDeterministic. Operand 226717 states and 314370 transitions. [2022-12-13 12:07:24,327 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:07:24,328 INFO L218 hiAutomatonCegarLoop]: Abstraction has 226717 states and 314370 transitions. [2022-12-13 12:07:24,415 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 226717 states and 314370 transitions. [2022-12-13 12:07:25,459 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 226717 to 119829. [2022-12-13 12:07:25,531 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 119829 states, 119829 states have (on average 1.3888123909904948) internal successors, (166420), 119828 states have internal predecessors, (166420), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:25,697 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119829 states to 119829 states and 166420 transitions. [2022-12-13 12:07:25,697 INFO L240 hiAutomatonCegarLoop]: Abstraction has 119829 states and 166420 transitions. [2022-12-13 12:07:25,698 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:07:25,698 INFO L428 stractBuchiCegarLoop]: Abstraction has 119829 states and 166420 transitions. [2022-12-13 12:07:25,698 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2022-12-13 12:07:25,698 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 119829 states and 166420 transitions. [2022-12-13 12:07:26,105 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 119222 [2022-12-13 12:07:26,106 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:26,106 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:26,107 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:26,107 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:26,107 INFO L748 eck$LassoCheckResult]: Stem: 1332661#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1332662#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1333751#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1333752#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1333121#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1333122#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1332991#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1332884#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1332604#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1332256#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1332257#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1332298#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1332299#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1333273#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1333274#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1333321#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1332706#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1332707#L1090 assume !(0 == ~M_E~0); 1332752#L1090-2 assume !(0 == ~T1_E~0); 1332753#L1095-1 assume !(0 == ~T2_E~0); 1333482#L1100-1 assume !(0 == ~T3_E~0); 1333483#L1105-1 assume !(0 == ~T4_E~0); 1332523#L1110-1 assume !(0 == ~T5_E~0); 1332524#L1115-1 assume !(0 == ~T6_E~0); 1332925#L1120-1 assume !(0 == ~T7_E~0); 1333244#L1125-1 assume !(0 == ~T8_E~0); 1333872#L1130-1 assume !(0 == ~T9_E~0); 1333507#L1135-1 assume !(0 == ~T10_E~0); 1332712#L1140-1 assume !(0 == ~T11_E~0); 1332713#L1145-1 assume !(0 == ~E_1~0); 1333434#L1150-1 assume !(0 == ~E_2~0); 1332902#L1155-1 assume !(0 == ~E_3~0); 1332903#L1160-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1333864#L1165-1 assume !(0 == ~E_5~0); 1333726#L1170-1 assume !(0 == ~E_6~0); 1333727#L1175-1 assume !(0 == ~E_7~0); 1334022#L1180-1 assume !(0 == ~E_8~0); 1334021#L1185-1 assume !(0 == ~E_9~0); 1334020#L1190-1 assume !(0 == ~E_10~0); 1334019#L1195-1 assume !(0 == ~E_11~0); 1334018#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1332917#L525 assume !(1 == ~m_pc~0); 1332339#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1332340#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1333601#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1333571#L1350 assume !(0 != activate_threads_~tmp~1#1); 1332699#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1332700#L544 assume !(1 == ~t1_pc~0); 1332923#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1332924#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1332313#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1332314#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1333209#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1333210#L563 assume !(1 == ~t2_pc~0); 1333417#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1333418#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1332898#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1332899#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1333300#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1333301#L582 assume !(1 == ~t3_pc~0); 1333433#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1333816#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1333817#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1333736#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1332428#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1332429#L601 assume !(1 == ~t4_pc~0); 1334004#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1334003#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1334002#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1334001#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1334000#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1333999#L620 assume !(1 == ~t5_pc~0); 1333998#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1333997#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1333996#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1333995#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1333994#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1333993#L639 assume !(1 == ~t6_pc~0); 1333991#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1333990#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1333989#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1333988#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1333987#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1333986#L658 assume !(1 == ~t7_pc~0); 1333984#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1333983#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1333982#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1333981#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1333980#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1333979#L677 assume !(1 == ~t8_pc~0); 1333978#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1333977#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1333976#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1333975#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1333974#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1333973#L696 assume !(1 == ~t9_pc~0); 1333971#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1333972#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1333969#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1333965#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1333964#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1333963#L715 assume !(1 == ~t10_pc~0); 1333962#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1333961#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1333960#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1333959#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1333958#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1333957#L734 assume !(1 == ~t11_pc~0); 1333955#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1333954#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1333953#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1333952#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1333951#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1333950#L1213 assume !(1 == ~M_E~0); 1333949#L1213-2 assume !(1 == ~T1_E~0); 1333948#L1218-1 assume !(1 == ~T2_E~0); 1333947#L1223-1 assume !(1 == ~T3_E~0); 1333946#L1228-1 assume !(1 == ~T4_E~0); 1333945#L1233-1 assume !(1 == ~T5_E~0); 1333944#L1238-1 assume !(1 == ~T6_E~0); 1333943#L1243-1 assume !(1 == ~T7_E~0); 1333942#L1248-1 assume !(1 == ~T8_E~0); 1333941#L1253-1 assume !(1 == ~T9_E~0); 1333940#L1258-1 assume !(1 == ~T10_E~0); 1333939#L1263-1 assume !(1 == ~T11_E~0); 1333938#L1268-1 assume !(1 == ~E_1~0); 1333937#L1273-1 assume !(1 == ~E_2~0); 1333936#L1278-1 assume !(1 == ~E_3~0); 1333935#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1332816#L1288-1 assume !(1 == ~E_5~0); 1333613#L1293-1 assume !(1 == ~E_6~0); 1333566#L1298-1 assume !(1 == ~E_7~0); 1333305#L1303-1 assume !(1 == ~E_8~0); 1332825#L1308-1 assume !(1 == ~E_9~0); 1332716#L1313-1 assume !(1 == ~E_10~0); 1332717#L1318-1 assume !(1 == ~E_11~0); 1332724#L1323-1 assume { :end_inline_reset_delta_events } true; 1332725#L1644-2 [2022-12-13 12:07:26,108 INFO L750 eck$LassoCheckResult]: Loop: 1332725#L1644-2 assume !false; 1403690#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1403685#L1065 assume !false; 1403682#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1403672#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1403662#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1403661#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1403657#L906 assume !(0 != eval_~tmp~0#1); 1403658#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1406390#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1406388#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1406386#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1406384#L1095-3 assume !(0 == ~T2_E~0); 1406382#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1406380#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1406378#L1110-3 assume !(0 == ~T5_E~0); 1406376#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1406374#L1120-3 assume !(0 == ~T7_E~0); 1406372#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1406370#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1406368#L1135-3 assume !(0 == ~T10_E~0); 1406366#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1406364#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1406362#L1150-3 assume !(0 == ~E_2~0); 1406360#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1406357#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1406356#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1406355#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1406354#L1175-3 assume !(0 == ~E_7~0); 1406353#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1406352#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1406351#L1190-3 assume !(0 == ~E_10~0); 1406350#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1406349#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1406348#L525-36 assume !(1 == ~m_pc~0); 1406347#L525-38 is_master_triggered_~__retres1~0#1 := 0; 1406346#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1406345#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1406344#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 1406343#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1406342#L544-36 assume !(1 == ~t1_pc~0); 1406341#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1406340#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1406339#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1406338#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1406337#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1406336#L563-36 assume 1 == ~t2_pc~0; 1406335#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1406333#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1406332#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1406331#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1406330#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1406329#L582-36 assume !(1 == ~t3_pc~0); 1406328#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1406327#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1406326#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1406325#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1406324#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1406323#L601-36 assume 1 == ~t4_pc~0; 1406321#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1406319#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1406318#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1406317#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1406316#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1406315#L620-36 assume !(1 == ~t5_pc~0); 1406314#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1406313#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1406312#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1406311#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1406310#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1406309#L639-36 assume 1 == ~t6_pc~0; 1406308#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1406306#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1406305#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1406304#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1406303#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1406302#L658-36 assume !(1 == ~t7_pc~0); 1406300#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1406299#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1406298#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1406297#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 1406296#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1406295#L677-36 assume !(1 == ~t8_pc~0); 1406294#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1406293#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1406292#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1406291#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1406290#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1406289#L696-36 assume !(1 == ~t9_pc~0); 1406288#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 1406286#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1406284#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1406282#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 1406280#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1406279#L715-36 assume !(1 == ~t10_pc~0); 1406278#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1406277#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1406276#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1406275#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1406274#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1406273#L734-36 assume 1 == ~t11_pc~0; 1406272#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1406270#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1406269#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1406268#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1406267#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1406266#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1406265#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1406264#L1218-3 assume !(1 == ~T2_E~0); 1406263#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1406262#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1406261#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1406260#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1406259#L1243-3 assume !(1 == ~T7_E~0); 1406248#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1406247#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1406246#L1258-3 assume !(1 == ~T10_E~0); 1406245#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1406244#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1406243#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1406242#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1406240#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1406238#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1406236#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1406234#L1298-3 assume !(1 == ~E_7~0); 1406232#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1406230#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1406228#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1406226#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1406160#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1405975#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1405962#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1405960#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1405958#L1663 assume !(0 == start_simulation_~tmp~3#1); 1405956#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1405858#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1403702#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1403700#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1403698#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1403697#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1403695#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1403693#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1332725#L1644-2 [2022-12-13 12:07:26,108 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:26,108 INFO L85 PathProgramCache]: Analyzing trace with hash 968512406, now seen corresponding path program 1 times [2022-12-13 12:07:26,108 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:26,108 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1048786489] [2022-12-13 12:07:26,108 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:26,108 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:26,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:26,141 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:26,141 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:26,141 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1048786489] [2022-12-13 12:07:26,142 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1048786489] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:26,142 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:26,142 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:26,142 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [246947730] [2022-12-13 12:07:26,142 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:26,142 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:07:26,142 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:26,143 INFO L85 PathProgramCache]: Analyzing trace with hash 1439984451, now seen corresponding path program 1 times [2022-12-13 12:07:26,143 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:26,143 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1415895243] [2022-12-13 12:07:26,143 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:26,143 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:26,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:26,176 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:26,177 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:26,177 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1415895243] [2022-12-13 12:07:26,177 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1415895243] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:26,177 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:26,177 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:07:26,177 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [357427351] [2022-12-13 12:07:26,177 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:26,177 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:07:26,178 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:07:26,178 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:07:26,178 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:07:26,178 INFO L87 Difference]: Start difference. First operand 119829 states and 166420 transitions. cyclomatic complexity: 46623 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:26,625 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:07:26,625 INFO L93 Difference]: Finished difference Result 179524 states and 248624 transitions. [2022-12-13 12:07:26,625 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 179524 states and 248624 transitions. [2022-12-13 12:07:27,382 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 178722 [2022-12-13 12:07:27,688 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 179524 states to 179524 states and 248624 transitions. [2022-12-13 12:07:27,688 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 179524 [2022-12-13 12:07:27,749 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 179524 [2022-12-13 12:07:27,750 INFO L73 IsDeterministic]: Start isDeterministic. Operand 179524 states and 248624 transitions. [2022-12-13 12:07:27,829 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:07:27,829 INFO L218 hiAutomatonCegarLoop]: Abstraction has 179524 states and 248624 transitions. [2022-12-13 12:07:28,069 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179524 states and 248624 transitions. [2022-12-13 12:07:29,007 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179524 to 108040. [2022-12-13 12:07:29,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108040 states, 108040 states have (on average 1.3829692706405035) internal successors, (149416), 108039 states have internal predecessors, (149416), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:29,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108040 states to 108040 states and 149416 transitions. [2022-12-13 12:07:29,269 INFO L240 hiAutomatonCegarLoop]: Abstraction has 108040 states and 149416 transitions. [2022-12-13 12:07:29,269 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:07:29,270 INFO L428 stractBuchiCegarLoop]: Abstraction has 108040 states and 149416 transitions. [2022-12-13 12:07:29,270 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2022-12-13 12:07:29,270 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108040 states and 149416 transitions. [2022-12-13 12:07:29,565 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 107538 [2022-12-13 12:07:29,565 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:29,565 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:29,567 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:29,567 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:29,567 INFO L748 eck$LassoCheckResult]: Stem: 1632032#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1632033#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1633122#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1633123#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1632481#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1632482#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1632350#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1632248#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1631973#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1631621#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1631622#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1631664#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1631665#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1632632#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1632633#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1632684#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1632075#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1632076#L1090 assume !(0 == ~M_E~0); 1632124#L1090-2 assume !(0 == ~T1_E~0); 1632125#L1095-1 assume !(0 == ~T2_E~0); 1632848#L1100-1 assume !(0 == ~T3_E~0); 1632849#L1105-1 assume !(0 == ~T4_E~0); 1631892#L1110-1 assume !(0 == ~T5_E~0); 1631893#L1115-1 assume !(0 == ~T6_E~0); 1632288#L1120-1 assume !(0 == ~T7_E~0); 1632602#L1125-1 assume !(0 == ~T8_E~0); 1633239#L1130-1 assume !(0 == ~T9_E~0); 1632873#L1135-1 assume !(0 == ~T10_E~0); 1632081#L1140-1 assume !(0 == ~T11_E~0); 1632082#L1145-1 assume !(0 == ~E_1~0); 1632794#L1150-1 assume !(0 == ~E_2~0); 1632263#L1155-1 assume !(0 == ~E_3~0); 1632264#L1160-1 assume !(0 == ~E_4~0); 1632355#L1165-1 assume !(0 == ~E_5~0); 1632356#L1170-1 assume !(0 == ~E_6~0); 1633098#L1175-1 assume !(0 == ~E_7~0); 1632438#L1180-1 assume !(0 == ~E_8~0); 1632439#L1185-1 assume !(0 == ~E_9~0); 1632077#L1190-1 assume !(0 == ~E_10~0); 1632078#L1195-1 assume !(0 == ~E_11~0); 1632454#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1632280#L525 assume !(1 == ~m_pc~0); 1631705#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1631706#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1632970#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1632940#L1350 assume !(0 != activate_threads_~tmp~1#1); 1632068#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1632069#L544 assume !(1 == ~t1_pc~0); 1632284#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1632285#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1631684#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1631685#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1631915#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1632567#L563 assume !(1 == ~t2_pc~0); 1632779#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1631727#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1631728#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1632146#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1632147#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1632656#L582 assume !(1 == ~t3_pc~0); 1632793#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1633181#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1631613#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1631614#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1631796#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1631797#L601 assume !(1 == ~t4_pc~0); 1632810#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1632289#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1631813#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1631814#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1632803#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1633174#L620 assume !(1 == ~t5_pc~0); 1632622#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1632623#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1632675#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1632976#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1633194#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1633195#L639 assume !(1 == ~t6_pc~0); 1632601#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1632184#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1632185#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1632233#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1632294#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1632295#L658 assume !(1 == ~t7_pc~0); 1632509#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1632510#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1633203#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1632733#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1632071#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1632072#L677 assume !(1 == ~t8_pc~0); 1632094#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1631879#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1631880#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1632142#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1632143#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1632927#L696 assume !(1 == ~t9_pc~0); 1632584#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1632585#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1633307#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1632608#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1632609#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1632853#L715 assume !(1 == ~t10_pc~0); 1633139#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1632709#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1632493#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1632494#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1632431#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1631867#L734 assume !(1 == ~t11_pc~0); 1631868#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1632360#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1632441#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1631611#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1631612#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1632676#L1213 assume !(1 == ~M_E~0); 1632429#L1213-2 assume !(1 == ~T1_E~0); 1632430#L1218-1 assume !(1 == ~T2_E~0); 1631642#L1223-1 assume !(1 == ~T3_E~0); 1631643#L1228-1 assume !(1 == ~T4_E~0); 1632402#L1233-1 assume !(1 == ~T5_E~0); 1633196#L1238-1 assume !(1 == ~T6_E~0); 1632801#L1243-1 assume !(1 == ~T7_E~0); 1632802#L1248-1 assume !(1 == ~T8_E~0); 1632859#L1253-1 assume !(1 == ~T9_E~0); 1632860#L1258-1 assume !(1 == ~T10_E~0); 1632832#L1263-1 assume !(1 == ~T11_E~0); 1632833#L1268-1 assume !(1 == ~E_1~0); 1632627#L1273-1 assume !(1 == ~E_2~0); 1632628#L1278-1 assume !(1 == ~E_3~0); 1632180#L1283-1 assume !(1 == ~E_4~0); 1632181#L1288-1 assume !(1 == ~E_5~0); 1632983#L1293-1 assume !(1 == ~E_6~0); 1632935#L1298-1 assume !(1 == ~E_7~0); 1632660#L1303-1 assume !(1 == ~E_8~0); 1632190#L1308-1 assume !(1 == ~E_9~0); 1632085#L1313-1 assume !(1 == ~E_10~0); 1632086#L1318-1 assume !(1 == ~E_11~0); 1632095#L1323-1 assume { :end_inline_reset_delta_events } true; 1632096#L1644-2 [2022-12-13 12:07:29,568 INFO L750 eck$LassoCheckResult]: Loop: 1632096#L1644-2 assume !false; 1735225#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1735220#L1065 assume !false; 1735217#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1735199#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1735189#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1710572#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1710110#L906 assume !(0 != eval_~tmp~0#1); 1710111#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1735443#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1735442#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1735441#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1735440#L1095-3 assume !(0 == ~T2_E~0); 1735439#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1735438#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1735437#L1110-3 assume !(0 == ~T5_E~0); 1735436#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1735435#L1120-3 assume !(0 == ~T7_E~0); 1735434#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1735433#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1735432#L1135-3 assume !(0 == ~T10_E~0); 1735431#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1735430#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1735429#L1150-3 assume !(0 == ~E_2~0); 1735428#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1735427#L1160-3 assume !(0 == ~E_4~0); 1735426#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1735425#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1735424#L1175-3 assume !(0 == ~E_7~0); 1735423#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1735422#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1735421#L1190-3 assume !(0 == ~E_10~0); 1735420#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1735419#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1735418#L525-36 assume !(1 == ~m_pc~0); 1735417#L525-38 is_master_triggered_~__retres1~0#1 := 0; 1735416#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1735415#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1735414#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 1735413#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1735412#L544-36 assume !(1 == ~t1_pc~0); 1735411#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1735410#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1735409#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1735408#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1735407#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1735406#L563-36 assume !(1 == ~t2_pc~0); 1735404#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1735403#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1735402#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1735401#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1735400#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1735399#L582-36 assume !(1 == ~t3_pc~0); 1735398#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1735397#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1735396#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1735395#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1735394#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1735392#L601-36 assume !(1 == ~t4_pc~0); 1735391#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1735390#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1735389#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1735388#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1735387#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1735386#L620-36 assume !(1 == ~t5_pc~0); 1735385#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1735384#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1735383#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1735382#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1735381#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1735380#L639-36 assume !(1 == ~t6_pc~0); 1735378#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 1735377#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1735376#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1735375#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1735374#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1735373#L658-36 assume !(1 == ~t7_pc~0); 1735371#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1735370#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1735369#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1735368#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 1735367#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1735366#L677-36 assume !(1 == ~t8_pc~0); 1735365#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1735364#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1735363#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1735362#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1735361#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1735360#L696-36 assume 1 == ~t9_pc~0; 1735358#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1735359#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1735444#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1735353#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1735352#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1735351#L715-36 assume !(1 == ~t10_pc~0); 1735350#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1735349#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1735348#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1735347#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1735346#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1735345#L734-36 assume !(1 == ~t11_pc~0); 1735343#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 1735342#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1735341#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1735340#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1735339#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1735338#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1735337#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1735336#L1218-3 assume !(1 == ~T2_E~0); 1735335#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1735334#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1735333#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1735332#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1735331#L1243-3 assume !(1 == ~T7_E~0); 1735329#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1735327#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1735325#L1258-3 assume !(1 == ~T10_E~0); 1735323#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1735321#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1735319#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1735317#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1735315#L1283-3 assume !(1 == ~E_4~0); 1735313#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1735311#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1735309#L1298-3 assume !(1 == ~E_7~0); 1735307#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1735305#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1735302#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1735300#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1735298#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1735296#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1735283#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1735281#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1735278#L1663 assume !(0 == start_simulation_~tmp~3#1); 1735275#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1735245#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1735239#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1735237#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1735234#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1735232#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1735230#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1735228#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1632096#L1644-2 [2022-12-13 12:07:29,568 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:29,568 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 1 times [2022-12-13 12:07:29,568 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:29,569 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2081412578] [2022-12-13 12:07:29,569 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:29,569 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:29,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:07:29,583 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:07:29,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:07:29,668 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:07:29,669 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:29,669 INFO L85 PathProgramCache]: Analyzing trace with hash 2073690342, now seen corresponding path program 1 times [2022-12-13 12:07:29,669 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:29,669 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [395431725] [2022-12-13 12:07:29,669 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:29,669 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:29,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:29,716 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:29,716 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:29,716 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [395431725] [2022-12-13 12:07:29,716 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [395431725] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:29,716 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:29,717 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:07:29,717 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1733078663] [2022-12-13 12:07:29,717 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:29,717 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:07:29,717 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:07:29,717 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 12:07:29,717 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 12:07:29,718 INFO L87 Difference]: Start difference. First operand 108040 states and 149416 transitions. cyclomatic complexity: 41408 Second operand has 5 states, 5 states have (on average 28.4) internal successors, (142), 5 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:30,418 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:07:30,418 INFO L93 Difference]: Finished difference Result 199498 states and 272698 transitions. [2022-12-13 12:07:30,418 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 199498 states and 272698 transitions. [2022-12-13 12:07:31,059 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 198640 [2022-12-13 12:07:31,592 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 199498 states to 199498 states and 272698 transitions. [2022-12-13 12:07:31,592 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 199498 [2022-12-13 12:07:31,675 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 199498 [2022-12-13 12:07:31,676 INFO L73 IsDeterministic]: Start isDeterministic. Operand 199498 states and 272698 transitions. [2022-12-13 12:07:31,759 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:07:31,759 INFO L218 hiAutomatonCegarLoop]: Abstraction has 199498 states and 272698 transitions. [2022-12-13 12:07:31,854 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 199498 states and 272698 transitions. [2022-12-13 12:07:32,918 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 199498 to 108364. [2022-12-13 12:07:32,993 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108364 states, 108364 states have (on average 1.381824222066369) internal successors, (149740), 108363 states have internal predecessors, (149740), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:33,133 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108364 states to 108364 states and 149740 transitions. [2022-12-13 12:07:33,133 INFO L240 hiAutomatonCegarLoop]: Abstraction has 108364 states and 149740 transitions. [2022-12-13 12:07:33,134 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-12-13 12:07:33,134 INFO L428 stractBuchiCegarLoop]: Abstraction has 108364 states and 149740 transitions. [2022-12-13 12:07:33,134 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2022-12-13 12:07:33,134 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108364 states and 149740 transitions. [2022-12-13 12:07:33,407 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 107862 [2022-12-13 12:07:33,407 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:33,408 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:33,409 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:33,409 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:33,409 INFO L748 eck$LassoCheckResult]: Stem: 1939581#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1939582#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1940765#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1940766#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1940062#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1940063#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1939921#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1939807#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1939521#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1939175#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1939176#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1939218#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1939219#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1940213#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1940214#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1940270#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1939628#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1939629#L1090 assume !(0 == ~M_E~0); 1939672#L1090-2 assume !(0 == ~T1_E~0); 1939673#L1095-1 assume !(0 == ~T2_E~0); 1940446#L1100-1 assume !(0 == ~T3_E~0); 1940447#L1105-1 assume !(0 == ~T4_E~0); 1939440#L1110-1 assume !(0 == ~T5_E~0); 1939441#L1115-1 assume !(0 == ~T6_E~0); 1939847#L1120-1 assume !(0 == ~T7_E~0); 1940183#L1125-1 assume !(0 == ~T8_E~0); 1940927#L1130-1 assume !(0 == ~T9_E~0); 1940472#L1135-1 assume !(0 == ~T10_E~0); 1939632#L1140-1 assume !(0 == ~T11_E~0); 1939633#L1145-1 assume !(0 == ~E_1~0); 1940393#L1150-1 assume !(0 == ~E_2~0); 1939824#L1155-1 assume !(0 == ~E_3~0); 1939825#L1160-1 assume !(0 == ~E_4~0); 1939927#L1165-1 assume !(0 == ~E_5~0); 1939928#L1170-1 assume !(0 == ~E_6~0); 1940735#L1175-1 assume !(0 == ~E_7~0); 1940015#L1180-1 assume !(0 == ~E_8~0); 1940016#L1185-1 assume !(0 == ~E_9~0); 1939626#L1190-1 assume !(0 == ~E_10~0); 1939627#L1195-1 assume !(0 == ~E_11~0); 1940032#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1939839#L525 assume !(1 == ~m_pc~0); 1939259#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1939260#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1940586#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1940553#L1350 assume !(0 != activate_threads_~tmp~1#1); 1939618#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1939619#L544 assume !(1 == ~t1_pc~0); 1939845#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1939846#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1939234#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1939235#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1939466#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1940148#L563 assume !(1 == ~t2_pc~0); 1940377#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1939278#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1939279#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1939699#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1939700#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1940244#L582 assume !(1 == ~t3_pc~0); 1940391#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1940850#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1939167#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1939168#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1939345#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1939346#L601 assume !(1 == ~t4_pc~0); 1940411#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1939848#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1939358#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1939359#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1940402#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1940837#L620 assume !(1 == ~t5_pc~0); 1940202#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1940203#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1940267#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1940593#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1940865#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1940866#L639 assume !(1 == ~t6_pc~0); 1940182#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1939739#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1939740#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1939791#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1939853#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1939854#L658 assume !(1 == ~t7_pc~0); 1940086#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1940087#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1940886#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1940328#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1939622#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1939623#L677 assume !(1 == ~t8_pc~0); 1939644#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1939423#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1939424#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1939695#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1939696#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1940540#L696 assume !(1 == ~t9_pc~0); 1940161#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1940162#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1941003#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1940189#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1940190#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1940452#L715 assume !(1 == ~t10_pc~0); 1940790#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1940304#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1940074#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1940075#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1940008#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1939417#L734 assume !(1 == ~t11_pc~0); 1939418#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1939929#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1940019#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1939163#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1939164#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1940268#L1213 assume !(1 == ~M_E~0); 1940005#L1213-2 assume !(1 == ~T1_E~0); 1940006#L1218-1 assume !(1 == ~T2_E~0); 1939196#L1223-1 assume !(1 == ~T3_E~0); 1939197#L1228-1 assume !(1 == ~T4_E~0); 1939978#L1233-1 assume !(1 == ~T5_E~0); 1940867#L1238-1 assume !(1 == ~T6_E~0); 1940400#L1243-1 assume !(1 == ~T7_E~0); 1940401#L1248-1 assume !(1 == ~T8_E~0); 1940458#L1253-1 assume !(1 == ~T9_E~0); 1940459#L1258-1 assume !(1 == ~T10_E~0); 1940431#L1263-1 assume !(1 == ~T11_E~0); 1940432#L1268-1 assume !(1 == ~E_1~0); 1940210#L1273-1 assume !(1 == ~E_2~0); 1940211#L1278-1 assume !(1 == ~E_3~0); 1939737#L1283-1 assume !(1 == ~E_4~0); 1939738#L1288-1 assume !(1 == ~E_5~0); 1940600#L1293-1 assume !(1 == ~E_6~0); 1940548#L1298-1 assume !(1 == ~E_7~0); 1940250#L1303-1 assume !(1 == ~E_8~0); 1939749#L1308-1 assume !(1 == ~E_9~0); 1939636#L1313-1 assume !(1 == ~E_10~0); 1939637#L1318-1 assume !(1 == ~E_11~0); 1939645#L1323-1 assume { :end_inline_reset_delta_events } true; 1939646#L1644-2 [2022-12-13 12:07:33,409 INFO L750 eck$LassoCheckResult]: Loop: 1939646#L1644-2 assume !false; 2013079#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2013072#L1065 assume !false; 2012213#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2011946#L829 assume !(0 == ~m_st~0); 2011947#L833 assume !(0 == ~t1_st~0); 2011936#L837 assume !(0 == ~t2_st~0); 2011937#L841 assume !(0 == ~t3_st~0); 2011940#L845 assume !(0 == ~t4_st~0); 2011942#L849 assume !(0 == ~t5_st~0); 2011944#L853 assume !(0 == ~t6_st~0); 2011945#L857 assume !(0 == ~t7_st~0); 2011948#L861 assume !(0 == ~t8_st~0); 2011938#L865 assume !(0 == ~t9_st~0); 2011939#L869 assume !(0 == ~t10_st~0); 2011941#L873 assume !(0 == ~t11_st~0);exists_runnable_thread_~__retres1~12#1 := 0; 2011943#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1986952#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1986953#L906 assume !(0 != eval_~tmp~0#1); 2013252#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2013251#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2013250#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2013249#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2013248#L1095-3 assume !(0 == ~T2_E~0); 2013247#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2013246#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2013245#L1110-3 assume !(0 == ~T5_E~0); 2013244#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2013243#L1120-3 assume !(0 == ~T7_E~0); 2013242#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2013241#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2013240#L1135-3 assume !(0 == ~T10_E~0); 2013239#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 2013238#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2013237#L1150-3 assume !(0 == ~E_2~0); 2013236#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2013235#L1160-3 assume !(0 == ~E_4~0); 2013234#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2013233#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2013232#L1175-3 assume !(0 == ~E_7~0); 2013231#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2013230#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2013229#L1190-3 assume !(0 == ~E_10~0); 2013228#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 2013227#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2013226#L525-36 assume !(1 == ~m_pc~0); 2013225#L525-38 is_master_triggered_~__retres1~0#1 := 0; 2013224#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2013223#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2013222#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 2013221#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2013220#L544-36 assume !(1 == ~t1_pc~0); 2013219#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 2013218#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2013217#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2013216#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2013215#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2013214#L563-36 assume !(1 == ~t2_pc~0); 2013212#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 2013211#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2013210#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2013209#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2013208#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2013207#L582-36 assume !(1 == ~t3_pc~0); 2013206#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 2013205#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2013204#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2013203#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2013202#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2013200#L601-36 assume !(1 == ~t4_pc~0); 2013199#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 2013198#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2013197#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2013196#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2013195#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2013194#L620-36 assume !(1 == ~t5_pc~0); 2013193#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 2013192#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2013191#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2013190#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2013189#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2013188#L639-36 assume !(1 == ~t6_pc~0); 2013186#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 2013185#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2013184#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2013183#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2013182#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2013181#L658-36 assume !(1 == ~t7_pc~0); 2013179#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 2013178#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2013177#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2013176#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 2013175#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2013174#L677-36 assume !(1 == ~t8_pc~0); 2013173#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 2013172#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2013171#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2013170#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2013169#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2013168#L696-36 assume 1 == ~t9_pc~0; 2013166#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2013164#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2013162#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2013160#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2013159#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2013158#L715-36 assume !(1 == ~t10_pc~0); 2013157#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 2013156#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2013155#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2013154#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2013153#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2013152#L734-36 assume !(1 == ~t11_pc~0); 2013150#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 2013149#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2013148#is_transmit11_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2013147#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2013146#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2013145#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2013144#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2013143#L1218-3 assume !(1 == ~T2_E~0); 2013142#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2013141#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2013140#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2013139#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2013138#L1243-3 assume !(1 == ~T7_E~0); 2013137#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2013136#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2013135#L1258-3 assume !(1 == ~T10_E~0); 2013134#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 2013133#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2013132#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2013131#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2013130#L1283-3 assume !(1 == ~E_4~0); 2013129#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2013128#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2013127#L1298-3 assume !(1 == ~E_7~0); 2013126#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2013125#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2013124#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2013123#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 2013122#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2013121#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 2013108#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2013106#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 2013103#L1663 assume !(0 == start_simulation_~tmp~3#1); 2013101#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2013093#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 2013088#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2013087#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 2013086#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2013085#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2013084#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 2013082#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1939646#L1644-2 [2022-12-13 12:07:33,410 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:33,410 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 2 times [2022-12-13 12:07:33,410 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:33,410 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1460682797] [2022-12-13 12:07:33,410 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:33,410 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:33,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:07:33,418 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:07:33,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:07:33,449 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:07:33,450 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:33,450 INFO L85 PathProgramCache]: Analyzing trace with hash -1213168140, now seen corresponding path program 1 times [2022-12-13 12:07:33,450 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:33,450 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1298360117] [2022-12-13 12:07:33,450 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:33,450 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:33,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:33,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:33,474 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:33,474 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1298360117] [2022-12-13 12:07:33,475 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1298360117] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:33,475 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:33,475 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:33,475 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1895320848] [2022-12-13 12:07:33,475 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:33,475 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:07:33,475 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:07:33,476 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:07:33,476 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:07:33,476 INFO L87 Difference]: Start difference. First operand 108364 states and 149740 transitions. cyclomatic complexity: 41408 Second operand has 3 states, 3 states have (on average 51.0) internal successors, (153), 3 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:34,041 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:07:34,041 INFO L93 Difference]: Finished difference Result 191532 states and 260856 transitions. [2022-12-13 12:07:34,041 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 191532 states and 260856 transitions. [2022-12-13 12:07:34,587 INFO L131 ngComponentsAnalysis]: Automaton has 60 accepting balls. 190812 [2022-12-13 12:07:35,102 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 191532 states to 191532 states and 260856 transitions. [2022-12-13 12:07:35,102 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 191532 [2022-12-13 12:07:35,151 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 191532 [2022-12-13 12:07:35,151 INFO L73 IsDeterministic]: Start isDeterministic. Operand 191532 states and 260856 transitions. [2022-12-13 12:07:35,199 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:07:35,200 INFO L218 hiAutomatonCegarLoop]: Abstraction has 191532 states and 260856 transitions. [2022-12-13 12:07:35,261 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 191532 states and 260856 transitions. [2022-12-13 12:07:36,477 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 191532 to 188924. [2022-12-13 12:07:36,599 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 188924 states, 188924 states have (on average 1.3625373165929158) internal successors, (257416), 188923 states have internal predecessors, (257416), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:37,102 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 188924 states to 188924 states and 257416 transitions. [2022-12-13 12:07:37,102 INFO L240 hiAutomatonCegarLoop]: Abstraction has 188924 states and 257416 transitions. [2022-12-13 12:07:37,103 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:07:37,103 INFO L428 stractBuchiCegarLoop]: Abstraction has 188924 states and 257416 transitions. [2022-12-13 12:07:37,103 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2022-12-13 12:07:37,103 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 188924 states and 257416 transitions. [2022-12-13 12:07:37,445 INFO L131 ngComponentsAnalysis]: Automaton has 60 accepting balls. 188204 [2022-12-13 12:07:37,445 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:37,445 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:37,445 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:37,445 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:37,446 INFO L748 eck$LassoCheckResult]: Stem: 2239482#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 2239483#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 2240636#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2240637#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2239952#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 2239953#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2239811#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2239704#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2239424#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2239077#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2239078#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2239119#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2239120#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2240113#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2240114#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 2240167#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 2239531#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2239532#L1090 assume !(0 == ~M_E~0); 2239577#L1090-2 assume !(0 == ~T1_E~0); 2239578#L1095-1 assume !(0 == ~T2_E~0); 2240330#L1100-1 assume !(0 == ~T3_E~0); 2240331#L1105-1 assume !(0 == ~T4_E~0); 2239344#L1110-1 assume !(0 == ~T5_E~0); 2239345#L1115-1 assume !(0 == ~T6_E~0); 2239744#L1120-1 assume !(0 == ~T7_E~0); 2240079#L1125-1 assume !(0 == ~T8_E~0); 2240778#L1130-1 assume !(0 == ~T9_E~0); 2240354#L1135-1 assume !(0 == ~T10_E~0); 2239534#L1140-1 assume !(0 == ~T11_E~0); 2239535#L1145-1 assume !(0 == ~E_1~0); 2240279#L1150-1 assume !(0 == ~E_2~0); 2239719#L1155-1 assume !(0 == ~E_3~0); 2239720#L1160-1 assume !(0 == ~E_4~0); 2239818#L1165-1 assume !(0 == ~E_5~0); 2239819#L1170-1 assume !(0 == ~E_6~0); 2240610#L1175-1 assume !(0 == ~E_7~0); 2239906#L1180-1 assume !(0 == ~E_8~0); 2239907#L1185-1 assume !(0 == ~E_9~0); 2239529#L1190-1 assume !(0 == ~E_10~0); 2239530#L1195-1 assume !(0 == ~E_11~0); 2239924#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2239739#L525 assume !(1 == ~m_pc~0); 2239160#L525-2 is_master_triggered_~__retres1~0#1 := 0; 2239161#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2240463#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2240428#L1350 assume !(0 != activate_threads_~tmp~1#1); 2239521#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2239522#L544 assume !(1 == ~t1_pc~0); 2239740#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2239741#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2239139#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2239140#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 2239367#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2240042#L563 assume !(1 == ~t2_pc~0); 2240266#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2239180#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2239181#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2239602#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 2239603#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2240135#L582 assume !(1 == ~t3_pc~0); 2240278#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2240710#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2239069#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2239070#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 2239249#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2239250#L601 assume !(1 == ~t4_pc~0); 2240296#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2239745#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2239266#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2239267#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 2240290#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2240698#L620 assume !(1 == ~t5_pc~0); 2240100#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2240101#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2240157#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2240472#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 2240732#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2240733#L639 assume !(1 == ~t6_pc~0); 2240078#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2239639#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2239640#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2239688#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 2239750#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2239751#L658 assume !(1 == ~t7_pc~0); 2239980#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2239981#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2240744#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2240216#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 2239524#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2239525#L677 assume !(1 == ~t8_pc~0); 2239548#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2239332#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2239333#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2239595#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 2239596#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2240415#L696 assume !(1 == ~t9_pc~0); 2240061#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2240062#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2240845#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2240089#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 2240090#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2240335#L715 assume !(1 == ~t10_pc~0); 2240658#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 2240192#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2239964#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2239965#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 2239899#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2239320#L734 assume !(1 == ~t11_pc~0); 2239321#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 2239823#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2239911#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2239067#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 2239068#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2240158#L1213 assume !(1 == ~M_E~0); 2239897#L1213-2 assume !(1 == ~T1_E~0); 2239898#L1218-1 assume !(1 == ~T2_E~0); 2239098#L1223-1 assume !(1 == ~T3_E~0); 2239099#L1228-1 assume !(1 == ~T4_E~0); 2239869#L1233-1 assume !(1 == ~T5_E~0); 2240734#L1238-1 assume !(1 == ~T6_E~0); 2240288#L1243-1 assume !(1 == ~T7_E~0); 2240289#L1248-1 assume !(1 == ~T8_E~0); 2240340#L1253-1 assume !(1 == ~T9_E~0); 2240341#L1258-1 assume !(1 == ~T10_E~0); 2240314#L1263-1 assume !(1 == ~T11_E~0); 2240315#L1268-1 assume !(1 == ~E_1~0); 2240105#L1273-1 assume !(1 == ~E_2~0); 2240106#L1278-1 assume !(1 == ~E_3~0); 2239635#L1283-1 assume !(1 == ~E_4~0); 2239636#L1288-1 assume !(1 == ~E_5~0); 2240477#L1293-1 assume !(1 == ~E_6~0); 2240423#L1298-1 assume !(1 == ~E_7~0); 2240140#L1303-1 assume !(1 == ~E_8~0); 2239645#L1308-1 assume !(1 == ~E_9~0); 2239538#L1313-1 assume !(1 == ~E_10~0); 2239539#L1318-1 assume !(1 == ~E_11~0); 2239549#L1323-1 assume { :end_inline_reset_delta_events } true; 2239550#L1644-2 assume !false; 2309812#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2309813#L1065 [2022-12-13 12:07:37,446 INFO L750 eck$LassoCheckResult]: Loop: 2309813#L1065 assume !false; 2312347#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2312345#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 2312344#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2312343#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2312342#L906 assume 0 != eval_~tmp~0#1; 2309790#L906-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 2309788#L914 assume !(0 != eval_~tmp_ndt_1~0#1); 2309784#L911 assume !(0 == ~t1_st~0); 2261221#L925 assume !(0 == ~t2_st~0); 2310002#L939 assume !(0 == ~t3_st~0); 2310003#L953 assume !(0 == ~t4_st~0); 2312372#L967 assume !(0 == ~t5_st~0); 2312369#L981 assume !(0 == ~t6_st~0); 2312365#L995 assume !(0 == ~t7_st~0); 2312361#L1009 assume !(0 == ~t8_st~0); 2312358#L1023 assume !(0 == ~t9_st~0); 2312354#L1037 assume !(0 == ~t10_st~0); 2312351#L1051 assume !(0 == ~t11_st~0); 2309813#L1065 [2022-12-13 12:07:37,446 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:37,446 INFO L85 PathProgramCache]: Analyzing trace with hash 1586711004, now seen corresponding path program 1 times [2022-12-13 12:07:37,446 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:37,446 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1442950934] [2022-12-13 12:07:37,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:37,447 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:37,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:07:37,454 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:07:37,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:07:37,483 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:07:37,483 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:37,483 INFO L85 PathProgramCache]: Analyzing trace with hash 1423790277, now seen corresponding path program 1 times [2022-12-13 12:07:37,483 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:37,483 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1922133296] [2022-12-13 12:07:37,483 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:37,483 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:37,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:07:37,486 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:07:37,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:07:37,488 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:07:37,489 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:37,489 INFO L85 PathProgramCache]: Analyzing trace with hash -1661089014, now seen corresponding path program 1 times [2022-12-13 12:07:37,489 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:37,489 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [71787254] [2022-12-13 12:07:37,489 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:37,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:37,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:37,517 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:37,518 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:37,518 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [71787254] [2022-12-13 12:07:37,518 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [71787254] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:37,518 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:37,518 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:37,518 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [421214975] [2022-12-13 12:07:37,518 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:37,619 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:07:37,619 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:07:37,619 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:07:37,620 INFO L87 Difference]: Start difference. First operand 188924 states and 257416 transitions. cyclomatic complexity: 68552 Second operand has 3 states, 3 states have (on average 52.666666666666664) internal successors, (158), 3 states have internal predecessors, (158), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:38,493 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:07:38,493 INFO L93 Difference]: Finished difference Result 368270 states and 498337 transitions. [2022-12-13 12:07:38,493 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 368270 states and 498337 transitions. [2022-12-13 12:07:39,782 INFO L131 ngComponentsAnalysis]: Automaton has 92 accepting balls. 358940 [2022-12-13 12:07:40,572 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 368270 states to 368270 states and 498337 transitions. [2022-12-13 12:07:40,572 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 368270 [2022-12-13 12:07:40,664 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 368270 [2022-12-13 12:07:40,664 INFO L73 IsDeterministic]: Start isDeterministic. Operand 368270 states and 498337 transitions. [2022-12-13 12:07:40,782 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:07:40,783 INFO L218 hiAutomatonCegarLoop]: Abstraction has 368270 states and 498337 transitions. [2022-12-13 12:07:40,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368270 states and 498337 transitions. [2022-12-13 12:07:43,517 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368270 to 362894. [2022-12-13 12:07:43,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 362894 states, 362894 states have (on average 1.3537865051502642) internal successors, (491281), 362893 states have internal predecessors, (491281), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:44,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 362894 states to 362894 states and 491281 transitions. [2022-12-13 12:07:44,165 INFO L240 hiAutomatonCegarLoop]: Abstraction has 362894 states and 491281 transitions. [2022-12-13 12:07:44,165 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:07:44,166 INFO L428 stractBuchiCegarLoop]: Abstraction has 362894 states and 491281 transitions. [2022-12-13 12:07:44,166 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2022-12-13 12:07:44,166 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 362894 states and 491281 transitions. [2022-12-13 12:07:45,131 INFO L131 ngComponentsAnalysis]: Automaton has 92 accepting balls. 353564 [2022-12-13 12:07:45,131 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:45,131 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:45,132 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:45,132 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:45,132 INFO L748 eck$LassoCheckResult]: Stem: 2796688#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 2796689#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 2797851#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2797852#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2797161#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 2797162#L761-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 2797188#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2796908#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2796909#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2796279#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2796280#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2796322#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2796323#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2797321#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2797322#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 2798004#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 2798005#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2797889#L1090 assume !(0 == ~M_E~0); 2797890#L1090-2 assume !(0 == ~T1_E~0); 2797984#L1095-1 assume !(0 == ~T2_E~0); 2797985#L1100-1 assume !(0 == ~T3_E~0); 2797579#L1105-1 assume !(0 == ~T4_E~0); 2797580#L1110-1 assume !(0 == ~T5_E~0); 2796951#L1115-1 assume !(0 == ~T6_E~0); 2796952#L1120-1 assume !(0 == ~T7_E~0); 2798010#L1125-1 assume !(0 == ~T8_E~0); 2798011#L1130-1 assume !(0 == ~T9_E~0); 2797576#L1135-1 assume !(0 == ~T10_E~0); 2797577#L1140-1 assume !(0 == ~T11_E~0); 2797499#L1145-1 assume !(0 == ~E_1~0); 2797500#L1150-1 assume !(0 == ~E_2~0); 2796925#L1155-1 assume !(0 == ~E_3~0); 2796926#L1160-1 assume !(0 == ~E_4~0); 2797026#L1165-1 assume !(0 == ~E_5~0); 2797027#L1170-1 assume !(0 == ~E_6~0); 2797952#L1175-1 assume !(0 == ~E_7~0); 2797953#L1180-1 assume !(0 == ~E_8~0); 2797672#L1185-1 assume !(0 == ~E_9~0); 2797673#L1190-1 assume !(0 == ~E_10~0); 2797133#L1195-1 assume !(0 == ~E_11~0); 2797134#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2796942#L525 assume !(1 == ~m_pc~0); 2796943#L525-2 is_master_triggered_~__retres1~0#1 := 0; 2797781#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2797782#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2797649#L1350 assume !(0 != activate_threads_~tmp~1#1); 2797650#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2797192#L544 assume !(1 == ~t1_pc~0); 2797193#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2797495#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2797496#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2796569#L1358 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2796570#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2797251#L563 assume !(1 == ~t2_pc~0); 2797479#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2797480#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2796921#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2796922#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 2797345#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2797346#L582 assume !(1 == ~t3_pc~0); 2798008#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2798009#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2796271#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2796272#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 2796450#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2796451#L601 assume !(1 == ~t4_pc~0); 2797598#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2797599#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2796467#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2796468#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 2798037#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2798038#L620 assume !(1 == ~t5_pc~0); 2797308#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2797309#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2797690#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2797691#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 2797945#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2797946#L639 assume !(1 == ~t6_pc~0); 2797283#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2797284#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2796892#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2796893#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 2796959#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2796960#L658 assume !(1 == ~t7_pc~0); 2797190#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2797191#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2798028#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2798029#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 2796727#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2796728#L677 assume !(1 == ~t8_pc~0); 2796750#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2796751#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2797602#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2797603#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 2797634#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2797635#L696 assume !(1 == ~t9_pc~0); 2797265#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2797266#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2798078#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2798079#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 2797558#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2797559#L715 assume !(1 == ~t10_pc~0); 2797978#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 2797979#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2797175#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2797176#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 2797108#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2797109#L734 assume !(1 == ~t11_pc~0); 2797031#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 2797032#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2797441#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2797442#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 2797370#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2797371#L1213 assume !(1 == ~M_E~0); 2797106#L1213-2 assume !(1 == ~T1_E~0); 2797107#L1218-1 assume !(1 == ~T2_E~0); 2796300#L1223-1 assume !(1 == ~T3_E~0); 2796301#L1228-1 assume !(1 == ~T4_E~0); 2797947#L1233-1 assume !(1 == ~T5_E~0); 2797948#L1238-1 assume !(1 == ~T6_E~0); 2797507#L1243-1 assume !(1 == ~T7_E~0); 2797508#L1248-1 assume !(1 == ~T8_E~0); 2797564#L1253-1 assume !(1 == ~T9_E~0); 2797565#L1258-1 assume !(1 == ~T10_E~0); 2797535#L1263-1 assume !(1 == ~T11_E~0); 2797536#L1268-1 assume !(1 == ~E_1~0); 2797313#L1273-1 assume !(1 == ~E_2~0); 2797314#L1278-1 assume !(1 == ~E_3~0); 2796839#L1283-1 assume !(1 == ~E_4~0); 2796840#L1288-1 assume !(1 == ~E_5~0); 2797698#L1293-1 assume !(1 == ~E_6~0); 2797699#L1298-1 assume !(1 == ~E_7~0); 2797349#L1303-1 assume !(1 == ~E_8~0); 2797350#L1308-1 assume !(1 == ~E_9~0); 2796740#L1313-1 assume !(1 == ~E_10~0); 2796741#L1318-1 assume !(1 == ~E_11~0); 2796752#L1323-1 assume { :end_inline_reset_delta_events } true; 2796753#L1644-2 assume !false; 2812803#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2812804#L1065 [2022-12-13 12:07:45,132 INFO L750 eck$LassoCheckResult]: Loop: 2812804#L1065 assume !false; 2994156#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2994154#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 2994153#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2994152#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2994151#L906 assume 0 != eval_~tmp~0#1; 2994149#L906-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 2994148#L914 assume !(0 != eval_~tmp_ndt_1~0#1); 2994147#L911 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 2979268#L928 assume !(0 != eval_~tmp_ndt_2~0#1); 2994058#L925 assume !(0 == ~t2_st~0); 2994057#L939 assume !(0 == ~t3_st~0); 2993547#L953 assume !(0 == ~t4_st~0); 2994179#L967 assume !(0 == ~t5_st~0); 2994177#L981 assume !(0 == ~t6_st~0); 2994173#L995 assume !(0 == ~t7_st~0); 2994169#L1009 assume !(0 == ~t8_st~0); 2994167#L1023 assume !(0 == ~t9_st~0); 2994163#L1037 assume !(0 == ~t10_st~0); 2994160#L1051 assume !(0 == ~t11_st~0); 2812804#L1065 [2022-12-13 12:07:45,133 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:45,133 INFO L85 PathProgramCache]: Analyzing trace with hash 963964252, now seen corresponding path program 1 times [2022-12-13 12:07:45,133 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:45,133 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [900213470] [2022-12-13 12:07:45,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:45,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:45,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:45,153 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:45,154 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:45,154 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [900213470] [2022-12-13 12:07:45,154 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [900213470] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:45,154 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:45,154 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:45,154 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [534102648] [2022-12-13 12:07:45,154 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:45,155 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:07:45,155 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:45,155 INFO L85 PathProgramCache]: Analyzing trace with hash -808873690, now seen corresponding path program 1 times [2022-12-13 12:07:45,155 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:45,155 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2005049535] [2022-12-13 12:07:45,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:45,155 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:45,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:07:45,159 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:07:45,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:07:45,163 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:07:45,291 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:07:45,291 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:07:45,291 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:07:45,291 INFO L87 Difference]: Start difference. First operand 362894 states and 491281 transitions. cyclomatic complexity: 128479 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:46,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:07:46,138 INFO L93 Difference]: Finished difference Result 298624 states and 404043 transitions. [2022-12-13 12:07:46,138 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 298624 states and 404043 transitions. [2022-12-13 12:07:47,310 INFO L131 ngComponentsAnalysis]: Automaton has 60 accepting balls. 297496 [2022-12-13 12:07:48,109 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 298624 states to 298624 states and 404043 transitions. [2022-12-13 12:07:48,109 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 298624 [2022-12-13 12:07:48,245 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 298624 [2022-12-13 12:07:48,245 INFO L73 IsDeterministic]: Start isDeterministic. Operand 298624 states and 404043 transitions. [2022-12-13 12:07:48,353 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:07:48,353 INFO L218 hiAutomatonCegarLoop]: Abstraction has 298624 states and 404043 transitions. [2022-12-13 12:07:48,490 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 298624 states and 404043 transitions. [2022-12-13 12:07:50,250 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 298624 to 298624. [2022-12-13 12:07:50,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 298624 states, 298624 states have (on average 1.3530158326189456) internal successors, (404043), 298623 states have internal predecessors, (404043), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:51,110 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 298624 states to 298624 states and 404043 transitions. [2022-12-13 12:07:51,110 INFO L240 hiAutomatonCegarLoop]: Abstraction has 298624 states and 404043 transitions. [2022-12-13 12:07:51,111 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:07:51,111 INFO L428 stractBuchiCegarLoop]: Abstraction has 298624 states and 404043 transitions. [2022-12-13 12:07:51,112 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2022-12-13 12:07:51,112 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 298624 states and 404043 transitions. [2022-12-13 12:07:51,813 INFO L131 ngComponentsAnalysis]: Automaton has 60 accepting balls. 297496 [2022-12-13 12:07:51,813 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:07:51,813 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:07:51,814 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:51,815 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:07:51,815 INFO L748 eck$LassoCheckResult]: Stem: 3458206#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 3458207#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 3459324#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3459325#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3458666#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 3458667#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3458532#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3458424#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3458148#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3457803#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3457804#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3457845#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3457846#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3458824#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3458825#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3458875#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 3458251#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3458252#L1090 assume !(0 == ~M_E~0); 3458294#L1090-2 assume !(0 == ~T1_E~0); 3458295#L1095-1 assume !(0 == ~T2_E~0); 3459041#L1100-1 assume !(0 == ~T3_E~0); 3459042#L1105-1 assume !(0 == ~T4_E~0); 3458066#L1110-1 assume !(0 == ~T5_E~0); 3458067#L1115-1 assume !(0 == ~T6_E~0); 3458464#L1120-1 assume !(0 == ~T7_E~0); 3458792#L1125-1 assume !(0 == ~T8_E~0); 3459464#L1130-1 assume !(0 == ~T9_E~0); 3459066#L1135-1 assume !(0 == ~T10_E~0); 3458257#L1140-1 assume !(0 == ~T11_E~0); 3458258#L1145-1 assume !(0 == ~E_1~0); 3458988#L1150-1 assume !(0 == ~E_2~0); 3458440#L1155-1 assume !(0 == ~E_3~0); 3458441#L1160-1 assume !(0 == ~E_4~0); 3458538#L1165-1 assume !(0 == ~E_5~0); 3458539#L1170-1 assume !(0 == ~E_6~0); 3459301#L1175-1 assume !(0 == ~E_7~0); 3458624#L1180-1 assume !(0 == ~E_8~0); 3458625#L1185-1 assume !(0 == ~E_9~0); 3458253#L1190-1 assume !(0 == ~E_10~0); 3458254#L1195-1 assume !(0 == ~E_11~0); 3458640#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3458455#L525 assume !(1 == ~m_pc~0); 3457886#L525-2 is_master_triggered_~__retres1~0#1 := 0; 3457887#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3459160#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3459131#L1350 assume !(0 != activate_threads_~tmp~1#1); 3458244#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3458245#L544 assume !(1 == ~t1_pc~0); 3458461#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3458462#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3457861#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3457862#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 3458090#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3458756#L563 assume !(1 == ~t2_pc~0); 3458972#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3457904#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3457905#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3458321#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 3458322#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3458852#L582 assume !(1 == ~t3_pc~0); 3458987#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3459395#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3457795#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3457796#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 3457972#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3457973#L601 assume !(1 == ~t4_pc~0); 3459005#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3458463#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3457985#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3457986#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 3458999#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3459388#L620 assume !(1 == ~t5_pc~0); 3458811#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3458812#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3458872#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3459166#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 3459414#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3459415#L639 assume !(1 == ~t6_pc~0); 3458790#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3458359#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3458360#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3458409#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 3458469#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3458470#L658 assume !(1 == ~t7_pc~0); 3458690#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3458691#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3459429#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3458930#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 3458247#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3458248#L677 assume !(1 == ~t8_pc~0); 3458270#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3458049#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3458050#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3458317#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 3458318#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3459120#L696 assume !(1 == ~t9_pc~0); 3458768#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3458769#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3459517#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3458798#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 3458799#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3459046#L715 assume !(1 == ~t10_pc~0); 3459349#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3458906#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3458678#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3458679#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 3458617#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3458043#L734 assume !(1 == ~t11_pc~0); 3458044#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 3458540#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3458627#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3457791#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 3457792#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3458873#L1213 assume !(1 == ~M_E~0); 3458613#L1213-2 assume !(1 == ~T1_E~0); 3458614#L1218-1 assume !(1 == ~T2_E~0); 3457824#L1223-1 assume !(1 == ~T3_E~0); 3457825#L1228-1 assume !(1 == ~T4_E~0); 3458587#L1233-1 assume !(1 == ~T5_E~0); 3459416#L1238-1 assume !(1 == ~T6_E~0); 3458997#L1243-1 assume !(1 == ~T7_E~0); 3458998#L1248-1 assume !(1 == ~T8_E~0); 3459052#L1253-1 assume !(1 == ~T9_E~0); 3459053#L1258-1 assume !(1 == ~T10_E~0); 3459025#L1263-1 assume !(1 == ~T11_E~0); 3459026#L1268-1 assume !(1 == ~E_1~0); 3458819#L1273-1 assume !(1 == ~E_2~0); 3458820#L1278-1 assume !(1 == ~E_3~0); 3458357#L1283-1 assume !(1 == ~E_4~0); 3458358#L1288-1 assume !(1 == ~E_5~0); 3459175#L1293-1 assume !(1 == ~E_6~0); 3459125#L1298-1 assume !(1 == ~E_7~0); 3458856#L1303-1 assume !(1 == ~E_8~0); 3458367#L1308-1 assume !(1 == ~E_9~0); 3458261#L1313-1 assume !(1 == ~E_10~0); 3458262#L1318-1 assume !(1 == ~E_11~0); 3458268#L1323-1 assume { :end_inline_reset_delta_events } true; 3458269#L1644-2 assume !false; 3614267#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3614262#L1065 [2022-12-13 12:07:51,815 INFO L750 eck$LassoCheckResult]: Loop: 3614262#L1065 assume !false; 3614261#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3614259#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3614258#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3614257#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3614256#L906 assume 0 != eval_~tmp~0#1; 3614255#L906-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 3614254#L914 assume !(0 != eval_~tmp_ndt_1~0#1); 3614253#L911 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 3539684#L928 assume !(0 != eval_~tmp_ndt_2~0#1); 3539685#L925 assume !(0 == ~t2_st~0); 3614314#L939 assume !(0 == ~t3_st~0); 3614305#L953 assume !(0 == ~t4_st~0); 3614299#L967 assume !(0 == ~t5_st~0); 3614293#L981 assume !(0 == ~t6_st~0); 3614285#L995 assume !(0 == ~t7_st~0); 3614280#L1009 assume !(0 == ~t8_st~0); 3614275#L1023 assume !(0 == ~t9_st~0); 3614270#L1037 assume !(0 == ~t10_st~0); 3614266#L1051 assume !(0 == ~t11_st~0); 3614262#L1065 [2022-12-13 12:07:51,815 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:51,816 INFO L85 PathProgramCache]: Analyzing trace with hash 1586711004, now seen corresponding path program 2 times [2022-12-13 12:07:51,816 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:51,816 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1267139524] [2022-12-13 12:07:51,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:51,816 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:51,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:07:51,826 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:07:51,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:07:51,856 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:07:51,857 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:51,857 INFO L85 PathProgramCache]: Analyzing trace with hash -808873690, now seen corresponding path program 2 times [2022-12-13 12:07:51,857 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:51,857 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1424365317] [2022-12-13 12:07:51,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:51,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:51,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:07:51,860 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:07:51,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:07:51,863 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:07:51,864 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:07:51,864 INFO L85 PathProgramCache]: Analyzing trace with hash -1950851199, now seen corresponding path program 1 times [2022-12-13 12:07:51,864 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:07:51,864 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1399945394] [2022-12-13 12:07:51,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:07:51,864 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:07:51,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:07:51,898 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:07:51,899 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:07:51,899 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1399945394] [2022-12-13 12:07:51,899 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1399945394] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:07:51,899 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:07:51,899 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:07:51,899 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [445289999] [2022-12-13 12:07:51,899 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:07:51,988 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:07:51,988 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:07:51,988 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:07:51,988 INFO L87 Difference]: Start difference. First operand 298624 states and 404043 transitions. cyclomatic complexity: 105479 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:07:53,370 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:07:53,370 INFO L93 Difference]: Finished difference Result 581512 states and 784283 transitions. [2022-12-13 12:07:53,370 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 581512 states and 784283 transitions. [2022-12-13 12:07:55,469 INFO L131 ngComponentsAnalysis]: Automaton has 60 accepting balls. 579404 [2022-12-13 12:07:56,332 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 581512 states to 581512 states and 784283 transitions. [2022-12-13 12:07:56,332 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 581512 [2022-12-13 12:07:56,675 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 581512 [2022-12-13 12:07:56,676 INFO L73 IsDeterministic]: Start isDeterministic. Operand 581512 states and 784283 transitions. [2022-12-13 12:07:56,858 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:07:56,858 INFO L218 hiAutomatonCegarLoop]: Abstraction has 581512 states and 784283 transitions. [2022-12-13 12:07:57,076 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 581512 states and 784283 transitions. [2022-12-13 12:08:00,447 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 581512 to 557152. [2022-12-13 12:08:00,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 557152 states, 557152 states have (on average 1.3508037304003215) internal successors, (752603), 557151 states have internal predecessors, (752603), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:08:01,914 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557152 states to 557152 states and 752603 transitions. [2022-12-13 12:08:01,914 INFO L240 hiAutomatonCegarLoop]: Abstraction has 557152 states and 752603 transitions. [2022-12-13 12:08:01,914 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:08:01,915 INFO L428 stractBuchiCegarLoop]: Abstraction has 557152 states and 752603 transitions. [2022-12-13 12:08:01,915 INFO L335 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2022-12-13 12:08:01,915 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 557152 states and 752603 transitions. [2022-12-13 12:08:03,550 INFO L131 ngComponentsAnalysis]: Automaton has 60 accepting balls. 555044 [2022-12-13 12:08:03,551 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:08:03,551 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:08:03,551 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:08:03,551 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:08:03,552 INFO L748 eck$LassoCheckResult]: Stem: 4338354#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 4338355#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 4339538#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4339539#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4338829#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 4338830#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4338691#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4338578#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4338295#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4337947#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4337948#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4337989#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4337990#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4338989#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4338990#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 4339046#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 4338403#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4338404#L1090 assume !(0 == ~M_E~0); 4338449#L1090-2 assume !(0 == ~T1_E~0); 4338450#L1095-1 assume !(0 == ~T2_E~0); 4339215#L1100-1 assume !(0 == ~T3_E~0); 4339216#L1105-1 assume !(0 == ~T4_E~0); 4338214#L1110-1 assume !(0 == ~T5_E~0); 4338215#L1115-1 assume !(0 == ~T6_E~0); 4338618#L1120-1 assume !(0 == ~T7_E~0); 4338957#L1125-1 assume !(0 == ~T8_E~0); 4339686#L1130-1 assume !(0 == ~T9_E~0); 4339241#L1135-1 assume !(0 == ~T10_E~0); 4338406#L1140-1 assume !(0 == ~T11_E~0); 4338407#L1145-1 assume !(0 == ~E_1~0); 4339162#L1150-1 assume !(0 == ~E_2~0); 4338594#L1155-1 assume !(0 == ~E_3~0); 4338595#L1160-1 assume !(0 == ~E_4~0); 4338696#L1165-1 assume !(0 == ~E_5~0); 4338697#L1170-1 assume !(0 == ~E_6~0); 4339513#L1175-1 assume !(0 == ~E_7~0); 4338783#L1180-1 assume !(0 == ~E_8~0); 4338784#L1185-1 assume !(0 == ~E_9~0); 4338401#L1190-1 assume !(0 == ~E_10~0); 4338402#L1195-1 assume !(0 == ~E_11~0); 4338800#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4338609#L525 assume !(1 == ~m_pc~0); 4338030#L525-2 is_master_triggered_~__retres1~0#1 := 0; 4338031#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4339354#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4339318#L1350 assume !(0 != activate_threads_~tmp~1#1); 4338394#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4338395#L544 assume !(1 == ~t1_pc~0); 4338615#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4338616#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4338006#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4338007#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 4338237#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4338921#L563 assume !(1 == ~t2_pc~0); 4339144#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4338051#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4338052#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4338478#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 4338479#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4339015#L582 assume !(1 == ~t3_pc~0); 4339159#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4339616#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4337939#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4337940#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 4338119#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4338120#L601 assume !(1 == ~t4_pc~0); 4339178#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4338617#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4338133#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4338134#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 4339173#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4339608#L620 assume !(1 == ~t5_pc~0); 4338974#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4338975#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4339037#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4339359#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 4339634#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4339635#L639 assume !(1 == ~t6_pc~0); 4338956#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4338513#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4338514#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4338563#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 4338623#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4338624#L658 assume !(1 == ~t7_pc~0); 4338860#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4338861#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4339650#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4339095#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 4338397#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4338398#L677 assume !(1 == ~t8_pc~0); 4338419#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4338198#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4338199#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4338469#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 4338470#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4339305#L696 assume !(1 == ~t9_pc~0); 4338933#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4338934#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4339761#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4338965#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 4338966#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4339220#L715 assume !(1 == ~t10_pc~0); 4339566#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4339073#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4338845#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4338846#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 4338776#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4338189#L734 assume !(1 == ~t11_pc~0); 4338190#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 4338698#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4338786#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4337935#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 4337936#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4339038#L1213 assume !(1 == ~M_E~0); 4338773#L1213-2 assume !(1 == ~T1_E~0); 4338774#L1218-1 assume !(1 == ~T2_E~0); 4337968#L1223-1 assume !(1 == ~T3_E~0); 4337969#L1228-1 assume !(1 == ~T4_E~0); 4338746#L1233-1 assume !(1 == ~T5_E~0); 4339636#L1238-1 assume !(1 == ~T6_E~0); 4339171#L1243-1 assume !(1 == ~T7_E~0); 4339172#L1248-1 assume !(1 == ~T8_E~0); 4339226#L1253-1 assume !(1 == ~T9_E~0); 4339227#L1258-1 assume !(1 == ~T10_E~0); 4339199#L1263-1 assume !(1 == ~T11_E~0); 4339200#L1268-1 assume !(1 == ~E_1~0); 4338982#L1273-1 assume !(1 == ~E_2~0); 4338983#L1278-1 assume !(1 == ~E_3~0); 4338509#L1283-1 assume !(1 == ~E_4~0); 4338510#L1288-1 assume !(1 == ~E_5~0); 4339367#L1293-1 assume !(1 == ~E_6~0); 4339310#L1298-1 assume !(1 == ~E_7~0); 4339018#L1303-1 assume !(1 == ~E_8~0); 4338519#L1308-1 assume !(1 == ~E_9~0); 4338410#L1313-1 assume !(1 == ~E_10~0); 4338411#L1318-1 assume !(1 == ~E_11~0); 4338420#L1323-1 assume { :end_inline_reset_delta_events } true; 4338421#L1644-2 assume !false; 4838304#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4838297#L1065 [2022-12-13 12:08:03,552 INFO L750 eck$LassoCheckResult]: Loop: 4838297#L1065 assume !false; 4838295#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4838293#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 4838292#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4838291#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4838290#L906 assume 0 != eval_~tmp~0#1; 4838289#L906-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 4582955#L914 assume !(0 != eval_~tmp_ndt_1~0#1); 4582956#L911 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 4697767#L928 assume !(0 != eval_~tmp_ndt_2~0#1); 4697764#L925 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 4697750#L942 assume !(0 != eval_~tmp_ndt_3~0#1); 4697762#L939 assume !(0 == ~t3_st~0); 4695931#L953 assume !(0 == ~t4_st~0); 4836542#L967 assume !(0 == ~t5_st~0); 4836541#L981 assume !(0 == ~t6_st~0); 4838325#L995 assume !(0 == ~t7_st~0); 4838320#L1009 assume !(0 == ~t8_st~0); 4838316#L1023 assume !(0 == ~t9_st~0); 4838309#L1037 assume !(0 == ~t10_st~0); 4838303#L1051 assume !(0 == ~t11_st~0); 4838297#L1065 [2022-12-13 12:08:03,552 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:08:03,552 INFO L85 PathProgramCache]: Analyzing trace with hash 1586711004, now seen corresponding path program 3 times [2022-12-13 12:08:03,552 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:08:03,552 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1428072039] [2022-12-13 12:08:03,552 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:08:03,552 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:08:03,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:08:03,560 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:08:03,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:08:03,602 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:08:03,603 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:08:03,603 INFO L85 PathProgramCache]: Analyzing trace with hash 1600153780, now seen corresponding path program 1 times [2022-12-13 12:08:03,603 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:08:03,603 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [46807506] [2022-12-13 12:08:03,603 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:08:03,603 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:08:03,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:08:03,606 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-13 12:08:03,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-13 12:08:03,610 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-12-13 12:08:03,610 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:08:03,610 INFO L85 PathProgramCache]: Analyzing trace with hash 558589369, now seen corresponding path program 1 times [2022-12-13 12:08:03,610 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:08:03,610 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [403955177] [2022-12-13 12:08:03,610 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:08:03,611 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:08:03,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:08:03,641 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:08:03,642 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:08:03,642 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [403955177] [2022-12-13 12:08:03,642 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [403955177] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:08:03,642 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:08:03,642 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:08:03,642 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [509178456] [2022-12-13 12:08:03,642 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:08:03,773 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:08:03,774 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:08:03,774 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:08:03,774 INFO L87 Difference]: Start difference. First operand 557152 states and 752603 transitions. cyclomatic complexity: 195511 Second operand has 3 states, 3 states have (on average 53.333333333333336) internal successors, (160), 3 states have internal predecessors, (160), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:08:05,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:08:05,972 INFO L93 Difference]: Finished difference Result 914956 states and 1234135 transitions. [2022-12-13 12:08:05,972 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 914956 states and 1234135 transitions. [2022-12-13 12:08:09,263 INFO L131 ngComponentsAnalysis]: Automaton has 60 accepting balls. 911488 [2022-12-13 12:08:10,899 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 914956 states to 914956 states and 1234135 transitions. [2022-12-13 12:08:10,899 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 914956 [2022-12-13 12:08:11,213 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 914956 [2022-12-13 12:08:11,213 INFO L73 IsDeterministic]: Start isDeterministic. Operand 914956 states and 1234135 transitions. [2022-12-13 12:08:11,491 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:08:11,491 INFO L218 hiAutomatonCegarLoop]: Abstraction has 914956 states and 1234135 transitions. [2022-12-13 12:08:11,937 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 914956 states and 1234135 transitions. [2022-12-13 12:08:17,824 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 914956 to 900236. [2022-12-13 12:08:18,173 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 900236 states, 900236 states have (on average 1.3493072927543444) internal successors, (1214695), 900235 states have internal predecessors, (1214695), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:08:20,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 900236 states to 900236 states and 1214695 transitions. [2022-12-13 12:08:20,167 INFO L240 hiAutomatonCegarLoop]: Abstraction has 900236 states and 1214695 transitions. [2022-12-13 12:08:20,168 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:08:20,168 INFO L428 stractBuchiCegarLoop]: Abstraction has 900236 states and 1214695 transitions. [2022-12-13 12:08:20,168 INFO L335 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2022-12-13 12:08:20,168 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 900236 states and 1214695 transitions.