./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.13.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dd3b27b3-47c1-4e25-9629-92a81d90b7c6/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dd3b27b3-47c1-4e25-9629-92a81d90b7c6/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dd3b27b3-47c1-4e25-9629-92a81d90b7c6/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dd3b27b3-47c1-4e25-9629-92a81d90b7c6/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.13.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dd3b27b3-47c1-4e25-9629-92a81d90b7c6/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dd3b27b3-47c1-4e25-9629-92a81d90b7c6/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 5975f0f3825b3a6653676f33bd69d14e1e58fcf0306bfb5508ab91dc8951d6c4 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 15:11:52,848 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 15:11:52,849 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 15:11:52,863 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 15:11:52,863 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 15:11:52,864 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 15:11:52,865 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 15:11:52,866 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 15:11:52,867 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 15:11:52,868 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 15:11:52,868 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 15:11:52,869 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 15:11:52,869 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 15:11:52,870 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 15:11:52,871 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 15:11:52,871 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 15:11:52,872 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 15:11:52,873 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 15:11:52,874 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 15:11:52,875 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 15:11:52,876 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 15:11:52,877 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 15:11:52,877 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 15:11:52,878 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 15:11:52,880 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 15:11:52,880 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 15:11:52,880 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 15:11:52,881 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 15:11:52,881 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 15:11:52,882 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 15:11:52,882 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 15:11:52,883 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 15:11:52,883 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 15:11:52,884 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 15:11:52,885 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 15:11:52,885 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 15:11:52,885 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 15:11:52,885 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 15:11:52,886 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 15:11:52,886 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 15:11:52,887 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 15:11:52,887 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dd3b27b3-47c1-4e25-9629-92a81d90b7c6/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 15:11:52,903 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 15:11:52,903 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 15:11:52,904 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 15:11:52,904 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 15:11:52,905 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 15:11:52,905 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 15:11:52,905 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 15:11:52,905 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 15:11:52,905 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 15:11:52,905 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 15:11:52,906 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 15:11:52,906 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 15:11:52,906 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 15:11:52,906 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 15:11:52,906 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 15:11:52,906 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 15:11:52,906 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 15:11:52,907 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 15:11:52,907 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 15:11:52,907 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 15:11:52,907 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 15:11:52,907 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 15:11:52,907 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 15:11:52,908 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 15:11:52,908 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 15:11:52,908 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 15:11:52,908 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 15:11:52,908 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 15:11:52,908 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 15:11:52,909 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 15:11:52,909 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 15:11:52,910 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 15:11:52,910 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dd3b27b3-47c1-4e25-9629-92a81d90b7c6/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dd3b27b3-47c1-4e25-9629-92a81d90b7c6/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 5975f0f3825b3a6653676f33bd69d14e1e58fcf0306bfb5508ab91dc8951d6c4 [2022-12-13 15:11:53,088 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 15:11:53,105 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 15:11:53,108 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 15:11:53,109 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 15:11:53,110 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 15:11:53,111 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dd3b27b3-47c1-4e25-9629-92a81d90b7c6/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/transmitter.13.cil.c [2022-12-13 15:11:55,648 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 15:11:55,832 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 15:11:55,833 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dd3b27b3-47c1-4e25-9629-92a81d90b7c6/sv-benchmarks/c/systemc/transmitter.13.cil.c [2022-12-13 15:11:55,843 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dd3b27b3-47c1-4e25-9629-92a81d90b7c6/bin/uautomizer-uyxdKDjOR8/data/0554673b3/10ae1144d60945d5a9f11ad5585f2c00/FLAG5513e3392 [2022-12-13 15:11:55,856 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dd3b27b3-47c1-4e25-9629-92a81d90b7c6/bin/uautomizer-uyxdKDjOR8/data/0554673b3/10ae1144d60945d5a9f11ad5585f2c00 [2022-12-13 15:11:55,858 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 15:11:55,859 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 15:11:55,860 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 15:11:55,860 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 15:11:55,864 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 15:11:55,865 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 03:11:55" (1/1) ... [2022-12-13 15:11:55,866 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3f699246 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:11:55, skipping insertion in model container [2022-12-13 15:11:55,866 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 03:11:55" (1/1) ... [2022-12-13 15:11:55,873 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 15:11:55,912 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 15:11:56,037 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dd3b27b3-47c1-4e25-9629-92a81d90b7c6/sv-benchmarks/c/systemc/transmitter.13.cil.c[706,719] [2022-12-13 15:11:56,154 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 15:11:56,169 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 15:11:56,180 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dd3b27b3-47c1-4e25-9629-92a81d90b7c6/sv-benchmarks/c/systemc/transmitter.13.cil.c[706,719] [2022-12-13 15:11:56,230 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 15:11:56,250 INFO L208 MainTranslator]: Completed translation [2022-12-13 15:11:56,251 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:11:56 WrapperNode [2022-12-13 15:11:56,251 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 15:11:56,252 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 15:11:56,252 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 15:11:56,252 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 15:11:56,258 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:11:56" (1/1) ... [2022-12-13 15:11:56,270 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:11:56" (1/1) ... [2022-12-13 15:11:56,351 INFO L138 Inliner]: procedures = 54, calls = 69, calls flagged for inlining = 64, calls inlined = 286, statements flattened = 4413 [2022-12-13 15:11:56,351 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 15:11:56,351 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 15:11:56,351 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 15:11:56,352 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 15:11:56,358 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:11:56" (1/1) ... [2022-12-13 15:11:56,359 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:11:56" (1/1) ... [2022-12-13 15:11:56,365 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:11:56" (1/1) ... [2022-12-13 15:11:56,366 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:11:56" (1/1) ... [2022-12-13 15:11:56,390 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:11:56" (1/1) ... [2022-12-13 15:11:56,414 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:11:56" (1/1) ... [2022-12-13 15:11:56,418 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:11:56" (1/1) ... [2022-12-13 15:11:56,426 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:11:56" (1/1) ... [2022-12-13 15:11:56,436 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 15:11:56,453 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 15:11:56,453 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 15:11:56,453 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 15:11:56,454 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:11:56" (1/1) ... [2022-12-13 15:11:56,461 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 15:11:56,468 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dd3b27b3-47c1-4e25-9629-92a81d90b7c6/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 15:11:56,478 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dd3b27b3-47c1-4e25-9629-92a81d90b7c6/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 15:11:56,480 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dd3b27b3-47c1-4e25-9629-92a81d90b7c6/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 15:11:56,520 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 15:11:56,520 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 15:11:56,520 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 15:11:56,520 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 15:11:56,613 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 15:11:56,614 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 15:11:58,248 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 15:11:58,268 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 15:11:58,268 INFO L300 CfgBuilder]: Removed 17 assume(true) statements. [2022-12-13 15:11:58,272 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 03:11:58 BoogieIcfgContainer [2022-12-13 15:11:58,272 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 15:11:58,273 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 15:11:58,273 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 15:11:58,276 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 15:11:58,277 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 15:11:58,277 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 03:11:55" (1/3) ... [2022-12-13 15:11:58,278 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6b505b62 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 03:11:58, skipping insertion in model container [2022-12-13 15:11:58,278 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 15:11:58,278 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 03:11:56" (2/3) ... [2022-12-13 15:11:58,278 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6b505b62 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 03:11:58, skipping insertion in model container [2022-12-13 15:11:58,278 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 15:11:58,278 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 03:11:58" (3/3) ... [2022-12-13 15:11:58,279 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.13.cil.c [2022-12-13 15:11:58,344 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 15:11:58,344 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 15:11:58,344 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 15:11:58,344 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 15:11:58,344 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 15:11:58,344 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 15:11:58,344 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 15:11:58,344 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 15:11:58,354 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1921 states, 1920 states have (on average 1.4984375) internal successors, (2877), 1920 states have internal predecessors, (2877), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:58,413 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1744 [2022-12-13 15:11:58,413 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:11:58,413 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:11:58,424 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:58,424 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:58,424 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 15:11:58,427 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1921 states, 1920 states have (on average 1.4984375) internal successors, (2877), 1920 states have internal predecessors, (2877), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:58,439 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1744 [2022-12-13 15:11:58,439 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:11:58,439 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:11:58,442 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:58,442 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:58,449 INFO L748 eck$LassoCheckResult]: Stem: 143#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1837#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 679#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1833#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1758#L881true assume !(1 == ~m_i~0);~m_st~0 := 2; 1055#L881-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1395#L886-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 259#L891-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1388#L896-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 535#L901-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 433#L906-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 787#L911-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 291#L916-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 542#L921-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 671#L926-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 796#L931-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 823#L936-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 904#L941-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 300#L946-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1816#L1258true assume 0 == ~M_E~0;~M_E~0 := 1; 1385#L1258-2true assume !(0 == ~T1_E~0); 483#L1263-1true assume !(0 == ~T2_E~0); 704#L1268-1true assume !(0 == ~T3_E~0); 1352#L1273-1true assume !(0 == ~T4_E~0); 1748#L1278-1true assume !(0 == ~T5_E~0); 1133#L1283-1true assume !(0 == ~T6_E~0); 1782#L1288-1true assume !(0 == ~T7_E~0); 1556#L1293-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1525#L1298-1true assume !(0 == ~T9_E~0); 1372#L1303-1true assume !(0 == ~T10_E~0); 194#L1308-1true assume !(0 == ~T11_E~0); 163#L1313-1true assume !(0 == ~T12_E~0); 1841#L1318-1true assume !(0 == ~T13_E~0); 166#L1323-1true assume !(0 == ~E_1~0); 264#L1328-1true assume !(0 == ~E_2~0); 1792#L1333-1true assume 0 == ~E_3~0;~E_3~0 := 1; 957#L1338-1true assume !(0 == ~E_4~0); 1093#L1343-1true assume !(0 == ~E_5~0); 1645#L1348-1true assume !(0 == ~E_6~0); 1661#L1353-1true assume !(0 == ~E_7~0); 720#L1358-1true assume !(0 == ~E_8~0); 986#L1363-1true assume !(0 == ~E_9~0); 1046#L1368-1true assume !(0 == ~E_10~0); 90#L1373-1true assume 0 == ~E_11~0;~E_11~0 := 1; 482#L1378-1true assume !(0 == ~E_12~0); 234#L1383-1true assume !(0 == ~E_13~0); 1082#L1388-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 722#L607true assume 1 == ~m_pc~0; 994#L608true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1089#L618true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 579#is_master_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 654#L1560true assume !(0 != activate_threads_~tmp~1#1); 1726#L1560-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 174#L626true assume !(1 == ~t1_pc~0); 1253#L626-2true is_transmit1_triggered_~__retres1~1#1 := 0; 323#L637true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 969#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1910#L1568true assume !(0 != activate_threads_~tmp___0~0#1); 126#L1568-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1322#L645true assume 1 == ~t2_pc~0; 183#L646true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1286#L656true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 219#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1902#L1576true assume !(0 != activate_threads_~tmp___1~0#1); 639#L1576-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1707#L664true assume 1 == ~t3_pc~0; 1626#L665true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 56#L675true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 947#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 409#L1584true assume !(0 != activate_threads_~tmp___2~0#1); 1403#L1584-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1619#L683true assume !(1 == ~t4_pc~0); 971#L683-2true is_transmit4_triggered_~__retres1~4#1 := 0; 774#L694true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1694#L1592true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 914#L1592-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 595#L702true assume 1 == ~t5_pc~0; 1683#L703true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 907#L713true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1553#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1378#L1600true assume !(0 != activate_threads_~tmp___4~0#1); 1222#L1600-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 73#L721true assume !(1 == ~t6_pc~0); 64#L721-2true is_transmit6_triggered_~__retres1~6#1 := 0; 139#L732true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 212#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 416#L1608true assume !(0 != activate_threads_~tmp___5~0#1); 1508#L1608-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 852#L740true assume 1 == ~t7_pc~0; 99#L741true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17#L751true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1856#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12#L1616true assume !(0 != activate_threads_~tmp___6~0#1); 754#L1616-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 374#L759true assume !(1 == ~t8_pc~0); 1363#L759-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1845#L770true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1499#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1062#L1624true assume !(0 != activate_threads_~tmp___7~0#1); 1667#L1624-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1554#L778true assume 1 == ~t9_pc~0; 1327#L779true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1259#L789true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 245#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28#L1632true assume !(0 != activate_threads_~tmp___8~0#1); 726#L1632-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 181#L797true assume !(1 == ~t10_pc~0); 251#L797-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1293#L808true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1292#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 480#L1640true assume !(0 != activate_threads_~tmp___9~0#1); 689#L1640-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1377#L816true assume 1 == ~t11_pc~0; 46#L817true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 572#L827true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1415#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 420#L1648true assume !(0 != activate_threads_~tmp___10~0#1); 1494#L1648-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 795#L835true assume 1 == ~t12_pc~0; 699#L836true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 130#L846true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 41#is_transmit12_triggered_returnLabel#1true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1786#L1656true assume !(0 != activate_threads_~tmp___11~0#1); 516#L1656-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1427#L854true assume !(1 == ~t13_pc~0); 292#L854-2true is_transmit13_triggered_~__retres1~13#1 := 0; 320#L865true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1348#is_transmit13_triggered_returnLabel#1true activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 138#L1664true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1214#L1664-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1793#L1401true assume !(1 == ~M_E~0); 412#L1401-2true assume !(1 == ~T1_E~0); 1225#L1406-1true assume !(1 == ~T2_E~0); 844#L1411-1true assume !(1 == ~T3_E~0); 1603#L1416-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 578#L1421-1true assume !(1 == ~T5_E~0); 290#L1426-1true assume !(1 == ~T6_E~0); 1000#L1431-1true assume !(1 == ~T7_E~0); 63#L1436-1true assume !(1 == ~T8_E~0); 739#L1441-1true assume !(1 == ~T9_E~0); 475#L1446-1true assume !(1 == ~T10_E~0); 1772#L1451-1true assume !(1 == ~T11_E~0); 1088#L1456-1true assume 1 == ~T12_E~0;~T12_E~0 := 2; 737#L1461-1true assume !(1 == ~T13_E~0); 430#L1466-1true assume !(1 == ~E_1~0); 1765#L1471-1true assume !(1 == ~E_2~0); 1061#L1476-1true assume !(1 == ~E_3~0); 1299#L1481-1true assume !(1 == ~E_4~0); 1583#L1486-1true assume !(1 == ~E_5~0); 202#L1491-1true assume !(1 == ~E_6~0); 34#L1496-1true assume 1 == ~E_7~0;~E_7~0 := 2; 750#L1501-1true assume !(1 == ~E_8~0); 472#L1506-1true assume !(1 == ~E_9~0); 1022#L1511-1true assume !(1 == ~E_10~0); 445#L1516-1true assume !(1 == ~E_11~0); 11#L1521-1true assume !(1 == ~E_12~0); 33#L1526-1true assume !(1 == ~E_13~0); 304#L1531-1true assume { :end_inline_reset_delta_events } true; 1152#L1892-2true [2022-12-13 15:11:58,451 INFO L750 eck$LassoCheckResult]: Loop: 1152#L1892-2true assume !false; 1867#L1893true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1496#L1233true assume !true; 534#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 329#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1622#L1258-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1901#L1258-5true assume !(0 == ~T1_E~0); 133#L1263-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1594#L1268-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1612#L1273-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1908#L1278-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1613#L1283-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 253#L1288-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1791#L1293-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1149#L1298-3true assume !(0 == ~T9_E~0); 1693#L1303-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1412#L1308-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1148#L1313-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 645#L1318-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 134#L1323-3true assume 0 == ~E_1~0;~E_1~0 := 1; 1287#L1328-3true assume 0 == ~E_2~0;~E_2~0 := 1; 1670#L1333-3true assume 0 == ~E_3~0;~E_3~0 := 1; 209#L1338-3true assume !(0 == ~E_4~0); 1040#L1343-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1526#L1348-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1296#L1353-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1336#L1358-3true assume 0 == ~E_8~0;~E_8~0 := 1; 607#L1363-3true assume 0 == ~E_9~0;~E_9~0 := 1; 324#L1368-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1885#L1373-3true assume 0 == ~E_11~0;~E_11~0 := 1; 869#L1378-3true assume !(0 == ~E_12~0); 1443#L1383-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1080#L1388-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1764#L607-42true assume 1 == ~m_pc~0; 708#L608-14true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 502#L618-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 404#is_master_triggered_returnLabel#15true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 336#L1560-42true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 690#L1560-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1203#L626-42true assume 1 == ~t1_pc~0; 389#L627-14true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1454#L637-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1750#is_transmit1_triggered_returnLabel#15true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1110#L1568-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 150#L1568-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1561#L645-42true assume !(1 == ~t2_pc~0); 1009#L645-44true is_transmit2_triggered_~__retres1~2#1 := 0; 1695#L656-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 605#is_transmit2_triggered_returnLabel#15true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 265#L1576-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18#L1576-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1655#L664-42true assume 1 == ~t3_pc~0; 449#L665-14true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1616#L675-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 935#is_transmit3_triggered_returnLabel#15true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 822#L1584-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1001#L1584-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1790#L683-42true assume 1 == ~t4_pc~0; 1700#L684-14true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 828#L694-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1004#is_transmit4_triggered_returnLabel#15true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1396#L1592-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1906#L1592-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1143#L702-42true assume 1 == ~t5_pc~0; 630#L703-14true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 574#L713-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 651#is_transmit5_triggered_returnLabel#15true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1273#L1600-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25#L1600-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 97#L721-42true assume 1 == ~t6_pc~0; 106#L722-14true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 356#L732-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 197#is_transmit6_triggered_returnLabel#15true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1577#L1608-42true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 461#L1608-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 367#L740-42true assume 1 == ~t7_pc~0; 1303#L741-14true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 548#L751-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 666#is_transmit7_triggered_returnLabel#15true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 451#L1616-42true assume !(0 != activate_threads_~tmp___6~0#1); 634#L1616-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1898#L759-42true assume !(1 == ~t8_pc~0); 1341#L759-44true is_transmit8_triggered_~__retres1~8#1 := 0; 486#L770-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 791#is_transmit8_triggered_returnLabel#15true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 536#L1624-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 597#L1624-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1155#L778-42true assume 1 == ~t9_pc~0; 493#L779-14true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 799#L789-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1769#is_transmit9_triggered_returnLabel#15true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 725#L1632-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1604#L1632-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 769#L797-42true assume !(1 == ~t10_pc~0); 1029#L797-44true is_transmit10_triggered_~__retres1~10#1 := 0; 920#L808-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 784#is_transmit10_triggered_returnLabel#15true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1877#L1640-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 800#L1640-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1711#L816-42true assume 1 == ~t11_pc~0; 8#L817-14true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1854#L827-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1474#is_transmit11_triggered_returnLabel#15true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 478#L1648-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 313#L1648-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 571#L835-42true assume !(1 == ~t12_pc~0); 499#L835-44true is_transmit12_triggered_~__retres1~12#1 := 0; 1228#L846-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 637#is_transmit12_triggered_returnLabel#15true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1840#L1656-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1221#L1656-44true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 933#L854-42true assume !(1 == ~t13_pc~0); 271#L854-44true is_transmit13_triggered_~__retres1~13#1 := 0; 473#L865-14true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 363#is_transmit13_triggered_returnLabel#15true activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 507#L1664-42true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 428#L1664-44true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1858#L1401-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1073#L1401-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 182#L1406-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 118#L1411-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1676#L1416-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 455#L1421-3true assume !(1 == ~T5_E~0); 1036#L1426-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 206#L1431-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 280#L1436-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 13#L1441-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1126#L1446-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1115#L1451-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 511#L1456-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 294#L1461-3true assume !(1 == ~T13_E~0); 1602#L1466-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1818#L1471-3true assume 1 == ~E_2~0;~E_2~0 := 2; 266#L1476-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1685#L1481-3true assume 1 == ~E_4~0;~E_4~0 := 2; 506#L1486-3true assume 1 == ~E_5~0;~E_5~0 := 2; 279#L1491-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1462#L1496-3true assume 1 == ~E_7~0;~E_7~0 := 2; 533#L1501-3true assume !(1 == ~E_8~0); 1585#L1506-3true assume 1 == ~E_9~0;~E_9~0 := 2; 865#L1511-3true assume 1 == ~E_10~0;~E_10~0 := 2; 857#L1516-3true assume 1 == ~E_11~0;~E_11~0 := 2; 1719#L1521-3true assume 1 == ~E_12~0;~E_12~0 := 2; 610#L1526-3true assume 1 == ~E_13~0;~E_13~0 := 2; 953#L1531-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1844#L959-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1880#L1031-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 193#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 488#L1911true assume !(0 == start_simulation_~tmp~3#1); 1290#L1911-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 889#L959-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1011#L1031-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 30#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 93#L1866true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 509#L1873true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1318#stop_simulation_returnLabel#1true start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1332#L1924true assume !(0 != start_simulation_~tmp___0~1#1); 1152#L1892-2true [2022-12-13 15:11:58,455 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:58,456 INFO L85 PathProgramCache]: Analyzing trace with hash 517365666, now seen corresponding path program 1 times [2022-12-13 15:11:58,462 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:58,463 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [834739073] [2022-12-13 15:11:58,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:58,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:58,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:58,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:58,675 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:58,675 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [834739073] [2022-12-13 15:11:58,676 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [834739073] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:58,676 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:58,676 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:11:58,677 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2062059968] [2022-12-13 15:11:58,678 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:58,681 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:11:58,681 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:58,682 INFO L85 PathProgramCache]: Analyzing trace with hash 1638807421, now seen corresponding path program 1 times [2022-12-13 15:11:58,682 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:58,682 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [972544365] [2022-12-13 15:11:58,682 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:58,682 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:58,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:58,759 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:58,759 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:58,760 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [972544365] [2022-12-13 15:11:58,760 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [972544365] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:58,760 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:58,760 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 15:11:58,761 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [404009657] [2022-12-13 15:11:58,761 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:58,762 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:11:58,763 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:11:58,794 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-12-13 15:11:58,795 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-12-13 15:11:58,800 INFO L87 Difference]: Start difference. First operand has 1921 states, 1920 states have (on average 1.4984375) internal successors, (2877), 1920 states have internal predecessors, (2877), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 78.5) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:58,854 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:11:58,855 INFO L93 Difference]: Finished difference Result 1920 states and 2841 transitions. [2022-12-13 15:11:58,856 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1920 states and 2841 transitions. [2022-12-13 15:11:58,867 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 15:11:58,877 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1920 states to 1914 states and 2835 transitions. [2022-12-13 15:11:58,878 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-12-13 15:11:58,880 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-12-13 15:11:58,881 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2835 transitions. [2022-12-13 15:11:58,886 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:11:58,887 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2835 transitions. [2022-12-13 15:11:58,904 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2835 transitions. [2022-12-13 15:11:58,950 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-12-13 15:11:58,955 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4811912225705328) internal successors, (2835), 1913 states have internal predecessors, (2835), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:58,962 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2835 transitions. [2022-12-13 15:11:58,963 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2835 transitions. [2022-12-13 15:11:58,964 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-12-13 15:11:58,966 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2835 transitions. [2022-12-13 15:11:58,966 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 15:11:58,967 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2835 transitions. [2022-12-13 15:11:58,972 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 15:11:58,972 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:11:58,973 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:11:58,974 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:58,975 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:58,975 INFO L748 eck$LassoCheckResult]: Stem: 4136#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 4137#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 5031#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5032#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5753#L881 assume !(1 == ~m_i~0);~m_st~0 := 2; 5429#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5430#L886-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4361#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4362#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4835#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4673#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4674#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4425#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4426#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4843#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5022#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5190#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5224#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 4441#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4442#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 5645#L1258-2 assume !(0 == ~T1_E~0); 4758#L1263-1 assume !(0 == ~T2_E~0); 4759#L1268-1 assume !(0 == ~T3_E~0); 5068#L1273-1 assume !(0 == ~T4_E~0); 5624#L1278-1 assume !(0 == ~T5_E~0); 5483#L1283-1 assume !(0 == ~T6_E~0); 5484#L1288-1 assume !(0 == ~T7_E~0); 5721#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5710#L1298-1 assume !(0 == ~T9_E~0); 5640#L1303-1 assume !(0 == ~T10_E~0); 4239#L1308-1 assume !(0 == ~T11_E~0); 4179#L1313-1 assume !(0 == ~T12_E~0); 4180#L1318-1 assume !(0 == ~T13_E~0); 4185#L1323-1 assume !(0 == ~E_1~0); 4186#L1328-1 assume !(0 == ~E_2~0); 4371#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5359#L1338-1 assume !(0 == ~E_4~0); 5360#L1343-1 assume !(0 == ~E_5~0); 5460#L1348-1 assume !(0 == ~E_6~0); 5740#L1353-1 assume !(0 == ~E_7~0); 5091#L1358-1 assume !(0 == ~E_8~0); 5092#L1363-1 assume !(0 == ~E_9~0); 5381#L1368-1 assume !(0 == ~E_10~0); 4032#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 4033#L1378-1 assume !(0 == ~E_12~0); 4314#L1383-1 assume !(0 == ~E_13~0); 4315#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5096#L607 assume 1 == ~m_pc~0; 5097#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4389#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4898#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4899#L1560 assume !(0 != activate_threads_~tmp~1#1); 5004#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4200#L626 assume !(1 == ~t1_pc~0); 4201#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4482#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4483#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5368#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 4104#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4105#L645 assume 1 == ~t2_pc~0; 4216#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4173#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4282#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4283#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 4978#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4979#L664 assume 1 == ~t3_pc~0; 5738#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3966#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3967#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4631#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 4632#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5653#L683 assume !(1 == ~t4_pc~0); 5208#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5161#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3990#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3991#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5316#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4921#L702 assume 1 == ~t5_pc~0; 4922#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4858#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5312#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5643#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 5551#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4002#L721 assume !(1 == ~t6_pc~0); 3983#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3984#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4128#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4267#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 4644#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5256#L740 assume 1 == ~t7_pc~0; 4048#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3883#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3884#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3873#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 3874#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4571#L759 assume !(1 == ~t8_pc~0); 4572#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4603#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5698#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5440#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 5441#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5720#L778 assume 1 == ~t9_pc~0; 5609#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4031#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4337#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3909#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 3910#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4212#L797 assume !(1 == ~t10_pc~0); 4213#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4347#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5586#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4754#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 4755#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5048#L816 assume 1 == ~t11_pc~0; 3944#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3945#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4887#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4650#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 4651#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5189#L835 assume 1 == ~t12_pc~0; 5063#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4095#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3934#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3935#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 4807#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4808#L854 assume !(1 == ~t13_pc~0); 4427#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 4428#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4477#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4126#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4127#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5547#L1401 assume !(1 == ~M_E~0); 4637#L1401-2 assume !(1 == ~T1_E~0); 4638#L1406-1 assume !(1 == ~T2_E~0); 5245#L1411-1 assume !(1 == ~T3_E~0); 5246#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4897#L1421-1 assume !(1 == ~T5_E~0); 4423#L1426-1 assume !(1 == ~T6_E~0); 4424#L1431-1 assume !(1 == ~T7_E~0); 3981#L1436-1 assume !(1 == ~T8_E~0); 3982#L1441-1 assume !(1 == ~T9_E~0); 4745#L1446-1 assume !(1 == ~T10_E~0); 4746#L1451-1 assume !(1 == ~T11_E~0); 5457#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5116#L1461-1 assume !(1 == ~T13_E~0); 4666#L1466-1 assume !(1 == ~E_1~0); 4667#L1471-1 assume !(1 == ~E_2~0); 5438#L1476-1 assume !(1 == ~E_3~0); 5439#L1481-1 assume !(1 == ~E_4~0); 5592#L1486-1 assume !(1 == ~E_5~0); 4252#L1491-1 assume !(1 == ~E_6~0); 3919#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 3920#L1501-1 assume !(1 == ~E_8~0); 4741#L1506-1 assume !(1 == ~E_9~0); 4742#L1511-1 assume !(1 == ~E_10~0); 4696#L1516-1 assume !(1 == ~E_11~0); 3871#L1521-1 assume !(1 == ~E_12~0); 3872#L1526-1 assume !(1 == ~E_13~0); 3918#L1531-1 assume { :end_inline_reset_delta_events } true; 4449#L1892-2 [2022-12-13 15:11:58,975 INFO L750 eck$LassoCheckResult]: Loop: 4449#L1892-2 assume !false; 5499#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5697#L1233 assume !false; 5680#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5005#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4985#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5528#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3960#L1046 assume !(0 != eval_~tmp~0#1); 3962#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4494#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4495#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5737#L1258-5 assume !(0 == ~T1_E~0); 4116#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4117#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5729#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5733#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5734#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4352#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4353#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5496#L1298-3 assume !(0 == ~T9_E~0); 5497#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5660#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5495#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4989#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4118#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4119#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5584#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4263#L1338-3 assume !(0 == ~E_4~0); 4264#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5415#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5589#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5590#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4936#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4484#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4485#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5276#L1378-3 assume !(0 == ~E_12~0); 5277#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5454#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5455#L607-42 assume 1 == ~m_pc~0; 5073#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4791#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4624#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4504#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4505#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5049#L626-42 assume 1 == ~t1_pc~0; 4595#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4596#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5684#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5470#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4152#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4153#L645-42 assume !(1 == ~t2_pc~0); 5395#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 5396#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4934#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4372#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3891#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3892#L664-42 assume !(1 == ~t3_pc~0); 4408#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 4409#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5335#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5222#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5223#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5388#L683-42 assume 1 == ~t4_pc~0; 5745#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5100#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5229#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5391#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5650#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5490#L702-42 assume 1 == ~t5_pc~0; 4966#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4586#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4890#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4999#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3903#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3904#L721-42 assume 1 == ~t6_pc~0; 4043#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4064#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4243#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4244#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4722#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4559#L740-42 assume 1 == ~t7_pc~0; 4560#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4279#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4851#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4705#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 4706#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4972#L759-42 assume 1 == ~t8_pc~0; 4827#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4764#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4765#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4836#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4837#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4926#L778-42 assume 1 == ~t9_pc~0; 4776#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4778#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5194#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5101#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5102#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5156#L797-42 assume !(1 == ~t10_pc~0); 4288#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 4287#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5174#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5175#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5195#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5196#L816-42 assume 1 == ~t11_pc~0; 3863#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3864#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5690#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4751#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4463#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4464#L835-42 assume !(1 == ~t12_pc~0); 4787#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 4788#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4975#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4976#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 5550#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5333#L854-42 assume !(1 == ~t13_pc~0); 4384#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 4385#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4551#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4552#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4662#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4663#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5448#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4215#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4090#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4091#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4712#L1421-3 assume !(1 == ~T5_E~0); 4713#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4257#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4258#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3875#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3876#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5474#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4799#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4431#L1461-3 assume !(1 == ~T13_E~0); 4432#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5731#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4373#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4374#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4796#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4401#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4402#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4833#L1501-3 assume !(1 == ~E_8~0); 4834#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5272#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 5260#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 5261#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4939#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 4940#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5355#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4190#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4237#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4238#L1911 assume !(0 == start_simulation_~tmp~3#1); 4768#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5294#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4328#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 3913#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 3914#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4037#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4797#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 5603#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 4449#L1892-2 [2022-12-13 15:11:58,976 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:58,976 INFO L85 PathProgramCache]: Analyzing trace with hash 517365666, now seen corresponding path program 2 times [2022-12-13 15:11:58,976 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:58,977 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1271845395] [2022-12-13 15:11:58,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:58,977 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:58,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:59,039 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:59,039 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:59,039 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1271845395] [2022-12-13 15:11:59,040 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1271845395] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:59,040 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:59,040 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:11:59,040 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2015878347] [2022-12-13 15:11:59,040 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:59,041 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:11:59,041 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:59,042 INFO L85 PathProgramCache]: Analyzing trace with hash -1408151266, now seen corresponding path program 1 times [2022-12-13 15:11:59,042 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:59,042 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [799168926] [2022-12-13 15:11:59,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:59,043 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:59,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:59,121 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:59,121 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:59,121 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [799168926] [2022-12-13 15:11:59,121 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [799168926] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:59,122 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:59,122 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:11:59,122 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [453427298] [2022-12-13 15:11:59,122 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:59,122 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:11:59,122 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:11:59,123 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:11:59,123 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:11:59,123 INFO L87 Difference]: Start difference. First operand 1914 states and 2835 transitions. cyclomatic complexity: 922 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:59,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:11:59,174 INFO L93 Difference]: Finished difference Result 1914 states and 2834 transitions. [2022-12-13 15:11:59,174 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2834 transitions. [2022-12-13 15:11:59,180 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 15:11:59,189 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2834 transitions. [2022-12-13 15:11:59,189 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-12-13 15:11:59,190 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-12-13 15:11:59,190 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2834 transitions. [2022-12-13 15:11:59,193 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:11:59,193 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2834 transitions. [2022-12-13 15:11:59,197 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2834 transitions. [2022-12-13 15:11:59,219 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-12-13 15:11:59,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4806687565308254) internal successors, (2834), 1913 states have internal predecessors, (2834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:59,227 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2834 transitions. [2022-12-13 15:11:59,228 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2834 transitions. [2022-12-13 15:11:59,228 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:11:59,229 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2834 transitions. [2022-12-13 15:11:59,229 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 15:11:59,229 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2834 transitions. [2022-12-13 15:11:59,238 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 15:11:59,238 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:11:59,238 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:11:59,240 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:59,241 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:59,241 INFO L748 eck$LassoCheckResult]: Stem: 7971#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 7972#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 8866#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8867#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9588#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 9264#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9265#L886-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8196#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8197#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8670#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8508#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8509#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8260#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8261#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8678#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8857#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9025#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9059#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 8276#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8277#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 9480#L1258-2 assume !(0 == ~T1_E~0); 8593#L1263-1 assume !(0 == ~T2_E~0); 8594#L1268-1 assume !(0 == ~T3_E~0); 8903#L1273-1 assume !(0 == ~T4_E~0); 9459#L1278-1 assume !(0 == ~T5_E~0); 9318#L1283-1 assume !(0 == ~T6_E~0); 9319#L1288-1 assume !(0 == ~T7_E~0); 9556#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9545#L1298-1 assume !(0 == ~T9_E~0); 9475#L1303-1 assume !(0 == ~T10_E~0); 8074#L1308-1 assume !(0 == ~T11_E~0); 8014#L1313-1 assume !(0 == ~T12_E~0); 8015#L1318-1 assume !(0 == ~T13_E~0); 8020#L1323-1 assume !(0 == ~E_1~0); 8021#L1328-1 assume !(0 == ~E_2~0); 8206#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 9194#L1338-1 assume !(0 == ~E_4~0); 9195#L1343-1 assume !(0 == ~E_5~0); 9295#L1348-1 assume !(0 == ~E_6~0); 9575#L1353-1 assume !(0 == ~E_7~0); 8926#L1358-1 assume !(0 == ~E_8~0); 8927#L1363-1 assume !(0 == ~E_9~0); 9216#L1368-1 assume !(0 == ~E_10~0); 7867#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 7868#L1378-1 assume !(0 == ~E_12~0); 8149#L1383-1 assume !(0 == ~E_13~0); 8150#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8931#L607 assume 1 == ~m_pc~0; 8932#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8224#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8733#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8734#L1560 assume !(0 != activate_threads_~tmp~1#1); 8839#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8035#L626 assume !(1 == ~t1_pc~0); 8036#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8317#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8318#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9203#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 7939#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7940#L645 assume 1 == ~t2_pc~0; 8051#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8008#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8117#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8118#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 8813#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8814#L664 assume 1 == ~t3_pc~0; 9573#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7801#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7802#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8466#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 8467#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9488#L683 assume !(1 == ~t4_pc~0); 9043#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8996#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7825#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7826#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9151#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8756#L702 assume 1 == ~t5_pc~0; 8757#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8693#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9147#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9478#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 9386#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7837#L721 assume !(1 == ~t6_pc~0); 7818#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7819#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7963#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8102#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 8479#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9091#L740 assume 1 == ~t7_pc~0; 7883#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7718#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7719#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7708#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 7709#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8406#L759 assume !(1 == ~t8_pc~0); 8407#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8438#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9533#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9275#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 9276#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9555#L778 assume 1 == ~t9_pc~0; 9444#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7866#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8172#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7744#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 7745#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8047#L797 assume !(1 == ~t10_pc~0); 8048#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8182#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9421#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8589#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 8590#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8883#L816 assume 1 == ~t11_pc~0; 7779#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7780#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8722#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8485#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 8486#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9024#L835 assume 1 == ~t12_pc~0; 8898#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7930#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7769#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7770#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 8642#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8643#L854 assume !(1 == ~t13_pc~0); 8262#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 8263#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8312#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7961#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 7962#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9382#L1401 assume !(1 == ~M_E~0); 8472#L1401-2 assume !(1 == ~T1_E~0); 8473#L1406-1 assume !(1 == ~T2_E~0); 9080#L1411-1 assume !(1 == ~T3_E~0); 9081#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8732#L1421-1 assume !(1 == ~T5_E~0); 8258#L1426-1 assume !(1 == ~T6_E~0); 8259#L1431-1 assume !(1 == ~T7_E~0); 7816#L1436-1 assume !(1 == ~T8_E~0); 7817#L1441-1 assume !(1 == ~T9_E~0); 8580#L1446-1 assume !(1 == ~T10_E~0); 8581#L1451-1 assume !(1 == ~T11_E~0); 9292#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8951#L1461-1 assume !(1 == ~T13_E~0); 8501#L1466-1 assume !(1 == ~E_1~0); 8502#L1471-1 assume !(1 == ~E_2~0); 9273#L1476-1 assume !(1 == ~E_3~0); 9274#L1481-1 assume !(1 == ~E_4~0); 9427#L1486-1 assume !(1 == ~E_5~0); 8087#L1491-1 assume !(1 == ~E_6~0); 7754#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7755#L1501-1 assume !(1 == ~E_8~0); 8576#L1506-1 assume !(1 == ~E_9~0); 8577#L1511-1 assume !(1 == ~E_10~0); 8531#L1516-1 assume !(1 == ~E_11~0); 7706#L1521-1 assume !(1 == ~E_12~0); 7707#L1526-1 assume !(1 == ~E_13~0); 7753#L1531-1 assume { :end_inline_reset_delta_events } true; 8284#L1892-2 [2022-12-13 15:11:59,242 INFO L750 eck$LassoCheckResult]: Loop: 8284#L1892-2 assume !false; 9334#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9532#L1233 assume !false; 9515#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8840#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8820#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 9363#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7795#L1046 assume !(0 != eval_~tmp~0#1); 7797#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8329#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8330#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9572#L1258-5 assume !(0 == ~T1_E~0); 7951#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7952#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9564#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9568#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9569#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8187#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8188#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9331#L1298-3 assume !(0 == ~T9_E~0); 9332#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9495#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9330#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8824#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 7953#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7954#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9419#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8098#L1338-3 assume !(0 == ~E_4~0); 8099#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9250#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9424#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9425#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8771#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8319#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8320#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 9111#L1378-3 assume !(0 == ~E_12~0); 9112#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 9289#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9290#L607-42 assume 1 == ~m_pc~0; 8908#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8626#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8459#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8339#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8340#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8884#L626-42 assume !(1 == ~t1_pc~0); 8432#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 8431#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9519#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9305#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7987#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7988#L645-42 assume !(1 == ~t2_pc~0); 9230#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 9231#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8769#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8207#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7726#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7727#L664-42 assume !(1 == ~t3_pc~0); 8243#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 8244#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9170#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9057#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9058#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9223#L683-42 assume !(1 == ~t4_pc~0); 8934#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 8935#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9064#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9226#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9485#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9325#L702-42 assume 1 == ~t5_pc~0; 8801#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8421#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8725#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8834#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7738#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7739#L721-42 assume 1 == ~t6_pc~0; 7878#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7899#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8078#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8079#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8557#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8394#L740-42 assume !(1 == ~t7_pc~0); 8113#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 8114#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8686#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8540#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 8541#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8807#L759-42 assume 1 == ~t8_pc~0; 8662#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8599#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8600#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8671#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8672#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8761#L778-42 assume 1 == ~t9_pc~0; 8611#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8613#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9029#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8936#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8937#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8991#L797-42 assume 1 == ~t10_pc~0; 8121#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8122#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9009#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9010#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9030#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9031#L816-42 assume 1 == ~t11_pc~0; 7698#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7699#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9525#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8586#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8298#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8299#L835-42 assume 1 == ~t12_pc~0; 8721#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 8623#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8810#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8811#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 9385#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9168#L854-42 assume 1 == ~t13_pc~0; 9169#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 8220#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8386#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8387#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 8497#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8498#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9283#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8050#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7925#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7926#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8547#L1421-3 assume !(1 == ~T5_E~0); 8548#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8092#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8093#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7710#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7711#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9309#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8634#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8266#L1461-3 assume !(1 == ~T13_E~0); 8267#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9566#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8208#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8209#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8631#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8236#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8237#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8668#L1501-3 assume !(1 == ~E_8~0); 8669#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9107#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9095#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 9096#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8774#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 8775#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9190#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8025#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8072#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 8073#L1911 assume !(0 == start_simulation_~tmp~3#1); 8603#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9129#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8163#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 7748#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 7749#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7872#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8632#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 9438#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 8284#L1892-2 [2022-12-13 15:11:59,242 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:59,242 INFO L85 PathProgramCache]: Analyzing trace with hash -2008130016, now seen corresponding path program 1 times [2022-12-13 15:11:59,243 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:59,243 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [403231236] [2022-12-13 15:11:59,243 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:59,243 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:59,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:59,303 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:59,304 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:59,304 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [403231236] [2022-12-13 15:11:59,304 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [403231236] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:59,304 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:59,304 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:11:59,305 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [446003749] [2022-12-13 15:11:59,305 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:59,305 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:11:59,306 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:59,306 INFO L85 PathProgramCache]: Analyzing trace with hash 326329950, now seen corresponding path program 1 times [2022-12-13 15:11:59,306 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:59,306 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1045626038] [2022-12-13 15:11:59,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:59,307 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:59,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:59,379 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:59,379 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:59,379 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1045626038] [2022-12-13 15:11:59,379 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1045626038] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:59,380 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:59,380 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:11:59,380 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1483747243] [2022-12-13 15:11:59,380 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:59,380 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:11:59,381 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:11:59,381 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:11:59,381 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:11:59,381 INFO L87 Difference]: Start difference. First operand 1914 states and 2834 transitions. cyclomatic complexity: 921 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:59,412 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:11:59,413 INFO L93 Difference]: Finished difference Result 1914 states and 2833 transitions. [2022-12-13 15:11:59,413 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2833 transitions. [2022-12-13 15:11:59,419 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 15:11:59,423 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2833 transitions. [2022-12-13 15:11:59,424 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-12-13 15:11:59,425 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-12-13 15:11:59,425 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2833 transitions. [2022-12-13 15:11:59,427 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:11:59,427 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2833 transitions. [2022-12-13 15:11:59,429 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2833 transitions. [2022-12-13 15:11:59,443 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-12-13 15:11:59,445 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.480146290491118) internal successors, (2833), 1913 states have internal predecessors, (2833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:59,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2833 transitions. [2022-12-13 15:11:59,448 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2833 transitions. [2022-12-13 15:11:59,448 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:11:59,449 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2833 transitions. [2022-12-13 15:11:59,449 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 15:11:59,449 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2833 transitions. [2022-12-13 15:11:59,454 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 15:11:59,454 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:11:59,454 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:11:59,455 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:59,455 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:59,456 INFO L748 eck$LassoCheckResult]: Stem: 11806#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 11807#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 12701#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12702#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13423#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 13099#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13100#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12031#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 12032#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 12505#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 12343#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12344#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12095#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12096#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12513#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12692#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12860#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 12894#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 12111#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12112#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 13315#L1258-2 assume !(0 == ~T1_E~0); 12428#L1263-1 assume !(0 == ~T2_E~0); 12429#L1268-1 assume !(0 == ~T3_E~0); 12738#L1273-1 assume !(0 == ~T4_E~0); 13294#L1278-1 assume !(0 == ~T5_E~0); 13153#L1283-1 assume !(0 == ~T6_E~0); 13154#L1288-1 assume !(0 == ~T7_E~0); 13391#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13380#L1298-1 assume !(0 == ~T9_E~0); 13310#L1303-1 assume !(0 == ~T10_E~0); 11909#L1308-1 assume !(0 == ~T11_E~0); 11849#L1313-1 assume !(0 == ~T12_E~0); 11850#L1318-1 assume !(0 == ~T13_E~0); 11855#L1323-1 assume !(0 == ~E_1~0); 11856#L1328-1 assume !(0 == ~E_2~0); 12041#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 13029#L1338-1 assume !(0 == ~E_4~0); 13030#L1343-1 assume !(0 == ~E_5~0); 13130#L1348-1 assume !(0 == ~E_6~0); 13410#L1353-1 assume !(0 == ~E_7~0); 12761#L1358-1 assume !(0 == ~E_8~0); 12762#L1363-1 assume !(0 == ~E_9~0); 13051#L1368-1 assume !(0 == ~E_10~0); 11702#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 11703#L1378-1 assume !(0 == ~E_12~0); 11984#L1383-1 assume !(0 == ~E_13~0); 11985#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12766#L607 assume 1 == ~m_pc~0; 12767#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 12059#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12568#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12569#L1560 assume !(0 != activate_threads_~tmp~1#1); 12674#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11870#L626 assume !(1 == ~t1_pc~0); 11871#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12152#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12153#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13038#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 11774#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11775#L645 assume 1 == ~t2_pc~0; 11886#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11843#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11952#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11953#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 12648#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12649#L664 assume 1 == ~t3_pc~0; 13408#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11636#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11637#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12301#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 12302#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13323#L683 assume !(1 == ~t4_pc~0); 12878#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12831#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11660#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11661#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12986#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12591#L702 assume 1 == ~t5_pc~0; 12592#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12528#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12982#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13313#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 13221#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11672#L721 assume !(1 == ~t6_pc~0); 11653#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 11654#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11798#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11937#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 12314#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12926#L740 assume 1 == ~t7_pc~0; 11718#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11553#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11554#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11543#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 11544#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12241#L759 assume !(1 == ~t8_pc~0); 12242#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12273#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13368#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13110#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 13111#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13390#L778 assume 1 == ~t9_pc~0; 13279#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11701#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12007#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11579#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 11580#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11882#L797 assume !(1 == ~t10_pc~0); 11883#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12017#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13256#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12424#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 12425#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12718#L816 assume 1 == ~t11_pc~0; 11614#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11615#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12557#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12320#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 12321#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12859#L835 assume 1 == ~t12_pc~0; 12733#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 11765#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11604#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11605#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 12477#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12478#L854 assume !(1 == ~t13_pc~0); 12097#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 12098#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12147#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11796#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 11797#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13217#L1401 assume !(1 == ~M_E~0); 12307#L1401-2 assume !(1 == ~T1_E~0); 12308#L1406-1 assume !(1 == ~T2_E~0); 12915#L1411-1 assume !(1 == ~T3_E~0); 12916#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12567#L1421-1 assume !(1 == ~T5_E~0); 12093#L1426-1 assume !(1 == ~T6_E~0); 12094#L1431-1 assume !(1 == ~T7_E~0); 11651#L1436-1 assume !(1 == ~T8_E~0); 11652#L1441-1 assume !(1 == ~T9_E~0); 12415#L1446-1 assume !(1 == ~T10_E~0); 12416#L1451-1 assume !(1 == ~T11_E~0); 13127#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12786#L1461-1 assume !(1 == ~T13_E~0); 12336#L1466-1 assume !(1 == ~E_1~0); 12337#L1471-1 assume !(1 == ~E_2~0); 13108#L1476-1 assume !(1 == ~E_3~0); 13109#L1481-1 assume !(1 == ~E_4~0); 13262#L1486-1 assume !(1 == ~E_5~0); 11922#L1491-1 assume !(1 == ~E_6~0); 11589#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 11590#L1501-1 assume !(1 == ~E_8~0); 12411#L1506-1 assume !(1 == ~E_9~0); 12412#L1511-1 assume !(1 == ~E_10~0); 12366#L1516-1 assume !(1 == ~E_11~0); 11541#L1521-1 assume !(1 == ~E_12~0); 11542#L1526-1 assume !(1 == ~E_13~0); 11588#L1531-1 assume { :end_inline_reset_delta_events } true; 12119#L1892-2 [2022-12-13 15:11:59,456 INFO L750 eck$LassoCheckResult]: Loop: 12119#L1892-2 assume !false; 13169#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13367#L1233 assume !false; 13350#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12675#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12655#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 13198#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11630#L1046 assume !(0 != eval_~tmp~0#1); 11632#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12164#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12165#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13407#L1258-5 assume !(0 == ~T1_E~0); 11786#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11787#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13399#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13403#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13404#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12022#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12023#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13166#L1298-3 assume !(0 == ~T9_E~0); 13167#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13330#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13165#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 12659#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 11788#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11789#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13254#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11933#L1338-3 assume !(0 == ~E_4~0); 11934#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13085#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13259#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13260#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12606#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12154#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12155#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 12946#L1378-3 assume !(0 == ~E_12~0); 12947#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13124#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13125#L607-42 assume 1 == ~m_pc~0; 12743#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 12461#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12294#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12174#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12175#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12719#L626-42 assume 1 == ~t1_pc~0; 12265#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12266#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13354#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13140#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11822#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11823#L645-42 assume !(1 == ~t2_pc~0); 13065#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 13066#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12604#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12042#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11561#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11562#L664-42 assume 1 == ~t3_pc~0; 12372#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12079#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13005#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12892#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12893#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13058#L683-42 assume !(1 == ~t4_pc~0); 12769#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 12770#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12899#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13061#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13320#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13160#L702-42 assume 1 == ~t5_pc~0; 12636#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12256#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12560#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12669#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11573#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11574#L721-42 assume 1 == ~t6_pc~0; 11713#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11734#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11913#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11914#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12392#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12229#L740-42 assume 1 == ~t7_pc~0; 12230#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11949#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12521#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12375#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 12376#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12642#L759-42 assume 1 == ~t8_pc~0; 12497#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12434#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12435#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12506#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12507#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12596#L778-42 assume 1 == ~t9_pc~0; 12446#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12448#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12864#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12771#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12772#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12826#L797-42 assume 1 == ~t10_pc~0; 11956#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11957#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12844#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12845#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12865#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12866#L816-42 assume 1 == ~t11_pc~0; 11533#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11534#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13360#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12421#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 12133#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12134#L835-42 assume !(1 == ~t12_pc~0); 12457#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 12458#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12645#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12646#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13220#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 13003#L854-42 assume !(1 == ~t13_pc~0); 12054#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 12055#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12221#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12222#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 12332#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12333#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13118#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11885#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11760#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11761#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12382#L1421-3 assume !(1 == ~T5_E~0); 12383#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11927#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11928#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11545#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11546#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13144#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12469#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12101#L1461-3 assume !(1 == ~T13_E~0); 12102#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13401#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12043#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12044#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12466#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12071#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12072#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12503#L1501-3 assume !(1 == ~E_8~0); 12504#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12942#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12930#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12931#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12609#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 12610#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13025#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 11860#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 11907#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 11908#L1911 assume !(0 == start_simulation_~tmp~3#1); 12438#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12964#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 11998#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 11583#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 11584#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11707#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12467#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 13273#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 12119#L1892-2 [2022-12-13 15:11:59,457 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:59,457 INFO L85 PathProgramCache]: Analyzing trace with hash -602938338, now seen corresponding path program 1 times [2022-12-13 15:11:59,457 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:59,457 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1682083684] [2022-12-13 15:11:59,457 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:59,457 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:59,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:59,510 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:59,510 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:59,511 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1682083684] [2022-12-13 15:11:59,511 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1682083684] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:59,511 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:59,511 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:11:59,511 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1836312809] [2022-12-13 15:11:59,512 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:59,512 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:11:59,512 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:59,512 INFO L85 PathProgramCache]: Analyzing trace with hash 857518015, now seen corresponding path program 1 times [2022-12-13 15:11:59,513 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:59,513 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1325162221] [2022-12-13 15:11:59,513 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:59,513 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:59,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:59,564 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:59,564 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:59,564 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1325162221] [2022-12-13 15:11:59,564 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1325162221] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:59,565 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:59,565 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:11:59,565 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1774885100] [2022-12-13 15:11:59,565 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:59,565 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:11:59,566 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:11:59,566 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:11:59,566 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:11:59,566 INFO L87 Difference]: Start difference. First operand 1914 states and 2833 transitions. cyclomatic complexity: 920 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:59,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:11:59,603 INFO L93 Difference]: Finished difference Result 1914 states and 2832 transitions. [2022-12-13 15:11:59,603 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2832 transitions. [2022-12-13 15:11:59,610 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 15:11:59,615 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2832 transitions. [2022-12-13 15:11:59,615 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-12-13 15:11:59,616 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-12-13 15:11:59,616 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2832 transitions. [2022-12-13 15:11:59,618 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:11:59,618 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2832 transitions. [2022-12-13 15:11:59,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2832 transitions. [2022-12-13 15:11:59,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-12-13 15:11:59,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4796238244514106) internal successors, (2832), 1913 states have internal predecessors, (2832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:59,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2832 transitions. [2022-12-13 15:11:59,640 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2832 transitions. [2022-12-13 15:11:59,640 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:11:59,640 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2832 transitions. [2022-12-13 15:11:59,641 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 15:11:59,641 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2832 transitions. [2022-12-13 15:11:59,646 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 15:11:59,646 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:11:59,646 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:11:59,648 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:59,648 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:59,648 INFO L748 eck$LassoCheckResult]: Stem: 15641#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 15642#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 16536#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16537#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17258#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 16934#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16935#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15866#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15867#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 16340#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 16178#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 16179#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 15930#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15931#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16348#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16527#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 16695#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 16729#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 15946#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15947#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 17150#L1258-2 assume !(0 == ~T1_E~0); 16263#L1263-1 assume !(0 == ~T2_E~0); 16264#L1268-1 assume !(0 == ~T3_E~0); 16573#L1273-1 assume !(0 == ~T4_E~0); 17129#L1278-1 assume !(0 == ~T5_E~0); 16988#L1283-1 assume !(0 == ~T6_E~0); 16989#L1288-1 assume !(0 == ~T7_E~0); 17226#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17215#L1298-1 assume !(0 == ~T9_E~0); 17145#L1303-1 assume !(0 == ~T10_E~0); 15744#L1308-1 assume !(0 == ~T11_E~0); 15684#L1313-1 assume !(0 == ~T12_E~0); 15685#L1318-1 assume !(0 == ~T13_E~0); 15690#L1323-1 assume !(0 == ~E_1~0); 15691#L1328-1 assume !(0 == ~E_2~0); 15876#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 16864#L1338-1 assume !(0 == ~E_4~0); 16865#L1343-1 assume !(0 == ~E_5~0); 16965#L1348-1 assume !(0 == ~E_6~0); 17245#L1353-1 assume !(0 == ~E_7~0); 16596#L1358-1 assume !(0 == ~E_8~0); 16597#L1363-1 assume !(0 == ~E_9~0); 16886#L1368-1 assume !(0 == ~E_10~0); 15537#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 15538#L1378-1 assume !(0 == ~E_12~0); 15819#L1383-1 assume !(0 == ~E_13~0); 15820#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16601#L607 assume 1 == ~m_pc~0; 16602#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 15894#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16403#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16404#L1560 assume !(0 != activate_threads_~tmp~1#1); 16509#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15705#L626 assume !(1 == ~t1_pc~0); 15706#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15987#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15988#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16873#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 15609#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15610#L645 assume 1 == ~t2_pc~0; 15721#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15678#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15787#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15788#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 16483#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16484#L664 assume 1 == ~t3_pc~0; 17243#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15471#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15472#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16136#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 16137#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17158#L683 assume !(1 == ~t4_pc~0); 16713#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16666#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15495#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15496#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16821#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16426#L702 assume 1 == ~t5_pc~0; 16427#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16363#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16817#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17148#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 17056#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15507#L721 assume !(1 == ~t6_pc~0); 15488#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 15489#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15633#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15772#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 16149#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16761#L740 assume 1 == ~t7_pc~0; 15553#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15388#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15389#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15378#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 15379#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16076#L759 assume !(1 == ~t8_pc~0); 16077#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16108#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17203#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16945#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 16946#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17225#L778 assume 1 == ~t9_pc~0; 17114#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15536#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15842#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15414#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 15415#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15717#L797 assume !(1 == ~t10_pc~0); 15718#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 15852#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17091#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16259#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 16260#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16553#L816 assume 1 == ~t11_pc~0; 15449#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15450#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16392#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16155#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 16156#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16694#L835 assume 1 == ~t12_pc~0; 16568#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 15600#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15439#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 15440#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 16312#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16313#L854 assume !(1 == ~t13_pc~0); 15932#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 15933#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 15982#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 15631#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 15632#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17052#L1401 assume !(1 == ~M_E~0); 16142#L1401-2 assume !(1 == ~T1_E~0); 16143#L1406-1 assume !(1 == ~T2_E~0); 16750#L1411-1 assume !(1 == ~T3_E~0); 16751#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16402#L1421-1 assume !(1 == ~T5_E~0); 15928#L1426-1 assume !(1 == ~T6_E~0); 15929#L1431-1 assume !(1 == ~T7_E~0); 15486#L1436-1 assume !(1 == ~T8_E~0); 15487#L1441-1 assume !(1 == ~T9_E~0); 16250#L1446-1 assume !(1 == ~T10_E~0); 16251#L1451-1 assume !(1 == ~T11_E~0); 16962#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 16621#L1461-1 assume !(1 == ~T13_E~0); 16171#L1466-1 assume !(1 == ~E_1~0); 16172#L1471-1 assume !(1 == ~E_2~0); 16943#L1476-1 assume !(1 == ~E_3~0); 16944#L1481-1 assume !(1 == ~E_4~0); 17097#L1486-1 assume !(1 == ~E_5~0); 15757#L1491-1 assume !(1 == ~E_6~0); 15424#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 15425#L1501-1 assume !(1 == ~E_8~0); 16246#L1506-1 assume !(1 == ~E_9~0); 16247#L1511-1 assume !(1 == ~E_10~0); 16201#L1516-1 assume !(1 == ~E_11~0); 15376#L1521-1 assume !(1 == ~E_12~0); 15377#L1526-1 assume !(1 == ~E_13~0); 15423#L1531-1 assume { :end_inline_reset_delta_events } true; 15954#L1892-2 [2022-12-13 15:11:59,648 INFO L750 eck$LassoCheckResult]: Loop: 15954#L1892-2 assume !false; 17004#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17202#L1233 assume !false; 17185#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16510#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16490#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 17033#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15465#L1046 assume !(0 != eval_~tmp~0#1); 15467#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15999#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16000#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17242#L1258-5 assume !(0 == ~T1_E~0); 15621#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15622#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17234#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17238#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17239#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15857#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15858#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17001#L1298-3 assume !(0 == ~T9_E~0); 17002#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17165#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 17000#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 16494#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 15623#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15624#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17089#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15768#L1338-3 assume !(0 == ~E_4~0); 15769#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16920#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17094#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17095#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16441#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15989#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15990#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16781#L1378-3 assume !(0 == ~E_12~0); 16782#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 16959#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16960#L607-42 assume 1 == ~m_pc~0; 16578#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16296#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16129#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16009#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16010#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16554#L626-42 assume 1 == ~t1_pc~0; 16100#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16101#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17189#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16975#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15657#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15658#L645-42 assume !(1 == ~t2_pc~0); 16900#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 16901#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16439#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15877#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15396#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15397#L664-42 assume !(1 == ~t3_pc~0); 15913#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 15914#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16840#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16727#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16728#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16893#L683-42 assume 1 == ~t4_pc~0; 17250#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16605#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16734#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16896#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17155#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16995#L702-42 assume 1 == ~t5_pc~0; 16471#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16091#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16395#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16504#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15408#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15409#L721-42 assume 1 == ~t6_pc~0; 15548#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15569#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15748#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15749#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16227#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16064#L740-42 assume 1 == ~t7_pc~0; 16065#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15784#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16356#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16210#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 16211#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16477#L759-42 assume 1 == ~t8_pc~0; 16332#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16269#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16270#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16341#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16342#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16431#L778-42 assume 1 == ~t9_pc~0; 16281#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16283#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16699#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16606#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16607#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16661#L797-42 assume !(1 == ~t10_pc~0); 15793#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 15792#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16679#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16680#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16700#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16701#L816-42 assume 1 == ~t11_pc~0; 15368#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15369#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17195#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16256#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 15968#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15969#L835-42 assume !(1 == ~t12_pc~0); 16292#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 16293#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16480#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16481#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17055#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16838#L854-42 assume !(1 == ~t13_pc~0); 15889#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 15890#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 16056#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16057#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 16167#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16168#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16953#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15720#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15595#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15596#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16217#L1421-3 assume !(1 == ~T5_E~0); 16218#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15762#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15763#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 15380#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15381#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16979#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 16304#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 15936#L1461-3 assume !(1 == ~T13_E~0); 15937#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17236#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15878#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15879#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16301#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15906#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15907#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16338#L1501-3 assume !(1 == ~E_8~0); 16339#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 16777#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16765#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 16766#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 16444#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 16445#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16860#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 15695#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 15742#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 15743#L1911 assume !(0 == start_simulation_~tmp~3#1); 16273#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16799#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 15833#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 15418#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 15419#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15542#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16302#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 17108#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 15954#L1892-2 [2022-12-13 15:11:59,648 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:59,649 INFO L85 PathProgramCache]: Analyzing trace with hash 1797695072, now seen corresponding path program 1 times [2022-12-13 15:11:59,649 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:59,649 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1132098796] [2022-12-13 15:11:59,649 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:59,649 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:59,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:59,684 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:59,684 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:59,684 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1132098796] [2022-12-13 15:11:59,684 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1132098796] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:59,684 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:59,685 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:11:59,685 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2111199646] [2022-12-13 15:11:59,685 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:59,685 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:11:59,686 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:59,686 INFO L85 PathProgramCache]: Analyzing trace with hash -1408151266, now seen corresponding path program 2 times [2022-12-13 15:11:59,686 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:59,686 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1641041219] [2022-12-13 15:11:59,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:59,686 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:59,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:59,742 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:59,742 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:59,742 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1641041219] [2022-12-13 15:11:59,742 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1641041219] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:59,742 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:59,743 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:11:59,743 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1268487238] [2022-12-13 15:11:59,743 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:59,743 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:11:59,743 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:11:59,744 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:11:59,744 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:11:59,744 INFO L87 Difference]: Start difference. First operand 1914 states and 2832 transitions. cyclomatic complexity: 919 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:59,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:11:59,781 INFO L93 Difference]: Finished difference Result 1914 states and 2831 transitions. [2022-12-13 15:11:59,781 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2831 transitions. [2022-12-13 15:11:59,786 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 15:11:59,790 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2831 transitions. [2022-12-13 15:11:59,791 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-12-13 15:11:59,792 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-12-13 15:11:59,792 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2831 transitions. [2022-12-13 15:11:59,795 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:11:59,795 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2831 transitions. [2022-12-13 15:11:59,797 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2831 transitions. [2022-12-13 15:11:59,811 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-12-13 15:11:59,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4791013584117032) internal successors, (2831), 1913 states have internal predecessors, (2831), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:59,816 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2831 transitions. [2022-12-13 15:11:59,817 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2831 transitions. [2022-12-13 15:11:59,817 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:11:59,818 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2831 transitions. [2022-12-13 15:11:59,818 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 15:11:59,818 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2831 transitions. [2022-12-13 15:11:59,825 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 15:11:59,826 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:11:59,826 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:11:59,828 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:59,829 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:11:59,829 INFO L748 eck$LassoCheckResult]: Stem: 19476#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 19477#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 20371#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20372#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21093#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 20769#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20770#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19701#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19702#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20175#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 20013#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 20014#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19765#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19766#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20183#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20362#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 20530#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 20564#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 19781#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19782#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 20985#L1258-2 assume !(0 == ~T1_E~0); 20098#L1263-1 assume !(0 == ~T2_E~0); 20099#L1268-1 assume !(0 == ~T3_E~0); 20408#L1273-1 assume !(0 == ~T4_E~0); 20964#L1278-1 assume !(0 == ~T5_E~0); 20823#L1283-1 assume !(0 == ~T6_E~0); 20824#L1288-1 assume !(0 == ~T7_E~0); 21061#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21050#L1298-1 assume !(0 == ~T9_E~0); 20980#L1303-1 assume !(0 == ~T10_E~0); 19579#L1308-1 assume !(0 == ~T11_E~0); 19519#L1313-1 assume !(0 == ~T12_E~0); 19520#L1318-1 assume !(0 == ~T13_E~0); 19525#L1323-1 assume !(0 == ~E_1~0); 19526#L1328-1 assume !(0 == ~E_2~0); 19711#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 20699#L1338-1 assume !(0 == ~E_4~0); 20700#L1343-1 assume !(0 == ~E_5~0); 20800#L1348-1 assume !(0 == ~E_6~0); 21080#L1353-1 assume !(0 == ~E_7~0); 20431#L1358-1 assume !(0 == ~E_8~0); 20432#L1363-1 assume !(0 == ~E_9~0); 20721#L1368-1 assume !(0 == ~E_10~0); 19372#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 19373#L1378-1 assume !(0 == ~E_12~0); 19654#L1383-1 assume !(0 == ~E_13~0); 19655#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20436#L607 assume 1 == ~m_pc~0; 20437#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 19729#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20238#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20239#L1560 assume !(0 != activate_threads_~tmp~1#1); 20344#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19540#L626 assume !(1 == ~t1_pc~0); 19541#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19822#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19823#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20708#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 19444#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19445#L645 assume 1 == ~t2_pc~0; 19556#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19513#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19622#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19623#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 20318#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20319#L664 assume 1 == ~t3_pc~0; 21078#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19306#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19307#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19971#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 19972#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20993#L683 assume !(1 == ~t4_pc~0); 20548#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20501#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19330#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19331#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20656#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20261#L702 assume 1 == ~t5_pc~0; 20262#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20198#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20652#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20983#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 20891#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19342#L721 assume !(1 == ~t6_pc~0); 19323#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19324#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19468#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19607#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 19984#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20596#L740 assume 1 == ~t7_pc~0; 19388#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19223#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19224#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19213#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 19214#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19911#L759 assume !(1 == ~t8_pc~0); 19912#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19943#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21038#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20780#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 20781#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21060#L778 assume 1 == ~t9_pc~0; 20949#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19371#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19677#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19249#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 19250#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19552#L797 assume !(1 == ~t10_pc~0); 19553#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19687#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20926#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20094#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 20095#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20388#L816 assume 1 == ~t11_pc~0; 19284#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19285#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20227#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19990#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 19991#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20529#L835 assume 1 == ~t12_pc~0; 20403#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 19435#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19274#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19275#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 20147#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20148#L854 assume !(1 == ~t13_pc~0); 19767#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 19768#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 19817#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19466#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 19467#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20887#L1401 assume !(1 == ~M_E~0); 19977#L1401-2 assume !(1 == ~T1_E~0); 19978#L1406-1 assume !(1 == ~T2_E~0); 20585#L1411-1 assume !(1 == ~T3_E~0); 20586#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20237#L1421-1 assume !(1 == ~T5_E~0); 19763#L1426-1 assume !(1 == ~T6_E~0); 19764#L1431-1 assume !(1 == ~T7_E~0); 19321#L1436-1 assume !(1 == ~T8_E~0); 19322#L1441-1 assume !(1 == ~T9_E~0); 20085#L1446-1 assume !(1 == ~T10_E~0); 20086#L1451-1 assume !(1 == ~T11_E~0); 20797#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 20456#L1461-1 assume !(1 == ~T13_E~0); 20006#L1466-1 assume !(1 == ~E_1~0); 20007#L1471-1 assume !(1 == ~E_2~0); 20778#L1476-1 assume !(1 == ~E_3~0); 20779#L1481-1 assume !(1 == ~E_4~0); 20932#L1486-1 assume !(1 == ~E_5~0); 19592#L1491-1 assume !(1 == ~E_6~0); 19259#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19260#L1501-1 assume !(1 == ~E_8~0); 20081#L1506-1 assume !(1 == ~E_9~0); 20082#L1511-1 assume !(1 == ~E_10~0); 20036#L1516-1 assume !(1 == ~E_11~0); 19211#L1521-1 assume !(1 == ~E_12~0); 19212#L1526-1 assume !(1 == ~E_13~0); 19258#L1531-1 assume { :end_inline_reset_delta_events } true; 19789#L1892-2 [2022-12-13 15:11:59,829 INFO L750 eck$LassoCheckResult]: Loop: 19789#L1892-2 assume !false; 20839#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21037#L1233 assume !false; 21020#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20345#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20325#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20868#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 19300#L1046 assume !(0 != eval_~tmp~0#1); 19302#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19834#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19835#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21077#L1258-5 assume !(0 == ~T1_E~0); 19456#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19457#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21069#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21073#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21074#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19692#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19693#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20836#L1298-3 assume !(0 == ~T9_E~0); 20837#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21000#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20835#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 20329#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 19458#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19459#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20924#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19603#L1338-3 assume !(0 == ~E_4~0); 19604#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20755#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20929#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20930#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20276#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19824#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19825#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 20616#L1378-3 assume !(0 == ~E_12~0); 20617#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 20794#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20795#L607-42 assume 1 == ~m_pc~0; 20413#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 20131#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19964#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19844#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19845#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20389#L626-42 assume !(1 == ~t1_pc~0); 19937#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 19936#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21024#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20810#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19492#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19493#L645-42 assume 1 == ~t2_pc~0; 20992#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20736#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20274#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19712#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19231#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19232#L664-42 assume !(1 == ~t3_pc~0); 19748#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 19749#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20675#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20562#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20563#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20728#L683-42 assume !(1 == ~t4_pc~0); 20439#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 20440#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20569#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20731#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20990#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20830#L702-42 assume 1 == ~t5_pc~0; 20306#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19926#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20230#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20339#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19243#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19244#L721-42 assume 1 == ~t6_pc~0; 19383#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19404#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19583#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19584#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20062#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19899#L740-42 assume !(1 == ~t7_pc~0); 19618#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 19619#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20191#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20045#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 20046#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20312#L759-42 assume 1 == ~t8_pc~0; 20167#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20104#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20105#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20176#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20177#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20266#L778-42 assume 1 == ~t9_pc~0; 20116#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20118#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20534#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20441#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20442#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20496#L797-42 assume 1 == ~t10_pc~0; 19626#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19627#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20514#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20515#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20535#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20536#L816-42 assume 1 == ~t11_pc~0; 19203#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19204#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21030#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20091#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 19803#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19804#L835-42 assume 1 == ~t12_pc~0; 20226#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20128#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20315#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20316#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 20890#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20673#L854-42 assume 1 == ~t13_pc~0; 20674#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 19725#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 19891#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19892#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 20002#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20003#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20788#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19555#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19430#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19431#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20052#L1421-3 assume !(1 == ~T5_E~0); 20053#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19597#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19598#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19215#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19216#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 20814#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 20139#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 19771#L1461-3 assume !(1 == ~T13_E~0); 19772#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21071#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19713#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19714#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20136#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19741#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19742#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20173#L1501-3 assume !(1 == ~E_8~0); 20174#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20612#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20600#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 20601#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 20279#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 20280#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20695#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 19530#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 19577#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 19578#L1911 assume !(0 == start_simulation_~tmp~3#1); 20108#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20634#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 19668#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 19253#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 19254#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19377#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20137#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 20943#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 19789#L1892-2 [2022-12-13 15:11:59,830 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:59,830 INFO L85 PathProgramCache]: Analyzing trace with hash 351114206, now seen corresponding path program 1 times [2022-12-13 15:11:59,830 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:59,830 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [172021291] [2022-12-13 15:11:59,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:59,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:59,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:59,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:59,870 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:59,870 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [172021291] [2022-12-13 15:11:59,870 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [172021291] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:59,870 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:59,870 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:11:59,870 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1366143484] [2022-12-13 15:11:59,871 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:59,871 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:11:59,871 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:11:59,871 INFO L85 PathProgramCache]: Analyzing trace with hash -676295745, now seen corresponding path program 1 times [2022-12-13 15:11:59,872 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:11:59,872 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1945885779] [2022-12-13 15:11:59,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:11:59,872 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:11:59,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:11:59,924 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:11:59,924 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:11:59,924 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1945885779] [2022-12-13 15:11:59,924 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1945885779] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:11:59,924 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:11:59,925 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:11:59,925 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1948321810] [2022-12-13 15:11:59,925 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:11:59,925 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:11:59,925 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:11:59,926 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:11:59,926 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:11:59,926 INFO L87 Difference]: Start difference. First operand 1914 states and 2831 transitions. cyclomatic complexity: 918 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:59,963 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:11:59,963 INFO L93 Difference]: Finished difference Result 1914 states and 2830 transitions. [2022-12-13 15:11:59,963 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2830 transitions. [2022-12-13 15:11:59,968 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 15:11:59,973 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2830 transitions. [2022-12-13 15:11:59,973 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-12-13 15:11:59,974 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-12-13 15:11:59,974 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2830 transitions. [2022-12-13 15:11:59,976 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:11:59,976 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2830 transitions. [2022-12-13 15:11:59,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2830 transitions. [2022-12-13 15:11:59,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-12-13 15:11:59,994 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4785788923719958) internal successors, (2830), 1913 states have internal predecessors, (2830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:11:59,996 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2830 transitions. [2022-12-13 15:11:59,996 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2830 transitions. [2022-12-13 15:11:59,997 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:11:59,997 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2830 transitions. [2022-12-13 15:11:59,997 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 15:11:59,997 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2830 transitions. [2022-12-13 15:12:00,002 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 15:12:00,002 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:00,002 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:00,004 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:00,004 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:00,004 INFO L748 eck$LassoCheckResult]: Stem: 23311#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 23312#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 24206#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24207#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24928#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 24604#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24605#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23536#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23537#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24010#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23848#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 23849#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23600#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 23601#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24018#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24197#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24365#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 24399#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 23616#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23617#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 24820#L1258-2 assume !(0 == ~T1_E~0); 23933#L1263-1 assume !(0 == ~T2_E~0); 23934#L1268-1 assume !(0 == ~T3_E~0); 24243#L1273-1 assume !(0 == ~T4_E~0); 24799#L1278-1 assume !(0 == ~T5_E~0); 24658#L1283-1 assume !(0 == ~T6_E~0); 24659#L1288-1 assume !(0 == ~T7_E~0); 24896#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24885#L1298-1 assume !(0 == ~T9_E~0); 24815#L1303-1 assume !(0 == ~T10_E~0); 23414#L1308-1 assume !(0 == ~T11_E~0); 23354#L1313-1 assume !(0 == ~T12_E~0); 23355#L1318-1 assume !(0 == ~T13_E~0); 23360#L1323-1 assume !(0 == ~E_1~0); 23361#L1328-1 assume !(0 == ~E_2~0); 23546#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 24534#L1338-1 assume !(0 == ~E_4~0); 24535#L1343-1 assume !(0 == ~E_5~0); 24635#L1348-1 assume !(0 == ~E_6~0); 24915#L1353-1 assume !(0 == ~E_7~0); 24266#L1358-1 assume !(0 == ~E_8~0); 24267#L1363-1 assume !(0 == ~E_9~0); 24556#L1368-1 assume !(0 == ~E_10~0); 23207#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 23208#L1378-1 assume !(0 == ~E_12~0); 23489#L1383-1 assume !(0 == ~E_13~0); 23490#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24271#L607 assume 1 == ~m_pc~0; 24272#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23564#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24073#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24074#L1560 assume !(0 != activate_threads_~tmp~1#1); 24179#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23375#L626 assume !(1 == ~t1_pc~0); 23376#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23657#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23658#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24543#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 23279#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23280#L645 assume 1 == ~t2_pc~0; 23391#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23348#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23457#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23458#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 24153#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24154#L664 assume 1 == ~t3_pc~0; 24913#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23141#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23142#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23806#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 23807#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24828#L683 assume !(1 == ~t4_pc~0); 24383#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24336#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23165#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23166#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24491#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24096#L702 assume 1 == ~t5_pc~0; 24097#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24033#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24487#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24818#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 24726#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23177#L721 assume !(1 == ~t6_pc~0); 23158#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 23159#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23303#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23442#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 23819#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24431#L740 assume 1 == ~t7_pc~0; 23223#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23058#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23059#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23048#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 23049#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23746#L759 assume !(1 == ~t8_pc~0); 23747#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 23778#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24873#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24615#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 24616#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24895#L778 assume 1 == ~t9_pc~0; 24784#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23206#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23512#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23084#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 23085#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23387#L797 assume !(1 == ~t10_pc~0); 23388#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 23522#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24761#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23929#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 23930#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24223#L816 assume 1 == ~t11_pc~0; 23119#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23120#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24062#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23825#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 23826#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24364#L835 assume 1 == ~t12_pc~0; 24238#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 23270#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 23109#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23110#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 23982#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 23983#L854 assume !(1 == ~t13_pc~0); 23602#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 23603#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 23652#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 23301#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 23302#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24722#L1401 assume !(1 == ~M_E~0); 23812#L1401-2 assume !(1 == ~T1_E~0); 23813#L1406-1 assume !(1 == ~T2_E~0); 24420#L1411-1 assume !(1 == ~T3_E~0); 24421#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24072#L1421-1 assume !(1 == ~T5_E~0); 23598#L1426-1 assume !(1 == ~T6_E~0); 23599#L1431-1 assume !(1 == ~T7_E~0); 23156#L1436-1 assume !(1 == ~T8_E~0); 23157#L1441-1 assume !(1 == ~T9_E~0); 23920#L1446-1 assume !(1 == ~T10_E~0); 23921#L1451-1 assume !(1 == ~T11_E~0); 24632#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 24291#L1461-1 assume !(1 == ~T13_E~0); 23841#L1466-1 assume !(1 == ~E_1~0); 23842#L1471-1 assume !(1 == ~E_2~0); 24613#L1476-1 assume !(1 == ~E_3~0); 24614#L1481-1 assume !(1 == ~E_4~0); 24767#L1486-1 assume !(1 == ~E_5~0); 23427#L1491-1 assume !(1 == ~E_6~0); 23094#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 23095#L1501-1 assume !(1 == ~E_8~0); 23916#L1506-1 assume !(1 == ~E_9~0); 23917#L1511-1 assume !(1 == ~E_10~0); 23871#L1516-1 assume !(1 == ~E_11~0); 23046#L1521-1 assume !(1 == ~E_12~0); 23047#L1526-1 assume !(1 == ~E_13~0); 23093#L1531-1 assume { :end_inline_reset_delta_events } true; 23624#L1892-2 [2022-12-13 15:12:00,004 INFO L750 eck$LassoCheckResult]: Loop: 23624#L1892-2 assume !false; 24674#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24872#L1233 assume !false; 24855#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24180#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24160#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24703#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 23135#L1046 assume !(0 != eval_~tmp~0#1); 23137#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23669#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23670#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 24912#L1258-5 assume !(0 == ~T1_E~0); 23291#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23292#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24904#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24908#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24909#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23527#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23528#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24671#L1298-3 assume !(0 == ~T9_E~0); 24672#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24835#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 24670#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 24164#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 23293#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23294#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24759#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23438#L1338-3 assume !(0 == ~E_4~0); 23439#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 24590#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24764#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24765#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24111#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 23659#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 23660#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24451#L1378-3 assume !(0 == ~E_12~0); 24452#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 24629#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24630#L607-42 assume 1 == ~m_pc~0; 24248#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23966#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23799#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23679#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 23680#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24224#L626-42 assume 1 == ~t1_pc~0; 23770#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23771#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24859#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24645#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23327#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23328#L645-42 assume !(1 == ~t2_pc~0); 24570#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 24571#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24109#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23547#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23066#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23067#L664-42 assume 1 == ~t3_pc~0; 23877#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23584#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24510#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24397#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24398#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24563#L683-42 assume !(1 == ~t4_pc~0); 24274#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 24275#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24404#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24566#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24825#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24665#L702-42 assume !(1 == ~t5_pc~0); 23760#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 23761#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24065#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24174#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 23078#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23079#L721-42 assume 1 == ~t6_pc~0; 23218#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23239#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23418#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23419#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23897#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23734#L740-42 assume 1 == ~t7_pc~0; 23735#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23454#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24026#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23880#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 23881#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24147#L759-42 assume 1 == ~t8_pc~0; 24002#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 23939#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23940#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24011#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24012#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24101#L778-42 assume !(1 == ~t9_pc~0); 23952#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 23953#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24369#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24276#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24277#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24331#L797-42 assume 1 == ~t10_pc~0; 23461#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 23462#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24349#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24350#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24370#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24371#L816-42 assume !(1 == ~t11_pc~0); 23040#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 23039#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24865#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23926#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 23638#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 23639#L835-42 assume !(1 == ~t12_pc~0); 23962#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 23963#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24150#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 24151#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 24725#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 24508#L854-42 assume !(1 == ~t13_pc~0); 23559#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 23560#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 23726#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 23727#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 23837#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23838#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24623#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23390#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23265#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23266#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23887#L1421-3 assume !(1 == ~T5_E~0); 23888#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23432#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23433#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 23050#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 23051#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 24649#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 23974#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 23606#L1461-3 assume !(1 == ~T13_E~0); 23607#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24906#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23548#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23549#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23971#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23576#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23577#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24008#L1501-3 assume !(1 == ~E_8~0); 24009#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24447#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24435#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24436#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 24114#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 24115#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24530#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 23365#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 23412#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 23413#L1911 assume !(0 == start_simulation_~tmp~3#1); 23943#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24469#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 23503#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 23088#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 23089#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23212#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23972#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 24778#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 23624#L1892-2 [2022-12-13 15:12:00,004 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:00,005 INFO L85 PathProgramCache]: Analyzing trace with hash 1274281632, now seen corresponding path program 1 times [2022-12-13 15:12:00,005 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:00,005 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1108015953] [2022-12-13 15:12:00,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:00,005 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:00,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:00,054 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:00,054 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:00,054 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1108015953] [2022-12-13 15:12:00,054 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1108015953] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:00,054 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:00,055 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:00,055 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1673780623] [2022-12-13 15:12:00,055 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:00,055 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:00,056 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:00,056 INFO L85 PathProgramCache]: Analyzing trace with hash 895622492, now seen corresponding path program 1 times [2022-12-13 15:12:00,056 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:00,056 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1478152579] [2022-12-13 15:12:00,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:00,056 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:00,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:00,099 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:00,100 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:00,100 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1478152579] [2022-12-13 15:12:00,100 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1478152579] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:00,100 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:00,100 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:00,100 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [963955419] [2022-12-13 15:12:00,101 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:00,101 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:00,101 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:00,101 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:12:00,102 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:12:00,102 INFO L87 Difference]: Start difference. First operand 1914 states and 2830 transitions. cyclomatic complexity: 917 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:00,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:00,126 INFO L93 Difference]: Finished difference Result 1914 states and 2829 transitions. [2022-12-13 15:12:00,126 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2829 transitions. [2022-12-13 15:12:00,132 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 15:12:00,137 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2829 transitions. [2022-12-13 15:12:00,137 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-12-13 15:12:00,138 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-12-13 15:12:00,138 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2829 transitions. [2022-12-13 15:12:00,140 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:12:00,140 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2829 transitions. [2022-12-13 15:12:00,142 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2829 transitions. [2022-12-13 15:12:00,156 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-12-13 15:12:00,158 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4780564263322884) internal successors, (2829), 1913 states have internal predecessors, (2829), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:00,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2829 transitions. [2022-12-13 15:12:00,161 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2829 transitions. [2022-12-13 15:12:00,161 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:12:00,162 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2829 transitions. [2022-12-13 15:12:00,162 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 15:12:00,162 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2829 transitions. [2022-12-13 15:12:00,166 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 15:12:00,166 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:00,166 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:00,168 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:00,168 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:00,168 INFO L748 eck$LassoCheckResult]: Stem: 27146#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 27147#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 28041#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28042#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28763#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 28439#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28440#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27371#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27372#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27845#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27683#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27684#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 27435#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 27436#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27853#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 28032#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 28200#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 28234#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 27451#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27452#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 28655#L1258-2 assume !(0 == ~T1_E~0); 27768#L1263-1 assume !(0 == ~T2_E~0); 27769#L1268-1 assume !(0 == ~T3_E~0); 28078#L1273-1 assume !(0 == ~T4_E~0); 28634#L1278-1 assume !(0 == ~T5_E~0); 28493#L1283-1 assume !(0 == ~T6_E~0); 28494#L1288-1 assume !(0 == ~T7_E~0); 28731#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28720#L1298-1 assume !(0 == ~T9_E~0); 28650#L1303-1 assume !(0 == ~T10_E~0); 27249#L1308-1 assume !(0 == ~T11_E~0); 27189#L1313-1 assume !(0 == ~T12_E~0); 27190#L1318-1 assume !(0 == ~T13_E~0); 27195#L1323-1 assume !(0 == ~E_1~0); 27196#L1328-1 assume !(0 == ~E_2~0); 27381#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 28369#L1338-1 assume !(0 == ~E_4~0); 28370#L1343-1 assume !(0 == ~E_5~0); 28470#L1348-1 assume !(0 == ~E_6~0); 28750#L1353-1 assume !(0 == ~E_7~0); 28101#L1358-1 assume !(0 == ~E_8~0); 28102#L1363-1 assume !(0 == ~E_9~0); 28391#L1368-1 assume !(0 == ~E_10~0); 27042#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 27043#L1378-1 assume !(0 == ~E_12~0); 27324#L1383-1 assume !(0 == ~E_13~0); 27325#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28106#L607 assume 1 == ~m_pc~0; 28107#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27399#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27908#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27909#L1560 assume !(0 != activate_threads_~tmp~1#1); 28014#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27210#L626 assume !(1 == ~t1_pc~0); 27211#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 27492#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27493#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28378#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 27114#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27115#L645 assume 1 == ~t2_pc~0; 27226#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27183#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27292#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27293#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 27988#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27989#L664 assume 1 == ~t3_pc~0; 28748#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26976#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26977#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27641#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 27642#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28663#L683 assume !(1 == ~t4_pc~0); 28218#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28171#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27000#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27001#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28326#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27931#L702 assume 1 == ~t5_pc~0; 27932#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27868#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28322#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28653#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 28561#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27012#L721 assume !(1 == ~t6_pc~0); 26993#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 26994#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27138#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27277#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 27654#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28266#L740 assume 1 == ~t7_pc~0; 27058#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26893#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26894#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26883#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 26884#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27581#L759 assume !(1 == ~t8_pc~0); 27582#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 27613#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28708#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28450#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 28451#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28730#L778 assume 1 == ~t9_pc~0; 28619#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27041#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27347#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26919#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 26920#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27222#L797 assume !(1 == ~t10_pc~0); 27223#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 27357#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28596#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 27764#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 27765#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28058#L816 assume 1 == ~t11_pc~0; 26954#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26955#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27897#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27660#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 27661#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28199#L835 assume 1 == ~t12_pc~0; 28073#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 27105#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 26944#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 26945#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 27817#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 27818#L854 assume !(1 == ~t13_pc~0); 27437#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 27438#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 27487#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 27136#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 27137#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28557#L1401 assume !(1 == ~M_E~0); 27647#L1401-2 assume !(1 == ~T1_E~0); 27648#L1406-1 assume !(1 == ~T2_E~0); 28255#L1411-1 assume !(1 == ~T3_E~0); 28256#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27907#L1421-1 assume !(1 == ~T5_E~0); 27433#L1426-1 assume !(1 == ~T6_E~0); 27434#L1431-1 assume !(1 == ~T7_E~0); 26991#L1436-1 assume !(1 == ~T8_E~0); 26992#L1441-1 assume !(1 == ~T9_E~0); 27755#L1446-1 assume !(1 == ~T10_E~0); 27756#L1451-1 assume !(1 == ~T11_E~0); 28467#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28126#L1461-1 assume !(1 == ~T13_E~0); 27676#L1466-1 assume !(1 == ~E_1~0); 27677#L1471-1 assume !(1 == ~E_2~0); 28448#L1476-1 assume !(1 == ~E_3~0); 28449#L1481-1 assume !(1 == ~E_4~0); 28602#L1486-1 assume !(1 == ~E_5~0); 27262#L1491-1 assume !(1 == ~E_6~0); 26929#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 26930#L1501-1 assume !(1 == ~E_8~0); 27751#L1506-1 assume !(1 == ~E_9~0); 27752#L1511-1 assume !(1 == ~E_10~0); 27706#L1516-1 assume !(1 == ~E_11~0); 26881#L1521-1 assume !(1 == ~E_12~0); 26882#L1526-1 assume !(1 == ~E_13~0); 26928#L1531-1 assume { :end_inline_reset_delta_events } true; 27459#L1892-2 [2022-12-13 15:12:00,168 INFO L750 eck$LassoCheckResult]: Loop: 27459#L1892-2 assume !false; 28509#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28707#L1233 assume !false; 28690#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28015#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27995#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28538#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 26970#L1046 assume !(0 != eval_~tmp~0#1); 26972#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27504#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27505#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28747#L1258-5 assume !(0 == ~T1_E~0); 27126#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27127#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28739#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28743#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28744#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27362#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27363#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28506#L1298-3 assume !(0 == ~T9_E~0); 28507#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28670#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 28505#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 27999#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 27128#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27129#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28594#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27273#L1338-3 assume !(0 == ~E_4~0); 27274#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28425#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28599#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28600#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27946#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 27494#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 27495#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28286#L1378-3 assume !(0 == ~E_12~0); 28287#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 28464#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28465#L607-42 assume 1 == ~m_pc~0; 28083#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27801#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27634#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27514#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27515#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28059#L626-42 assume 1 == ~t1_pc~0; 27605#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27606#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28694#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28480#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 27162#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27163#L645-42 assume !(1 == ~t2_pc~0); 28405#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 28406#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27944#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27382#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26901#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26902#L664-42 assume 1 == ~t3_pc~0; 27712#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27419#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28345#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28232#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28233#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28398#L683-42 assume 1 == ~t4_pc~0; 28755#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28110#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28239#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28401#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28660#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28500#L702-42 assume 1 == ~t5_pc~0; 27976#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27596#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27900#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28009#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26913#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26914#L721-42 assume 1 == ~t6_pc~0; 27053#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27074#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27253#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27254#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27732#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27569#L740-42 assume 1 == ~t7_pc~0; 27570#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27289#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27861#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27715#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 27716#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27982#L759-42 assume 1 == ~t8_pc~0; 27837#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27774#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27775#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27846#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27847#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27936#L778-42 assume 1 == ~t9_pc~0; 27786#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27788#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28204#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28111#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28112#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28166#L797-42 assume 1 == ~t10_pc~0; 27296#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 27297#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28184#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28185#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28205#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28206#L816-42 assume 1 == ~t11_pc~0; 26873#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26874#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28700#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27761#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 27473#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 27474#L835-42 assume !(1 == ~t12_pc~0); 27797#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 27798#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 27985#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 27986#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 28560#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 28343#L854-42 assume !(1 == ~t13_pc~0); 27394#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 27395#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 27561#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 27562#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 27672#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27673#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28458#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27225#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27100#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27101#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27722#L1421-3 assume !(1 == ~T5_E~0); 27723#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27267#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27268#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26885#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 26886#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28484#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 27809#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 27441#L1461-3 assume !(1 == ~T13_E~0); 27442#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28741#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27383#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27384#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27806#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27411#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27412#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27843#L1501-3 assume !(1 == ~E_8~0); 27844#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28282#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 28270#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28271#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 27949#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 27950#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28365#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27200#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 27247#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 27248#L1911 assume !(0 == start_simulation_~tmp~3#1); 27778#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28304#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27338#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 26923#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 26924#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27047#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27807#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 28613#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 27459#L1892-2 [2022-12-13 15:12:00,169 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:00,169 INFO L85 PathProgramCache]: Analyzing trace with hash 888419230, now seen corresponding path program 1 times [2022-12-13 15:12:00,169 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:00,169 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [703847231] [2022-12-13 15:12:00,169 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:00,169 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:00,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:00,199 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:00,199 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:00,199 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [703847231] [2022-12-13 15:12:00,199 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [703847231] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:00,199 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:00,199 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:00,200 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [776794750] [2022-12-13 15:12:00,200 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:00,200 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:00,200 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:00,201 INFO L85 PathProgramCache]: Analyzing trace with hash 1860574880, now seen corresponding path program 1 times [2022-12-13 15:12:00,201 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:00,201 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [932506463] [2022-12-13 15:12:00,201 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:00,201 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:00,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:00,244 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:00,245 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:00,245 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [932506463] [2022-12-13 15:12:00,245 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [932506463] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:00,245 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:00,245 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:00,245 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2011405113] [2022-12-13 15:12:00,245 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:00,246 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:00,246 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:00,246 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:12:00,246 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:12:00,247 INFO L87 Difference]: Start difference. First operand 1914 states and 2829 transitions. cyclomatic complexity: 916 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:00,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:00,281 INFO L93 Difference]: Finished difference Result 1914 states and 2828 transitions. [2022-12-13 15:12:00,281 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2828 transitions. [2022-12-13 15:12:00,287 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 15:12:00,291 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2828 transitions. [2022-12-13 15:12:00,291 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-12-13 15:12:00,292 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-12-13 15:12:00,292 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2828 transitions. [2022-12-13 15:12:00,294 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:12:00,294 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2828 transitions. [2022-12-13 15:12:00,296 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2828 transitions. [2022-12-13 15:12:00,310 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-12-13 15:12:00,312 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.477533960292581) internal successors, (2828), 1913 states have internal predecessors, (2828), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:00,315 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2828 transitions. [2022-12-13 15:12:00,315 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2828 transitions. [2022-12-13 15:12:00,315 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:12:00,316 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2828 transitions. [2022-12-13 15:12:00,316 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 15:12:00,316 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2828 transitions. [2022-12-13 15:12:00,321 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 15:12:00,321 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:00,321 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:00,322 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:00,322 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:00,323 INFO L748 eck$LassoCheckResult]: Stem: 30981#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 30982#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 31876#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31877#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32598#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 32274#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32275#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31206#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31207#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31680#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31518#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 31519#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 31270#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 31271#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 31688#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 31867#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 32035#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 32069#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 31286#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31287#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 32490#L1258-2 assume !(0 == ~T1_E~0); 31603#L1263-1 assume !(0 == ~T2_E~0); 31604#L1268-1 assume !(0 == ~T3_E~0); 31913#L1273-1 assume !(0 == ~T4_E~0); 32469#L1278-1 assume !(0 == ~T5_E~0); 32328#L1283-1 assume !(0 == ~T6_E~0); 32329#L1288-1 assume !(0 == ~T7_E~0); 32566#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32555#L1298-1 assume !(0 == ~T9_E~0); 32485#L1303-1 assume !(0 == ~T10_E~0); 31084#L1308-1 assume !(0 == ~T11_E~0); 31024#L1313-1 assume !(0 == ~T12_E~0); 31025#L1318-1 assume !(0 == ~T13_E~0); 31030#L1323-1 assume !(0 == ~E_1~0); 31031#L1328-1 assume !(0 == ~E_2~0); 31216#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 32204#L1338-1 assume !(0 == ~E_4~0); 32205#L1343-1 assume !(0 == ~E_5~0); 32305#L1348-1 assume !(0 == ~E_6~0); 32585#L1353-1 assume !(0 == ~E_7~0); 31936#L1358-1 assume !(0 == ~E_8~0); 31937#L1363-1 assume !(0 == ~E_9~0); 32226#L1368-1 assume !(0 == ~E_10~0); 30877#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 30878#L1378-1 assume !(0 == ~E_12~0); 31159#L1383-1 assume !(0 == ~E_13~0); 31160#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31941#L607 assume 1 == ~m_pc~0; 31942#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31234#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31743#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31744#L1560 assume !(0 != activate_threads_~tmp~1#1); 31849#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31045#L626 assume !(1 == ~t1_pc~0); 31046#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31327#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31328#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32213#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 30949#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30950#L645 assume 1 == ~t2_pc~0; 31061#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31018#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31127#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31128#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 31823#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31824#L664 assume 1 == ~t3_pc~0; 32583#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30811#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30812#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31476#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 31477#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32498#L683 assume !(1 == ~t4_pc~0); 32053#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 32006#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30835#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30836#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32161#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31766#L702 assume 1 == ~t5_pc~0; 31767#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31703#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32157#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32488#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 32396#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30847#L721 assume !(1 == ~t6_pc~0); 30828#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 30829#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30973#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31112#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 31489#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32101#L740 assume 1 == ~t7_pc~0; 30893#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30728#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30729#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30718#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 30719#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31416#L759 assume !(1 == ~t8_pc~0); 31417#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 31448#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32543#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32285#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 32286#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32565#L778 assume 1 == ~t9_pc~0; 32454#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30876#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31182#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30754#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 30755#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31057#L797 assume !(1 == ~t10_pc~0); 31058#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 31192#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32431#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 31599#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 31600#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 31893#L816 assume 1 == ~t11_pc~0; 30789#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 30790#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31732#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31495#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 31496#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32034#L835 assume 1 == ~t12_pc~0; 31908#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 30940#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30779#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 30780#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 31652#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 31653#L854 assume !(1 == ~t13_pc~0); 31272#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 31273#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 31322#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 30971#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 30972#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32392#L1401 assume !(1 == ~M_E~0); 31482#L1401-2 assume !(1 == ~T1_E~0); 31483#L1406-1 assume !(1 == ~T2_E~0); 32090#L1411-1 assume !(1 == ~T3_E~0); 32091#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31742#L1421-1 assume !(1 == ~T5_E~0); 31268#L1426-1 assume !(1 == ~T6_E~0); 31269#L1431-1 assume !(1 == ~T7_E~0); 30826#L1436-1 assume !(1 == ~T8_E~0); 30827#L1441-1 assume !(1 == ~T9_E~0); 31590#L1446-1 assume !(1 == ~T10_E~0); 31591#L1451-1 assume !(1 == ~T11_E~0); 32302#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 31961#L1461-1 assume !(1 == ~T13_E~0); 31511#L1466-1 assume !(1 == ~E_1~0); 31512#L1471-1 assume !(1 == ~E_2~0); 32283#L1476-1 assume !(1 == ~E_3~0); 32284#L1481-1 assume !(1 == ~E_4~0); 32437#L1486-1 assume !(1 == ~E_5~0); 31097#L1491-1 assume !(1 == ~E_6~0); 30764#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 30765#L1501-1 assume !(1 == ~E_8~0); 31586#L1506-1 assume !(1 == ~E_9~0); 31587#L1511-1 assume !(1 == ~E_10~0); 31541#L1516-1 assume !(1 == ~E_11~0); 30716#L1521-1 assume !(1 == ~E_12~0); 30717#L1526-1 assume !(1 == ~E_13~0); 30763#L1531-1 assume { :end_inline_reset_delta_events } true; 31294#L1892-2 [2022-12-13 15:12:00,323 INFO L750 eck$LassoCheckResult]: Loop: 31294#L1892-2 assume !false; 32344#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32542#L1233 assume !false; 32525#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 31850#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31830#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 32373#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30805#L1046 assume !(0 != eval_~tmp~0#1); 30807#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31339#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31340#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 32582#L1258-5 assume !(0 == ~T1_E~0); 30961#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30962#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32574#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32578#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32579#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 31197#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31198#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32341#L1298-3 assume !(0 == ~T9_E~0); 32342#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32505#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32340#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 31834#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 30963#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30964#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32429#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31108#L1338-3 assume !(0 == ~E_4~0); 31109#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32260#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32434#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 32435#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 31781#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 31329#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31330#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32121#L1378-3 assume !(0 == ~E_12~0); 32122#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 32299#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32300#L607-42 assume 1 == ~m_pc~0; 31918#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31636#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31469#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31349#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31350#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31894#L626-42 assume 1 == ~t1_pc~0; 31440#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 31441#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32529#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32315#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30997#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30998#L645-42 assume !(1 == ~t2_pc~0); 32240#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 32241#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31779#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31217#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30736#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30737#L664-42 assume !(1 == ~t3_pc~0); 31253#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 31254#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32180#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32067#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32068#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32233#L683-42 assume !(1 == ~t4_pc~0); 31944#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 31945#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32074#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32236#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32495#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32335#L702-42 assume 1 == ~t5_pc~0; 31811#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31431#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31735#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31844#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30748#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30749#L721-42 assume 1 == ~t6_pc~0; 30888#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30909#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31088#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31089#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 31567#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31404#L740-42 assume !(1 == ~t7_pc~0); 31123#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 31124#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31696#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 31550#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 31551#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31817#L759-42 assume 1 == ~t8_pc~0; 31672#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31609#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31610#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 31681#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 31682#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31771#L778-42 assume 1 == ~t9_pc~0; 31621#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31623#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32039#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31946#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 31947#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32001#L797-42 assume 1 == ~t10_pc~0; 31131#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 31132#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32019#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32020#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32040#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32041#L816-42 assume 1 == ~t11_pc~0; 30708#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 30709#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32535#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31596#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 31308#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 31309#L835-42 assume !(1 == ~t12_pc~0); 31632#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 31633#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 31820#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 31821#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 32395#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 32178#L854-42 assume 1 == ~t13_pc~0; 32179#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 31230#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 31396#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 31397#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 31507#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31508#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32293#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31060#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30935#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30936#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31557#L1421-3 assume !(1 == ~T5_E~0); 31558#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 31102#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 31103#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30720#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30721#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32319#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31644#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 31276#L1461-3 assume !(1 == ~T13_E~0); 31277#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32576#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 31218#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31219#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31641#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31246#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 31247#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 31678#L1501-3 assume !(1 == ~E_8~0); 31679#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32117#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32105#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 32106#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 31784#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 31785#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32200#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31035#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 31082#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 31083#L1911 assume !(0 == start_simulation_~tmp~3#1); 31613#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32139#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31173#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 30758#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 30759#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30882#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31642#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 32448#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 31294#L1892-2 [2022-12-13 15:12:00,323 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:00,323 INFO L85 PathProgramCache]: Analyzing trace with hash 1153066720, now seen corresponding path program 1 times [2022-12-13 15:12:00,324 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:00,324 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1752864147] [2022-12-13 15:12:00,324 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:00,324 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:00,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:00,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:00,356 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:00,356 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1752864147] [2022-12-13 15:12:00,356 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1752864147] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:00,356 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:00,356 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:00,356 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1826504957] [2022-12-13 15:12:00,357 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:00,357 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:00,357 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:00,357 INFO L85 PathProgramCache]: Analyzing trace with hash 502016542, now seen corresponding path program 1 times [2022-12-13 15:12:00,357 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:00,358 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2044041270] [2022-12-13 15:12:00,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:00,358 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:00,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:00,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:00,399 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:00,400 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2044041270] [2022-12-13 15:12:00,400 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2044041270] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:00,400 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:00,400 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:00,400 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1313965572] [2022-12-13 15:12:00,400 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:00,401 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:00,401 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:00,401 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:12:00,401 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:12:00,401 INFO L87 Difference]: Start difference. First operand 1914 states and 2828 transitions. cyclomatic complexity: 915 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:00,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:00,424 INFO L93 Difference]: Finished difference Result 1914 states and 2827 transitions. [2022-12-13 15:12:00,424 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2827 transitions. [2022-12-13 15:12:00,428 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 15:12:00,432 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2827 transitions. [2022-12-13 15:12:00,433 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-12-13 15:12:00,433 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-12-13 15:12:00,433 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2827 transitions. [2022-12-13 15:12:00,435 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:12:00,435 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2827 transitions. [2022-12-13 15:12:00,437 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2827 transitions. [2022-12-13 15:12:00,451 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-12-13 15:12:00,453 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4770114942528736) internal successors, (2827), 1913 states have internal predecessors, (2827), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:00,455 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2827 transitions. [2022-12-13 15:12:00,455 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2827 transitions. [2022-12-13 15:12:00,456 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:12:00,456 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2827 transitions. [2022-12-13 15:12:00,456 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 15:12:00,456 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2827 transitions. [2022-12-13 15:12:00,460 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 15:12:00,461 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:00,461 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:00,462 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:00,462 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:00,462 INFO L748 eck$LassoCheckResult]: Stem: 34816#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 34817#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 35712#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35713#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36433#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 36109#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36110#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35041#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35042#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35517#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35353#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35354#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35105#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 35106#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 35523#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 35702#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 35870#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 35905#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 35121#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35122#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 36325#L1258-2 assume !(0 == ~T1_E~0); 35438#L1263-1 assume !(0 == ~T2_E~0); 35439#L1268-1 assume !(0 == ~T3_E~0); 35748#L1273-1 assume !(0 == ~T4_E~0); 36304#L1278-1 assume !(0 == ~T5_E~0); 36163#L1283-1 assume !(0 == ~T6_E~0); 36164#L1288-1 assume !(0 == ~T7_E~0); 36402#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36390#L1298-1 assume !(0 == ~T9_E~0); 36320#L1303-1 assume !(0 == ~T10_E~0); 34919#L1308-1 assume !(0 == ~T11_E~0); 34862#L1313-1 assume !(0 == ~T12_E~0); 34863#L1318-1 assume !(0 == ~T13_E~0); 34867#L1323-1 assume !(0 == ~E_1~0); 34868#L1328-1 assume !(0 == ~E_2~0); 35051#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 36039#L1338-1 assume !(0 == ~E_4~0); 36040#L1343-1 assume !(0 == ~E_5~0); 36140#L1348-1 assume !(0 == ~E_6~0); 36420#L1353-1 assume !(0 == ~E_7~0); 35771#L1358-1 assume !(0 == ~E_8~0); 35772#L1363-1 assume !(0 == ~E_9~0); 36061#L1368-1 assume !(0 == ~E_10~0); 34712#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 34713#L1378-1 assume !(0 == ~E_12~0); 34996#L1383-1 assume !(0 == ~E_13~0); 34997#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35776#L607 assume 1 == ~m_pc~0; 35777#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35071#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35581#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35582#L1560 assume !(0 != activate_threads_~tmp~1#1); 35684#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34880#L626 assume !(1 == ~t1_pc~0); 34881#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 35164#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35165#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36048#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 34785#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34786#L645 assume 1 == ~t2_pc~0; 34898#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34853#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34964#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34965#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 35658#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35659#L664 assume 1 == ~t3_pc~0; 36418#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34650#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34651#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35311#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 35312#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36333#L683 assume !(1 == ~t4_pc~0); 35888#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 35841#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34670#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34671#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35996#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35605#L702 assume 1 == ~t5_pc~0; 35606#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35539#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35992#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36323#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 36232#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34686#L721 assume !(1 == ~t6_pc~0); 34663#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 34664#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34808#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34947#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 35324#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35936#L740 assume 1 == ~t7_pc~0; 34728#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34563#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34564#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34553#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 34554#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35252#L759 assume !(1 == ~t8_pc~0); 35253#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 35283#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36381#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36120#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 36121#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36400#L778 assume 1 == ~t9_pc~0; 36291#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34711#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35017#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34589#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 34590#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34893#L797 assume !(1 == ~t10_pc~0); 34894#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 35027#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36266#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35434#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 35435#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35728#L816 assume 1 == ~t11_pc~0; 34626#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34627#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35569#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35330#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 35331#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 35869#L835 assume 1 == ~t12_pc~0; 35743#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 34775#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34614#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34615#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 35487#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 35488#L854 assume !(1 == ~t13_pc~0); 35107#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 35108#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 35159#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34806#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 34807#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36227#L1401 assume !(1 == ~M_E~0); 35317#L1401-2 assume !(1 == ~T1_E~0); 35318#L1406-1 assume !(1 == ~T2_E~0); 35925#L1411-1 assume !(1 == ~T3_E~0); 35926#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35577#L1421-1 assume !(1 == ~T5_E~0); 35103#L1426-1 assume !(1 == ~T6_E~0); 35104#L1431-1 assume !(1 == ~T7_E~0); 34661#L1436-1 assume !(1 == ~T8_E~0); 34662#L1441-1 assume !(1 == ~T9_E~0); 35425#L1446-1 assume !(1 == ~T10_E~0); 35426#L1451-1 assume !(1 == ~T11_E~0); 36137#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35796#L1461-1 assume !(1 == ~T13_E~0); 35346#L1466-1 assume !(1 == ~E_1~0); 35347#L1471-1 assume !(1 == ~E_2~0); 36118#L1476-1 assume !(1 == ~E_3~0); 36119#L1481-1 assume !(1 == ~E_4~0); 36272#L1486-1 assume !(1 == ~E_5~0); 34932#L1491-1 assume !(1 == ~E_6~0); 34599#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 34600#L1501-1 assume !(1 == ~E_8~0); 35421#L1506-1 assume !(1 == ~E_9~0); 35422#L1511-1 assume !(1 == ~E_10~0); 35376#L1516-1 assume !(1 == ~E_11~0); 34551#L1521-1 assume !(1 == ~E_12~0); 34552#L1526-1 assume !(1 == ~E_13~0); 34598#L1531-1 assume { :end_inline_reset_delta_events } true; 35129#L1892-2 [2022-12-13 15:12:00,463 INFO L750 eck$LassoCheckResult]: Loop: 35129#L1892-2 assume !false; 36179#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36377#L1233 assume !false; 36360#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 35685#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35665#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 36208#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 34640#L1046 assume !(0 != eval_~tmp~0#1); 34642#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35174#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35175#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 36417#L1258-5 assume !(0 == ~T1_E~0); 34796#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34797#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36409#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36413#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36414#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35032#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 35033#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36176#L1298-3 assume !(0 == ~T9_E~0); 36177#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36340#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36175#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 35669#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 34798#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 34799#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36264#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34943#L1338-3 assume !(0 == ~E_4~0); 34944#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36095#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36269#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36270#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35616#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35162#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 35163#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 35956#L1378-3 assume !(0 == ~E_12~0); 35957#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 36134#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36135#L607-42 assume 1 == ~m_pc~0; 35753#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35471#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35304#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35184#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35185#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35729#L626-42 assume 1 == ~t1_pc~0; 35275#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35276#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36364#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36150#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34832#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34833#L645-42 assume !(1 == ~t2_pc~0); 36075#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 36076#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35614#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35052#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34571#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34572#L664-42 assume !(1 == ~t3_pc~0); 35088#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 35089#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36015#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35902#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 35903#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36068#L683-42 assume !(1 == ~t4_pc~0); 35779#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 35780#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35909#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36071#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36330#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36170#L702-42 assume !(1 == ~t5_pc~0); 35265#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 35266#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35570#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35679#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 34583#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34584#L721-42 assume 1 == ~t6_pc~0; 34723#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 34744#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34923#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34924#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35402#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35239#L740-42 assume 1 == ~t7_pc~0; 35240#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34959#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35531#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35385#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 35386#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35652#L759-42 assume 1 == ~t8_pc~0; 35507#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35444#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35445#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35515#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35516#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35604#L778-42 assume 1 == ~t9_pc~0; 35456#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35458#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35874#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35781#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35782#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35836#L797-42 assume 1 == ~t10_pc~0; 34966#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 34967#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35854#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35855#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35875#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35876#L816-42 assume !(1 == ~t11_pc~0); 34545#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 34544#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36370#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35431#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35143#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 35144#L835-42 assume !(1 == ~t12_pc~0); 35467#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 35468#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35655#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 35656#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 36230#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 36013#L854-42 assume !(1 == ~t13_pc~0); 35064#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 35065#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 35231#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 35232#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 35342#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35343#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36128#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34892#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34770#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34771#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35392#L1421-3 assume !(1 == ~T5_E~0); 35393#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34937#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34938#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 34555#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34556#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36154#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35479#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35111#L1461-3 assume !(1 == ~T13_E~0); 35112#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36411#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35053#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 35054#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 35476#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35081#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35082#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35513#L1501-3 assume !(1 == ~E_8~0); 35514#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 35952#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 35940#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 35941#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 35619#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 35620#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36035#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 34870#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 34917#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 34918#L1911 assume !(0 == start_simulation_~tmp~3#1); 35448#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 35974#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35008#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 34593#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 34594#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34717#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35477#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 36283#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 35129#L1892-2 [2022-12-13 15:12:00,463 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:00,463 INFO L85 PathProgramCache]: Analyzing trace with hash -778058914, now seen corresponding path program 1 times [2022-12-13 15:12:00,463 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:00,463 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [132723481] [2022-12-13 15:12:00,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:00,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:00,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:00,508 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:00,508 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:00,508 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [132723481] [2022-12-13 15:12:00,508 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [132723481] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:00,509 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:00,509 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:00,509 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [517594064] [2022-12-13 15:12:00,509 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:00,510 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:00,510 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:00,510 INFO L85 PathProgramCache]: Analyzing trace with hash 310188508, now seen corresponding path program 1 times [2022-12-13 15:12:00,510 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:00,510 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1283111954] [2022-12-13 15:12:00,511 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:00,511 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:00,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:00,568 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:00,568 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:00,568 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1283111954] [2022-12-13 15:12:00,569 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1283111954] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:00,569 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:00,569 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:00,569 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [296088781] [2022-12-13 15:12:00,569 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:00,570 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:00,570 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:00,570 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:12:00,570 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:12:00,570 INFO L87 Difference]: Start difference. First operand 1914 states and 2827 transitions. cyclomatic complexity: 914 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:00,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:00,604 INFO L93 Difference]: Finished difference Result 1914 states and 2826 transitions. [2022-12-13 15:12:00,605 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2826 transitions. [2022-12-13 15:12:00,609 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 15:12:00,614 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2826 transitions. [2022-12-13 15:12:00,614 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-12-13 15:12:00,615 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-12-13 15:12:00,615 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2826 transitions. [2022-12-13 15:12:00,617 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:12:00,617 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2826 transitions. [2022-12-13 15:12:00,619 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2826 transitions. [2022-12-13 15:12:00,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-12-13 15:12:00,635 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4764890282131662) internal successors, (2826), 1913 states have internal predecessors, (2826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:00,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2826 transitions. [2022-12-13 15:12:00,637 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2826 transitions. [2022-12-13 15:12:00,638 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:12:00,638 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2826 transitions. [2022-12-13 15:12:00,638 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 15:12:00,638 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2826 transitions. [2022-12-13 15:12:00,642 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 15:12:00,642 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:00,642 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:00,644 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:00,644 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:00,644 INFO L748 eck$LassoCheckResult]: Stem: 38651#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 38652#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 39547#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39548#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 40268#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 39944#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39945#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38876#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38877#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39352#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39188#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 39189#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38940#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 38941#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 39358#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 39537#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 39705#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 39740#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 38956#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38957#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 40160#L1258-2 assume !(0 == ~T1_E~0); 39273#L1263-1 assume !(0 == ~T2_E~0); 39274#L1268-1 assume !(0 == ~T3_E~0); 39583#L1273-1 assume !(0 == ~T4_E~0); 40139#L1278-1 assume !(0 == ~T5_E~0); 39998#L1283-1 assume !(0 == ~T6_E~0); 39999#L1288-1 assume !(0 == ~T7_E~0); 40237#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40225#L1298-1 assume !(0 == ~T9_E~0); 40155#L1303-1 assume !(0 == ~T10_E~0); 38754#L1308-1 assume !(0 == ~T11_E~0); 38694#L1313-1 assume !(0 == ~T12_E~0); 38695#L1318-1 assume !(0 == ~T13_E~0); 38702#L1323-1 assume !(0 == ~E_1~0); 38703#L1328-1 assume !(0 == ~E_2~0); 38886#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 39874#L1338-1 assume !(0 == ~E_4~0); 39875#L1343-1 assume !(0 == ~E_5~0); 39975#L1348-1 assume !(0 == ~E_6~0); 40255#L1353-1 assume !(0 == ~E_7~0); 39606#L1358-1 assume !(0 == ~E_8~0); 39607#L1363-1 assume !(0 == ~E_9~0); 39896#L1368-1 assume !(0 == ~E_10~0); 38547#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 38548#L1378-1 assume !(0 == ~E_12~0); 38831#L1383-1 assume !(0 == ~E_13~0); 38832#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39611#L607 assume 1 == ~m_pc~0; 39612#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 38906#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39416#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39417#L1560 assume !(0 != activate_threads_~tmp~1#1); 39519#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38715#L626 assume !(1 == ~t1_pc~0); 38716#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 38999#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39000#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39883#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 38619#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38620#L645 assume 1 == ~t2_pc~0; 38733#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38688#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38799#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38800#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 39493#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39494#L664 assume 1 == ~t3_pc~0; 40253#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38485#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38486#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39146#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 39147#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40168#L683 assume !(1 == ~t4_pc~0); 39723#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 39676#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38505#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38506#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 39831#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39440#L702 assume 1 == ~t5_pc~0; 39441#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39374#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39827#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40158#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 40067#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38521#L721 assume !(1 == ~t6_pc~0); 38498#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 38499#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38643#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38782#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 39159#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39771#L740 assume 1 == ~t7_pc~0; 38563#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38398#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38399#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38388#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 38389#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39087#L759 assume !(1 == ~t8_pc~0); 39088#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 39118#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40215#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39955#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 39956#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40235#L778 assume 1 == ~t9_pc~0; 40126#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38546#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38852#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38424#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 38425#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38728#L797 assume !(1 == ~t10_pc~0); 38729#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 38862#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40101#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39269#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 39270#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39563#L816 assume 1 == ~t11_pc~0; 38461#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38462#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39404#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39165#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 39166#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 39704#L835 assume 1 == ~t12_pc~0; 39578#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 38610#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38449#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38450#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 39322#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 39323#L854 assume !(1 == ~t13_pc~0); 38942#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 38943#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 38994#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38641#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 38642#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40062#L1401 assume !(1 == ~M_E~0); 39152#L1401-2 assume !(1 == ~T1_E~0); 39153#L1406-1 assume !(1 == ~T2_E~0); 39760#L1411-1 assume !(1 == ~T3_E~0); 39761#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39412#L1421-1 assume !(1 == ~T5_E~0); 38938#L1426-1 assume !(1 == ~T6_E~0); 38939#L1431-1 assume !(1 == ~T7_E~0); 38496#L1436-1 assume !(1 == ~T8_E~0); 38497#L1441-1 assume !(1 == ~T9_E~0); 39262#L1446-1 assume !(1 == ~T10_E~0); 39263#L1451-1 assume !(1 == ~T11_E~0); 39972#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 39631#L1461-1 assume !(1 == ~T13_E~0); 39181#L1466-1 assume !(1 == ~E_1~0); 39182#L1471-1 assume !(1 == ~E_2~0); 39953#L1476-1 assume !(1 == ~E_3~0); 39954#L1481-1 assume !(1 == ~E_4~0); 40107#L1486-1 assume !(1 == ~E_5~0); 38767#L1491-1 assume !(1 == ~E_6~0); 38434#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 38435#L1501-1 assume !(1 == ~E_8~0); 39256#L1506-1 assume !(1 == ~E_9~0); 39257#L1511-1 assume !(1 == ~E_10~0); 39211#L1516-1 assume !(1 == ~E_11~0); 38386#L1521-1 assume !(1 == ~E_12~0); 38387#L1526-1 assume !(1 == ~E_13~0); 38433#L1531-1 assume { :end_inline_reset_delta_events } true; 38964#L1892-2 [2022-12-13 15:12:00,644 INFO L750 eck$LassoCheckResult]: Loop: 38964#L1892-2 assume !false; 40014#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40212#L1233 assume !false; 40195#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 39520#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 39500#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 40043#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 38475#L1046 assume !(0 != eval_~tmp~0#1); 38477#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 39010#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 39011#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40252#L1258-5 assume !(0 == ~T1_E~0); 38635#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38636#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40244#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40248#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40249#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 38867#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 38868#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40011#L1298-3 assume !(0 == ~T9_E~0); 40012#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 40175#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 40010#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 39504#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 38631#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 38632#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40099#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38776#L1338-3 assume !(0 == ~E_4~0); 38777#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 39930#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 40104#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40105#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 39451#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 38997#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 38998#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 39791#L1378-3 assume !(0 == ~E_12~0); 39792#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 39969#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39970#L607-42 assume 1 == ~m_pc~0; 39588#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 39306#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39139#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39019#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39020#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39564#L626-42 assume 1 == ~t1_pc~0; 39110#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 39111#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40199#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39985#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38665#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38666#L645-42 assume !(1 == ~t2_pc~0); 39910#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 39911#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39449#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38887#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38406#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38407#L664-42 assume 1 == ~t3_pc~0; 39217#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38924#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39850#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39737#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 39738#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39903#L683-42 assume 1 == ~t4_pc~0; 40260#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39615#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39744#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39906#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40165#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40005#L702-42 assume 1 == ~t5_pc~0; 39481#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39101#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39405#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39514#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38418#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38419#L721-42 assume 1 == ~t6_pc~0; 38558#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38579#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38758#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38759#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 39237#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39074#L740-42 assume 1 == ~t7_pc~0; 39075#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38794#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39366#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 39220#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 39221#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39487#L759-42 assume 1 == ~t8_pc~0; 39342#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 39279#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39280#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39350#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39351#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39439#L778-42 assume 1 == ~t9_pc~0; 39291#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39293#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39708#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39616#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 39617#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39671#L797-42 assume 1 == ~t10_pc~0; 38801#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38802#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39689#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39690#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 39710#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39711#L816-42 assume 1 == ~t11_pc~0; 38378#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38379#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40205#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39266#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 38978#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 38979#L835-42 assume !(1 == ~t12_pc~0); 39302#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 39303#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 39489#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39490#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 40065#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 39848#L854-42 assume !(1 == ~t13_pc~0); 38897#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 38898#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 39066#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 39067#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 39177#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39178#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 39963#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38727#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38605#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38606#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39227#L1421-3 assume !(1 == ~T5_E~0); 39228#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38772#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38773#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38390#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38391#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 39989#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 39314#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 38946#L1461-3 assume !(1 == ~T13_E~0); 38947#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 40246#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38888#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38889#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39311#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38916#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38917#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 39348#L1501-3 assume !(1 == ~E_8~0); 39349#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 39787#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 39775#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 39776#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 39454#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 39455#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 39870#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 38705#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 38752#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 38753#L1911 assume !(0 == start_simulation_~tmp~3#1); 39283#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 39809#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 38843#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 38428#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 38429#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38552#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 39312#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 40118#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 38964#L1892-2 [2022-12-13 15:12:00,644 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:00,644 INFO L85 PathProgramCache]: Analyzing trace with hash 1619928924, now seen corresponding path program 1 times [2022-12-13 15:12:00,645 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:00,645 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1110091341] [2022-12-13 15:12:00,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:00,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:00,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:00,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:00,673 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:00,673 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1110091341] [2022-12-13 15:12:00,674 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1110091341] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:00,674 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:00,674 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:00,674 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [213405491] [2022-12-13 15:12:00,674 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:00,674 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:00,675 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:00,675 INFO L85 PathProgramCache]: Analyzing trace with hash 1860574880, now seen corresponding path program 2 times [2022-12-13 15:12:00,675 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:00,675 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2108824885] [2022-12-13 15:12:00,675 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:00,675 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:00,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:00,722 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:00,723 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:00,723 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2108824885] [2022-12-13 15:12:00,723 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2108824885] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:00,723 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:00,723 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:00,723 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1082117243] [2022-12-13 15:12:00,723 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:00,724 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:00,724 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:00,724 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:12:00,724 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:12:00,725 INFO L87 Difference]: Start difference. First operand 1914 states and 2826 transitions. cyclomatic complexity: 913 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:00,747 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:00,747 INFO L93 Difference]: Finished difference Result 1914 states and 2825 transitions. [2022-12-13 15:12:00,747 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2825 transitions. [2022-12-13 15:12:00,752 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 15:12:00,756 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2825 transitions. [2022-12-13 15:12:00,757 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-12-13 15:12:00,757 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-12-13 15:12:00,758 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2825 transitions. [2022-12-13 15:12:00,759 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:12:00,759 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2825 transitions. [2022-12-13 15:12:00,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2825 transitions. [2022-12-13 15:12:00,775 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-12-13 15:12:00,777 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4759665621734588) internal successors, (2825), 1913 states have internal predecessors, (2825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:00,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2825 transitions. [2022-12-13 15:12:00,780 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2825 transitions. [2022-12-13 15:12:00,780 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:12:00,780 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2825 transitions. [2022-12-13 15:12:00,780 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 15:12:00,781 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2825 transitions. [2022-12-13 15:12:00,784 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 15:12:00,784 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:00,784 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:00,786 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:00,786 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:00,786 INFO L748 eck$LassoCheckResult]: Stem: 42486#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 42487#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 43381#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43382#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 44103#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 43779#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43780#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42711#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42712#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43187#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43023#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43024#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42775#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 42776#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 43193#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 43372#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 43540#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 43574#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 42791#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42792#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 43995#L1258-2 assume !(0 == ~T1_E~0); 43108#L1263-1 assume !(0 == ~T2_E~0); 43109#L1268-1 assume !(0 == ~T3_E~0); 43418#L1273-1 assume !(0 == ~T4_E~0); 43974#L1278-1 assume !(0 == ~T5_E~0); 43833#L1283-1 assume !(0 == ~T6_E~0); 43834#L1288-1 assume !(0 == ~T7_E~0); 44072#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44060#L1298-1 assume !(0 == ~T9_E~0); 43990#L1303-1 assume !(0 == ~T10_E~0); 42589#L1308-1 assume !(0 == ~T11_E~0); 42529#L1313-1 assume !(0 == ~T12_E~0); 42530#L1318-1 assume !(0 == ~T13_E~0); 42537#L1323-1 assume !(0 == ~E_1~0); 42538#L1328-1 assume !(0 == ~E_2~0); 42721#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 43709#L1338-1 assume !(0 == ~E_4~0); 43710#L1343-1 assume !(0 == ~E_5~0); 43810#L1348-1 assume !(0 == ~E_6~0); 44090#L1353-1 assume !(0 == ~E_7~0); 43441#L1358-1 assume !(0 == ~E_8~0); 43442#L1363-1 assume !(0 == ~E_9~0); 43731#L1368-1 assume !(0 == ~E_10~0); 42382#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 42383#L1378-1 assume !(0 == ~E_12~0); 42666#L1383-1 assume !(0 == ~E_13~0); 42667#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43446#L607 assume 1 == ~m_pc~0; 43447#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 42739#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43251#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43252#L1560 assume !(0 != activate_threads_~tmp~1#1); 43354#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42550#L626 assume !(1 == ~t1_pc~0); 42551#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 42832#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42833#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43718#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 42454#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42455#L645 assume 1 == ~t2_pc~0; 42568#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42523#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42634#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42635#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 43328#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43329#L664 assume 1 == ~t3_pc~0; 44088#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42320#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42321#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42981#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 42982#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44003#L683 assume !(1 == ~t4_pc~0); 43558#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 43511#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42340#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42341#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43666#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43275#L702 assume 1 == ~t5_pc~0; 43276#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43209#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43662#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43993#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 43902#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42356#L721 assume !(1 == ~t6_pc~0); 42333#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 42334#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42478#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42617#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 42994#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43606#L740 assume 1 == ~t7_pc~0; 42398#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42233#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42234#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42223#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 42224#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42922#L759 assume !(1 == ~t8_pc~0); 42923#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 42953#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44050#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43790#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 43791#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44070#L778 assume 1 == ~t9_pc~0; 43959#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 42381#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42687#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42259#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 42260#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42563#L797 assume !(1 == ~t10_pc~0); 42564#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 42697#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43936#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43104#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 43105#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43398#L816 assume 1 == ~t11_pc~0; 42296#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42297#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43239#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43000#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 43001#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43539#L835 assume 1 == ~t12_pc~0; 43413#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 42445#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42284#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42285#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 43157#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 43158#L854 assume !(1 == ~t13_pc~0); 42777#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 42778#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42827#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42476#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 42477#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43897#L1401 assume !(1 == ~M_E~0); 42987#L1401-2 assume !(1 == ~T1_E~0); 42988#L1406-1 assume !(1 == ~T2_E~0); 43595#L1411-1 assume !(1 == ~T3_E~0); 43596#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43247#L1421-1 assume !(1 == ~T5_E~0); 42773#L1426-1 assume !(1 == ~T6_E~0); 42774#L1431-1 assume !(1 == ~T7_E~0); 42331#L1436-1 assume !(1 == ~T8_E~0); 42332#L1441-1 assume !(1 == ~T9_E~0); 43097#L1446-1 assume !(1 == ~T10_E~0); 43098#L1451-1 assume !(1 == ~T11_E~0); 43807#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 43466#L1461-1 assume !(1 == ~T13_E~0); 43016#L1466-1 assume !(1 == ~E_1~0); 43017#L1471-1 assume !(1 == ~E_2~0); 43788#L1476-1 assume !(1 == ~E_3~0); 43789#L1481-1 assume !(1 == ~E_4~0); 43942#L1486-1 assume !(1 == ~E_5~0); 42602#L1491-1 assume !(1 == ~E_6~0); 42269#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 42270#L1501-1 assume !(1 == ~E_8~0); 43091#L1506-1 assume !(1 == ~E_9~0); 43092#L1511-1 assume !(1 == ~E_10~0); 43046#L1516-1 assume !(1 == ~E_11~0); 42221#L1521-1 assume !(1 == ~E_12~0); 42222#L1526-1 assume !(1 == ~E_13~0); 42268#L1531-1 assume { :end_inline_reset_delta_events } true; 42799#L1892-2 [2022-12-13 15:12:00,786 INFO L750 eck$LassoCheckResult]: Loop: 42799#L1892-2 assume !false; 43849#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44047#L1233 assume !false; 44030#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43355#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 43335#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 43878#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 42310#L1046 assume !(0 != eval_~tmp~0#1); 42312#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 42845#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 42846#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44087#L1258-5 assume !(0 == ~T1_E~0); 42468#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42469#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44079#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44083#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44084#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 42702#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 42703#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 43846#L1298-3 assume !(0 == ~T9_E~0); 43847#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 44010#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 43845#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 43339#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 42470#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 42471#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43934#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42613#L1338-3 assume !(0 == ~E_4~0); 42614#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 43765#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 43940#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 43941#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 43286#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 42834#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 42835#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43626#L1378-3 assume !(0 == ~E_12~0); 43627#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 43804#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43805#L607-42 assume 1 == ~m_pc~0; 43426#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 43141#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42974#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 42854#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42855#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43399#L626-42 assume 1 == ~t1_pc~0; 42945#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 42946#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44034#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43820#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42500#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42501#L645-42 assume !(1 == ~t2_pc~0); 43744#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 43745#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43284#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42722#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42241#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42242#L664-42 assume !(1 == ~t3_pc~0); 42758#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 42759#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43685#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43572#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43573#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43738#L683-42 assume !(1 == ~t4_pc~0); 43449#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 43450#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43578#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43741#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44000#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43840#L702-42 assume 1 == ~t5_pc~0; 43316#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 42936#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43240#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43349#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42253#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42254#L721-42 assume 1 == ~t6_pc~0; 42393#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 42414#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42593#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42594#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 43072#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42909#L740-42 assume !(1 == ~t7_pc~0); 42628#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 42629#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43201#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43055#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 43056#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43322#L759-42 assume 1 == ~t8_pc~0; 43177#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 43114#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43115#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43185#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43186#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43274#L778-42 assume 1 == ~t9_pc~0; 43126#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43128#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43543#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43451#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 43452#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43506#L797-42 assume 1 == ~t10_pc~0; 42636#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 42637#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43524#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43525#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 43545#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43546#L816-42 assume 1 == ~t11_pc~0; 42213#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42214#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44040#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43101#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 42813#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 42814#L835-42 assume !(1 == ~t12_pc~0); 43136#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 43137#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 43324#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43325#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 43900#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 43683#L854-42 assume 1 == ~t13_pc~0; 43684#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 42733#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42901#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42902#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 43012#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43013#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 43798#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42562#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42440#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42441#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43062#L1421-3 assume !(1 == ~T5_E~0); 43063#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42607#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42608#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 42225#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42226#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43824#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43149#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 42781#L1461-3 assume !(1 == ~T13_E~0); 42782#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44081#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42723#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42724#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43146#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42751#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 42752#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 43182#L1501-3 assume !(1 == ~E_8~0); 43183#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43622#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 43610#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 43611#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 43289#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 43290#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43705#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 42540#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 42587#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 42588#L1911 assume !(0 == start_simulation_~tmp~3#1); 43118#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43644#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 42678#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 42263#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 42264#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42387#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43147#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 43953#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 42799#L1892-2 [2022-12-13 15:12:00,786 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:00,787 INFO L85 PathProgramCache]: Analyzing trace with hash 1281641374, now seen corresponding path program 1 times [2022-12-13 15:12:00,787 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:00,787 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1545401648] [2022-12-13 15:12:00,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:00,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:00,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:00,830 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:00,830 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:00,830 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1545401648] [2022-12-13 15:12:00,830 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1545401648] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:00,830 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:00,830 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:00,830 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1083764095] [2022-12-13 15:12:00,831 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:00,831 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:00,831 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:00,832 INFO L85 PathProgramCache]: Analyzing trace with hash 502016542, now seen corresponding path program 2 times [2022-12-13 15:12:00,832 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:00,832 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [989292712] [2022-12-13 15:12:00,832 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:00,832 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:00,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:00,875 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:00,875 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:00,875 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [989292712] [2022-12-13 15:12:00,875 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [989292712] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:00,875 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:00,876 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:00,876 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [818640127] [2022-12-13 15:12:00,876 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:00,876 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:00,876 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:00,877 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:12:00,877 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:12:00,877 INFO L87 Difference]: Start difference. First operand 1914 states and 2825 transitions. cyclomatic complexity: 912 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:00,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:00,907 INFO L93 Difference]: Finished difference Result 1914 states and 2824 transitions. [2022-12-13 15:12:00,907 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2824 transitions. [2022-12-13 15:12:00,914 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 15:12:00,918 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2824 transitions. [2022-12-13 15:12:00,918 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-12-13 15:12:00,919 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-12-13 15:12:00,920 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2824 transitions. [2022-12-13 15:12:00,921 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:12:00,921 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2824 transitions. [2022-12-13 15:12:00,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2824 transitions. [2022-12-13 15:12:00,936 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-12-13 15:12:00,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4754440961337514) internal successors, (2824), 1913 states have internal predecessors, (2824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:00,941 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2824 transitions. [2022-12-13 15:12:00,942 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2824 transitions. [2022-12-13 15:12:00,942 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:12:00,942 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2824 transitions. [2022-12-13 15:12:00,942 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-12-13 15:12:00,942 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2824 transitions. [2022-12-13 15:12:00,946 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 15:12:00,946 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:00,946 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:00,948 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:00,948 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:00,948 INFO L748 eck$LassoCheckResult]: Stem: 46321#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 46322#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 47216#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 47217#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47938#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 47614#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47615#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46546#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46547#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47022#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46858#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46859#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46610#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 46611#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47028#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47207#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 47375#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 47409#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 46626#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46627#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 47830#L1258-2 assume !(0 == ~T1_E~0); 46943#L1263-1 assume !(0 == ~T2_E~0); 46944#L1268-1 assume !(0 == ~T3_E~0); 47253#L1273-1 assume !(0 == ~T4_E~0); 47809#L1278-1 assume !(0 == ~T5_E~0); 47668#L1283-1 assume !(0 == ~T6_E~0); 47669#L1288-1 assume !(0 == ~T7_E~0); 47906#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47895#L1298-1 assume !(0 == ~T9_E~0); 47825#L1303-1 assume !(0 == ~T10_E~0); 46424#L1308-1 assume !(0 == ~T11_E~0); 46364#L1313-1 assume !(0 == ~T12_E~0); 46365#L1318-1 assume !(0 == ~T13_E~0); 46372#L1323-1 assume !(0 == ~E_1~0); 46373#L1328-1 assume !(0 == ~E_2~0); 46556#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 47544#L1338-1 assume !(0 == ~E_4~0); 47545#L1343-1 assume !(0 == ~E_5~0); 47645#L1348-1 assume !(0 == ~E_6~0); 47925#L1353-1 assume !(0 == ~E_7~0); 47276#L1358-1 assume !(0 == ~E_8~0); 47277#L1363-1 assume !(0 == ~E_9~0); 47566#L1368-1 assume !(0 == ~E_10~0); 46217#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 46218#L1378-1 assume !(0 == ~E_12~0); 46501#L1383-1 assume !(0 == ~E_13~0); 46502#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47281#L607 assume 1 == ~m_pc~0; 47282#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 46574#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47086#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47087#L1560 assume !(0 != activate_threads_~tmp~1#1); 47189#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46385#L626 assume !(1 == ~t1_pc~0); 46386#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46667#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46668#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47553#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 46289#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46290#L645 assume 1 == ~t2_pc~0; 46403#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46358#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46469#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46470#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 47163#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47164#L664 assume 1 == ~t3_pc~0; 47923#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46153#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46154#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46816#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 46817#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47838#L683 assume !(1 == ~t4_pc~0); 47393#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 47346#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46175#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46176#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47501#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47110#L702 assume 1 == ~t5_pc~0; 47111#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47044#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47497#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47828#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 47737#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46191#L721 assume !(1 == ~t6_pc~0); 46168#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 46169#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46313#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46452#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 46829#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47441#L740 assume 1 == ~t7_pc~0; 46233#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46068#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46069#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46058#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 46059#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46757#L759 assume !(1 == ~t8_pc~0); 46758#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 46788#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47885#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47625#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 47626#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47905#L778 assume 1 == ~t9_pc~0; 47794#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46216#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46522#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46094#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 46095#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46398#L797 assume !(1 == ~t10_pc~0); 46399#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 46532#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47771#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46939#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 46940#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47233#L816 assume 1 == ~t11_pc~0; 46131#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46132#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47072#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46835#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 46836#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47374#L835 assume 1 == ~t12_pc~0; 47248#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 46280#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46119#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46120#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 46992#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 46993#L854 assume !(1 == ~t13_pc~0); 46612#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 46613#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46662#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46311#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46312#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47732#L1401 assume !(1 == ~M_E~0); 46822#L1401-2 assume !(1 == ~T1_E~0); 46823#L1406-1 assume !(1 == ~T2_E~0); 47430#L1411-1 assume !(1 == ~T3_E~0); 47431#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47082#L1421-1 assume !(1 == ~T5_E~0); 46608#L1426-1 assume !(1 == ~T6_E~0); 46609#L1431-1 assume !(1 == ~T7_E~0); 46166#L1436-1 assume !(1 == ~T8_E~0); 46167#L1441-1 assume !(1 == ~T9_E~0); 46932#L1446-1 assume !(1 == ~T10_E~0); 46933#L1451-1 assume !(1 == ~T11_E~0); 47642#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47301#L1461-1 assume !(1 == ~T13_E~0); 46851#L1466-1 assume !(1 == ~E_1~0); 46852#L1471-1 assume !(1 == ~E_2~0); 47623#L1476-1 assume !(1 == ~E_3~0); 47624#L1481-1 assume !(1 == ~E_4~0); 47777#L1486-1 assume !(1 == ~E_5~0); 46437#L1491-1 assume !(1 == ~E_6~0); 46104#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 46105#L1501-1 assume !(1 == ~E_8~0); 46926#L1506-1 assume !(1 == ~E_9~0); 46927#L1511-1 assume !(1 == ~E_10~0); 46881#L1516-1 assume !(1 == ~E_11~0); 46056#L1521-1 assume !(1 == ~E_12~0); 46057#L1526-1 assume !(1 == ~E_13~0); 46103#L1531-1 assume { :end_inline_reset_delta_events } true; 46634#L1892-2 [2022-12-13 15:12:00,948 INFO L750 eck$LassoCheckResult]: Loop: 46634#L1892-2 assume !false; 47684#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47882#L1233 assume !false; 47865#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47190#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 47170#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 47713#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 46145#L1046 assume !(0 != eval_~tmp~0#1); 46147#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46680#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46681#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 47922#L1258-5 assume !(0 == ~T1_E~0); 46303#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46304#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47914#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47918#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47919#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 46537#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 46538#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47681#L1298-3 assume !(0 == ~T9_E~0); 47682#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 47845#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 47680#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 47174#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 46305#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 46306#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47769#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46448#L1338-3 assume !(0 == ~E_4~0); 46449#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47600#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47775#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 47776#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 47121#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 46669#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 46670#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 47461#L1378-3 assume !(0 == ~E_12~0); 47462#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 47639#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47640#L607-42 assume 1 == ~m_pc~0; 47261#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 46976#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46811#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46689#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46690#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47237#L626-42 assume !(1 == ~t1_pc~0); 46785#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 46784#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47869#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47655#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46337#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46338#L645-42 assume !(1 == ~t2_pc~0); 47580#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 47581#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47119#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46557#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46076#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46077#L664-42 assume 1 == ~t3_pc~0; 46887#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46591#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47520#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47407#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47408#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47573#L683-42 assume !(1 == ~t4_pc~0); 47283#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 47284#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47413#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47576#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47835#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47675#L702-42 assume !(1 == ~t5_pc~0); 46769#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 46770#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47075#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47184#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46088#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46089#L721-42 assume 1 == ~t6_pc~0; 46228#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46249#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46428#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46429#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46907#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46744#L740-42 assume 1 == ~t7_pc~0; 46745#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46464#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47036#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46890#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 46891#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47157#L759-42 assume 1 == ~t8_pc~0; 47012#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46949#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46950#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47020#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47021#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47109#L778-42 assume 1 == ~t9_pc~0; 46961#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46963#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47378#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47285#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 47286#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47341#L797-42 assume 1 == ~t10_pc~0; 46471#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 46472#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47359#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47360#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 47380#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47381#L816-42 assume 1 == ~t11_pc~0; 46048#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46049#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47875#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46936#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 46648#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 46649#L835-42 assume !(1 == ~t12_pc~0); 46969#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 46970#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 47159#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 47160#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 47735#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 47518#L854-42 assume !(1 == ~t13_pc~0); 46567#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 46568#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46736#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46737#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46847#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46848#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 47633#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46397#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46275#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46276#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46897#L1421-3 assume !(1 == ~T5_E~0); 46898#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46442#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46443#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 46060#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46061#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47659#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 46984#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 46616#L1461-3 assume !(1 == ~T13_E~0); 46617#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 47916#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46558#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46559#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 46981#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46586#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46587#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 47017#L1501-3 assume !(1 == ~E_8~0); 47018#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 47457#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 47445#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 47446#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 47124#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 47125#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47540#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 46375#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 46422#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 46423#L1911 assume !(0 == start_simulation_~tmp~3#1); 46953#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47479#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 46513#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 46098#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 46099#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46222#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46982#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 47788#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 46634#L1892-2 [2022-12-13 15:12:00,949 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:00,949 INFO L85 PathProgramCache]: Analyzing trace with hash 855086876, now seen corresponding path program 1 times [2022-12-13 15:12:00,949 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:00,949 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1611056388] [2022-12-13 15:12:00,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:00,949 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:00,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:00,979 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:00,979 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:00,979 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1611056388] [2022-12-13 15:12:00,979 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1611056388] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:00,979 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:00,979 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:00,979 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1771917567] [2022-12-13 15:12:00,980 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:00,980 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:00,980 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:00,980 INFO L85 PathProgramCache]: Analyzing trace with hash 253258621, now seen corresponding path program 1 times [2022-12-13 15:12:00,981 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:00,981 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [832494421] [2022-12-13 15:12:00,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:00,981 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:00,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:01,028 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:01,028 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:01,028 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [832494421] [2022-12-13 15:12:01,028 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [832494421] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:01,028 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:01,028 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:01,028 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [293262889] [2022-12-13 15:12:01,028 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:01,029 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:01,029 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:01,029 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:12:01,029 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:12:01,030 INFO L87 Difference]: Start difference. First operand 1914 states and 2824 transitions. cyclomatic complexity: 911 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:01,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:01,059 INFO L93 Difference]: Finished difference Result 1914 states and 2823 transitions. [2022-12-13 15:12:01,059 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2823 transitions. [2022-12-13 15:12:01,065 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 15:12:01,069 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2823 transitions. [2022-12-13 15:12:01,070 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-12-13 15:12:01,070 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-12-13 15:12:01,071 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2823 transitions. [2022-12-13 15:12:01,072 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:12:01,072 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2823 transitions. [2022-12-13 15:12:01,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2823 transitions. [2022-12-13 15:12:01,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-12-13 15:12:01,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.474921630094044) internal successors, (2823), 1913 states have internal predecessors, (2823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:01,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2823 transitions. [2022-12-13 15:12:01,093 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2823 transitions. [2022-12-13 15:12:01,093 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:12:01,093 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2823 transitions. [2022-12-13 15:12:01,094 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-12-13 15:12:01,094 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2823 transitions. [2022-12-13 15:12:01,100 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 15:12:01,100 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:01,100 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:01,102 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:01,102 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:01,102 INFO L748 eck$LassoCheckResult]: Stem: 50156#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 50157#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 51051#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 51052#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 51773#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 51449#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51450#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50381#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50382#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50857#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50693#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50694#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50445#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50446#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50863#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 51042#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 51210#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 51244#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 50461#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50462#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 51665#L1258-2 assume !(0 == ~T1_E~0); 50778#L1263-1 assume !(0 == ~T2_E~0); 50779#L1268-1 assume !(0 == ~T3_E~0); 51088#L1273-1 assume !(0 == ~T4_E~0); 51644#L1278-1 assume !(0 == ~T5_E~0); 51503#L1283-1 assume !(0 == ~T6_E~0); 51504#L1288-1 assume !(0 == ~T7_E~0); 51741#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51730#L1298-1 assume !(0 == ~T9_E~0); 51660#L1303-1 assume !(0 == ~T10_E~0); 50259#L1308-1 assume !(0 == ~T11_E~0); 50199#L1313-1 assume !(0 == ~T12_E~0); 50200#L1318-1 assume !(0 == ~T13_E~0); 50207#L1323-1 assume !(0 == ~E_1~0); 50208#L1328-1 assume !(0 == ~E_2~0); 50391#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 51379#L1338-1 assume !(0 == ~E_4~0); 51380#L1343-1 assume !(0 == ~E_5~0); 51480#L1348-1 assume !(0 == ~E_6~0); 51760#L1353-1 assume !(0 == ~E_7~0); 51111#L1358-1 assume !(0 == ~E_8~0); 51112#L1363-1 assume !(0 == ~E_9~0); 51401#L1368-1 assume !(0 == ~E_10~0); 50052#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 50053#L1378-1 assume !(0 == ~E_12~0); 50336#L1383-1 assume !(0 == ~E_13~0); 50337#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51116#L607 assume 1 == ~m_pc~0; 51117#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50409#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50918#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50919#L1560 assume !(0 != activate_threads_~tmp~1#1); 51024#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50220#L626 assume !(1 == ~t1_pc~0); 50221#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50502#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50503#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 51388#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 50124#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50125#L645 assume 1 == ~t2_pc~0; 50236#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50193#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50304#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50305#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 50998#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50999#L664 assume 1 == ~t3_pc~0; 51758#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49986#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49987#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50651#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 50652#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51673#L683 assume !(1 == ~t4_pc~0); 51228#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 51181#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50010#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50011#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51336#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50945#L702 assume 1 == ~t5_pc~0; 50946#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50879#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51332#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51663#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 51572#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50024#L721 assume !(1 == ~t6_pc~0); 50003#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 50004#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50148#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50287#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 50664#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51276#L740 assume 1 == ~t7_pc~0; 50068#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49903#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49904#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49893#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 49894#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50592#L759 assume !(1 == ~t8_pc~0); 50593#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 50623#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51718#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51460#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 51461#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51740#L778 assume 1 == ~t9_pc~0; 51629#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50051#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50357#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49929#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 49930#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50233#L797 assume !(1 == ~t10_pc~0); 50234#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 50367#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51606#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50774#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 50775#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51068#L816 assume 1 == ~t11_pc~0; 49966#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49967#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50907#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50670#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 50671#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 51209#L835 assume 1 == ~t12_pc~0; 51083#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 50115#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 49954#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 49955#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 50827#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 50828#L854 assume !(1 == ~t13_pc~0); 50447#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 50448#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50497#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50146#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50147#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51567#L1401 assume !(1 == ~M_E~0); 50657#L1401-2 assume !(1 == ~T1_E~0); 50658#L1406-1 assume !(1 == ~T2_E~0); 51265#L1411-1 assume !(1 == ~T3_E~0); 51266#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50917#L1421-1 assume !(1 == ~T5_E~0); 50443#L1426-1 assume !(1 == ~T6_E~0); 50444#L1431-1 assume !(1 == ~T7_E~0); 50001#L1436-1 assume !(1 == ~T8_E~0); 50002#L1441-1 assume !(1 == ~T9_E~0); 50767#L1446-1 assume !(1 == ~T10_E~0); 50768#L1451-1 assume !(1 == ~T11_E~0); 51477#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 51136#L1461-1 assume !(1 == ~T13_E~0); 50686#L1466-1 assume !(1 == ~E_1~0); 50687#L1471-1 assume !(1 == ~E_2~0); 51458#L1476-1 assume !(1 == ~E_3~0); 51459#L1481-1 assume !(1 == ~E_4~0); 51612#L1486-1 assume !(1 == ~E_5~0); 50272#L1491-1 assume !(1 == ~E_6~0); 49939#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 49940#L1501-1 assume !(1 == ~E_8~0); 50761#L1506-1 assume !(1 == ~E_9~0); 50762#L1511-1 assume !(1 == ~E_10~0); 50716#L1516-1 assume !(1 == ~E_11~0); 49891#L1521-1 assume !(1 == ~E_12~0); 49892#L1526-1 assume !(1 == ~E_13~0); 49938#L1531-1 assume { :end_inline_reset_delta_events } true; 50469#L1892-2 [2022-12-13 15:12:01,103 INFO L750 eck$LassoCheckResult]: Loop: 50469#L1892-2 assume !false; 51519#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 51717#L1233 assume !false; 51700#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51025#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 51005#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51548#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 49980#L1046 assume !(0 != eval_~tmp~0#1); 49982#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50515#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50516#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 51757#L1258-5 assume !(0 == ~T1_E~0); 50136#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50137#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 51749#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 51753#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51754#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50372#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50373#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51516#L1298-3 assume !(0 == ~T9_E~0); 51517#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 51680#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 51515#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 51009#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 50138#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 50139#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 51604#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50283#L1338-3 assume !(0 == ~E_4~0); 50284#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51435#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 51610#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 51611#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50956#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 50504#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 50505#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 51296#L1378-3 assume !(0 == ~E_12~0); 51297#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 51474#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51475#L607-42 assume 1 == ~m_pc~0; 51096#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50811#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50646#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50524#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50525#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51072#L626-42 assume 1 == ~t1_pc~0; 50618#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50619#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51704#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 51490#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50172#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50173#L645-42 assume !(1 == ~t2_pc~0); 51415#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 51416#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50954#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50392#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49911#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49912#L664-42 assume 1 == ~t3_pc~0; 50724#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50429#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51355#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51242#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51243#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51408#L683-42 assume !(1 == ~t4_pc~0); 51121#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 51122#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51249#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51411#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51670#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51513#L702-42 assume 1 == ~t5_pc~0; 50989#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50606#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50912#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51019#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 49923#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49924#L721-42 assume 1 == ~t6_pc~0; 50062#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 50084#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50263#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50264#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50742#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50577#L740-42 assume 1 == ~t7_pc~0; 50578#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50296#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50871#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50725#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 50726#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50992#L759-42 assume !(1 == ~t8_pc~0); 50848#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 50784#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50785#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50855#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 50856#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50944#L778-42 assume 1 == ~t9_pc~0; 50796#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50798#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51211#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 51118#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 51119#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51176#L797-42 assume 1 == ~t10_pc~0; 50306#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 50307#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51194#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 51195#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 51215#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51216#L816-42 assume 1 == ~t11_pc~0; 49883#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49884#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 51710#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50771#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50483#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50484#L835-42 assume !(1 == ~t12_pc~0); 50804#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 50805#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50994#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50995#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 51570#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 51353#L854-42 assume !(1 == ~t13_pc~0); 50402#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 50403#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50571#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50572#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50682#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50683#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 51468#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50232#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50110#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50111#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50732#L1421-3 assume !(1 == ~T5_E~0); 50733#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50277#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50278#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49895#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49896#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 51494#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50819#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 50451#L1461-3 assume !(1 == ~T13_E~0); 50452#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 51751#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50393#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50394#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50816#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50421#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50422#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50852#L1501-3 assume !(1 == ~E_8~0); 50853#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 51292#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 51279#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 51280#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 50959#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 50960#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51375#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50210#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 50257#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 50258#L1911 assume !(0 == start_simulation_~tmp~3#1); 50786#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51314#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50348#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 49933#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 49934#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50057#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50817#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 51623#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 50469#L1892-2 [2022-12-13 15:12:01,103 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:01,103 INFO L85 PathProgramCache]: Analyzing trace with hash 1395516382, now seen corresponding path program 1 times [2022-12-13 15:12:01,103 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:01,103 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1078240707] [2022-12-13 15:12:01,104 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:01,104 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:01,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:01,154 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:01,154 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:01,154 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1078240707] [2022-12-13 15:12:01,154 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1078240707] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:01,154 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:01,155 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 15:12:01,155 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1703081472] [2022-12-13 15:12:01,155 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:01,155 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:01,155 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:01,156 INFO L85 PathProgramCache]: Analyzing trace with hash 936635870, now seen corresponding path program 1 times [2022-12-13 15:12:01,156 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:01,156 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2101360417] [2022-12-13 15:12:01,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:01,156 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:01,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:01,204 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:01,204 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:01,204 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2101360417] [2022-12-13 15:12:01,204 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2101360417] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:01,204 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:01,204 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:01,205 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [363473423] [2022-12-13 15:12:01,205 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:01,205 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:01,205 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:01,206 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:12:01,206 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:12:01,206 INFO L87 Difference]: Start difference. First operand 1914 states and 2823 transitions. cyclomatic complexity: 910 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:01,326 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:01,326 INFO L93 Difference]: Finished difference Result 3555 states and 5213 transitions. [2022-12-13 15:12:01,326 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3555 states and 5213 transitions. [2022-12-13 15:12:01,338 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3382 [2022-12-13 15:12:01,344 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3555 states to 3555 states and 5213 transitions. [2022-12-13 15:12:01,344 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3555 [2022-12-13 15:12:01,346 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3555 [2022-12-13 15:12:01,346 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3555 states and 5213 transitions. [2022-12-13 15:12:01,350 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:12:01,350 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3555 states and 5213 transitions. [2022-12-13 15:12:01,353 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3555 states and 5213 transitions. [2022-12-13 15:12:01,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3555 to 3555. [2022-12-13 15:12:01,386 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3555 states, 3555 states have (on average 1.4663853727144867) internal successors, (5213), 3554 states have internal predecessors, (5213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:01,390 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3555 states to 3555 states and 5213 transitions. [2022-12-13 15:12:01,391 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3555 states and 5213 transitions. [2022-12-13 15:12:01,391 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:12:01,391 INFO L428 stractBuchiCegarLoop]: Abstraction has 3555 states and 5213 transitions. [2022-12-13 15:12:01,391 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-12-13 15:12:01,391 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3555 states and 5213 transitions. [2022-12-13 15:12:01,399 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3382 [2022-12-13 15:12:01,399 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:01,399 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:01,400 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:01,400 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:01,401 INFO L748 eck$LassoCheckResult]: Stem: 55631#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 55632#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 56538#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 56539#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 57324#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 56946#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 56947#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55857#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55858#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56336#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 56170#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 56171#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 55921#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 55922#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 56344#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 56529#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 56701#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 56736#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 55937#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55938#L1258 assume !(0 == ~M_E~0); 57184#L1258-2 assume !(0 == ~T1_E~0); 56258#L1263-1 assume !(0 == ~T2_E~0); 56259#L1268-1 assume !(0 == ~T3_E~0); 56576#L1273-1 assume !(0 == ~T4_E~0); 57159#L1278-1 assume !(0 == ~T5_E~0); 57002#L1283-1 assume !(0 == ~T6_E~0); 57003#L1288-1 assume !(0 == ~T7_E~0); 57274#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 57260#L1298-1 assume !(0 == ~T9_E~0); 57178#L1303-1 assume !(0 == ~T10_E~0); 55734#L1308-1 assume !(0 == ~T11_E~0); 55674#L1313-1 assume !(0 == ~T12_E~0); 55675#L1318-1 assume !(0 == ~T13_E~0); 55680#L1323-1 assume !(0 == ~E_1~0); 55681#L1328-1 assume !(0 == ~E_2~0); 55867#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 56875#L1338-1 assume !(0 == ~E_4~0); 56876#L1343-1 assume !(0 == ~E_5~0); 56978#L1348-1 assume !(0 == ~E_6~0); 57304#L1353-1 assume !(0 == ~E_7~0); 56599#L1358-1 assume !(0 == ~E_8~0); 56600#L1363-1 assume !(0 == ~E_9~0); 56897#L1368-1 assume !(0 == ~E_10~0); 55527#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 55528#L1378-1 assume !(0 == ~E_12~0); 55810#L1383-1 assume !(0 == ~E_13~0); 55811#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56603#L607 assume !(1 == ~m_pc~0); 55884#L607-2 is_master_triggered_~__retres1~0#1 := 0; 55885#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56402#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 56403#L1560 assume !(0 != activate_threads_~tmp~1#1); 56511#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55695#L626 assume !(1 == ~t1_pc~0); 55696#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 55978#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55979#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 56884#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 55599#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55600#L645 assume 1 == ~t2_pc~0; 55711#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 55668#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55778#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 55779#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 56485#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56486#L664 assume 1 == ~t3_pc~0; 57298#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 55462#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55463#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 56128#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 56129#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57193#L683 assume !(1 == ~t4_pc~0); 56719#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 56671#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55486#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 55487#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 56832#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56425#L702 assume 1 == ~t5_pc~0; 56426#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 56360#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 56828#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 57182#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 57073#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55497#L721 assume !(1 == ~t6_pc~0); 55479#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 55480#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 55623#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 55763#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 56141#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 56770#L740 assume 1 == ~t7_pc~0; 55543#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 55379#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55380#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 55369#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 55370#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 56068#L759 assume !(1 == ~t8_pc~0); 56069#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 56100#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 57243#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 56957#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 56958#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 57273#L778 assume 1 == ~t9_pc~0; 57142#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 55526#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 55833#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 55405#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 55406#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 55707#L797 assume !(1 == ~t10_pc~0); 55708#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 55843#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 57113#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 56254#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 56255#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 56555#L816 assume 1 == ~t11_pc~0; 55440#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 55441#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 56391#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 56147#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 56148#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 56700#L835 assume 1 == ~t12_pc~0; 56570#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 55590#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 55430#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 55431#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 56308#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 56309#L854 assume !(1 == ~t13_pc~0); 55923#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 55924#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 55973#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 55621#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 55622#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57069#L1401 assume !(1 == ~M_E~0); 56134#L1401-2 assume !(1 == ~T1_E~0); 56135#L1406-1 assume !(1 == ~T2_E~0); 56759#L1411-1 assume !(1 == ~T3_E~0); 56760#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56401#L1421-1 assume !(1 == ~T5_E~0); 55919#L1426-1 assume !(1 == ~T6_E~0); 55920#L1431-1 assume !(1 == ~T7_E~0); 55477#L1436-1 assume !(1 == ~T8_E~0); 55478#L1441-1 assume !(1 == ~T9_E~0); 56243#L1446-1 assume !(1 == ~T10_E~0); 56244#L1451-1 assume !(1 == ~T11_E~0); 56975#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 56623#L1461-1 assume !(1 == ~T13_E~0); 56163#L1466-1 assume !(1 == ~E_1~0); 56164#L1471-1 assume !(1 == ~E_2~0); 56955#L1476-1 assume !(1 == ~E_3~0); 56956#L1481-1 assume !(1 == ~E_4~0); 57120#L1486-1 assume !(1 == ~E_5~0); 55747#L1491-1 assume !(1 == ~E_6~0); 55415#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 55416#L1501-1 assume !(1 == ~E_8~0); 56239#L1506-1 assume !(1 == ~E_9~0); 56240#L1511-1 assume !(1 == ~E_10~0); 56193#L1516-1 assume !(1 == ~E_11~0); 55367#L1521-1 assume !(1 == ~E_12~0); 55368#L1526-1 assume !(1 == ~E_13~0); 55414#L1531-1 assume { :end_inline_reset_delta_events } true; 55945#L1892-2 [2022-12-13 15:12:01,401 INFO L750 eck$LassoCheckResult]: Loop: 55945#L1892-2 assume !false; 57018#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57242#L1233 assume !false; 57224#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 56512#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 56492#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 57050#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 55456#L1046 assume !(0 != eval_~tmp~0#1); 55458#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 55990#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 55991#L1258-3 assume !(0 == ~M_E~0); 57297#L1258-5 assume !(0 == ~T1_E~0); 55611#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 55612#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 57287#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 57292#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 57293#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 55848#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 55849#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 57015#L1298-3 assume !(0 == ~T9_E~0); 57016#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 57201#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 57014#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 56496#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 55613#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 55614#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 57111#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 55758#L1338-3 assume !(0 == ~E_4~0); 55759#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 56932#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 57117#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 57118#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 56441#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 55980#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 55981#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 56793#L1378-3 assume !(0 == ~E_12~0); 56794#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 57221#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 58793#L607-42 assume !(1 == ~m_pc~0); 56582#L607-44 is_master_triggered_~__retres1~0#1 := 0; 56291#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56121#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 56000#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 56001#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56556#L626-42 assume 1 == ~t1_pc~0; 56092#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 56093#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 57228#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 56988#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 55647#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55648#L645-42 assume 1 == ~t2_pc~0; 57192#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 56912#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56439#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 55868#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 55387#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55388#L664-42 assume !(1 == ~t3_pc~0); 55904#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 55905#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 56851#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 56734#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 56735#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 56904#L683-42 assume !(1 == ~t4_pc~0); 56606#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 56607#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56741#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 56907#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 57189#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 57009#L702-42 assume !(1 == ~t5_pc~0); 56082#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 56083#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 56394#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 56506#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 55399#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55400#L721-42 assume 1 == ~t6_pc~0; 55538#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 55559#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 55738#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 55739#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 56220#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 56055#L740-42 assume !(1 == ~t7_pc~0); 56056#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 58854#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 58853#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 58852#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 58851#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 58850#L759-42 assume 1 == ~t8_pc~0; 56328#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 56264#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 56265#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 56337#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 56338#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 56430#L778-42 assume 1 == ~t9_pc~0; 56276#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 56278#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 56705#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 58816#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 58815#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 58814#L797-42 assume 1 == ~t10_pc~0; 55782#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 55783#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 56684#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 56685#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 56706#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 56707#L816-42 assume !(1 == ~t11_pc~0); 55361#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 55360#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 57234#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 56250#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 56251#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 56388#L835-42 assume 1 == ~t12_pc~0; 56389#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 58803#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58802#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 58801#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 58800#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 58799#L854-42 assume !(1 == ~t13_pc~0); 58797#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 58796#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 58795#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 58794#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 56159#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56160#L1401-3 assume !(1 == ~M_E~0); 56965#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 55710#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 55585#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 55586#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56210#L1421-3 assume !(1 == ~T5_E~0); 56211#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 55752#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 55753#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 55371#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 55372#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 56992#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 56300#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 55927#L1461-3 assume !(1 == ~T13_E~0); 55928#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 57290#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 55869#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 55870#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 56296#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 55897#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 55898#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 56334#L1501-3 assume !(1 == ~E_8~0); 56335#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 56788#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 56789#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 58502#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 58501#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 58500#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 58490#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 58485#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 58484#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 57573#L1911 assume !(0 == start_simulation_~tmp~3#1); 57570#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 57568#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 57553#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 57552#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 57551#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 57550#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 57549#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 57146#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 55945#L1892-2 [2022-12-13 15:12:01,401 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:01,401 INFO L85 PathProgramCache]: Analyzing trace with hash -1486214853, now seen corresponding path program 1 times [2022-12-13 15:12:01,401 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:01,401 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [597833114] [2022-12-13 15:12:01,402 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:01,402 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:01,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:01,457 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:01,458 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:01,458 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [597833114] [2022-12-13 15:12:01,458 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [597833114] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:01,458 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:01,458 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:01,458 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [623959413] [2022-12-13 15:12:01,458 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:01,459 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:01,459 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:01,459 INFO L85 PathProgramCache]: Analyzing trace with hash 151995032, now seen corresponding path program 1 times [2022-12-13 15:12:01,459 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:01,459 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [687041813] [2022-12-13 15:12:01,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:01,460 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:01,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:01,510 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:01,511 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:01,511 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [687041813] [2022-12-13 15:12:01,511 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [687041813] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:01,511 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:01,511 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:01,511 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [284365625] [2022-12-13 15:12:01,511 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:01,512 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:01,512 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:01,512 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 15:12:01,512 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 15:12:01,512 INFO L87 Difference]: Start difference. First operand 3555 states and 5213 transitions. cyclomatic complexity: 1659 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:01,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:01,633 INFO L93 Difference]: Finished difference Result 6962 states and 10199 transitions. [2022-12-13 15:12:01,633 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6962 states and 10199 transitions. [2022-12-13 15:12:01,656 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6764 [2022-12-13 15:12:01,670 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6962 states to 6962 states and 10199 transitions. [2022-12-13 15:12:01,671 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6962 [2022-12-13 15:12:01,675 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6962 [2022-12-13 15:12:01,675 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6962 states and 10199 transitions. [2022-12-13 15:12:01,681 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:12:01,681 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6962 states and 10199 transitions. [2022-12-13 15:12:01,686 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6962 states and 10199 transitions. [2022-12-13 15:12:01,737 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6962 to 6962. [2022-12-13 15:12:01,743 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6962 states, 6962 states have (on average 1.4649525998276358) internal successors, (10199), 6961 states have internal predecessors, (10199), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:01,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6962 states to 6962 states and 10199 transitions. [2022-12-13 15:12:01,753 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6962 states and 10199 transitions. [2022-12-13 15:12:01,753 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 15:12:01,753 INFO L428 stractBuchiCegarLoop]: Abstraction has 6962 states and 10199 transitions. [2022-12-13 15:12:01,754 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-12-13 15:12:01,754 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6962 states and 10199 transitions. [2022-12-13 15:12:01,769 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6764 [2022-12-13 15:12:01,769 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:01,769 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:01,770 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:01,770 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:01,771 INFO L748 eck$LassoCheckResult]: Stem: 66161#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 66162#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 67064#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 67065#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 67824#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 67474#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 67475#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 66388#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 66389#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 66868#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 66702#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 66703#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 66453#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 66454#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 66876#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 67055#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 67226#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 67260#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 66469#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 66470#L1258 assume !(0 == ~M_E~0); 67701#L1258-2 assume !(0 == ~T1_E~0); 66789#L1263-1 assume !(0 == ~T2_E~0); 66790#L1268-1 assume !(0 == ~T3_E~0); 67102#L1273-1 assume !(0 == ~T4_E~0); 67678#L1278-1 assume !(0 == ~T5_E~0); 67531#L1283-1 assume !(0 == ~T6_E~0); 67532#L1288-1 assume !(0 == ~T7_E~0); 67779#L1293-1 assume !(0 == ~T8_E~0); 67766#L1298-1 assume !(0 == ~T9_E~0); 67695#L1303-1 assume !(0 == ~T10_E~0); 66265#L1308-1 assume !(0 == ~T11_E~0); 66204#L1313-1 assume !(0 == ~T12_E~0); 66205#L1318-1 assume !(0 == ~T13_E~0); 66210#L1323-1 assume !(0 == ~E_1~0); 66211#L1328-1 assume !(0 == ~E_2~0); 66398#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 67401#L1338-1 assume !(0 == ~E_4~0); 67402#L1343-1 assume !(0 == ~E_5~0); 67505#L1348-1 assume !(0 == ~E_6~0); 67805#L1353-1 assume !(0 == ~E_7~0); 67125#L1358-1 assume !(0 == ~E_8~0); 67126#L1363-1 assume !(0 == ~E_9~0); 67423#L1368-1 assume !(0 == ~E_10~0); 66057#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 66058#L1378-1 assume !(0 == ~E_12~0); 66341#L1383-1 assume !(0 == ~E_13~0); 66342#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67129#L607 assume !(1 == ~m_pc~0); 66415#L607-2 is_master_triggered_~__retres1~0#1 := 0; 66416#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 66931#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 66932#L1560 assume !(0 != activate_threads_~tmp~1#1); 67037#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66225#L626 assume !(1 == ~t1_pc~0); 66226#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 66511#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66512#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 67410#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 66129#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66130#L645 assume 1 == ~t2_pc~0; 66242#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 66198#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66308#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 66309#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 67011#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67012#L664 assume 1 == ~t3_pc~0; 67801#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 65990#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65991#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 66660#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 66661#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67709#L683 assume !(1 == ~t4_pc~0); 67244#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 67197#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66015#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 66016#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 67357#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66954#L702 assume 1 == ~t5_pc~0; 66955#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 66891#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 67353#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 67699#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 67599#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 66027#L721 assume !(1 == ~t6_pc~0); 66008#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 66009#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 66153#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 66293#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 66673#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 67295#L740 assume 1 == ~t7_pc~0; 66073#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 65906#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 65907#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 65896#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 65897#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 66600#L759 assume !(1 == ~t8_pc~0); 66601#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 66632#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 67754#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 67485#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 67486#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 67778#L778 assume 1 == ~t9_pc~0; 67662#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 66056#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66364#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 65932#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 65933#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 66239#L797 assume !(1 == ~t10_pc~0); 66240#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 66374#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 67638#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 66785#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 66786#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 67082#L816 assume 1 == ~t11_pc~0; 65968#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 65969#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 66920#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 66679#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 66680#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 67225#L835 assume 1 == ~t12_pc~0; 67097#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 66120#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 65958#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 65959#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 66840#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 66841#L854 assume !(1 == ~t13_pc~0); 66455#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 66456#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 66506#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 66151#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 66152#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 67595#L1401 assume !(1 == ~M_E~0); 66666#L1401-2 assume !(1 == ~T1_E~0); 66667#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 67603#L1411-1 assume !(1 == ~T3_E~0); 68130#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 68129#L1421-1 assume !(1 == ~T5_E~0); 68128#L1426-1 assume !(1 == ~T6_E~0); 68127#L1431-1 assume !(1 == ~T7_E~0); 68126#L1436-1 assume !(1 == ~T8_E~0); 66006#L1441-1 assume !(1 == ~T9_E~0); 68125#L1446-1 assume !(1 == ~T10_E~0); 68124#L1451-1 assume !(1 == ~T11_E~0); 68123#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 68122#L1461-1 assume !(1 == ~T13_E~0); 68121#L1466-1 assume !(1 == ~E_1~0); 67826#L1471-1 assume !(1 == ~E_2~0); 67483#L1476-1 assume !(1 == ~E_3~0); 67484#L1481-1 assume !(1 == ~E_4~0); 67645#L1486-1 assume !(1 == ~E_5~0); 66278#L1491-1 assume !(1 == ~E_6~0); 65943#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 65944#L1501-1 assume !(1 == ~E_8~0); 68097#L1506-1 assume !(1 == ~E_9~0); 68096#L1511-1 assume !(1 == ~E_10~0); 66726#L1516-1 assume !(1 == ~E_11~0); 66727#L1521-1 assume !(1 == ~E_12~0); 65941#L1526-1 assume !(1 == ~E_13~0); 65942#L1531-1 assume { :end_inline_reset_delta_events } true; 67902#L1892-2 [2022-12-13 15:12:01,771 INFO L750 eck$LassoCheckResult]: Loop: 67902#L1892-2 assume !false; 67896#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 67895#L1233 assume !false; 67894#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 67879#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 67864#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 67862#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 67859#L1046 assume !(0 != eval_~tmp~0#1); 67856#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 67854#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 67852#L1258-3 assume !(0 == ~M_E~0); 67849#L1258-5 assume !(0 == ~T1_E~0); 67847#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 67848#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 72616#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 72615#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 72614#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 72613#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 72612#L1293-3 assume !(0 == ~T8_E~0); 72611#L1298-3 assume !(0 == ~T9_E~0); 72610#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 72609#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 72608#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 72607#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 72606#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 72605#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 72604#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 72603#L1338-3 assume !(0 == ~E_4~0); 72602#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 72601#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 72600#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 72599#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 72598#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 72597#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 72596#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 72595#L1378-3 assume !(0 == ~E_12~0); 72594#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 72593#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 72592#L607-42 assume !(1 == ~m_pc~0); 72590#L607-44 is_master_triggered_~__retres1~0#1 := 0; 72589#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 72588#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 72587#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 72586#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 72585#L626-42 assume 1 == ~t1_pc~0; 72583#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 72582#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 72581#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 72580#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 72579#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 72578#L645-42 assume 1 == ~t2_pc~0; 72577#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 72575#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 72574#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 72573#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 72572#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 72571#L664-42 assume 1 == ~t3_pc~0; 72569#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 72568#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 72567#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 72566#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 72565#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 72564#L683-42 assume 1 == ~t4_pc~0; 72563#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 72559#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 72557#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 72556#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 72555#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 72554#L702-42 assume !(1 == ~t5_pc~0); 72553#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 72551#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 72550#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 72549#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 72548#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 72547#L721-42 assume !(1 == ~t6_pc~0); 72545#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 72544#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 72543#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 72542#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 72541#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 72540#L740-42 assume !(1 == ~t7_pc~0); 72539#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 72537#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 72509#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 72508#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 72507#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 72506#L759-42 assume !(1 == ~t8_pc~0); 72505#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 72503#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 72502#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 72501#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 72500#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 72499#L778-42 assume !(1 == ~t9_pc~0); 72497#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 72496#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 72495#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 72494#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 72493#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 72492#L797-42 assume !(1 == ~t10_pc~0); 72491#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 72489#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 72488#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 72487#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 72486#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 72485#L816-42 assume !(1 == ~t11_pc~0); 65888#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 65887#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 67746#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 66782#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 66492#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 66493#L835-42 assume !(1 == ~t12_pc~0); 66817#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 66818#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 67007#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 67008#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 67843#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 70357#L854-42 assume !(1 == ~t13_pc~0); 69001#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 68998#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 68996#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 68994#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 68992#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68990#L1401-3 assume !(1 == ~M_E~0); 68553#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 68986#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 66238#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 68983#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 68981#L1421-3 assume !(1 == ~T5_E~0); 68979#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 68976#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 68974#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 66430#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 68971#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 68969#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 68967#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 68964#L1461-3 assume !(1 == ~T13_E~0); 68962#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 68960#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 68958#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 68956#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 68954#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 68951#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 68949#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 68947#L1501-3 assume !(1 == ~E_8~0); 68945#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 68943#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 68941#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 68938#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 68936#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 68113#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68059#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68049#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68047#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 67955#L1911 assume !(0 == start_simulation_~tmp~3#1); 67952#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 67950#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 67936#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 67932#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 67930#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 67928#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 67927#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 67913#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 67902#L1892-2 [2022-12-13 15:12:01,771 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:01,771 INFO L85 PathProgramCache]: Analyzing trace with hash -1259435077, now seen corresponding path program 1 times [2022-12-13 15:12:01,771 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:01,772 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [667805291] [2022-12-13 15:12:01,772 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:01,772 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:01,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:01,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:01,848 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:01,849 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [667805291] [2022-12-13 15:12:01,849 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [667805291] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:01,849 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:01,849 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:01,849 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [909297467] [2022-12-13 15:12:01,849 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:01,850 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:01,850 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:01,850 INFO L85 PathProgramCache]: Analyzing trace with hash -931531213, now seen corresponding path program 1 times [2022-12-13 15:12:01,850 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:01,850 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1829470834] [2022-12-13 15:12:01,851 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:01,851 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:01,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:01,906 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:01,906 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:01,906 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1829470834] [2022-12-13 15:12:01,906 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1829470834] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:01,906 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:01,906 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:01,907 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [20072714] [2022-12-13 15:12:01,907 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:01,907 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:01,907 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:01,908 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 15:12:01,908 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 15:12:01,908 INFO L87 Difference]: Start difference. First operand 6962 states and 10199 transitions. cyclomatic complexity: 3239 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:02,107 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:02,107 INFO L93 Difference]: Finished difference Result 13360 states and 19568 transitions. [2022-12-13 15:12:02,107 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13360 states and 19568 transitions. [2022-12-13 15:12:02,145 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13128 [2022-12-13 15:12:02,173 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13360 states to 13360 states and 19568 transitions. [2022-12-13 15:12:02,173 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13360 [2022-12-13 15:12:02,181 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13360 [2022-12-13 15:12:02,181 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13360 states and 19568 transitions. [2022-12-13 15:12:02,192 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:12:02,192 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13360 states and 19568 transitions. [2022-12-13 15:12:02,201 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13360 states and 19568 transitions. [2022-12-13 15:12:02,341 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13360 to 13356. [2022-12-13 15:12:02,354 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13356 states, 13356 states have (on average 1.4648098233003894) internal successors, (19564), 13355 states have internal predecessors, (19564), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:02,374 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13356 states to 13356 states and 19564 transitions. [2022-12-13 15:12:02,374 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13356 states and 19564 transitions. [2022-12-13 15:12:02,374 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 15:12:02,375 INFO L428 stractBuchiCegarLoop]: Abstraction has 13356 states and 19564 transitions. [2022-12-13 15:12:02,375 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-12-13 15:12:02,375 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13356 states and 19564 transitions. [2022-12-13 15:12:02,406 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13128 [2022-12-13 15:12:02,406 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:02,406 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:02,407 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:02,408 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:02,408 INFO L748 eck$LassoCheckResult]: Stem: 86492#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 86493#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 87407#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 87408#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 88213#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 87822#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 87823#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 86719#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 86720#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 87202#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 87037#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 87038#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 86787#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 86788#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 87210#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 87398#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 87566#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 87602#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 86803#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86804#L1258 assume !(0 == ~M_E~0); 88069#L1258-2 assume !(0 == ~T1_E~0); 87124#L1263-1 assume !(0 == ~T2_E~0); 87125#L1268-1 assume !(0 == ~T3_E~0); 87445#L1273-1 assume !(0 == ~T4_E~0); 88047#L1278-1 assume !(0 == ~T5_E~0); 87888#L1283-1 assume !(0 == ~T6_E~0); 87889#L1288-1 assume !(0 == ~T7_E~0); 88157#L1293-1 assume !(0 == ~T8_E~0); 88145#L1298-1 assume !(0 == ~T9_E~0); 88064#L1303-1 assume !(0 == ~T10_E~0); 86596#L1308-1 assume !(0 == ~T11_E~0); 86535#L1313-1 assume !(0 == ~T12_E~0); 86536#L1318-1 assume !(0 == ~T13_E~0); 86541#L1323-1 assume !(0 == ~E_1~0); 86542#L1328-1 assume !(0 == ~E_2~0); 86729#L1333-1 assume !(0 == ~E_3~0); 87745#L1338-1 assume !(0 == ~E_4~0); 87746#L1343-1 assume !(0 == ~E_5~0); 87861#L1348-1 assume !(0 == ~E_6~0); 88186#L1353-1 assume !(0 == ~E_7~0); 87468#L1358-1 assume !(0 == ~E_8~0); 87469#L1363-1 assume !(0 == ~E_9~0); 87767#L1368-1 assume !(0 == ~E_10~0); 86388#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 86389#L1378-1 assume !(0 == ~E_12~0); 86672#L1383-1 assume !(0 == ~E_13~0); 86673#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 87472#L607 assume !(1 == ~m_pc~0); 86747#L607-2 is_master_triggered_~__retres1~0#1 := 0; 86748#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87267#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 87268#L1560 assume !(0 != activate_threads_~tmp~1#1); 87377#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 86556#L626 assume !(1 == ~t1_pc~0); 86557#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 86844#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86845#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 87754#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 86460#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86461#L645 assume 1 == ~t2_pc~0; 86573#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 86529#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 86639#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 86640#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 87350#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 87351#L664 assume 1 == ~t3_pc~0; 88182#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 86321#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86322#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 86994#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 86995#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88079#L683 assume !(1 == ~t4_pc~0); 87585#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 87536#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86345#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 86346#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 87701#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 87290#L702 assume 1 == ~t5_pc~0; 87291#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 87226#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 87697#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 88067#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 87959#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 86357#L721 assume !(1 == ~t6_pc~0); 86338#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 86339#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 86484#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 86624#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 87007#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 87639#L740 assume 1 == ~t7_pc~0; 86404#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 86238#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86239#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 86228#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 86229#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 86934#L759 assume !(1 == ~t8_pc~0); 86935#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 86966#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 88132#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 87834#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 87835#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 88156#L778 assume 1 == ~t9_pc~0; 88029#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 86386#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 86695#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 86264#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 86265#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 86568#L797 assume !(1 == ~t10_pc~0); 86569#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 86705#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 88004#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 87120#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 87121#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 87424#L816 assume 1 == ~t11_pc~0; 86299#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 86300#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 87255#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 87013#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 87014#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 87565#L835 assume 1 == ~t12_pc~0; 87440#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 86451#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 86289#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 86290#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 87173#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 87174#L854 assume !(1 == ~t13_pc~0); 86789#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 86790#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86839#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 86482#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 86483#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 87954#L1401 assume !(1 == ~M_E~0); 87000#L1401-2 assume !(1 == ~T1_E~0); 87001#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 87962#L1411-1 assume !(1 == ~T3_E~0); 90200#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 87265#L1421-1 assume !(1 == ~T5_E~0); 87266#L1426-1 assume !(1 == ~T6_E~0); 87775#L1431-1 assume !(1 == ~T7_E~0); 86336#L1436-1 assume !(1 == ~T8_E~0); 86337#L1441-1 assume !(1 == ~T9_E~0); 87111#L1446-1 assume !(1 == ~T10_E~0); 87112#L1451-1 assume !(1 == ~T11_E~0); 88225#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 89899#L1461-1 assume !(1 == ~T13_E~0); 89897#L1466-1 assume !(1 == ~E_1~0); 88221#L1471-1 assume !(1 == ~E_2~0); 88222#L1476-1 assume !(1 == ~E_3~0); 89741#L1481-1 assume !(1 == ~E_4~0); 89740#L1486-1 assume !(1 == ~E_5~0); 89738#L1491-1 assume !(1 == ~E_6~0); 89695#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 89691#L1501-1 assume !(1 == ~E_8~0); 89647#L1506-1 assume !(1 == ~E_9~0); 89627#L1511-1 assume !(1 == ~E_10~0); 89625#L1516-1 assume !(1 == ~E_11~0); 89623#L1521-1 assume !(1 == ~E_12~0); 89607#L1526-1 assume !(1 == ~E_13~0); 89589#L1531-1 assume { :end_inline_reset_delta_events } true; 89577#L1892-2 [2022-12-13 15:12:02,408 INFO L750 eck$LassoCheckResult]: Loop: 89577#L1892-2 assume !false; 89571#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 89570#L1233 assume !false; 89569#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 89554#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 89539#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 89537#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 89534#L1046 assume !(0 != eval_~tmp~0#1); 89531#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 89529#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 89527#L1258-3 assume !(0 == ~M_E~0); 89524#L1258-5 assume !(0 == ~T1_E~0); 89522#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 89523#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 93850#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 93848#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 93846#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 93844#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 93843#L1293-3 assume !(0 == ~T8_E~0); 93108#L1298-3 assume !(0 == ~T9_E~0); 93105#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 93103#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 93101#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 93099#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 93097#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 93095#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 93092#L1333-3 assume !(0 == ~E_3~0); 92533#L1338-3 assume !(0 == ~E_4~0); 92531#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 92529#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 92235#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 92232#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 92231#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 92229#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 91927#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 91924#L1378-3 assume !(0 == ~E_12~0); 91922#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 91920#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 91791#L607-42 assume !(1 == ~m_pc~0); 91788#L607-44 is_master_triggered_~__retres1~0#1 := 0; 91786#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 91784#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 91782#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 91779#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 91777#L626-42 assume 1 == ~t1_pc~0; 91773#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 91771#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 91769#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 91767#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 91765#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 91763#L645-42 assume 1 == ~t2_pc~0; 91760#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 91758#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 91572#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 91569#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 91567#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 91565#L664-42 assume !(1 == ~t3_pc~0); 91563#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 91560#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 91558#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 91555#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 91553#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 91551#L683-42 assume !(1 == ~t4_pc~0); 91547#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 91545#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 91542#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 91540#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 91538#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 91536#L702-42 assume 1 == ~t5_pc~0; 91533#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 91531#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 91530#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 91527#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 91525#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 91523#L721-42 assume 1 == ~t6_pc~0; 91521#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 91518#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 91516#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 91513#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 91511#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 91509#L740-42 assume 1 == ~t7_pc~0; 91505#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 91503#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 91500#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 91498#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 91496#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 91494#L759-42 assume 1 == ~t8_pc~0; 91491#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 91489#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 91488#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 91335#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 91334#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 91331#L778-42 assume 1 == ~t9_pc~0; 91329#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 91326#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 91324#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 91322#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 91320#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 91319#L797-42 assume 1 == ~t10_pc~0; 91317#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 91314#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 91312#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 91310#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 91308#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 91306#L816-42 assume !(1 == ~t11_pc~0); 91303#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 91302#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 91077#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 91075#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 91073#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 91071#L835-42 assume !(1 == ~t12_pc~0); 91069#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 91066#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 91065#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 91064#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 91062#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 91060#L854-42 assume !(1 == ~t13_pc~0); 90859#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 90643#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 90641#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 90639#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 90637#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 90635#L1401-3 assume !(1 == ~M_E~0); 90250#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 90632#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 86572#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 90317#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 90186#L1421-3 assume !(1 == ~T5_E~0); 90183#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 90110#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 90108#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 90103#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 90018#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 89950#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 89893#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 89890#L1461-3 assume !(1 == ~T13_E~0); 89888#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 88234#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 88235#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 89830#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 89828#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 89826#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 89824#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 89821#L1501-3 assume !(1 == ~E_8~0); 89819#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 89817#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 89815#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 89813#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 89811#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 89808#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 89795#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 89789#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 89787#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 89783#L1911 assume !(0 == start_simulation_~tmp~3#1); 89735#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 89690#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 89646#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 89626#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 89624#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 89608#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 89606#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 89588#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 89577#L1892-2 [2022-12-13 15:12:02,408 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:02,408 INFO L85 PathProgramCache]: Analyzing trace with hash -312397191, now seen corresponding path program 1 times [2022-12-13 15:12:02,408 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:02,409 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1506785060] [2022-12-13 15:12:02,409 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:02,409 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:02,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:02,459 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:02,459 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:02,459 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1506785060] [2022-12-13 15:12:02,459 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1506785060] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:02,459 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:02,459 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:02,459 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [201166845] [2022-12-13 15:12:02,459 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:02,460 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:02,460 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:02,460 INFO L85 PathProgramCache]: Analyzing trace with hash 1918436341, now seen corresponding path program 1 times [2022-12-13 15:12:02,460 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:02,460 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1311932277] [2022-12-13 15:12:02,461 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:02,461 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:02,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:02,505 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:02,506 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:02,506 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1311932277] [2022-12-13 15:12:02,506 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1311932277] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:02,506 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:02,506 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:02,506 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [451753327] [2022-12-13 15:12:02,506 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:02,507 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:02,507 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:02,507 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 15:12:02,507 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 15:12:02,507 INFO L87 Difference]: Start difference. First operand 13356 states and 19564 transitions. cyclomatic complexity: 6212 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:02,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:02,761 INFO L93 Difference]: Finished difference Result 25712 states and 37649 transitions. [2022-12-13 15:12:02,761 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25712 states and 37649 transitions. [2022-12-13 15:12:02,864 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 25456 [2022-12-13 15:12:02,913 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25712 states to 25712 states and 37649 transitions. [2022-12-13 15:12:02,913 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25712 [2022-12-13 15:12:02,923 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25712 [2022-12-13 15:12:02,923 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25712 states and 37649 transitions. [2022-12-13 15:12:02,933 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:12:02,933 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25712 states and 37649 transitions. [2022-12-13 15:12:02,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25712 states and 37649 transitions. [2022-12-13 15:12:03,221 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25712 to 25704. [2022-12-13 15:12:03,243 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25704 states, 25704 states have (on average 1.4644024276377217) internal successors, (37641), 25703 states have internal predecessors, (37641), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:03,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25704 states to 25704 states and 37641 transitions. [2022-12-13 15:12:03,293 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25704 states and 37641 transitions. [2022-12-13 15:12:03,293 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 15:12:03,294 INFO L428 stractBuchiCegarLoop]: Abstraction has 25704 states and 37641 transitions. [2022-12-13 15:12:03,294 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-12-13 15:12:03,294 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25704 states and 37641 transitions. [2022-12-13 15:12:03,373 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 25456 [2022-12-13 15:12:03,373 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:03,373 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:03,374 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:03,374 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:03,375 INFO L748 eck$LassoCheckResult]: Stem: 125569#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 125570#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 126492#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 126493#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 127347#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 126916#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 126917#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 125795#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 125796#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 126282#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 126114#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 126115#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 125860#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 125861#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 126290#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 126483#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 126654#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 126692#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 125876#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 125877#L1258 assume !(0 == ~M_E~0); 127182#L1258-2 assume !(0 == ~T1_E~0); 126203#L1263-1 assume !(0 == ~T2_E~0); 126204#L1268-1 assume !(0 == ~T3_E~0); 126530#L1273-1 assume !(0 == ~T4_E~0); 127154#L1278-1 assume !(0 == ~T5_E~0); 126980#L1283-1 assume !(0 == ~T6_E~0); 126981#L1288-1 assume !(0 == ~T7_E~0); 127286#L1293-1 assume !(0 == ~T8_E~0); 127272#L1298-1 assume !(0 == ~T9_E~0); 127173#L1303-1 assume !(0 == ~T10_E~0); 125672#L1308-1 assume !(0 == ~T11_E~0); 125612#L1313-1 assume !(0 == ~T12_E~0); 125613#L1318-1 assume !(0 == ~T13_E~0); 125618#L1323-1 assume !(0 == ~E_1~0); 125619#L1328-1 assume !(0 == ~E_2~0); 125805#L1333-1 assume !(0 == ~E_3~0); 126837#L1338-1 assume !(0 == ~E_4~0); 126838#L1343-1 assume !(0 == ~E_5~0); 126953#L1348-1 assume !(0 == ~E_6~0); 127320#L1353-1 assume !(0 == ~E_7~0); 126553#L1358-1 assume !(0 == ~E_8~0); 126554#L1363-1 assume !(0 == ~E_9~0); 126861#L1368-1 assume !(0 == ~E_10~0); 125465#L1373-1 assume !(0 == ~E_11~0); 125466#L1378-1 assume !(0 == ~E_12~0); 125748#L1383-1 assume !(0 == ~E_13~0); 125749#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 126557#L607 assume !(1 == ~m_pc~0); 125822#L607-2 is_master_triggered_~__retres1~0#1 := 0; 125823#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 126348#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 126349#L1560 assume !(0 != activate_threads_~tmp~1#1); 126461#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 125633#L626 assume !(1 == ~t1_pc~0); 125634#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 125919#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 125920#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 126848#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 125537#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 125538#L645 assume 1 == ~t2_pc~0; 125649#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 125606#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 125716#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 125717#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 126433#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 126434#L664 assume 1 == ~t3_pc~0; 127315#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 125399#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 125400#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 126072#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 126073#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 127190#L683 assume !(1 == ~t4_pc~0); 126674#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 126624#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 125423#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 125424#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 126792#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 126371#L702 assume 1 == ~t5_pc~0; 126372#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 126306#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 126788#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 127177#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 127061#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 125435#L721 assume !(1 == ~t6_pc~0); 125416#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 125417#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 125561#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 125701#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 126085#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 126728#L740 assume 1 == ~t7_pc~0; 125481#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 125316#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 125317#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 125306#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 125307#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 126012#L759 assume !(1 == ~t8_pc~0); 126013#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 126044#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 127256#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 126927#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 126928#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 127285#L778 assume 1 == ~t9_pc~0; 127135#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 125464#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 125771#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 125342#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 125343#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 125645#L797 assume !(1 == ~t10_pc~0); 125646#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 125781#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 127109#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 126199#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 126200#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 126509#L816 assume 1 == ~t11_pc~0; 125377#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 125378#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 126337#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 126091#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 126092#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 126653#L835 assume 1 == ~t12_pc~0; 126525#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 125528#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 125367#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 125368#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 126253#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 126254#L854 assume !(1 == ~t13_pc~0); 125862#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 125863#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 125914#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 125559#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 125560#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 127056#L1401 assume !(1 == ~M_E~0); 126078#L1401-2 assume !(1 == ~T1_E~0); 126079#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 126716#L1411-1 assume !(1 == ~T3_E~0); 126717#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 126347#L1421-1 assume !(1 == ~T5_E~0); 125858#L1426-1 assume !(1 == ~T6_E~0); 125859#L1431-1 assume !(1 == ~T7_E~0); 125414#L1436-1 assume !(1 == ~T8_E~0); 125415#L1441-1 assume !(1 == ~T9_E~0); 126190#L1446-1 assume !(1 == ~T10_E~0); 126191#L1451-1 assume !(1 == ~T11_E~0); 126950#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 126576#L1461-1 assume !(1 == ~T13_E~0); 126107#L1466-1 assume !(1 == ~E_1~0); 126108#L1471-1 assume !(1 == ~E_2~0); 126925#L1476-1 assume !(1 == ~E_3~0); 126926#L1481-1 assume !(1 == ~E_4~0); 127116#L1486-1 assume !(1 == ~E_5~0); 125686#L1491-1 assume !(1 == ~E_6~0); 125352#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 125353#L1501-1 assume !(1 == ~E_8~0); 126186#L1506-1 assume !(1 == ~E_9~0); 126187#L1511-1 assume !(1 == ~E_10~0); 126139#L1516-1 assume !(1 == ~E_11~0); 125304#L1521-1 assume !(1 == ~E_12~0); 125305#L1526-1 assume !(1 == ~E_13~0); 125351#L1531-1 assume { :end_inline_reset_delta_events } true; 125884#L1892-2 [2022-12-13 15:12:03,375 INFO L750 eck$LassoCheckResult]: Loop: 125884#L1892-2 assume !false; 127476#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 136939#L1233 assume !false; 136937#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 136859#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 136853#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 136851#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 136848#L1046 assume !(0 != eval_~tmp~0#1); 136847#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 136846#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 136845#L1258-3 assume !(0 == ~M_E~0); 136844#L1258-5 assume !(0 == ~T1_E~0); 136842#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 136839#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 136837#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 136835#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 136833#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 136831#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 136830#L1293-3 assume !(0 == ~T8_E~0); 136829#L1298-3 assume !(0 == ~T9_E~0); 136828#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 136827#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 136826#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 136825#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 136824#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 136822#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 136819#L1333-3 assume !(0 == ~E_3~0); 136817#L1338-3 assume !(0 == ~E_4~0); 136815#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 136813#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 136811#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 136809#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 135112#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 135110#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 135107#L1373-3 assume !(0 == ~E_11~0); 135105#L1378-3 assume !(0 == ~E_12~0); 135103#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 135101#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 135099#L607-42 assume !(1 == ~m_pc~0); 134600#L607-44 is_master_triggered_~__retres1~0#1 := 0; 134598#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 134596#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 134594#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 134592#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 134589#L626-42 assume 1 == ~t1_pc~0; 134586#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 134584#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 134582#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 134580#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 134578#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 134577#L645-42 assume 1 == ~t2_pc~0; 134574#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 134030#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 134028#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 134025#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 134023#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 134021#L664-42 assume 1 == ~t3_pc~0; 134018#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 134016#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 134014#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 134011#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 134009#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 134007#L683-42 assume !(1 == ~t4_pc~0); 134004#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 134002#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 134000#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 133997#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 133995#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 133993#L702-42 assume 1 == ~t5_pc~0; 133990#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 133988#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 133986#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 133983#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 133981#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 133979#L721-42 assume !(1 == ~t6_pc~0); 133976#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 133974#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 133972#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 133969#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 133967#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 133965#L740-42 assume 1 == ~t7_pc~0; 133962#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 133960#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 133958#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 133955#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 133953#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 133951#L759-42 assume 1 == ~t8_pc~0; 133948#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 133947#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 133946#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 133945#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 133944#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 133943#L778-42 assume 1 == ~t9_pc~0; 133942#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 133940#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 133939#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 133938#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 133937#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 133936#L797-42 assume 1 == ~t10_pc~0; 133934#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 133933#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 133932#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 133931#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 133521#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 133518#L816-42 assume !(1 == ~t11_pc~0); 133515#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 133513#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 133511#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 133509#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 133507#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 133504#L835-42 assume !(1 == ~t12_pc~0); 133502#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 132746#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 132744#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 132742#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 132741#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 132737#L854-42 assume !(1 == ~t13_pc~0); 132734#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 132732#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 132730#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 132728#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 132726#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 132724#L1401-3 assume !(1 == ~M_E~0); 132721#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 132720#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 127734#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 132719#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 132717#L1421-3 assume !(1 == ~T5_E~0); 132714#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 132712#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 132710#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 132707#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 132705#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 132703#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 132700#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 132698#L1461-3 assume !(1 == ~T13_E~0); 132696#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 132694#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 132692#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 132343#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 132688#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 132686#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 132684#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 132682#L1501-3 assume !(1 == ~E_8~0); 132680#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 132678#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 132675#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 132671#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 132669#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 132667#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 132212#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 132206#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 132203#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 132201#L1911 assume !(0 == start_simulation_~tmp~3#1); 127526#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 127501#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 127486#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 127484#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 127482#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 127481#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 127480#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 127478#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 125884#L1892-2 [2022-12-13 15:12:03,375 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:03,375 INFO L85 PathProgramCache]: Analyzing trace with hash -645040329, now seen corresponding path program 1 times [2022-12-13 15:12:03,375 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:03,375 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [96775384] [2022-12-13 15:12:03,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:03,375 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:03,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:03,422 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:03,423 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:03,423 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [96775384] [2022-12-13 15:12:03,423 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [96775384] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:03,423 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:03,423 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:03,423 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [619329455] [2022-12-13 15:12:03,423 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:03,424 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:03,424 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:03,424 INFO L85 PathProgramCache]: Analyzing trace with hash -2080430733, now seen corresponding path program 1 times [2022-12-13 15:12:03,424 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:03,424 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [205076940] [2022-12-13 15:12:03,424 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:03,424 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:03,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:03,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:03,467 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:03,467 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [205076940] [2022-12-13 15:12:03,467 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [205076940] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:03,467 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:03,467 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:03,467 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [884093696] [2022-12-13 15:12:03,467 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:03,468 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:03,468 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:03,468 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 15:12:03,468 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 15:12:03,468 INFO L87 Difference]: Start difference. First operand 25704 states and 37641 transitions. cyclomatic complexity: 11945 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:03,872 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:03,872 INFO L93 Difference]: Finished difference Result 74990 states and 108892 transitions. [2022-12-13 15:12:03,872 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 74990 states and 108892 transitions. [2022-12-13 15:12:04,115 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 73032 [2022-12-13 15:12:04,280 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 74990 states to 74990 states and 108892 transitions. [2022-12-13 15:12:04,280 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 74990 [2022-12-13 15:12:04,306 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 74990 [2022-12-13 15:12:04,306 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74990 states and 108892 transitions. [2022-12-13 15:12:04,341 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:12:04,341 INFO L218 hiAutomatonCegarLoop]: Abstraction has 74990 states and 108892 transitions. [2022-12-13 15:12:04,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74990 states and 108892 transitions. [2022-12-13 15:12:04,833 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74990 to 72678. [2022-12-13 15:12:04,884 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72678 states, 72678 states have (on average 1.454140179971931) internal successors, (105684), 72677 states have internal predecessors, (105684), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:05,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72678 states to 72678 states and 105684 transitions. [2022-12-13 15:12:05,059 INFO L240 hiAutomatonCegarLoop]: Abstraction has 72678 states and 105684 transitions. [2022-12-13 15:12:05,060 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 15:12:05,060 INFO L428 stractBuchiCegarLoop]: Abstraction has 72678 states and 105684 transitions. [2022-12-13 15:12:05,061 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-12-13 15:12:05,061 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72678 states and 105684 transitions. [2022-12-13 15:12:05,170 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 72352 [2022-12-13 15:12:05,170 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:05,170 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:05,172 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:05,172 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:05,172 INFO L748 eck$LassoCheckResult]: Stem: 226272#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 226273#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 227177#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 227178#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 228005#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 227605#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 227606#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 226498#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 226499#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 226974#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 226810#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 226811#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 226562#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 226563#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 226982#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 227168#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 227339#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 227374#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 226578#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 226579#L1258 assume !(0 == ~M_E~0); 227846#L1258-2 assume !(0 == ~T1_E~0); 226896#L1263-1 assume !(0 == ~T2_E~0); 226897#L1268-1 assume !(0 == ~T3_E~0); 227214#L1273-1 assume !(0 == ~T4_E~0); 227818#L1278-1 assume !(0 == ~T5_E~0); 227662#L1283-1 assume !(0 == ~T6_E~0); 227663#L1288-1 assume !(0 == ~T7_E~0); 227944#L1293-1 assume !(0 == ~T8_E~0); 227929#L1298-1 assume !(0 == ~T9_E~0); 227838#L1303-1 assume !(0 == ~T10_E~0); 226374#L1308-1 assume !(0 == ~T11_E~0); 226315#L1313-1 assume !(0 == ~T12_E~0); 226316#L1318-1 assume !(0 == ~T13_E~0); 226321#L1323-1 assume !(0 == ~E_1~0); 226322#L1328-1 assume !(0 == ~E_2~0); 226508#L1333-1 assume !(0 == ~E_3~0); 227523#L1338-1 assume !(0 == ~E_4~0); 227524#L1343-1 assume !(0 == ~E_5~0); 227636#L1348-1 assume !(0 == ~E_6~0); 227979#L1353-1 assume !(0 == ~E_7~0); 227236#L1358-1 assume !(0 == ~E_8~0); 227237#L1363-1 assume !(0 == ~E_9~0); 227547#L1368-1 assume !(0 == ~E_10~0); 226168#L1373-1 assume !(0 == ~E_11~0); 226169#L1378-1 assume !(0 == ~E_12~0); 226451#L1383-1 assume !(0 == ~E_13~0); 226452#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 227240#L607 assume !(1 == ~m_pc~0); 226525#L607-2 is_master_triggered_~__retres1~0#1 := 0; 226526#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 227038#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 227039#L1560 assume !(0 != activate_threads_~tmp~1#1); 227147#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 226336#L626 assume !(1 == ~t1_pc~0); 226337#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 226621#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 226622#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 227532#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 226240#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 226241#L645 assume !(1 == ~t2_pc~0); 226308#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 226309#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 226418#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 226419#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 227121#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 227122#L664 assume 1 == ~t3_pc~0; 227973#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 226103#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 226104#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 226769#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 226770#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 227860#L683 assume !(1 == ~t4_pc~0); 227358#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 227309#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 226127#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 226128#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 227476#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 227062#L702 assume 1 == ~t5_pc~0; 227063#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 226997#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 227471#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 227843#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 227733#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 226138#L721 assume !(1 == ~t6_pc~0); 226120#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 226121#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 226264#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 226403#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 226782#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 227410#L740 assume 1 == ~t7_pc~0; 226184#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 226020#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 226021#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 226010#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 226011#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 226709#L759 assume !(1 == ~t8_pc~0); 226710#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 226741#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 227915#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 227616#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 227617#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 227943#L778 assume 1 == ~t9_pc~0; 227801#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 226167#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 226474#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 226046#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 226047#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 226348#L797 assume !(1 == ~t10_pc~0); 226349#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 226484#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 227777#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 226892#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 226893#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 227194#L816 assume 1 == ~t11_pc~0; 226081#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 226082#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 227026#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 226788#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 226789#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 227338#L835 assume 1 == ~t12_pc~0; 227209#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 226231#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 226071#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 226072#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 226946#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 226947#L854 assume !(1 == ~t13_pc~0); 226564#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 226565#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 226616#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 226262#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 226263#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 227728#L1401 assume !(1 == ~M_E~0); 226775#L1401-2 assume !(1 == ~T1_E~0); 226776#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 227736#L1411-1 assume !(1 == ~T3_E~0); 227964#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 227965#L1421-1 assume !(1 == ~T5_E~0); 226560#L1426-1 assume !(1 == ~T6_E~0); 226561#L1431-1 assume !(1 == ~T7_E~0); 226118#L1436-1 assume !(1 == ~T8_E~0); 226119#L1441-1 assume !(1 == ~T9_E~0); 226882#L1446-1 assume !(1 == ~T10_E~0); 226883#L1451-1 assume !(1 == ~T11_E~0); 227633#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 227259#L1461-1 assume !(1 == ~T13_E~0); 226804#L1466-1 assume !(1 == ~E_1~0); 226805#L1471-1 assume !(1 == ~E_2~0); 227614#L1476-1 assume !(1 == ~E_3~0); 227615#L1481-1 assume !(1 == ~E_4~0); 227783#L1486-1 assume !(1 == ~E_5~0); 288487#L1491-1 assume !(1 == ~E_6~0); 288485#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 227275#L1501-1 assume !(1 == ~E_8~0); 227276#L1506-1 assume !(1 == ~E_9~0); 288361#L1511-1 assume !(1 == ~E_10~0); 288359#L1516-1 assume !(1 == ~E_11~0); 226833#L1521-1 assume !(1 == ~E_12~0); 288357#L1526-1 assume !(1 == ~E_13~0); 226586#L1531-1 assume { :end_inline_reset_delta_events } true; 226587#L1892-2 [2022-12-13 15:12:05,172 INFO L750 eck$LassoCheckResult]: Loop: 226587#L1892-2 assume !false; 227678#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 227914#L1233 assume !false; 227895#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 227149#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 227128#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 227708#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 226097#L1046 assume !(0 != eval_~tmp~0#1); 226099#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 226633#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 226634#L1258-3 assume !(0 == ~M_E~0); 227972#L1258-5 assume !(0 == ~T1_E~0); 226252#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 226253#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 227960#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 227967#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 227968#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 226489#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 226490#L1293-3 assume !(0 == ~T8_E~0); 228015#L1298-3 assume !(0 == ~T9_E~0); 298131#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 298130#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 298129#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 298128#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 298127#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 298126#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 298125#L1333-3 assume !(0 == ~E_3~0); 298124#L1338-3 assume !(0 == ~E_4~0); 298123#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 298122#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 298121#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 298120#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 298119#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 298118#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 298117#L1373-3 assume !(0 == ~E_11~0); 298116#L1378-3 assume !(0 == ~E_12~0); 298115#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 298114#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 298113#L607-42 assume !(1 == ~m_pc~0); 298112#L607-44 is_master_triggered_~__retres1~0#1 := 0; 298111#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 298110#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 298109#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 298108#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 298107#L626-42 assume 1 == ~t1_pc~0; 298105#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 298104#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 298103#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 227647#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 226288#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 226289#L645-42 assume !(1 == ~t2_pc~0); 227568#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 227569#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 227076#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 226509#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 226028#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 226029#L664-42 assume !(1 == ~t3_pc~0); 226545#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 226546#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 227497#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 227372#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 227373#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 227559#L683-42 assume 1 == ~t4_pc~0; 227990#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 227243#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 227379#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 227562#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 227853#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 227669#L702-42 assume 1 == ~t5_pc~0; 227107#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 226724#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 227029#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 227142#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 226040#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 226041#L721-42 assume 1 == ~t6_pc~0; 226179#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 226200#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 226378#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 226379#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 226859#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 226697#L740-42 assume 1 == ~t7_pc~0; 226698#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 226415#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 226990#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 226842#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 226843#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 227115#L759-42 assume !(1 == ~t8_pc~0); 226967#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 226902#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 226903#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 297768#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 227067#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 227068#L778-42 assume !(1 == ~t9_pc~0); 226915#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 226916#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 227343#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 227244#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 227245#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 227302#L797-42 assume 1 == ~t10_pc~0; 226422#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 226423#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 227322#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 227323#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 227344#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 227345#L816-42 assume !(1 == ~t11_pc~0); 226002#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 226001#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 227907#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 226889#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 226602#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 226603#L835-42 assume 1 == ~t12_pc~0; 227025#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 226926#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 227118#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 227119#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 227732#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 227495#L854-42 assume !(1 == ~t13_pc~0); 226521#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 226522#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 226689#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 226690#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 226800#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 226801#L1401-3 assume !(1 == ~M_E~0); 227625#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 226351#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 226226#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 226227#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 226849#L1421-3 assume !(1 == ~T5_E~0); 226850#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 226392#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 226393#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 226012#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 226013#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 227651#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 226938#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 226568#L1461-3 assume !(1 == ~T13_E~0); 226569#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 227963#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 226510#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 226511#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 226935#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 226538#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 226539#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 226972#L1501-3 assume !(1 == ~E_8~0); 226973#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 227427#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 227415#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 227416#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 227081#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 227082#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 227517#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 226326#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 226372#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 226373#L1911 assume !(0 == start_simulation_~tmp~3#1); 226906#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 227449#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 226465#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 226050#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 226051#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 226173#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 226936#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 227794#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 226587#L1892-2 [2022-12-13 15:12:05,173 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:05,173 INFO L85 PathProgramCache]: Analyzing trace with hash -1648097194, now seen corresponding path program 1 times [2022-12-13 15:12:05,173 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:05,173 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [69847235] [2022-12-13 15:12:05,173 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:05,173 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:05,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:05,219 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:05,219 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:05,220 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [69847235] [2022-12-13 15:12:05,220 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [69847235] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:05,220 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:05,220 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:05,220 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [976384027] [2022-12-13 15:12:05,220 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:05,220 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:05,220 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:05,220 INFO L85 PathProgramCache]: Analyzing trace with hash 731822482, now seen corresponding path program 1 times [2022-12-13 15:12:05,221 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:05,221 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1744242879] [2022-12-13 15:12:05,221 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:05,221 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:05,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:05,251 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:05,251 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:05,251 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1744242879] [2022-12-13 15:12:05,251 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1744242879] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:05,252 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:05,252 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:05,252 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1717447557] [2022-12-13 15:12:05,252 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:05,252 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:05,252 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:05,252 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 15:12:05,252 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 15:12:05,253 INFO L87 Difference]: Start difference. First operand 72678 states and 105684 transitions. cyclomatic complexity: 33022 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:06,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:06,015 INFO L93 Difference]: Finished difference Result 210029 states and 303417 transitions. [2022-12-13 15:12:06,015 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 210029 states and 303417 transitions. [2022-12-13 15:12:06,799 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 206072 [2022-12-13 15:12:07,300 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 210029 states to 210029 states and 303417 transitions. [2022-12-13 15:12:07,301 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 210029 [2022-12-13 15:12:07,365 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 210029 [2022-12-13 15:12:07,365 INFO L73 IsDeterministic]: Start isDeterministic. Operand 210029 states and 303417 transitions. [2022-12-13 15:12:07,527 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:12:07,527 INFO L218 hiAutomatonCegarLoop]: Abstraction has 210029 states and 303417 transitions. [2022-12-13 15:12:07,600 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 210029 states and 303417 transitions. [2022-12-13 15:12:08,869 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 210029 to 202813. [2022-12-13 15:12:08,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 202813 states, 202813 states have (on average 1.4468944298442408) internal successors, (293449), 202812 states have internal predecessors, (293449), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:09,363 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 202813 states to 202813 states and 293449 transitions. [2022-12-13 15:12:09,363 INFO L240 hiAutomatonCegarLoop]: Abstraction has 202813 states and 293449 transitions. [2022-12-13 15:12:09,364 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 15:12:09,364 INFO L428 stractBuchiCegarLoop]: Abstraction has 202813 states and 293449 transitions. [2022-12-13 15:12:09,364 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-12-13 15:12:09,364 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 202813 states and 293449 transitions. [2022-12-13 15:12:09,892 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 202328 [2022-12-13 15:12:09,892 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:09,892 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:09,894 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:09,894 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:09,894 INFO L748 eck$LassoCheckResult]: Stem: 508994#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 508995#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 509929#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 509930#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 510938#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 510403#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 510404#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 509226#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 509227#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 509721#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 509546#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 509547#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 509291#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 509292#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 509730#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 509919#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 510096#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 510135#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 509309#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 509310#L1258 assume !(0 == ~M_E~0); 510688#L1258-2 assume !(0 == ~T1_E~0); 509635#L1263-1 assume !(0 == ~T2_E~0); 509636#L1268-1 assume !(0 == ~T3_E~0); 509966#L1273-1 assume !(0 == ~T4_E~0); 510661#L1278-1 assume !(0 == ~T5_E~0); 510467#L1283-1 assume !(0 == ~T6_E~0); 510468#L1288-1 assume !(0 == ~T7_E~0); 510826#L1293-1 assume !(0 == ~T8_E~0); 510799#L1298-1 assume !(0 == ~T9_E~0); 510683#L1303-1 assume !(0 == ~T10_E~0); 509097#L1308-1 assume !(0 == ~T11_E~0); 509037#L1313-1 assume !(0 == ~T12_E~0); 509038#L1318-1 assume !(0 == ~T13_E~0); 509044#L1323-1 assume !(0 == ~E_1~0); 509045#L1328-1 assume !(0 == ~E_2~0); 509237#L1333-1 assume !(0 == ~E_3~0); 510299#L1338-1 assume !(0 == ~E_4~0); 510300#L1343-1 assume !(0 == ~E_5~0); 510437#L1348-1 assume !(0 == ~E_6~0); 510878#L1353-1 assume !(0 == ~E_7~0); 509990#L1358-1 assume !(0 == ~E_8~0); 509991#L1363-1 assume !(0 == ~E_9~0); 510333#L1368-1 assume !(0 == ~E_10~0); 508888#L1373-1 assume !(0 == ~E_11~0); 508889#L1378-1 assume !(0 == ~E_12~0); 509177#L1383-1 assume !(0 == ~E_13~0); 509178#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 509994#L607 assume !(1 == ~m_pc~0); 509254#L607-2 is_master_triggered_~__retres1~0#1 := 0; 509255#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 509789#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 509790#L1560 assume !(0 != activate_threads_~tmp~1#1); 509900#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 509059#L626 assume !(1 == ~t1_pc~0); 509060#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 509352#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 509353#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 510310#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 508962#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 508963#L645 assume !(1 == ~t2_pc~0); 509030#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 509031#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 509144#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 509145#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 509872#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 509873#L664 assume !(1 == ~t3_pc~0); 510359#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 508819#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 508820#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 509504#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 509505#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 510704#L683 assume !(1 == ~t4_pc~0); 510118#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 510065#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 508844#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 508845#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 510242#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 509812#L702 assume 1 == ~t5_pc~0; 509813#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 509745#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 510238#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 510686#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 510561#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 508854#L721 assume !(1 == ~t6_pc~0); 508837#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 508838#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 508986#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 509130#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 509518#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 510173#L740 assume 1 == ~t7_pc~0; 508905#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 508737#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 508738#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 508727#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 508728#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 509442#L759 assume !(1 == ~t8_pc~0); 509443#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 509474#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 510779#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 510416#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 510417#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 510824#L778 assume 1 == ~t9_pc~0; 510640#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 508886#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 509200#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 508762#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 508763#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 509071#L797 assume !(1 == ~t10_pc~0); 509072#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 509212#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 510608#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 509631#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 509632#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 509946#L816 assume 1 == ~t11_pc~0; 508797#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 508798#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 509778#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 509524#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 509525#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 510095#L835 assume 1 == ~t12_pc~0; 509961#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 508952#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 508787#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 508788#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 509687#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 509688#L854 assume !(1 == ~t13_pc~0); 509293#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 509294#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 509347#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 508984#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 508985#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 510553#L1401 assume !(1 == ~M_E~0); 509510#L1401-2 assume !(1 == ~T1_E~0); 509511#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 510563#L1411-1 assume !(1 == ~T3_E~0); 590331#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 590329#L1421-1 assume !(1 == ~T5_E~0); 590327#L1426-1 assume !(1 == ~T6_E~0); 590325#L1431-1 assume !(1 == ~T7_E~0); 590323#L1436-1 assume !(1 == ~T8_E~0); 590321#L1441-1 assume !(1 == ~T9_E~0); 590319#L1446-1 assume !(1 == ~T10_E~0); 590317#L1451-1 assume !(1 == ~T11_E~0); 590315#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 590313#L1461-1 assume !(1 == ~T13_E~0); 509540#L1466-1 assume !(1 == ~E_1~0); 509541#L1471-1 assume !(1 == ~E_2~0); 510414#L1476-1 assume !(1 == ~E_3~0); 510415#L1481-1 assume !(1 == ~E_4~0); 662738#L1486-1 assume !(1 == ~E_5~0); 509111#L1491-1 assume !(1 == ~E_6~0); 509112#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 510029#L1501-1 assume !(1 == ~E_8~0); 509616#L1506-1 assume !(1 == ~E_9~0); 509617#L1511-1 assume !(1 == ~E_10~0); 509569#L1516-1 assume !(1 == ~E_11~0); 508725#L1521-1 assume !(1 == ~E_12~0); 508726#L1526-1 assume !(1 == ~E_13~0); 508771#L1531-1 assume { :end_inline_reset_delta_events } true; 509317#L1892-2 [2022-12-13 15:12:09,894 INFO L750 eck$LassoCheckResult]: Loop: 509317#L1892-2 assume !false; 703191#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 703189#L1233 assume !false; 703187#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 703164#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 703162#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 703160#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 703157#L1046 assume !(0 != eval_~tmp~0#1); 703158#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 706892#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 706890#L1258-3 assume !(0 == ~M_E~0); 706888#L1258-5 assume !(0 == ~T1_E~0); 706886#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 706884#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 706882#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 706880#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 706878#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 706876#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 706874#L1293-3 assume !(0 == ~T8_E~0); 706872#L1298-3 assume !(0 == ~T9_E~0); 706870#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 706868#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 706866#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 706864#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 706862#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 706860#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 706858#L1333-3 assume !(0 == ~E_3~0); 706856#L1338-3 assume !(0 == ~E_4~0); 706854#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 706852#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 706850#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 706848#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 706846#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 706844#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 706842#L1373-3 assume !(0 == ~E_11~0); 706840#L1378-3 assume !(0 == ~E_12~0); 706837#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 706835#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 706832#L607-42 assume !(1 == ~m_pc~0); 706829#L607-44 is_master_triggered_~__retres1~0#1 := 0; 706826#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 706823#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 706820#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 706815#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 706812#L626-42 assume 1 == ~t1_pc~0; 706808#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 706806#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 706802#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 706800#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 509010#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 509011#L645-42 assume !(1 == ~t2_pc~0); 510355#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 510356#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 509826#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 509238#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 508745#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 508746#L664-42 assume !(1 == ~t3_pc~0); 509274#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 509275#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 510865#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 510133#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 510134#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 510958#L683-42 assume !(1 == ~t4_pc~0); 509996#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 509997#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 510346#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 510347#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 510696#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 510475#L702-42 assume 1 == ~t5_pc~0; 509857#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 509457#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 509781#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 509895#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 508756#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 508757#L721-42 assume !(1 == ~t6_pc~0); 508901#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 508921#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 509101#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 509102#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 509597#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 509430#L740-42 assume 1 == ~t7_pc~0; 509431#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 509141#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 509738#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 509579#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 509580#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 509865#L759-42 assume !(1 == ~t8_pc~0); 509712#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 509641#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 509642#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 509722#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 509723#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 510489#L778-42 assume !(1 == ~t9_pc~0); 509654#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 509655#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 706740#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 706738#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 706736#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 706735#L797-42 assume !(1 == ~t10_pc~0); 706734#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 706732#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 706731#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 706730#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 706729#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 706728#L816-42 assume !(1 == ~t11_pc~0); 706726#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 706725#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 706724#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 706723#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 706722#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 706721#L835-42 assume 1 == ~t12_pc~0; 510149#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 509666#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 509868#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 509869#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 510560#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 510266#L854-42 assume !(1 == ~t13_pc~0); 510268#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 706715#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 509421#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 509422#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 509676#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 510984#L1401-3 assume !(1 == ~M_E~0); 510985#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 707894#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 593427#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 707892#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 707891#L1421-3 assume !(1 == ~T5_E~0); 707890#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 707889#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 707888#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 673162#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 707887#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 707886#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 707885#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 707884#L1461-3 assume !(1 == ~T13_E~0); 707883#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 707882#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 707881#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 658751#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 707880#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 707879#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 707878#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 707877#L1501-3 assume !(1 == ~E_8~0); 707876#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 707875#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 707874#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 691273#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 509832#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 509833#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 510295#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 705052#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 705050#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 705049#L1911 assume !(0 == start_simulation_~tmp~3#1); 705047#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 703231#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 703216#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 703214#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 703212#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 703210#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 703207#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 703205#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 509317#L1892-2 [2022-12-13 15:12:09,895 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:09,895 INFO L85 PathProgramCache]: Analyzing trace with hash -1375101771, now seen corresponding path program 1 times [2022-12-13 15:12:09,895 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:09,895 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [193580634] [2022-12-13 15:12:09,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:09,895 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:09,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:09,945 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:09,946 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:09,946 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [193580634] [2022-12-13 15:12:09,946 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [193580634] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:09,946 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:09,946 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 15:12:09,946 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [196196927] [2022-12-13 15:12:09,947 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:09,947 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:09,947 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:09,948 INFO L85 PathProgramCache]: Analyzing trace with hash 1635878639, now seen corresponding path program 1 times [2022-12-13 15:12:09,948 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:09,948 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [371470874] [2022-12-13 15:12:09,948 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:09,948 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:09,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:10,007 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:10,008 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:10,008 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [371470874] [2022-12-13 15:12:10,008 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [371470874] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:10,008 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:10,008 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:10,008 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [793618655] [2022-12-13 15:12:10,009 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:10,009 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:10,009 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:10,009 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 15:12:10,010 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 15:12:10,010 INFO L87 Difference]: Start difference. First operand 202813 states and 293449 transitions. cyclomatic complexity: 90668 Second operand has 5 states, 5 states have (on average 31.8) internal successors, (159), 5 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:11,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:11,403 INFO L93 Difference]: Finished difference Result 547726 states and 795256 transitions. [2022-12-13 15:12:11,403 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 547726 states and 795256 transitions. [2022-12-13 15:12:13,353 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 546472 [2022-12-13 15:12:14,265 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 547726 states to 547726 states and 795256 transitions. [2022-12-13 15:12:14,265 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 547726 [2022-12-13 15:12:14,434 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 547726 [2022-12-13 15:12:14,434 INFO L73 IsDeterministic]: Start isDeterministic. Operand 547726 states and 795256 transitions. [2022-12-13 15:12:14,694 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:12:14,694 INFO L218 hiAutomatonCegarLoop]: Abstraction has 547726 states and 795256 transitions. [2022-12-13 15:12:14,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 547726 states and 795256 transitions. [2022-12-13 15:12:17,018 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 547726 to 207976. [2022-12-13 15:12:17,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 207976 states, 207976 states have (on average 1.4358002846482287) internal successors, (298612), 207975 states have internal predecessors, (298612), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:17,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207976 states to 207976 states and 298612 transitions. [2022-12-13 15:12:17,440 INFO L240 hiAutomatonCegarLoop]: Abstraction has 207976 states and 298612 transitions. [2022-12-13 15:12:17,440 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 15:12:17,440 INFO L428 stractBuchiCegarLoop]: Abstraction has 207976 states and 298612 transitions. [2022-12-13 15:12:17,440 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-12-13 15:12:17,441 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 207976 states and 298612 transitions. [2022-12-13 15:12:18,127 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 207488 [2022-12-13 15:12:18,127 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:18,127 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:18,129 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:18,129 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:18,129 INFO L748 eck$LassoCheckResult]: Stem: 1259541#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1259542#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1260462#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1260463#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1261413#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 1260923#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1260924#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1259767#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1259768#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1260256#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1260086#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1260087#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1259832#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1259833#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1260262#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1260451#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1260632#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1260672#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1259848#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1259849#L1258 assume !(0 == ~M_E~0); 1261191#L1258-2 assume !(0 == ~T1_E~0); 1260172#L1263-1 assume !(0 == ~T2_E~0); 1260173#L1268-1 assume !(0 == ~T3_E~0); 1260500#L1273-1 assume !(0 == ~T4_E~0); 1261163#L1278-1 assume !(0 == ~T5_E~0); 1260978#L1283-1 assume !(0 == ~T6_E~0); 1260979#L1288-1 assume !(0 == ~T7_E~0); 1261336#L1293-1 assume !(0 == ~T8_E~0); 1261314#L1298-1 assume !(0 == ~T9_E~0); 1261183#L1303-1 assume !(0 == ~T10_E~0); 1259643#L1308-1 assume !(0 == ~T11_E~0); 1259584#L1313-1 assume !(0 == ~T12_E~0); 1259585#L1318-1 assume !(0 == ~T13_E~0); 1259592#L1323-1 assume !(0 == ~E_1~0); 1259593#L1328-1 assume !(0 == ~E_2~0); 1259777#L1333-1 assume !(0 == ~E_3~0); 1260835#L1338-1 assume !(0 == ~E_4~0); 1260836#L1343-1 assume !(0 == ~E_5~0); 1260952#L1348-1 assume !(0 == ~E_6~0); 1261371#L1353-1 assume !(0 == ~E_7~0); 1260522#L1358-1 assume !(0 == ~E_8~0); 1260523#L1363-1 assume !(0 == ~E_9~0); 1260862#L1368-1 assume !(0 == ~E_10~0); 1259436#L1373-1 assume !(0 == ~E_11~0); 1259437#L1378-1 assume !(0 == ~E_12~0); 1259721#L1383-1 assume !(0 == ~E_13~0); 1259722#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1260526#L607 assume !(1 == ~m_pc~0); 1259796#L607-2 is_master_triggered_~__retres1~0#1 := 0; 1259797#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1260324#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1260325#L1560 assume !(0 != activate_threads_~tmp~1#1); 1260430#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1259605#L626 assume !(1 == ~t1_pc~0); 1259606#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1259893#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1259894#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1260844#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 1259510#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1259511#L645 assume !(1 == ~t2_pc~0); 1259577#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1259578#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1259687#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1259688#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 1260404#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1260405#L664 assume !(1 == ~t3_pc~0); 1260885#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1259375#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1259376#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1260044#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 1260045#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1261209#L683 assume !(1 == ~t4_pc~0); 1260653#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1260602#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1260603#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1261389#L1592 assume !(0 != activate_threads_~tmp___3~0#1); 1260780#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1260349#L702 assume 1 == ~t5_pc~0; 1260350#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1260281#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1260774#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1261189#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 1261061#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1259410#L721 assume !(1 == ~t6_pc~0); 1259388#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1259389#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1259533#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1259673#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 1260057#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1260710#L740 assume 1 == ~t7_pc~0; 1259452#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1259289#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1259290#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1259279#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 1259280#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1259982#L759 assume !(1 == ~t8_pc~0); 1259983#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1260013#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1261293#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1260933#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 1260934#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1261334#L778 assume 1 == ~t9_pc~0; 1261141#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1259435#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1259742#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1259314#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 1259315#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1259618#L797 assume !(1 == ~t10_pc~0); 1259619#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1259753#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1261109#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1260168#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 1260169#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1260478#L816 assume 1 == ~t11_pc~0; 1259351#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1259352#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1260312#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1260063#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 1260064#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1260631#L835 assume 1 == ~t12_pc~0; 1260493#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1259499#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1259339#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1259340#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 1260224#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1260225#L854 assume !(1 == ~t13_pc~0); 1259834#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 1259835#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1259888#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1259531#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1259532#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1261052#L1401 assume !(1 == ~M_E~0); 1260050#L1401-2 assume !(1 == ~T1_E~0); 1260051#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1260699#L1411-1 assume !(1 == ~T3_E~0); 1260700#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1260320#L1421-1 assume !(1 == ~T5_E~0); 1259830#L1426-1 assume !(1 == ~T6_E~0); 1259831#L1431-1 assume !(1 == ~T7_E~0); 1259386#L1436-1 assume !(1 == ~T8_E~0); 1259387#L1441-1 assume !(1 == ~T9_E~0); 1260160#L1446-1 assume !(1 == ~T10_E~0); 1260161#L1451-1 assume !(1 == ~T11_E~0); 1260949#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1260546#L1461-1 assume !(1 == ~T13_E~0); 1260080#L1466-1 assume !(1 == ~E_1~0); 1260081#L1471-1 assume !(1 == ~E_2~0); 1260931#L1476-1 assume !(1 == ~E_3~0); 1260932#L1481-1 assume !(1 == ~E_4~0); 1445340#L1486-1 assume !(1 == ~E_5~0); 1445338#L1491-1 assume !(1 == ~E_6~0); 1259324#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1259325#L1501-1 assume !(1 == ~E_8~0); 1260154#L1506-1 assume !(1 == ~E_9~0); 1260155#L1511-1 assume !(1 == ~E_10~0); 1260108#L1516-1 assume !(1 == ~E_11~0); 1259277#L1521-1 assume !(1 == ~E_12~0); 1259278#L1526-1 assume !(1 == ~E_13~0); 1259323#L1531-1 assume { :end_inline_reset_delta_events } true; 1259856#L1892-2 [2022-12-13 15:12:18,129 INFO L750 eck$LassoCheckResult]: Loop: 1259856#L1892-2 assume !false; 1260995#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1261289#L1233 assume !false; 1261249#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1260433#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1260411#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1261032#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1259365#L1046 assume !(0 != eval_~tmp~0#1); 1259367#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1467193#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1467191#L1258-3 assume !(0 == ~M_E~0); 1467189#L1258-5 assume !(0 == ~T1_E~0); 1467186#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1467184#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1467182#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1467180#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1467153#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1467152#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1467151#L1293-3 assume !(0 == ~T8_E~0); 1467150#L1298-3 assume !(0 == ~T9_E~0); 1467149#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1467148#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1467147#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1467146#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1467145#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1261106#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1261107#L1333-3 assume !(0 == ~E_3~0); 1261378#L1338-3 assume !(0 == ~E_4~0); 1466765#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1261315#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1261114#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1261115#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1260360#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1259891#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1259892#L1373-3 assume !(0 == ~E_11~0); 1260735#L1378-3 assume !(0 == ~E_12~0); 1260736#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1260946#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1260947#L607-42 assume !(1 == ~m_pc~0); 1260759#L607-44 is_master_triggered_~__retres1~0#1 := 0; 1260206#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1260037#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1259913#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1259914#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1260479#L626-42 assume !(1 == ~t1_pc~0); 1260007#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 1260006#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1261256#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1260962#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1259555#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1259556#L645-42 assume !(1 == ~t2_pc~0); 1260880#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1260881#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1260358#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1259778#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1259297#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1259298#L664-42 assume !(1 == ~t3_pc~0); 1259815#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 1259816#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1260805#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1260668#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1260669#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1260871#L683-42 assume 1 == ~t4_pc~0; 1261435#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1466490#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1466488#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1466486#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1466475#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1466472#L702-42 assume !(1 == ~t5_pc~0); 1466468#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 1466465#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1466463#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1466461#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1466438#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1466435#L721-42 assume !(1 == ~t6_pc~0); 1466428#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 1466426#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1466408#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1466405#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1466398#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1466391#L740-42 assume !(1 == ~t7_pc~0); 1466366#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 1466355#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1466333#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1466323#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 1466301#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1466284#L759-42 assume !(1 == ~t8_pc~0); 1466276#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 1466268#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1466263#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1466257#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1466252#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1466246#L778-42 assume !(1 == ~t9_pc~0); 1466167#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 1465316#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1261421#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1260531#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1260532#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1260595#L797-42 assume 1 == ~t10_pc~0; 1259691#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1259692#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1260616#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1260617#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1260637#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1260638#L816-42 assume !(1 == ~t11_pc~0); 1259271#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 1259270#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1261269#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1260165#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1259872#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1259873#L835-42 assume 1 == ~t12_pc~0; 1260309#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1260203#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1260400#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1260401#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1261059#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1260803#L854-42 assume 1 == ~t13_pc~0; 1260804#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1259789#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1259960#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1259961#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1260076#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1260077#L1401-3 assume !(1 == ~M_E~0); 1260941#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1259617#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1259494#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1259495#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1260125#L1421-3 assume !(1 == ~T5_E~0); 1260126#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1259662#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1259663#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1259809#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1260974#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1260966#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1260216#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1259838#L1461-3 assume !(1 == ~T13_E~0); 1259839#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1261354#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1261442#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1428832#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1467138#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1259807#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1259808#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1261260#L1501-3 assume !(1 == ~E_8~0); 1466919#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1466918#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1466917#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1440503#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1466916#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1466915#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1261449#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1259595#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1259641#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1259642#L1911 assume !(0 == start_simulation_~tmp~3#1); 1260182#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1260752#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1259733#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1259318#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1259319#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1259441#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1260213#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1261134#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 1259856#L1892-2 [2022-12-13 15:12:18,129 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:18,129 INFO L85 PathProgramCache]: Analyzing trace with hash 1040734579, now seen corresponding path program 1 times [2022-12-13 15:12:18,130 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:18,130 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1180246756] [2022-12-13 15:12:18,130 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:18,130 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:18,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:18,165 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:18,165 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:18,166 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1180246756] [2022-12-13 15:12:18,166 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1180246756] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:18,166 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:18,166 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 15:12:18,166 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [203134352] [2022-12-13 15:12:18,166 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:18,166 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:18,167 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:18,167 INFO L85 PathProgramCache]: Analyzing trace with hash 652933487, now seen corresponding path program 1 times [2022-12-13 15:12:18,167 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:18,167 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1973682332] [2022-12-13 15:12:18,167 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:18,167 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:18,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:18,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:18,206 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:18,207 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1973682332] [2022-12-13 15:12:18,207 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1973682332] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:18,207 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:18,207 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:18,207 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [738542699] [2022-12-13 15:12:18,207 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:18,207 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:18,208 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:18,208 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 15:12:18,208 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 15:12:18,208 INFO L87 Difference]: Start difference. First operand 207976 states and 298612 transitions. cyclomatic complexity: 90668 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:19,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:19,334 INFO L93 Difference]: Finished difference Result 399423 states and 571771 transitions. [2022-12-13 15:12:19,334 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 399423 states and 571771 transitions. [2022-12-13 15:12:20,938 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 398408 [2022-12-13 15:12:21,774 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 399423 states to 399423 states and 571771 transitions. [2022-12-13 15:12:21,775 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 399423 [2022-12-13 15:12:21,904 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 399423 [2022-12-13 15:12:21,904 INFO L73 IsDeterministic]: Start isDeterministic. Operand 399423 states and 571771 transitions. [2022-12-13 15:12:22,014 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:12:22,015 INFO L218 hiAutomatonCegarLoop]: Abstraction has 399423 states and 571771 transitions. [2022-12-13 15:12:22,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 399423 states and 571771 transitions. [2022-12-13 15:12:24,473 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 399423 to 399135. [2022-12-13 15:12:24,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 399135 states, 399135 states have (on average 1.4318037756648754) internal successors, (571483), 399134 states have internal predecessors, (571483), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:25,688 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399135 states to 399135 states and 571483 transitions. [2022-12-13 15:12:25,688 INFO L240 hiAutomatonCegarLoop]: Abstraction has 399135 states and 571483 transitions. [2022-12-13 15:12:25,689 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 15:12:25,689 INFO L428 stractBuchiCegarLoop]: Abstraction has 399135 states and 571483 transitions. [2022-12-13 15:12:25,689 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-12-13 15:12:25,689 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 399135 states and 571483 transitions. [2022-12-13 15:12:26,794 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 398120 [2022-12-13 15:12:26,794 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:26,794 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:26,796 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:26,796 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:26,796 INFO L748 eck$LassoCheckResult]: Stem: 1866946#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1866947#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1867868#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1867869#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1868789#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 1868323#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1868324#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1867172#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1867173#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1867664#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1867494#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1867495#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1867239#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1867240#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1867673#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1867858#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1868036#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1868075#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1867255#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1867256#L1258 assume !(0 == ~M_E~0); 1868600#L1258-2 assume !(0 == ~T1_E~0); 1867581#L1263-1 assume !(0 == ~T2_E~0); 1867582#L1268-1 assume !(0 == ~T3_E~0); 1867905#L1273-1 assume !(0 == ~T4_E~0); 1868572#L1278-1 assume !(0 == ~T5_E~0); 1868382#L1283-1 assume !(0 == ~T6_E~0); 1868383#L1288-1 assume !(0 == ~T7_E~0); 1868720#L1293-1 assume !(0 == ~T8_E~0); 1868703#L1298-1 assume !(0 == ~T9_E~0); 1868593#L1303-1 assume !(0 == ~T10_E~0); 1867048#L1308-1 assume !(0 == ~T11_E~0); 1866989#L1313-1 assume !(0 == ~T12_E~0); 1866990#L1318-1 assume !(0 == ~T13_E~0); 1866995#L1323-1 assume !(0 == ~E_1~0); 1866996#L1328-1 assume !(0 == ~E_2~0); 1867182#L1333-1 assume !(0 == ~E_3~0); 1868229#L1338-1 assume !(0 == ~E_4~0); 1868230#L1343-1 assume !(0 == ~E_5~0); 1868358#L1348-1 assume !(0 == ~E_6~0); 1868760#L1353-1 assume !(0 == ~E_7~0); 1867931#L1358-1 assume !(0 == ~E_8~0); 1867932#L1363-1 assume !(0 == ~E_9~0); 1868258#L1368-1 assume !(0 == ~E_10~0); 1866842#L1373-1 assume !(0 == ~E_11~0); 1866843#L1378-1 assume !(0 == ~E_12~0); 1867124#L1383-1 assume !(0 == ~E_13~0); 1867125#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1867935#L607 assume !(1 == ~m_pc~0); 1867199#L607-2 is_master_triggered_~__retres1~0#1 := 0; 1867200#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1867732#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1867733#L1560 assume !(0 != activate_threads_~tmp~1#1); 1867839#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1867010#L626 assume !(1 == ~t1_pc~0); 1867011#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1867297#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1867298#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1868240#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 1866914#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1866915#L645 assume !(1 == ~t2_pc~0); 1866982#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1866983#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1867091#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1867092#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 1867813#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1867814#L664 assume !(1 == ~t3_pc~0); 1868281#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1866777#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1866778#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1867451#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 1867452#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1868615#L683 assume !(1 == ~t4_pc~0); 1868058#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1868007#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1866801#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1866802#L1592 assume !(0 != activate_threads_~tmp___3~0#1); 1868181#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1867756#L702 assume !(1 == ~t5_pc~0); 1867688#L702-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1867689#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1868177#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1868596#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 1868467#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1866812#L721 assume !(1 == ~t6_pc~0); 1866794#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1866795#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1866938#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1867077#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 1867465#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1868112#L740 assume 1 == ~t7_pc~0; 1866858#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1866695#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1866696#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1866685#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 1866686#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1867386#L759 assume !(1 == ~t8_pc~0); 1867387#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1867419#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1868683#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1868333#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 1868334#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1868719#L778 assume 1 == ~t9_pc~0; 1868547#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1866841#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1867147#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1866720#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 1866721#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1867022#L797 assume !(1 == ~t10_pc~0); 1867023#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1867158#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1868519#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1867577#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 1867578#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1867885#L816 assume 1 == ~t11_pc~0; 1866755#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1866756#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1867721#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1867471#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 1867472#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1868035#L835 assume 1 == ~t12_pc~0; 1867900#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1866905#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1866745#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1866746#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 1867634#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1867635#L854 assume !(1 == ~t13_pc~0); 1867241#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 1867242#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1867292#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1866936#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1866937#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1868459#L1401 assume !(1 == ~M_E~0); 1867457#L1401-2 assume !(1 == ~T1_E~0); 1867458#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1868102#L1411-1 assume !(1 == ~T3_E~0); 1868103#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1867731#L1421-1 assume !(1 == ~T5_E~0); 1867237#L1426-1 assume !(1 == ~T6_E~0); 1867238#L1431-1 assume !(1 == ~T7_E~0); 1866792#L1436-1 assume !(1 == ~T8_E~0); 1866793#L1441-1 assume !(1 == ~T9_E~0); 1867567#L1446-1 assume !(1 == ~T10_E~0); 1867568#L1451-1 assume !(1 == ~T11_E~0); 1868355#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1867954#L1461-1 assume !(1 == ~T13_E~0); 1867488#L1466-1 assume !(1 == ~E_1~0); 1867489#L1471-1 assume !(1 == ~E_2~0); 1868331#L1476-1 assume !(1 == ~E_3~0); 1868332#L1481-1 assume !(1 == ~E_4~0); 1868527#L1486-1 assume !(1 == ~E_5~0); 1867061#L1491-1 assume !(1 == ~E_6~0); 1866730#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1866731#L1501-1 assume !(1 == ~E_8~0); 1867563#L1506-1 assume !(1 == ~E_9~0); 1867564#L1511-1 assume !(1 == ~E_10~0); 1867516#L1516-1 assume !(1 == ~E_11~0); 1867517#L1521-1 assume !(1 == ~E_12~0); 2014987#L1526-1 assume !(1 == ~E_13~0); 2014985#L1531-1 assume { :end_inline_reset_delta_events } true; 2014981#L1892-2 [2022-12-13 15:12:26,796 INFO L750 eck$LassoCheckResult]: Loop: 2014981#L1892-2 assume !false; 2013560#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2013558#L1233 assume !false; 2013556#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1936330#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1936328#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1936327#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1936325#L1046 assume !(0 != eval_~tmp~0#1); 1936326#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2015376#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2015374#L1258-3 assume !(0 == ~M_E~0); 2015370#L1258-5 assume !(0 == ~T1_E~0); 2015368#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2015366#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2015364#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2015362#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2015360#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2015358#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2015356#L1293-3 assume !(0 == ~T8_E~0); 2015354#L1298-3 assume !(0 == ~T9_E~0); 2015353#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 2015351#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 2015349#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 2015348#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 2015347#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2015346#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2015345#L1333-3 assume !(0 == ~E_3~0); 2015344#L1338-3 assume !(0 == ~E_4~0); 2015343#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2015342#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2015341#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2015340#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2015339#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2015338#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 2015323#L1373-3 assume !(0 == ~E_11~0); 2015321#L1378-3 assume !(0 == ~E_12~0); 2015319#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 2015316#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2015315#L607-42 assume !(1 == ~m_pc~0); 2015313#L607-44 is_master_triggered_~__retres1~0#1 := 0; 2015311#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2015309#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2015307#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2015305#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2015303#L626-42 assume 1 == ~t1_pc~0; 2015300#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2015297#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2015295#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2015293#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2015291#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2015289#L645-42 assume !(1 == ~t2_pc~0); 2015287#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 2015285#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2015283#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2015281#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2015279#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2015277#L664-42 assume !(1 == ~t3_pc~0); 2015275#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 2015273#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2015271#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2015269#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2015267#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2015254#L683-42 assume 1 == ~t4_pc~0; 2015255#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2015256#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2015456#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2015245#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2015243#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2015241#L702-42 assume !(1 == ~t5_pc~0); 2015239#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 2015237#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2015234#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2015232#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2015230#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2015228#L721-42 assume 1 == ~t6_pc~0; 2015226#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2015223#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2015220#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2015218#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2015216#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2015214#L740-42 assume !(1 == ~t7_pc~0); 2015212#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 2015209#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2015206#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2015204#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 2015202#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2015200#L759-42 assume !(1 == ~t8_pc~0); 2015198#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 2015195#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2015192#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2015190#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2015188#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2015186#L778-42 assume !(1 == ~t9_pc~0); 2015183#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 2015181#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2015178#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2015176#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2015174#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2015172#L797-42 assume !(1 == ~t10_pc~0); 2015170#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 2015167#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2015164#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 2015162#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2015160#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2015158#L816-42 assume 1 == ~t11_pc~0; 2015156#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 2015153#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2015150#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 2015148#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2015146#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 2015144#L835-42 assume !(1 == ~t12_pc~0); 2015142#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 2015139#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 2015136#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 2015134#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 2015132#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 2015130#L854-42 assume 1 == ~t13_pc~0; 2015128#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 2015124#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 2015122#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 2015118#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 2015117#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2015115#L1401-3 assume !(1 == ~M_E~0); 2015111#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2015109#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1974081#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2015102#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2015100#L1421-3 assume !(1 == ~T5_E~0); 2015098#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2015096#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2015094#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2015090#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2015088#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2015086#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 2015082#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 2015080#L1461-3 assume !(1 == ~T13_E~0); 2015078#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2015076#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2015074#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2015070#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2015068#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2015066#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2015064#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2015063#L1501-3 assume !(1 == ~E_8~0); 2015061#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2015060#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2015059#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1998175#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 2015058#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 2015056#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 2015032#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 2015026#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 2015024#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 2015021#L1911 assume !(0 == start_simulation_~tmp~3#1); 2015018#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 2015016#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 2015001#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 2014999#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 2014997#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2014995#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2014993#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 2014984#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 2014981#L1892-2 [2022-12-13 15:12:26,797 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:26,797 INFO L85 PathProgramCache]: Analyzing trace with hash -944094126, now seen corresponding path program 1 times [2022-12-13 15:12:26,797 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:26,797 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [879569021] [2022-12-13 15:12:26,797 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:26,797 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:26,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:26,842 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:26,842 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:26,842 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [879569021] [2022-12-13 15:12:26,842 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [879569021] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:26,842 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:26,842 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:26,842 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1019984145] [2022-12-13 15:12:26,842 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:26,842 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:26,843 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:26,843 INFO L85 PathProgramCache]: Analyzing trace with hash 1472991824, now seen corresponding path program 1 times [2022-12-13 15:12:26,843 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:26,843 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [962836989] [2022-12-13 15:12:26,843 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:26,843 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:26,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:26,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:26,869 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:26,869 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [962836989] [2022-12-13 15:12:26,869 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [962836989] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:26,870 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:26,870 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:26,870 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1275135847] [2022-12-13 15:12:26,870 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:26,870 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:26,870 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:26,870 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 15:12:26,870 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 15:12:26,870 INFO L87 Difference]: Start difference. First operand 399135 states and 571483 transitions. cyclomatic complexity: 172412 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:29,970 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:29,970 INFO L93 Difference]: Finished difference Result 1144622 states and 1630592 transitions. [2022-12-13 15:12:29,970 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1144622 states and 1630592 transitions. [2022-12-13 15:12:34,016 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 1127544 [2022-12-13 15:12:36,268 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1144622 states to 1144622 states and 1630592 transitions. [2022-12-13 15:12:36,268 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1144622 [2022-12-13 15:12:36,773 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1144622 [2022-12-13 15:12:36,774 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1144622 states and 1630592 transitions. [2022-12-13 15:12:37,039 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 15:12:37,039 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1144622 states and 1630592 transitions. [2022-12-13 15:12:37,453 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1144622 states and 1630592 transitions. [2022-12-13 15:12:44,950 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1144622 to 1115374. [2022-12-13 15:12:45,396 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1115374 states, 1115374 states have (on average 1.426348471454418) internal successors, (1590912), 1115373 states have internal predecessors, (1590912), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:47,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1115374 states to 1115374 states and 1590912 transitions. [2022-12-13 15:12:47,638 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1115374 states and 1590912 transitions. [2022-12-13 15:12:47,639 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 15:12:47,639 INFO L428 stractBuchiCegarLoop]: Abstraction has 1115374 states and 1590912 transitions. [2022-12-13 15:12:47,639 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-12-13 15:12:47,639 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1115374 states and 1590912 transitions. [2022-12-13 15:12:49,941 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 1113144 [2022-12-13 15:12:49,942 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 15:12:49,942 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 15:12:49,943 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:49,943 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 15:12:49,943 INFO L748 eck$LassoCheckResult]: Stem: 3410708#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 3410709#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 3411672#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3411673#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3412782#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 3412186#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3412187#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3410939#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3410940#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3411443#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3411267#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3411268#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3411006#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3411007#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3411453#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3411661#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 3411850#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 3411893#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 3411022#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3411023#L1258 assume !(0 == ~M_E~0); 3412510#L1258-2 assume !(0 == ~T1_E~0); 3411356#L1263-1 assume !(0 == ~T2_E~0); 3411357#L1268-1 assume !(0 == ~T3_E~0); 3411714#L1273-1 assume !(0 == ~T4_E~0); 3412479#L1278-1 assume !(0 == ~T5_E~0); 3412263#L1283-1 assume !(0 == ~T6_E~0); 3412264#L1288-1 assume !(0 == ~T7_E~0); 3412649#L1293-1 assume !(0 == ~T8_E~0); 3412623#L1298-1 assume !(0 == ~T9_E~0); 3412503#L1303-1 assume !(0 == ~T10_E~0); 3410811#L1308-1 assume !(0 == ~T11_E~0); 3410751#L1313-1 assume !(0 == ~T12_E~0); 3410752#L1318-1 assume !(0 == ~T13_E~0); 3410758#L1323-1 assume !(0 == ~E_1~0); 3410759#L1328-1 assume !(0 == ~E_2~0); 3410949#L1333-1 assume !(0 == ~E_3~0); 3412074#L1338-1 assume !(0 == ~E_4~0); 3412075#L1343-1 assume !(0 == ~E_5~0); 3412226#L1348-1 assume !(0 == ~E_6~0); 3412718#L1353-1 assume !(0 == ~E_7~0); 3411737#L1358-1 assume !(0 == ~E_8~0); 3411738#L1363-1 assume !(0 == ~E_9~0); 3412108#L1368-1 assume !(0 == ~E_10~0); 3410606#L1373-1 assume !(0 == ~E_11~0); 3410607#L1378-1 assume !(0 == ~E_12~0); 3410888#L1383-1 assume !(0 == ~E_13~0); 3410889#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3411741#L607 assume !(1 == ~m_pc~0); 3410967#L607-2 is_master_triggered_~__retres1~0#1 := 0; 3410968#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3411514#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3411515#L1560 assume !(0 != activate_threads_~tmp~1#1); 3411634#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3410773#L626 assume !(1 == ~t1_pc~0); 3410774#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3411064#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3411065#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3412085#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 3410676#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3410677#L645 assume !(1 == ~t2_pc~0); 3410744#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3410745#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3410856#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3410857#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 3411607#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3411608#L664 assume !(1 == ~t3_pc~0); 3412141#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3410542#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3410543#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3411226#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 3411227#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3412528#L683 assume !(1 == ~t4_pc~0); 3411876#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3412087#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3410566#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3410567#L1592 assume !(0 != activate_threads_~tmp___3~0#1); 3412015#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3411539#L702 assume !(1 == ~t5_pc~0); 3411468#L702-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3411469#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3412010#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3412507#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 3412355#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3410577#L721 assume !(1 == ~t6_pc~0); 3410559#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3410560#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3410700#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3410842#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 3411239#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3411935#L740 assume !(1 == ~t7_pc~0); 3411936#L740-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3410462#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3410463#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3410452#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 3410453#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3411159#L759 assume !(1 == ~t8_pc~0); 3411160#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3411195#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3412605#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3412196#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 3412197#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3412648#L778 assume 1 == ~t9_pc~0; 3412455#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3410605#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3410913#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3410485#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 3410486#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3410785#L797 assume !(1 == ~t10_pc~0); 3410786#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3410925#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3412423#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3411352#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 3411353#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3411692#L816 assume 1 == ~t11_pc~0; 3410520#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3410521#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3411503#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3411245#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 3411246#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 3411849#L835 assume 1 == ~t12_pc~0; 3411708#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 3410667#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3410510#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3410511#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 3411409#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 3411410#L854 assume !(1 == ~t13_pc~0); 3411008#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 3411009#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 3411059#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3410698#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 3410699#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3412349#L1401 assume !(1 == ~M_E~0); 3411232#L1401-2 assume !(1 == ~T1_E~0); 3411233#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3411925#L1411-1 assume !(1 == ~T3_E~0); 3411926#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3411513#L1421-1 assume !(1 == ~T5_E~0); 3411004#L1426-1 assume !(1 == ~T6_E~0); 3411005#L1431-1 assume !(1 == ~T7_E~0); 3410557#L1436-1 assume !(1 == ~T8_E~0); 3410558#L1441-1 assume !(1 == ~T9_E~0); 3411343#L1446-1 assume !(1 == ~T10_E~0); 3411344#L1451-1 assume !(1 == ~T11_E~0); 3412223#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 3411766#L1461-1 assume !(1 == ~T13_E~0); 3411261#L1466-1 assume !(1 == ~E_1~0); 3411262#L1471-1 assume !(1 == ~E_2~0); 3412194#L1476-1 assume !(1 == ~E_3~0); 3412195#L1481-1 assume !(1 == ~E_4~0); 3412430#L1486-1 assume !(1 == ~E_5~0); 3410824#L1491-1 assume !(1 == ~E_6~0); 3410495#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 3410496#L1501-1 assume !(1 == ~E_8~0); 3411339#L1506-1 assume !(1 == ~E_9~0); 3411340#L1511-1 assume !(1 == ~E_10~0); 3411291#L1516-1 assume !(1 == ~E_11~0); 3410450#L1521-1 assume !(1 == ~E_12~0); 3410451#L1526-1 assume !(1 == ~E_13~0); 3410494#L1531-1 assume { :end_inline_reset_delta_events } true; 3411030#L1892-2 [2022-12-13 15:12:49,943 INFO L750 eck$LassoCheckResult]: Loop: 3411030#L1892-2 assume !false; 4095173#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4095171#L1233 assume !false; 4095169#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4095134#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4095132#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4095130#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4095127#L1046 assume !(0 != eval_~tmp~0#1); 4095125#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4095122#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4095120#L1258-3 assume !(0 == ~M_E~0); 4095118#L1258-5 assume !(0 == ~T1_E~0); 4095116#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4095114#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4095112#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4095110#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4095108#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4095106#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4095104#L1293-3 assume !(0 == ~T8_E~0); 4095102#L1298-3 assume !(0 == ~T9_E~0); 4095100#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4095097#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4095095#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4095093#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4095091#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4095089#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4095087#L1333-3 assume !(0 == ~E_3~0); 4095084#L1338-3 assume !(0 == ~E_4~0); 4095082#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4095080#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4095078#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4095076#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4095074#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4095071#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4095069#L1373-3 assume !(0 == ~E_11~0); 4095067#L1378-3 assume !(0 == ~E_12~0); 4095065#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 4095063#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4095061#L607-42 assume !(1 == ~m_pc~0); 4095058#L607-44 is_master_triggered_~__retres1~0#1 := 0; 4095056#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4095054#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4095052#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4095050#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4095048#L626-42 assume 1 == ~t1_pc~0; 4095044#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4095042#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4095040#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4095038#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4095036#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4095034#L645-42 assume !(1 == ~t2_pc~0); 4095031#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 4095029#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4095027#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4095025#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4095023#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4095022#L664-42 assume !(1 == ~t3_pc~0); 4095021#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 4095020#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4095019#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4095018#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4095017#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4095016#L683-42 assume !(1 == ~t4_pc~0); 4095014#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 4095012#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4095010#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4095009#L1592-42 assume !(0 != activate_threads_~tmp___3~0#1); 4095007#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4095006#L702-42 assume !(1 == ~t5_pc~0); 4095005#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 4095004#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4095003#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4095002#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4095001#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4095000#L721-42 assume !(1 == ~t6_pc~0); 4094998#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 4094997#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4094996#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4094995#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4094994#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4094993#L740-42 assume !(1 == ~t7_pc~0); 4094992#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 4094991#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4094990#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4094989#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 4094988#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4094987#L759-42 assume !(1 == ~t8_pc~0); 4094986#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 4094983#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4094981#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4094980#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4094979#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4094978#L778-42 assume !(1 == ~t9_pc~0); 4094976#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 4094975#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4094974#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4094973#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4094971#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4094970#L797-42 assume 1 == ~t10_pc~0; 4094968#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4094967#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4094966#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4094965#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4094964#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4094963#L816-42 assume 1 == ~t11_pc~0; 4094962#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4094960#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4094958#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4094956#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4094954#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4094952#L835-42 assume !(1 == ~t12_pc~0); 4094950#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 4094947#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4094945#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4094943#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4094941#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4094939#L854-42 assume !(1 == ~t13_pc~0); 4094936#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 4094934#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4094932#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4094930#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4094928#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4094926#L1401-3 assume !(1 == ~M_E~0); 4094718#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4094923#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3809682#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4094920#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4094918#L1421-3 assume !(1 == ~T5_E~0); 4094916#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4094914#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4094912#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4013710#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4094909#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4094907#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4094905#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4094903#L1461-3 assume !(1 == ~T13_E~0); 4094901#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4094899#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4094897#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4092681#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4094894#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4094892#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4094890#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4094887#L1501-3 assume !(1 == ~E_8~0); 4094885#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4094883#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4094881#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4052894#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4094878#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 4094876#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4094852#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4094846#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4094844#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4094840#L1911 assume !(0 == start_simulation_~tmp~3#1); 4094841#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4096051#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4096037#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4096036#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 4096035#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4096034#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4096033#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 4096031#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 3411030#L1892-2 [2022-12-13 15:12:49,944 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:49,944 INFO L85 PathProgramCache]: Analyzing trace with hash -37337679, now seen corresponding path program 1 times [2022-12-13 15:12:49,944 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:49,944 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1575822840] [2022-12-13 15:12:49,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:49,945 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:49,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:50,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:50,011 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:50,011 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1575822840] [2022-12-13 15:12:50,011 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1575822840] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:50,011 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:50,011 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:50,012 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1080832073] [2022-12-13 15:12:50,012 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:50,012 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 15:12:50,012 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 15:12:50,012 INFO L85 PathProgramCache]: Analyzing trace with hash -1397525364, now seen corresponding path program 1 times [2022-12-13 15:12:50,013 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 15:12:50,013 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1214536737] [2022-12-13 15:12:50,013 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 15:12:50,013 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 15:12:50,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 15:12:50,056 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 15:12:50,056 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 15:12:50,056 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1214536737] [2022-12-13 15:12:50,056 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1214536737] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 15:12:50,056 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 15:12:50,056 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 15:12:50,056 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [873355544] [2022-12-13 15:12:50,056 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 15:12:50,057 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 15:12:50,057 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 15:12:50,057 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 15:12:50,057 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 15:12:50,057 INFO L87 Difference]: Start difference. First operand 1115374 states and 1590912 transitions. cyclomatic complexity: 475666 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 15:12:58,644 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 15:12:58,645 INFO L93 Difference]: Finished difference Result 3181181 states and 4518021 transitions. [2022-12-13 15:12:58,645 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3181181 states and 4518021 transitions.