./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.15.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08bc3c25-ee1c-40e2-8340-8325d3c067d5/bin/uautomizer-uyxdKDjOR8/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08bc3c25-ee1c-40e2-8340-8325d3c067d5/bin/uautomizer-uyxdKDjOR8/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08bc3c25-ee1c-40e2-8340-8325d3c067d5/bin/uautomizer-uyxdKDjOR8/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08bc3c25-ee1c-40e2-8340-8325d3c067d5/bin/uautomizer-uyxdKDjOR8/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.15.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08bc3c25-ee1c-40e2-8340-8325d3c067d5/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08bc3c25-ee1c-40e2-8340-8325d3c067d5/bin/uautomizer-uyxdKDjOR8 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 05397c7941b2acd95b1b6d02c6c64b476ab8b290a5b56301ff8db7ca1986067b --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-13 12:58:04,827 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-13 12:58:04,829 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-13 12:58:04,847 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-13 12:58:04,848 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-13 12:58:04,849 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-13 12:58:04,850 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-13 12:58:04,851 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-13 12:58:04,853 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-13 12:58:04,854 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-13 12:58:04,854 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-13 12:58:04,855 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-13 12:58:04,856 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-13 12:58:04,857 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-13 12:58:04,858 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-13 12:58:04,859 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-13 12:58:04,859 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-13 12:58:04,860 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-13 12:58:04,862 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-13 12:58:04,863 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-13 12:58:04,864 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-13 12:58:04,866 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-13 12:58:04,867 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-13 12:58:04,867 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-13 12:58:04,870 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-13 12:58:04,871 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-13 12:58:04,871 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-13 12:58:04,872 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-13 12:58:04,872 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-13 12:58:04,873 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-13 12:58:04,873 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-13 12:58:04,874 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-13 12:58:04,875 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-13 12:58:04,875 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-13 12:58:04,876 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-13 12:58:04,876 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-13 12:58:04,877 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-13 12:58:04,877 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-13 12:58:04,877 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-13 12:58:04,878 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-13 12:58:04,878 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-13 12:58:04,879 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08bc3c25-ee1c-40e2-8340-8325d3c067d5/bin/uautomizer-uyxdKDjOR8/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-12-13 12:58:04,899 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-13 12:58:04,899 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-13 12:58:04,900 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-13 12:58:04,900 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-13 12:58:04,901 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-13 12:58:04,901 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-13 12:58:04,901 INFO L138 SettingsManager]: * Use SBE=true [2022-12-13 12:58:04,902 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-12-13 12:58:04,902 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-12-13 12:58:04,902 INFO L138 SettingsManager]: * Use old map elimination=false [2022-12-13 12:58:04,902 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-12-13 12:58:04,902 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-12-13 12:58:04,902 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-12-13 12:58:04,903 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-13 12:58:04,903 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-13 12:58:04,903 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-12-13 12:58:04,903 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-13 12:58:04,903 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-13 12:58:04,903 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-13 12:58:04,904 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-12-13 12:58:04,904 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-12-13 12:58:04,904 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-12-13 12:58:04,904 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-13 12:58:04,904 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-13 12:58:04,904 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-12-13 12:58:04,904 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-13 12:58:04,905 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-12-13 12:58:04,905 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-13 12:58:04,905 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-12-13 12:58:04,905 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-13 12:58:04,905 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-12-13 12:58:04,906 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-12-13 12:58:04,906 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08bc3c25-ee1c-40e2-8340-8325d3c067d5/bin/uautomizer-uyxdKDjOR8/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08bc3c25-ee1c-40e2-8340-8325d3c067d5/bin/uautomizer-uyxdKDjOR8 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 05397c7941b2acd95b1b6d02c6c64b476ab8b290a5b56301ff8db7ca1986067b [2022-12-13 12:58:05,117 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-13 12:58:05,136 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-13 12:58:05,138 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-13 12:58:05,139 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-13 12:58:05,139 INFO L275 PluginConnector]: CDTParser initialized [2022-12-13 12:58:05,140 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08bc3c25-ee1c-40e2-8340-8325d3c067d5/bin/uautomizer-uyxdKDjOR8/../../sv-benchmarks/c/systemc/transmitter.15.cil.c [2022-12-13 12:58:07,658 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-13 12:58:07,828 INFO L351 CDTParser]: Found 1 translation units. [2022-12-13 12:58:07,829 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08bc3c25-ee1c-40e2-8340-8325d3c067d5/sv-benchmarks/c/systemc/transmitter.15.cil.c [2022-12-13 12:58:07,837 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08bc3c25-ee1c-40e2-8340-8325d3c067d5/bin/uautomizer-uyxdKDjOR8/data/7928deefd/f9a8906dd1bc4cf18102c1e0bed522cf/FLAGb2dbb9291 [2022-12-13 12:58:08,239 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08bc3c25-ee1c-40e2-8340-8325d3c067d5/bin/uautomizer-uyxdKDjOR8/data/7928deefd/f9a8906dd1bc4cf18102c1e0bed522cf [2022-12-13 12:58:08,243 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-13 12:58:08,246 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-13 12:58:08,248 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-13 12:58:08,248 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-13 12:58:08,254 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-13 12:58:08,255 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 12:58:08" (1/1) ... [2022-12-13 12:58:08,256 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@376beb8f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:58:08, skipping insertion in model container [2022-12-13 12:58:08,256 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.12 12:58:08" (1/1) ... [2022-12-13 12:58:08,264 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-13 12:58:08,295 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-13 12:58:08,390 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08bc3c25-ee1c-40e2-8340-8325d3c067d5/sv-benchmarks/c/systemc/transmitter.15.cil.c[706,719] [2022-12-13 12:58:08,473 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 12:58:08,484 INFO L203 MainTranslator]: Completed pre-run [2022-12-13 12:58:08,492 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08bc3c25-ee1c-40e2-8340-8325d3c067d5/sv-benchmarks/c/systemc/transmitter.15.cil.c[706,719] [2022-12-13 12:58:08,536 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-13 12:58:08,550 INFO L208 MainTranslator]: Completed translation [2022-12-13 12:58:08,550 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:58:08 WrapperNode [2022-12-13 12:58:08,550 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-13 12:58:08,551 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-13 12:58:08,551 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-13 12:58:08,551 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-13 12:58:08,557 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:58:08" (1/1) ... [2022-12-13 12:58:08,565 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:58:08" (1/1) ... [2022-12-13 12:58:08,633 INFO L138 Inliner]: procedures = 54, calls = 69, calls flagged for inlining = 64, calls inlined = 286, statements flattened = 4413 [2022-12-13 12:58:08,633 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-13 12:58:08,634 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-13 12:58:08,634 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-13 12:58:08,634 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-13 12:58:08,641 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:58:08" (1/1) ... [2022-12-13 12:58:08,641 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:58:08" (1/1) ... [2022-12-13 12:58:08,648 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:58:08" (1/1) ... [2022-12-13 12:58:08,649 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:58:08" (1/1) ... [2022-12-13 12:58:08,675 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:58:08" (1/1) ... [2022-12-13 12:58:08,718 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:58:08" (1/1) ... [2022-12-13 12:58:08,725 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:58:08" (1/1) ... [2022-12-13 12:58:08,735 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:58:08" (1/1) ... [2022-12-13 12:58:08,760 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-13 12:58:08,761 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-13 12:58:08,761 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-13 12:58:08,761 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-13 12:58:08,762 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:58:08" (1/1) ... [2022-12-13 12:58:08,768 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-12-13 12:58:08,778 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08bc3c25-ee1c-40e2-8340-8325d3c067d5/bin/uautomizer-uyxdKDjOR8/z3 [2022-12-13 12:58:08,789 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08bc3c25-ee1c-40e2-8340-8325d3c067d5/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-12-13 12:58:08,792 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08bc3c25-ee1c-40e2-8340-8325d3c067d5/bin/uautomizer-uyxdKDjOR8/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-12-13 12:58:08,826 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-13 12:58:08,826 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-13 12:58:08,826 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-13 12:58:08,827 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-13 12:58:08,920 INFO L235 CfgBuilder]: Building ICFG [2022-12-13 12:58:08,922 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-13 12:58:10,449 INFO L276 CfgBuilder]: Performing block encoding [2022-12-13 12:58:10,467 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-13 12:58:10,467 INFO L300 CfgBuilder]: Removed 17 assume(true) statements. [2022-12-13 12:58:10,470 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 12:58:10 BoogieIcfgContainer [2022-12-13 12:58:10,470 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-13 12:58:10,471 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-12-13 12:58:10,471 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-12-13 12:58:10,474 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-12-13 12:58:10,474 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 12:58:10,474 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.12 12:58:08" (1/3) ... [2022-12-13 12:58:10,475 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6b15ceb3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 12:58:10, skipping insertion in model container [2022-12-13 12:58:10,475 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 12:58:10,475 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.12 12:58:08" (2/3) ... [2022-12-13 12:58:10,475 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6b15ceb3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.12 12:58:10, skipping insertion in model container [2022-12-13 12:58:10,476 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-12-13 12:58:10,476 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.12 12:58:10" (3/3) ... [2022-12-13 12:58:10,477 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.15.cil.c [2022-12-13 12:58:10,546 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-12-13 12:58:10,546 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-12-13 12:58:10,546 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-12-13 12:58:10,546 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-12-13 12:58:10,546 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-12-13 12:58:10,546 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-12-13 12:58:10,546 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-12-13 12:58:10,546 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-12-13 12:58:10,556 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1920 states, 1919 states have (on average 1.498697238144867) internal successors, (2876), 1919 states have internal predecessors, (2876), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:10,617 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1743 [2022-12-13 12:58:10,618 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:58:10,618 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:58:10,631 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:10,631 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:10,631 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-12-13 12:58:10,634 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1920 states, 1919 states have (on average 1.498697238144867) internal successors, (2876), 1919 states have internal predecessors, (2876), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:10,647 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1743 [2022-12-13 12:58:10,647 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:58:10,647 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:58:10,652 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:10,652 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:10,660 INFO L748 eck$LassoCheckResult]: Stem: 143#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1836#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 678#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1832#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1757#L881true assume !(1 == ~m_i~0);~m_st~0 := 2; 1054#L881-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1394#L886-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 259#L891-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1387#L896-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 535#L901-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 433#L906-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 786#L911-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 291#L916-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 542#L921-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 670#L926-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 795#L931-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 822#L936-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 903#L941-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 300#L946-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1815#L1258true assume 0 == ~M_E~0;~M_E~0 := 1; 1384#L1258-2true assume !(0 == ~T1_E~0); 483#L1263-1true assume !(0 == ~T2_E~0); 703#L1268-1true assume !(0 == ~T3_E~0); 1351#L1273-1true assume !(0 == ~T4_E~0); 1747#L1278-1true assume !(0 == ~T5_E~0); 1132#L1283-1true assume !(0 == ~T6_E~0); 1781#L1288-1true assume !(0 == ~T7_E~0); 1554#L1293-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1523#L1298-1true assume !(0 == ~T9_E~0); 1371#L1303-1true assume !(0 == ~T10_E~0); 194#L1308-1true assume !(0 == ~T11_E~0); 163#L1313-1true assume !(0 == ~T12_E~0); 1840#L1318-1true assume !(0 == ~T13_E~0); 166#L1323-1true assume !(0 == ~E_1~0); 264#L1328-1true assume !(0 == ~E_2~0); 1791#L1333-1true assume 0 == ~E_3~0;~E_3~0 := 1; 956#L1338-1true assume !(0 == ~E_4~0); 1092#L1343-1true assume !(0 == ~E_5~0); 1643#L1348-1true assume !(0 == ~E_6~0); 1659#L1353-1true assume !(0 == ~E_7~0); 719#L1358-1true assume !(0 == ~E_8~0); 985#L1363-1true assume !(0 == ~E_9~0); 1045#L1368-1true assume !(0 == ~E_10~0); 90#L1373-1true assume 0 == ~E_11~0;~E_11~0 := 1; 482#L1378-1true assume !(0 == ~E_12~0); 234#L1383-1true assume !(0 == ~E_13~0); 1081#L1388-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 721#L607true assume 1 == ~m_pc~0; 993#L608true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1088#L618true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 579#is_master_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 653#L1560true assume !(0 != activate_threads_~tmp~1#1); 1725#L1560-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 174#L626true assume !(1 == ~t1_pc~0); 1252#L626-2true is_transmit1_triggered_~__retres1~1#1 := 0; 323#L637true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 968#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1909#L1568true assume !(0 != activate_threads_~tmp___0~0#1); 126#L1568-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1321#L645true assume 1 == ~t2_pc~0; 183#L646true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1285#L656true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 219#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1901#L1576true assume !(0 != activate_threads_~tmp___1~0#1); 638#L1576-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1706#L664true assume 1 == ~t3_pc~0; 1624#L665true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 56#L675true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 946#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 409#L1584true assume !(0 != activate_threads_~tmp___2~0#1); 1402#L1584-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1617#L683true assume !(1 == ~t4_pc~0); 970#L683-2true is_transmit4_triggered_~__retres1~4#1 := 0; 773#L694true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1692#L1592true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 913#L1592-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 595#L702true assume 1 == ~t5_pc~0; 1681#L703true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 906#L713true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1551#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1377#L1600true assume !(0 != activate_threads_~tmp___4~0#1); 1221#L1600-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 73#L721true assume !(1 == ~t6_pc~0); 64#L721-2true is_transmit6_triggered_~__retres1~6#1 := 0; 139#L732true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 212#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 416#L1608true assume !(0 != activate_threads_~tmp___5~0#1); 1506#L1608-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 851#L740true assume 1 == ~t7_pc~0; 99#L741true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17#L751true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1855#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12#L1616true assume !(0 != activate_threads_~tmp___6~0#1); 753#L1616-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 374#L759true assume !(1 == ~t8_pc~0); 1362#L759-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1844#L770true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1497#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1061#L1624true assume !(0 != activate_threads_~tmp___7~0#1); 1665#L1624-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1552#L778true assume 1 == ~t9_pc~0; 1326#L779true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1258#L789true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 245#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28#L1632true assume !(0 != activate_threads_~tmp___8~0#1); 725#L1632-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 181#L797true assume !(1 == ~t10_pc~0); 251#L797-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1292#L808true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1291#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 480#L1640true assume !(0 != activate_threads_~tmp___9~0#1); 688#L1640-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1376#L816true assume 1 == ~t11_pc~0; 46#L817true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 572#L827true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1414#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 420#L1648true assume !(0 != activate_threads_~tmp___10~0#1); 1492#L1648-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 794#L835true assume 1 == ~t12_pc~0; 698#L836true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 130#L846true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 41#is_transmit12_triggered_returnLabel#1true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1785#L1656true assume !(0 != activate_threads_~tmp___11~0#1); 516#L1656-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1426#L854true assume !(1 == ~t13_pc~0); 292#L854-2true is_transmit13_triggered_~__retres1~13#1 := 0; 320#L865true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1347#is_transmit13_triggered_returnLabel#1true activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 138#L1664true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1213#L1664-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1792#L1401true assume !(1 == ~M_E~0); 412#L1401-2true assume !(1 == ~T1_E~0); 1224#L1406-1true assume !(1 == ~T2_E~0); 843#L1411-1true assume !(1 == ~T3_E~0); 1601#L1416-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 578#L1421-1true assume !(1 == ~T5_E~0); 290#L1426-1true assume !(1 == ~T6_E~0); 999#L1431-1true assume !(1 == ~T7_E~0); 63#L1436-1true assume !(1 == ~T8_E~0); 738#L1441-1true assume !(1 == ~T9_E~0); 475#L1446-1true assume !(1 == ~T10_E~0); 1771#L1451-1true assume !(1 == ~T11_E~0); 1087#L1456-1true assume 1 == ~T12_E~0;~T12_E~0 := 2; 736#L1461-1true assume !(1 == ~T13_E~0); 430#L1466-1true assume !(1 == ~E_1~0); 1764#L1471-1true assume !(1 == ~E_2~0); 1060#L1476-1true assume !(1 == ~E_3~0); 1298#L1481-1true assume !(1 == ~E_4~0); 1581#L1486-1true assume !(1 == ~E_5~0); 202#L1491-1true assume !(1 == ~E_6~0); 34#L1496-1true assume 1 == ~E_7~0;~E_7~0 := 2; 749#L1501-1true assume !(1 == ~E_8~0); 472#L1506-1true assume !(1 == ~E_9~0); 1021#L1511-1true assume !(1 == ~E_10~0); 445#L1516-1true assume !(1 == ~E_11~0); 11#L1521-1true assume !(1 == ~E_12~0); 33#L1526-1true assume !(1 == ~E_13~0); 304#L1531-1true assume { :end_inline_reset_delta_events } true; 1151#L1892-2true [2022-12-13 12:58:10,669 INFO L750 eck$LassoCheckResult]: Loop: 1151#L1892-2true assume !false; 1866#L1893true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1494#L1233true assume !true; 534#eval_returnLabel#1true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 329#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1620#L1258-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1900#L1258-5true assume !(0 == ~T1_E~0); 133#L1263-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1592#L1268-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1610#L1273-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1907#L1278-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1611#L1283-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 253#L1288-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1790#L1293-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1148#L1298-3true assume !(0 == ~T9_E~0); 1691#L1303-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1411#L1308-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1147#L1313-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 644#L1318-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 134#L1323-3true assume 0 == ~E_1~0;~E_1~0 := 1; 1286#L1328-3true assume 0 == ~E_2~0;~E_2~0 := 1; 1668#L1333-3true assume 0 == ~E_3~0;~E_3~0 := 1; 209#L1338-3true assume !(0 == ~E_4~0); 1039#L1343-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1524#L1348-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1295#L1353-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1335#L1358-3true assume 0 == ~E_8~0;~E_8~0 := 1; 607#L1363-3true assume 0 == ~E_9~0;~E_9~0 := 1; 324#L1368-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1884#L1373-3true assume 0 == ~E_11~0;~E_11~0 := 1; 868#L1378-3true assume !(0 == ~E_12~0); 1442#L1383-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1079#L1388-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1763#L607-42true assume 1 == ~m_pc~0; 707#L608-14true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 502#L618-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 404#is_master_triggered_returnLabel#15true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 336#L1560-42true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 689#L1560-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1202#L626-42true assume 1 == ~t1_pc~0; 389#L627-14true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1453#L637-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1749#is_transmit1_triggered_returnLabel#15true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1109#L1568-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 150#L1568-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1559#L645-42true assume !(1 == ~t2_pc~0); 1008#L645-44true is_transmit2_triggered_~__retres1~2#1 := 0; 1693#L656-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 605#is_transmit2_triggered_returnLabel#15true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 265#L1576-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18#L1576-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1653#L664-42true assume 1 == ~t3_pc~0; 449#L665-14true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1614#L675-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 934#is_transmit3_triggered_returnLabel#15true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 821#L1584-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1000#L1584-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1789#L683-42true assume !(1 == ~t4_pc~0); 723#L683-44true is_transmit4_triggered_~__retres1~4#1 := 0; 827#L694-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1003#is_transmit4_triggered_returnLabel#15true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1395#L1592-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1905#L1592-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1142#L702-42true assume 1 == ~t5_pc~0; 629#L703-14true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 574#L713-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 650#is_transmit5_triggered_returnLabel#15true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1272#L1600-42true assume !(0 != activate_threads_~tmp___4~0#1); 25#L1600-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 97#L721-42true assume 1 == ~t6_pc~0; 106#L722-14true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 356#L732-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 197#is_transmit6_triggered_returnLabel#15true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1575#L1608-42true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 461#L1608-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 367#L740-42true assume 1 == ~t7_pc~0; 1302#L741-14true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 548#L751-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 665#is_transmit7_triggered_returnLabel#15true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 451#L1616-42true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 633#L1616-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1897#L759-42true assume 1 == ~t8_pc~0; 529#L760-14true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 486#L770-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 790#is_transmit8_triggered_returnLabel#15true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 536#L1624-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 597#L1624-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1154#L778-42true assume 1 == ~t9_pc~0; 493#L779-14true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 798#L789-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1768#is_transmit9_triggered_returnLabel#15true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 724#L1632-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1602#L1632-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 768#L797-42true assume !(1 == ~t10_pc~0); 1028#L797-44true is_transmit10_triggered_~__retres1~10#1 := 0; 919#L808-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 783#is_transmit10_triggered_returnLabel#15true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1876#L1640-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 799#L1640-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1710#L816-42true assume 1 == ~t11_pc~0; 8#L817-14true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1853#L827-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1472#is_transmit11_triggered_returnLabel#15true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 478#L1648-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 313#L1648-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 571#L835-42true assume 1 == ~t12_pc~0; 832#L836-14true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1227#L846-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 636#is_transmit12_triggered_returnLabel#15true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1839#L1656-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1220#L1656-44true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 932#L854-42true assume !(1 == ~t13_pc~0); 271#L854-44true is_transmit13_triggered_~__retres1~13#1 := 0; 473#L865-14true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 363#is_transmit13_triggered_returnLabel#15true activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 507#L1664-42true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 428#L1664-44true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1857#L1401-3true assume !(1 == ~M_E~0); 1072#L1401-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 182#L1406-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 118#L1411-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1674#L1416-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 455#L1421-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1035#L1426-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 206#L1431-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 280#L1436-3true assume !(1 == ~T8_E~0); 13#L1441-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1125#L1446-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1114#L1451-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 511#L1456-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 294#L1461-3true assume 1 == ~T13_E~0;~T13_E~0 := 2; 1600#L1466-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1817#L1471-3true assume 1 == ~E_2~0;~E_2~0 := 2; 266#L1476-3true assume !(1 == ~E_3~0); 1683#L1481-3true assume 1 == ~E_4~0;~E_4~0 := 2; 506#L1486-3true assume 1 == ~E_5~0;~E_5~0 := 2; 279#L1491-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1461#L1496-3true assume 1 == ~E_7~0;~E_7~0 := 2; 533#L1501-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1583#L1506-3true assume 1 == ~E_9~0;~E_9~0 := 2; 864#L1511-3true assume 1 == ~E_10~0;~E_10~0 := 2; 856#L1516-3true assume !(1 == ~E_11~0); 1718#L1521-3true assume 1 == ~E_12~0;~E_12~0 := 2; 610#L1526-3true assume 1 == ~E_13~0;~E_13~0 := 2; 952#L1531-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1843#L959-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1879#L1031-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 193#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 488#L1911true assume !(0 == start_simulation_~tmp~3#1); 1289#L1911-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 888#L959-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1010#L1031-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 30#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 93#L1866true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 509#L1873true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1317#stop_simulation_returnLabel#1true start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1331#L1924true assume !(0 != start_simulation_~tmp___0~1#1); 1151#L1892-2true [2022-12-13 12:58:10,676 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:10,676 INFO L85 PathProgramCache]: Analyzing trace with hash 517365666, now seen corresponding path program 1 times [2022-12-13 12:58:10,685 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:10,685 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1771810400] [2022-12-13 12:58:10,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:10,686 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:10,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:10,962 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:10,962 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:10,962 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1771810400] [2022-12-13 12:58:10,963 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1771810400] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:10,963 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:10,963 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:10,964 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1571023993] [2022-12-13 12:58:10,965 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:10,968 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:58:10,969 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:10,969 INFO L85 PathProgramCache]: Analyzing trace with hash 1138552431, now seen corresponding path program 1 times [2022-12-13 12:58:10,970 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:10,970 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [14118210] [2022-12-13 12:58:10,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:10,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:10,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:11,034 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:11,035 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:11,035 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [14118210] [2022-12-13 12:58:11,035 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [14118210] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:11,035 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:11,035 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 12:58:11,036 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [741614554] [2022-12-13 12:58:11,036 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:11,037 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:58:11,038 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:58:11,062 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-12-13 12:58:11,062 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-12-13 12:58:11,066 INFO L87 Difference]: Start difference. First operand has 1920 states, 1919 states have (on average 1.498697238144867) internal successors, (2876), 1919 states have internal predecessors, (2876), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 78.5) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:11,124 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:58:11,125 INFO L93 Difference]: Finished difference Result 1919 states and 2840 transitions. [2022-12-13 12:58:11,126 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1919 states and 2840 transitions. [2022-12-13 12:58:11,135 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 12:58:11,147 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1919 states to 1914 states and 2835 transitions. [2022-12-13 12:58:11,147 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-12-13 12:58:11,150 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-12-13 12:58:11,150 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2835 transitions. [2022-12-13 12:58:11,157 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:58:11,158 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2835 transitions. [2022-12-13 12:58:11,175 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2835 transitions. [2022-12-13 12:58:11,220 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-12-13 12:58:11,223 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4811912225705328) internal successors, (2835), 1913 states have internal predecessors, (2835), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:11,226 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2835 transitions. [2022-12-13 12:58:11,227 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2835 transitions. [2022-12-13 12:58:11,228 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-12-13 12:58:11,230 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2835 transitions. [2022-12-13 12:58:11,231 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-12-13 12:58:11,231 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2835 transitions. [2022-12-13 12:58:11,237 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 12:58:11,237 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:58:11,237 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:58:11,239 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:11,239 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:11,239 INFO L748 eck$LassoCheckResult]: Stem: 4134#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 4135#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 5029#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5030#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5751#L881 assume !(1 == ~m_i~0);~m_st~0 := 2; 5427#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5428#L886-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4359#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4360#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4833#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4671#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4672#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4423#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4424#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4841#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5020#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5188#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5222#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 4439#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4440#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 5643#L1258-2 assume !(0 == ~T1_E~0); 4756#L1263-1 assume !(0 == ~T2_E~0); 4757#L1268-1 assume !(0 == ~T3_E~0); 5066#L1273-1 assume !(0 == ~T4_E~0); 5622#L1278-1 assume !(0 == ~T5_E~0); 5481#L1283-1 assume !(0 == ~T6_E~0); 5482#L1288-1 assume !(0 == ~T7_E~0); 5719#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5708#L1298-1 assume !(0 == ~T9_E~0); 5638#L1303-1 assume !(0 == ~T10_E~0); 4237#L1308-1 assume !(0 == ~T11_E~0); 4177#L1313-1 assume !(0 == ~T12_E~0); 4178#L1318-1 assume !(0 == ~T13_E~0); 4183#L1323-1 assume !(0 == ~E_1~0); 4184#L1328-1 assume !(0 == ~E_2~0); 4369#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5357#L1338-1 assume !(0 == ~E_4~0); 5358#L1343-1 assume !(0 == ~E_5~0); 5458#L1348-1 assume !(0 == ~E_6~0); 5738#L1353-1 assume !(0 == ~E_7~0); 5089#L1358-1 assume !(0 == ~E_8~0); 5090#L1363-1 assume !(0 == ~E_9~0); 5379#L1368-1 assume !(0 == ~E_10~0); 4030#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 4031#L1378-1 assume !(0 == ~E_12~0); 4312#L1383-1 assume !(0 == ~E_13~0); 4313#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5094#L607 assume 1 == ~m_pc~0; 5095#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4387#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4896#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4897#L1560 assume !(0 != activate_threads_~tmp~1#1); 5002#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4198#L626 assume !(1 == ~t1_pc~0); 4199#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4480#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4481#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5366#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 4102#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4103#L645 assume 1 == ~t2_pc~0; 4214#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4171#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4280#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4281#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 4976#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4977#L664 assume 1 == ~t3_pc~0; 5736#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3964#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3965#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4629#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 4630#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5651#L683 assume !(1 == ~t4_pc~0); 5206#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5159#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3988#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3989#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5314#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4919#L702 assume 1 == ~t5_pc~0; 4920#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4856#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5310#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5641#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 5549#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4000#L721 assume !(1 == ~t6_pc~0); 3981#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3982#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4126#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4265#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 4642#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5254#L740 assume 1 == ~t7_pc~0; 4046#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3881#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3882#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3871#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 3872#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4569#L759 assume !(1 == ~t8_pc~0); 4570#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4601#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5696#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5438#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 5439#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5718#L778 assume 1 == ~t9_pc~0; 5607#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4029#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4335#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3907#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 3908#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4210#L797 assume !(1 == ~t10_pc~0); 4211#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4345#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5584#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4752#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 4753#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5046#L816 assume 1 == ~t11_pc~0; 3942#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3943#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4885#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4648#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 4649#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5187#L835 assume 1 == ~t12_pc~0; 5061#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4093#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3932#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3933#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 4805#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4806#L854 assume !(1 == ~t13_pc~0); 4425#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 4426#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4475#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4124#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4125#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5545#L1401 assume !(1 == ~M_E~0); 4635#L1401-2 assume !(1 == ~T1_E~0); 4636#L1406-1 assume !(1 == ~T2_E~0); 5243#L1411-1 assume !(1 == ~T3_E~0); 5244#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4895#L1421-1 assume !(1 == ~T5_E~0); 4421#L1426-1 assume !(1 == ~T6_E~0); 4422#L1431-1 assume !(1 == ~T7_E~0); 3979#L1436-1 assume !(1 == ~T8_E~0); 3980#L1441-1 assume !(1 == ~T9_E~0); 4743#L1446-1 assume !(1 == ~T10_E~0); 4744#L1451-1 assume !(1 == ~T11_E~0); 5455#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5114#L1461-1 assume !(1 == ~T13_E~0); 4664#L1466-1 assume !(1 == ~E_1~0); 4665#L1471-1 assume !(1 == ~E_2~0); 5436#L1476-1 assume !(1 == ~E_3~0); 5437#L1481-1 assume !(1 == ~E_4~0); 5590#L1486-1 assume !(1 == ~E_5~0); 4250#L1491-1 assume !(1 == ~E_6~0); 3917#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 3918#L1501-1 assume !(1 == ~E_8~0); 4739#L1506-1 assume !(1 == ~E_9~0); 4740#L1511-1 assume !(1 == ~E_10~0); 4694#L1516-1 assume !(1 == ~E_11~0); 3869#L1521-1 assume !(1 == ~E_12~0); 3870#L1526-1 assume !(1 == ~E_13~0); 3916#L1531-1 assume { :end_inline_reset_delta_events } true; 4447#L1892-2 [2022-12-13 12:58:11,240 INFO L750 eck$LassoCheckResult]: Loop: 4447#L1892-2 assume !false; 5497#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5695#L1233 assume !false; 5678#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5003#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4983#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5526#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3958#L1046 assume !(0 != eval_~tmp~0#1); 3960#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4492#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4493#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5735#L1258-5 assume !(0 == ~T1_E~0); 4114#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4115#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5727#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5731#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5732#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4350#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4351#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5494#L1298-3 assume !(0 == ~T9_E~0); 5495#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5658#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5493#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4987#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4116#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4117#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5582#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4261#L1338-3 assume !(0 == ~E_4~0); 4262#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5413#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5587#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5588#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4934#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4482#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4483#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5274#L1378-3 assume !(0 == ~E_12~0); 5275#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5452#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5453#L607-42 assume !(1 == ~m_pc~0); 5072#L607-44 is_master_triggered_~__retres1~0#1 := 0; 4789#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4622#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4502#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4503#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5047#L626-42 assume 1 == ~t1_pc~0; 4593#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4594#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5682#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5468#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4150#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4151#L645-42 assume !(1 == ~t2_pc~0); 5393#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 5394#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4932#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4370#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3889#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3890#L664-42 assume !(1 == ~t3_pc~0); 4406#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 4407#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5333#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5220#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5221#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5386#L683-42 assume !(1 == ~t4_pc~0); 5097#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 5098#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5227#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5389#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5648#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5488#L702-42 assume 1 == ~t5_pc~0; 4964#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4584#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4888#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4997#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 3901#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3902#L721-42 assume 1 == ~t6_pc~0; 4041#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4062#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4241#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4242#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4720#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4557#L740-42 assume !(1 == ~t7_pc~0); 4276#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 4277#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4849#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4703#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4704#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4970#L759-42 assume 1 == ~t8_pc~0; 4825#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4762#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4763#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4834#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4835#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4924#L778-42 assume 1 == ~t9_pc~0; 4774#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4776#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5192#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5099#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5100#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5154#L797-42 assume 1 == ~t10_pc~0; 4284#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4285#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5172#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5173#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5193#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5194#L816-42 assume 1 == ~t11_pc~0; 3861#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3862#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5688#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4749#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4461#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4462#L835-42 assume !(1 == ~t12_pc~0); 4785#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 4786#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4973#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4974#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 5548#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5331#L854-42 assume 1 == ~t13_pc~0; 5332#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4383#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4549#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4550#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4660#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4661#L1401-3 assume !(1 == ~M_E~0); 5446#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4213#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4088#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4089#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4710#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4711#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4255#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4256#L1436-3 assume !(1 == ~T8_E~0); 3873#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3874#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5472#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4797#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4429#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 4430#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5729#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4371#L1476-3 assume !(1 == ~E_3~0); 4372#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4794#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4399#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4400#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4831#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4832#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5270#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 5258#L1516-3 assume !(1 == ~E_11~0); 5259#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4937#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 4938#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5353#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4188#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4235#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4236#L1911 assume !(0 == start_simulation_~tmp~3#1); 4766#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5292#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4327#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 3911#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 3912#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4035#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4795#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 5601#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 4447#L1892-2 [2022-12-13 12:58:11,240 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:11,240 INFO L85 PathProgramCache]: Analyzing trace with hash 517365666, now seen corresponding path program 2 times [2022-12-13 12:58:11,241 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:11,241 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2136717543] [2022-12-13 12:58:11,241 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:11,241 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:11,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:11,300 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:11,301 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:11,301 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2136717543] [2022-12-13 12:58:11,301 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2136717543] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:11,301 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:11,301 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:11,301 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [433869018] [2022-12-13 12:58:11,301 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:11,301 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:58:11,302 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:11,302 INFO L85 PathProgramCache]: Analyzing trace with hash 1102798351, now seen corresponding path program 1 times [2022-12-13 12:58:11,302 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:11,302 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1438294615] [2022-12-13 12:58:11,302 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:11,303 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:11,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:11,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:11,379 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:11,379 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1438294615] [2022-12-13 12:58:11,379 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1438294615] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:11,379 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:11,379 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:11,380 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [894818855] [2022-12-13 12:58:11,380 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:11,380 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:58:11,380 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:58:11,381 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:58:11,381 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:58:11,381 INFO L87 Difference]: Start difference. First operand 1914 states and 2835 transitions. cyclomatic complexity: 922 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:11,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:58:11,419 INFO L93 Difference]: Finished difference Result 1914 states and 2834 transitions. [2022-12-13 12:58:11,419 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2834 transitions. [2022-12-13 12:58:11,425 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 12:58:11,430 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2834 transitions. [2022-12-13 12:58:11,430 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-12-13 12:58:11,431 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-12-13 12:58:11,431 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2834 transitions. [2022-12-13 12:58:11,433 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:58:11,433 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2834 transitions. [2022-12-13 12:58:11,435 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2834 transitions. [2022-12-13 12:58:11,449 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-12-13 12:58:11,451 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4806687565308254) internal successors, (2834), 1913 states have internal predecessors, (2834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:11,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2834 transitions. [2022-12-13 12:58:11,453 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2834 transitions. [2022-12-13 12:58:11,454 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:58:11,454 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2834 transitions. [2022-12-13 12:58:11,454 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-12-13 12:58:11,454 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2834 transitions. [2022-12-13 12:58:11,460 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 12:58:11,460 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:58:11,460 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:58:11,461 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:11,461 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:11,462 INFO L748 eck$LassoCheckResult]: Stem: 7969#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 7970#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 8864#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8865#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9586#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 9262#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9263#L886-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8194#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8195#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8668#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8506#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8507#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8258#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8259#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8676#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8855#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9023#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9057#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 8274#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8275#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 9478#L1258-2 assume !(0 == ~T1_E~0); 8591#L1263-1 assume !(0 == ~T2_E~0); 8592#L1268-1 assume !(0 == ~T3_E~0); 8901#L1273-1 assume !(0 == ~T4_E~0); 9457#L1278-1 assume !(0 == ~T5_E~0); 9316#L1283-1 assume !(0 == ~T6_E~0); 9317#L1288-1 assume !(0 == ~T7_E~0); 9554#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9543#L1298-1 assume !(0 == ~T9_E~0); 9473#L1303-1 assume !(0 == ~T10_E~0); 8072#L1308-1 assume !(0 == ~T11_E~0); 8012#L1313-1 assume !(0 == ~T12_E~0); 8013#L1318-1 assume !(0 == ~T13_E~0); 8018#L1323-1 assume !(0 == ~E_1~0); 8019#L1328-1 assume !(0 == ~E_2~0); 8204#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 9192#L1338-1 assume !(0 == ~E_4~0); 9193#L1343-1 assume !(0 == ~E_5~0); 9293#L1348-1 assume !(0 == ~E_6~0); 9573#L1353-1 assume !(0 == ~E_7~0); 8924#L1358-1 assume !(0 == ~E_8~0); 8925#L1363-1 assume !(0 == ~E_9~0); 9214#L1368-1 assume !(0 == ~E_10~0); 7865#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 7866#L1378-1 assume !(0 == ~E_12~0); 8147#L1383-1 assume !(0 == ~E_13~0); 8148#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8929#L607 assume 1 == ~m_pc~0; 8930#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8222#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8731#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8732#L1560 assume !(0 != activate_threads_~tmp~1#1); 8837#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8033#L626 assume !(1 == ~t1_pc~0); 8034#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8315#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8316#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9201#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 7937#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7938#L645 assume 1 == ~t2_pc~0; 8049#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8006#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8115#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8116#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 8811#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8812#L664 assume 1 == ~t3_pc~0; 9571#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7799#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7800#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8464#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 8465#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9486#L683 assume !(1 == ~t4_pc~0); 9041#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8994#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7823#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7824#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9149#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8754#L702 assume 1 == ~t5_pc~0; 8755#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8691#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9145#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9476#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 9384#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7835#L721 assume !(1 == ~t6_pc~0); 7816#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7817#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7961#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8100#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 8477#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9089#L740 assume 1 == ~t7_pc~0; 7881#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7716#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7717#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7706#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 7707#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8404#L759 assume !(1 == ~t8_pc~0); 8405#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8436#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9531#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9273#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 9274#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9553#L778 assume 1 == ~t9_pc~0; 9442#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7864#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8170#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7742#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 7743#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8045#L797 assume !(1 == ~t10_pc~0); 8046#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8180#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9419#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8587#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 8588#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8881#L816 assume 1 == ~t11_pc~0; 7777#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7778#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8720#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8483#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 8484#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9022#L835 assume 1 == ~t12_pc~0; 8896#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7928#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7767#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7768#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 8640#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8641#L854 assume !(1 == ~t13_pc~0); 8260#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 8261#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8310#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7959#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 7960#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9380#L1401 assume !(1 == ~M_E~0); 8470#L1401-2 assume !(1 == ~T1_E~0); 8471#L1406-1 assume !(1 == ~T2_E~0); 9078#L1411-1 assume !(1 == ~T3_E~0); 9079#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8730#L1421-1 assume !(1 == ~T5_E~0); 8256#L1426-1 assume !(1 == ~T6_E~0); 8257#L1431-1 assume !(1 == ~T7_E~0); 7814#L1436-1 assume !(1 == ~T8_E~0); 7815#L1441-1 assume !(1 == ~T9_E~0); 8578#L1446-1 assume !(1 == ~T10_E~0); 8579#L1451-1 assume !(1 == ~T11_E~0); 9290#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8949#L1461-1 assume !(1 == ~T13_E~0); 8499#L1466-1 assume !(1 == ~E_1~0); 8500#L1471-1 assume !(1 == ~E_2~0); 9271#L1476-1 assume !(1 == ~E_3~0); 9272#L1481-1 assume !(1 == ~E_4~0); 9425#L1486-1 assume !(1 == ~E_5~0); 8085#L1491-1 assume !(1 == ~E_6~0); 7752#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7753#L1501-1 assume !(1 == ~E_8~0); 8574#L1506-1 assume !(1 == ~E_9~0); 8575#L1511-1 assume !(1 == ~E_10~0); 8529#L1516-1 assume !(1 == ~E_11~0); 7704#L1521-1 assume !(1 == ~E_12~0); 7705#L1526-1 assume !(1 == ~E_13~0); 7751#L1531-1 assume { :end_inline_reset_delta_events } true; 8282#L1892-2 [2022-12-13 12:58:11,462 INFO L750 eck$LassoCheckResult]: Loop: 8282#L1892-2 assume !false; 9332#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9530#L1233 assume !false; 9513#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8838#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8818#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 9361#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7793#L1046 assume !(0 != eval_~tmp~0#1); 7795#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8327#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8328#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9570#L1258-5 assume !(0 == ~T1_E~0); 7949#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7950#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9562#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9566#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9567#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8185#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8186#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9329#L1298-3 assume !(0 == ~T9_E~0); 9330#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9493#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9328#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8822#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 7951#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7952#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9417#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8096#L1338-3 assume !(0 == ~E_4~0); 8097#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9248#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9422#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9423#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8769#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8317#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8318#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 9109#L1378-3 assume !(0 == ~E_12~0); 9110#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 9287#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9288#L607-42 assume 1 == ~m_pc~0; 8906#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8624#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8457#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8337#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8338#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8882#L626-42 assume 1 == ~t1_pc~0; 8428#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8429#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9517#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9303#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7985#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7986#L645-42 assume !(1 == ~t2_pc~0); 9228#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 9229#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8767#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8205#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7724#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7725#L664-42 assume !(1 == ~t3_pc~0); 8241#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 8242#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9168#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9055#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9056#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9221#L683-42 assume !(1 == ~t4_pc~0); 8932#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 8933#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9062#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9224#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9483#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9323#L702-42 assume !(1 == ~t5_pc~0); 8418#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 8419#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8723#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8832#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 7736#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7737#L721-42 assume 1 == ~t6_pc~0; 7876#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7897#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8076#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8077#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8555#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8392#L740-42 assume 1 == ~t7_pc~0; 8393#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8112#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8684#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8538#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8539#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8805#L759-42 assume 1 == ~t8_pc~0; 8660#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8597#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8598#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8669#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8670#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8759#L778-42 assume 1 == ~t9_pc~0; 8609#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8611#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9027#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8934#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8935#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8989#L797-42 assume 1 == ~t10_pc~0; 8119#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8120#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9007#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9008#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9028#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9029#L816-42 assume 1 == ~t11_pc~0; 7696#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7697#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9523#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8584#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8296#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8297#L835-42 assume !(1 == ~t12_pc~0); 8620#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 8621#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8808#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8809#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 9383#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9166#L854-42 assume !(1 == ~t13_pc~0); 8217#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 8218#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8384#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8385#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 8495#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8496#L1401-3 assume !(1 == ~M_E~0); 9281#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8048#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7923#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7924#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8545#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8546#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8090#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8091#L1436-3 assume !(1 == ~T8_E~0); 7708#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7709#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9307#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8632#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8264#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 8265#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9564#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8206#L1476-3 assume !(1 == ~E_3~0); 8207#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8629#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8234#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8235#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8666#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8667#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9105#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9093#L1516-3 assume !(1 == ~E_11~0); 9094#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8772#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 8773#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9188#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8023#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8070#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 8071#L1911 assume !(0 == start_simulation_~tmp~3#1); 8601#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9127#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8162#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 7746#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 7747#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7870#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8630#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 9436#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 8282#L1892-2 [2022-12-13 12:58:11,463 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:11,463 INFO L85 PathProgramCache]: Analyzing trace with hash -2008130016, now seen corresponding path program 1 times [2022-12-13 12:58:11,463 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:11,463 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [73043671] [2022-12-13 12:58:11,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:11,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:11,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:11,511 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:11,511 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:11,511 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [73043671] [2022-12-13 12:58:11,512 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [73043671] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:11,512 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:11,512 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:11,512 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1024468453] [2022-12-13 12:58:11,512 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:11,512 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:58:11,513 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:11,513 INFO L85 PathProgramCache]: Analyzing trace with hash 447451599, now seen corresponding path program 1 times [2022-12-13 12:58:11,513 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:11,514 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [974026119] [2022-12-13 12:58:11,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:11,514 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:11,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:11,575 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:11,575 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:11,576 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [974026119] [2022-12-13 12:58:11,576 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [974026119] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:11,576 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:11,576 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:11,576 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1097347738] [2022-12-13 12:58:11,577 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:11,577 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:58:11,577 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:58:11,577 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:58:11,578 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:58:11,578 INFO L87 Difference]: Start difference. First operand 1914 states and 2834 transitions. cyclomatic complexity: 921 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:11,612 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:58:11,612 INFO L93 Difference]: Finished difference Result 1914 states and 2833 transitions. [2022-12-13 12:58:11,612 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2833 transitions. [2022-12-13 12:58:11,618 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 12:58:11,623 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2833 transitions. [2022-12-13 12:58:11,623 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-12-13 12:58:11,625 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-12-13 12:58:11,625 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2833 transitions. [2022-12-13 12:58:11,627 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:58:11,627 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2833 transitions. [2022-12-13 12:58:11,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2833 transitions. [2022-12-13 12:58:11,642 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-12-13 12:58:11,644 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.480146290491118) internal successors, (2833), 1913 states have internal predecessors, (2833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:11,647 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2833 transitions. [2022-12-13 12:58:11,647 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2833 transitions. [2022-12-13 12:58:11,648 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:58:11,648 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2833 transitions. [2022-12-13 12:58:11,648 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-12-13 12:58:11,648 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2833 transitions. [2022-12-13 12:58:11,654 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 12:58:11,654 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:58:11,654 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:58:11,656 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:11,656 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:11,656 INFO L748 eck$LassoCheckResult]: Stem: 11804#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 11805#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 12699#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12700#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13421#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 13097#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13098#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12029#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 12030#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 12503#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 12341#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12342#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12093#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12094#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12511#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12690#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12858#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 12892#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 12109#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12110#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 13313#L1258-2 assume !(0 == ~T1_E~0); 12426#L1263-1 assume !(0 == ~T2_E~0); 12427#L1268-1 assume !(0 == ~T3_E~0); 12736#L1273-1 assume !(0 == ~T4_E~0); 13292#L1278-1 assume !(0 == ~T5_E~0); 13151#L1283-1 assume !(0 == ~T6_E~0); 13152#L1288-1 assume !(0 == ~T7_E~0); 13389#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13378#L1298-1 assume !(0 == ~T9_E~0); 13308#L1303-1 assume !(0 == ~T10_E~0); 11907#L1308-1 assume !(0 == ~T11_E~0); 11847#L1313-1 assume !(0 == ~T12_E~0); 11848#L1318-1 assume !(0 == ~T13_E~0); 11853#L1323-1 assume !(0 == ~E_1~0); 11854#L1328-1 assume !(0 == ~E_2~0); 12039#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 13027#L1338-1 assume !(0 == ~E_4~0); 13028#L1343-1 assume !(0 == ~E_5~0); 13128#L1348-1 assume !(0 == ~E_6~0); 13408#L1353-1 assume !(0 == ~E_7~0); 12759#L1358-1 assume !(0 == ~E_8~0); 12760#L1363-1 assume !(0 == ~E_9~0); 13049#L1368-1 assume !(0 == ~E_10~0); 11700#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 11701#L1378-1 assume !(0 == ~E_12~0); 11982#L1383-1 assume !(0 == ~E_13~0); 11983#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12764#L607 assume 1 == ~m_pc~0; 12765#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 12057#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12566#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12567#L1560 assume !(0 != activate_threads_~tmp~1#1); 12672#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11868#L626 assume !(1 == ~t1_pc~0); 11869#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12150#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12151#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13036#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 11772#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11773#L645 assume 1 == ~t2_pc~0; 11884#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11841#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11950#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11951#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 12646#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12647#L664 assume 1 == ~t3_pc~0; 13406#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11634#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11635#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12299#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 12300#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13321#L683 assume !(1 == ~t4_pc~0); 12876#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12829#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11658#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11659#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12984#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12589#L702 assume 1 == ~t5_pc~0; 12590#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12526#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12980#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13311#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 13219#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11670#L721 assume !(1 == ~t6_pc~0); 11651#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 11652#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11796#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11935#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 12312#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12924#L740 assume 1 == ~t7_pc~0; 11716#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11551#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11552#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11541#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 11542#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12239#L759 assume !(1 == ~t8_pc~0); 12240#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12271#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13366#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13108#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 13109#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13388#L778 assume 1 == ~t9_pc~0; 13277#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11699#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12005#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11577#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 11578#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11880#L797 assume !(1 == ~t10_pc~0); 11881#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12015#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13254#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12422#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 12423#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12716#L816 assume 1 == ~t11_pc~0; 11612#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11613#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12555#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12318#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 12319#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12857#L835 assume 1 == ~t12_pc~0; 12731#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 11763#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11602#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11603#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 12475#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12476#L854 assume !(1 == ~t13_pc~0); 12095#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 12096#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12145#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11794#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 11795#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13215#L1401 assume !(1 == ~M_E~0); 12305#L1401-2 assume !(1 == ~T1_E~0); 12306#L1406-1 assume !(1 == ~T2_E~0); 12913#L1411-1 assume !(1 == ~T3_E~0); 12914#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12565#L1421-1 assume !(1 == ~T5_E~0); 12091#L1426-1 assume !(1 == ~T6_E~0); 12092#L1431-1 assume !(1 == ~T7_E~0); 11649#L1436-1 assume !(1 == ~T8_E~0); 11650#L1441-1 assume !(1 == ~T9_E~0); 12413#L1446-1 assume !(1 == ~T10_E~0); 12414#L1451-1 assume !(1 == ~T11_E~0); 13125#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12784#L1461-1 assume !(1 == ~T13_E~0); 12334#L1466-1 assume !(1 == ~E_1~0); 12335#L1471-1 assume !(1 == ~E_2~0); 13106#L1476-1 assume !(1 == ~E_3~0); 13107#L1481-1 assume !(1 == ~E_4~0); 13260#L1486-1 assume !(1 == ~E_5~0); 11920#L1491-1 assume !(1 == ~E_6~0); 11587#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 11588#L1501-1 assume !(1 == ~E_8~0); 12409#L1506-1 assume !(1 == ~E_9~0); 12410#L1511-1 assume !(1 == ~E_10~0); 12364#L1516-1 assume !(1 == ~E_11~0); 11539#L1521-1 assume !(1 == ~E_12~0); 11540#L1526-1 assume !(1 == ~E_13~0); 11586#L1531-1 assume { :end_inline_reset_delta_events } true; 12117#L1892-2 [2022-12-13 12:58:11,657 INFO L750 eck$LassoCheckResult]: Loop: 12117#L1892-2 assume !false; 13167#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13365#L1233 assume !false; 13348#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12673#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12653#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 13196#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11628#L1046 assume !(0 != eval_~tmp~0#1); 11630#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12162#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12163#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13405#L1258-5 assume !(0 == ~T1_E~0); 11784#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11785#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13397#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13401#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13402#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12020#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12021#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13164#L1298-3 assume !(0 == ~T9_E~0); 13165#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13328#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13163#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 12657#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 11786#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11787#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13252#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11931#L1338-3 assume !(0 == ~E_4~0); 11932#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13083#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13257#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13258#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12604#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12152#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12153#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 12944#L1378-3 assume !(0 == ~E_12~0); 12945#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13122#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13123#L607-42 assume 1 == ~m_pc~0; 12741#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 12459#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12292#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12172#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12173#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12717#L626-42 assume 1 == ~t1_pc~0; 12263#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12264#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13352#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13138#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11820#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11821#L645-42 assume !(1 == ~t2_pc~0); 13063#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 13064#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12602#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12040#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11559#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11560#L664-42 assume 1 == ~t3_pc~0; 12370#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12077#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13003#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12890#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12891#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13056#L683-42 assume 1 == ~t4_pc~0; 13413#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12768#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12897#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13059#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13318#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13158#L702-42 assume 1 == ~t5_pc~0; 12634#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12254#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12558#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12667#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 11571#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11572#L721-42 assume !(1 == ~t6_pc~0); 11712#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 11732#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11911#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11912#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12390#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12227#L740-42 assume 1 == ~t7_pc~0; 12228#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11947#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12519#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12373#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12374#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12640#L759-42 assume !(1 == ~t8_pc~0); 12496#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 12432#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12433#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12504#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12505#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12594#L778-42 assume 1 == ~t9_pc~0; 12444#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12446#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12862#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12769#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12770#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12824#L797-42 assume 1 == ~t10_pc~0; 11954#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11955#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12842#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12843#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12863#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12864#L816-42 assume 1 == ~t11_pc~0; 11531#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11532#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13358#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12419#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 12131#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12132#L835-42 assume !(1 == ~t12_pc~0); 12455#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 12456#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12643#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12644#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13218#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 13001#L854-42 assume !(1 == ~t13_pc~0); 12052#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 12053#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12219#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12220#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 12330#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12331#L1401-3 assume !(1 == ~M_E~0); 13116#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11883#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11758#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11759#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12380#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12381#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11925#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11926#L1436-3 assume !(1 == ~T8_E~0); 11543#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11544#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13142#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12467#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12099#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 12100#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13399#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12041#L1476-3 assume !(1 == ~E_3~0); 12042#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12464#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12069#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12070#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12501#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12502#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12940#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12928#L1516-3 assume !(1 == ~E_11~0); 12929#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12607#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 12608#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13023#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 11858#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 11905#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 11906#L1911 assume !(0 == start_simulation_~tmp~3#1); 12436#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12962#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 11997#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 11581#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 11582#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11705#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12465#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 13271#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 12117#L1892-2 [2022-12-13 12:58:11,657 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:11,658 INFO L85 PathProgramCache]: Analyzing trace with hash -602938338, now seen corresponding path program 1 times [2022-12-13 12:58:11,658 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:11,658 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [102633114] [2022-12-13 12:58:11,658 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:11,658 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:11,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:11,697 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:11,697 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:11,698 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [102633114] [2022-12-13 12:58:11,698 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [102633114] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:11,698 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:11,698 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:11,698 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1744112648] [2022-12-13 12:58:11,698 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:11,699 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:58:11,699 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:11,699 INFO L85 PathProgramCache]: Analyzing trace with hash 2137502768, now seen corresponding path program 1 times [2022-12-13 12:58:11,699 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:11,700 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1453618249] [2022-12-13 12:58:11,700 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:11,700 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:11,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:11,766 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:11,766 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:11,766 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1453618249] [2022-12-13 12:58:11,766 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1453618249] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:11,766 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:11,766 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:11,767 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [459540535] [2022-12-13 12:58:11,767 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:11,767 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:58:11,767 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:58:11,768 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:58:11,768 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:58:11,768 INFO L87 Difference]: Start difference. First operand 1914 states and 2833 transitions. cyclomatic complexity: 920 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:11,805 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:58:11,805 INFO L93 Difference]: Finished difference Result 1914 states and 2832 transitions. [2022-12-13 12:58:11,805 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2832 transitions. [2022-12-13 12:58:11,815 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 12:58:11,823 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2832 transitions. [2022-12-13 12:58:11,823 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-12-13 12:58:11,825 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-12-13 12:58:11,825 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2832 transitions. [2022-12-13 12:58:11,828 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:58:11,828 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2832 transitions. [2022-12-13 12:58:11,832 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2832 transitions. [2022-12-13 12:58:11,858 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-12-13 12:58:11,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4796238244514106) internal successors, (2832), 1913 states have internal predecessors, (2832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:11,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2832 transitions. [2022-12-13 12:58:11,865 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2832 transitions. [2022-12-13 12:58:11,865 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:58:11,865 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2832 transitions. [2022-12-13 12:58:11,866 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-12-13 12:58:11,866 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2832 transitions. [2022-12-13 12:58:11,871 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 12:58:11,872 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:58:11,872 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:58:11,873 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:11,873 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:11,874 INFO L748 eck$LassoCheckResult]: Stem: 15639#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 15640#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 16534#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16535#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17256#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 16932#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16933#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15864#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15865#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 16338#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 16176#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 16177#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 15928#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15929#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16346#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16525#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 16693#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 16727#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 15944#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15945#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 17148#L1258-2 assume !(0 == ~T1_E~0); 16261#L1263-1 assume !(0 == ~T2_E~0); 16262#L1268-1 assume !(0 == ~T3_E~0); 16571#L1273-1 assume !(0 == ~T4_E~0); 17127#L1278-1 assume !(0 == ~T5_E~0); 16986#L1283-1 assume !(0 == ~T6_E~0); 16987#L1288-1 assume !(0 == ~T7_E~0); 17224#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17213#L1298-1 assume !(0 == ~T9_E~0); 17143#L1303-1 assume !(0 == ~T10_E~0); 15742#L1308-1 assume !(0 == ~T11_E~0); 15682#L1313-1 assume !(0 == ~T12_E~0); 15683#L1318-1 assume !(0 == ~T13_E~0); 15688#L1323-1 assume !(0 == ~E_1~0); 15689#L1328-1 assume !(0 == ~E_2~0); 15874#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 16862#L1338-1 assume !(0 == ~E_4~0); 16863#L1343-1 assume !(0 == ~E_5~0); 16963#L1348-1 assume !(0 == ~E_6~0); 17243#L1353-1 assume !(0 == ~E_7~0); 16594#L1358-1 assume !(0 == ~E_8~0); 16595#L1363-1 assume !(0 == ~E_9~0); 16884#L1368-1 assume !(0 == ~E_10~0); 15535#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 15536#L1378-1 assume !(0 == ~E_12~0); 15817#L1383-1 assume !(0 == ~E_13~0); 15818#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16599#L607 assume 1 == ~m_pc~0; 16600#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 15892#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16401#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16402#L1560 assume !(0 != activate_threads_~tmp~1#1); 16507#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15703#L626 assume !(1 == ~t1_pc~0); 15704#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15985#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15986#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16871#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 15607#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15608#L645 assume 1 == ~t2_pc~0; 15719#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15676#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15785#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15786#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 16481#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16482#L664 assume 1 == ~t3_pc~0; 17241#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15469#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15470#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16134#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 16135#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17156#L683 assume !(1 == ~t4_pc~0); 16711#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16664#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15493#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15494#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16819#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16424#L702 assume 1 == ~t5_pc~0; 16425#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16361#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16815#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17146#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 17054#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15505#L721 assume !(1 == ~t6_pc~0); 15486#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 15487#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15631#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15770#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 16147#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16759#L740 assume 1 == ~t7_pc~0; 15551#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15386#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15387#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15376#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 15377#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16074#L759 assume !(1 == ~t8_pc~0); 16075#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16106#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17201#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16943#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 16944#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17223#L778 assume 1 == ~t9_pc~0; 17112#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15534#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15840#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15412#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 15413#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15715#L797 assume !(1 == ~t10_pc~0); 15716#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 15850#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17089#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16257#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 16258#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16551#L816 assume 1 == ~t11_pc~0; 15447#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15448#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16390#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16153#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 16154#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16692#L835 assume 1 == ~t12_pc~0; 16566#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 15598#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15437#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 15438#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 16310#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16311#L854 assume !(1 == ~t13_pc~0); 15930#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 15931#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 15980#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 15629#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 15630#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17050#L1401 assume !(1 == ~M_E~0); 16140#L1401-2 assume !(1 == ~T1_E~0); 16141#L1406-1 assume !(1 == ~T2_E~0); 16748#L1411-1 assume !(1 == ~T3_E~0); 16749#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16400#L1421-1 assume !(1 == ~T5_E~0); 15926#L1426-1 assume !(1 == ~T6_E~0); 15927#L1431-1 assume !(1 == ~T7_E~0); 15484#L1436-1 assume !(1 == ~T8_E~0); 15485#L1441-1 assume !(1 == ~T9_E~0); 16248#L1446-1 assume !(1 == ~T10_E~0); 16249#L1451-1 assume !(1 == ~T11_E~0); 16960#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 16619#L1461-1 assume !(1 == ~T13_E~0); 16169#L1466-1 assume !(1 == ~E_1~0); 16170#L1471-1 assume !(1 == ~E_2~0); 16941#L1476-1 assume !(1 == ~E_3~0); 16942#L1481-1 assume !(1 == ~E_4~0); 17095#L1486-1 assume !(1 == ~E_5~0); 15755#L1491-1 assume !(1 == ~E_6~0); 15422#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 15423#L1501-1 assume !(1 == ~E_8~0); 16244#L1506-1 assume !(1 == ~E_9~0); 16245#L1511-1 assume !(1 == ~E_10~0); 16199#L1516-1 assume !(1 == ~E_11~0); 15374#L1521-1 assume !(1 == ~E_12~0); 15375#L1526-1 assume !(1 == ~E_13~0); 15421#L1531-1 assume { :end_inline_reset_delta_events } true; 15952#L1892-2 [2022-12-13 12:58:11,874 INFO L750 eck$LassoCheckResult]: Loop: 15952#L1892-2 assume !false; 17002#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17200#L1233 assume !false; 17183#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16508#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16488#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 17031#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15463#L1046 assume !(0 != eval_~tmp~0#1); 15465#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15997#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15998#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17240#L1258-5 assume !(0 == ~T1_E~0); 15619#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15620#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17232#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17236#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17237#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15855#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15856#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16999#L1298-3 assume !(0 == ~T9_E~0); 17000#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17163#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 16998#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 16492#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 15621#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15622#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17087#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15766#L1338-3 assume !(0 == ~E_4~0); 15767#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16918#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17092#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17093#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16439#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15987#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15988#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16779#L1378-3 assume !(0 == ~E_12~0); 16780#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 16957#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16958#L607-42 assume 1 == ~m_pc~0; 16576#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16294#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16127#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16007#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16008#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16552#L626-42 assume 1 == ~t1_pc~0; 16098#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16099#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17187#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16973#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15655#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15656#L645-42 assume !(1 == ~t2_pc~0); 16898#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 16899#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16437#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15875#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15394#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15395#L664-42 assume !(1 == ~t3_pc~0); 15911#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 15912#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16838#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16725#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16726#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16891#L683-42 assume 1 == ~t4_pc~0; 17248#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16603#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16732#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16894#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17153#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16993#L702-42 assume 1 == ~t5_pc~0; 16469#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16089#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16393#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16502#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 15406#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15407#L721-42 assume 1 == ~t6_pc~0; 15546#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15567#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15746#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15747#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16225#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16062#L740-42 assume !(1 == ~t7_pc~0); 15781#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 15782#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16354#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16208#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16209#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16475#L759-42 assume 1 == ~t8_pc~0; 16330#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16267#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16268#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16339#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16340#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16429#L778-42 assume 1 == ~t9_pc~0; 16279#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16281#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16697#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16604#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16605#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16659#L797-42 assume 1 == ~t10_pc~0; 15789#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 15790#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16677#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16678#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16698#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16699#L816-42 assume 1 == ~t11_pc~0; 15366#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15367#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17193#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16254#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 15966#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15967#L835-42 assume !(1 == ~t12_pc~0); 16290#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 16291#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16478#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16479#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17053#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16836#L854-42 assume 1 == ~t13_pc~0; 16837#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 15888#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 16054#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16055#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 16165#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16166#L1401-3 assume !(1 == ~M_E~0); 16951#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15718#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15593#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15594#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16215#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16216#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15760#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15761#L1436-3 assume !(1 == ~T8_E~0); 15378#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15379#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16977#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 16302#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 15934#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 15935#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17234#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15876#L1476-3 assume !(1 == ~E_3~0); 15877#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16299#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15904#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15905#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16336#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16337#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 16775#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16763#L1516-3 assume !(1 == ~E_11~0); 16764#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 16442#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 16443#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16858#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 15693#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 15740#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 15741#L1911 assume !(0 == start_simulation_~tmp~3#1); 16271#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16797#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 15832#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 15416#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 15417#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15540#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16300#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 17106#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 15952#L1892-2 [2022-12-13 12:58:11,875 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:11,875 INFO L85 PathProgramCache]: Analyzing trace with hash 1797695072, now seen corresponding path program 1 times [2022-12-13 12:58:11,875 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:11,875 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [865088747] [2022-12-13 12:58:11,875 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:11,875 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:11,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:11,912 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:11,912 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:11,912 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [865088747] [2022-12-13 12:58:11,913 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [865088747] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:11,913 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:11,913 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:11,913 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1620408358] [2022-12-13 12:58:11,913 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:11,913 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:58:11,913 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:11,913 INFO L85 PathProgramCache]: Analyzing trace with hash 500689105, now seen corresponding path program 1 times [2022-12-13 12:58:11,914 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:11,914 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1395875306] [2022-12-13 12:58:11,914 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:11,914 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:11,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:11,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:11,966 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:11,966 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1395875306] [2022-12-13 12:58:11,966 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1395875306] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:11,966 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:11,967 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:11,967 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [82420918] [2022-12-13 12:58:11,967 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:11,967 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:58:11,967 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:58:11,968 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:58:11,968 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:58:11,968 INFO L87 Difference]: Start difference. First operand 1914 states and 2832 transitions. cyclomatic complexity: 919 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:12,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:58:12,006 INFO L93 Difference]: Finished difference Result 1914 states and 2831 transitions. [2022-12-13 12:58:12,006 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2831 transitions. [2022-12-13 12:58:12,014 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 12:58:12,022 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2831 transitions. [2022-12-13 12:58:12,022 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-12-13 12:58:12,024 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-12-13 12:58:12,024 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2831 transitions. [2022-12-13 12:58:12,027 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:58:12,027 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2831 transitions. [2022-12-13 12:58:12,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2831 transitions. [2022-12-13 12:58:12,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-12-13 12:58:12,056 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4791013584117032) internal successors, (2831), 1913 states have internal predecessors, (2831), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:12,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2831 transitions. [2022-12-13 12:58:12,061 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2831 transitions. [2022-12-13 12:58:12,061 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:58:12,062 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2831 transitions. [2022-12-13 12:58:12,062 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-12-13 12:58:12,062 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2831 transitions. [2022-12-13 12:58:12,069 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 12:58:12,069 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:58:12,069 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:58:12,072 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:12,072 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:12,072 INFO L748 eck$LassoCheckResult]: Stem: 19474#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 19475#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 20369#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20370#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21091#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 20767#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20768#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19699#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19700#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20173#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 20011#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 20012#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19763#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19764#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20181#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20360#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 20528#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 20562#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 19779#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19780#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 20983#L1258-2 assume !(0 == ~T1_E~0); 20096#L1263-1 assume !(0 == ~T2_E~0); 20097#L1268-1 assume !(0 == ~T3_E~0); 20406#L1273-1 assume !(0 == ~T4_E~0); 20962#L1278-1 assume !(0 == ~T5_E~0); 20821#L1283-1 assume !(0 == ~T6_E~0); 20822#L1288-1 assume !(0 == ~T7_E~0); 21059#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21048#L1298-1 assume !(0 == ~T9_E~0); 20978#L1303-1 assume !(0 == ~T10_E~0); 19577#L1308-1 assume !(0 == ~T11_E~0); 19517#L1313-1 assume !(0 == ~T12_E~0); 19518#L1318-1 assume !(0 == ~T13_E~0); 19523#L1323-1 assume !(0 == ~E_1~0); 19524#L1328-1 assume !(0 == ~E_2~0); 19709#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 20697#L1338-1 assume !(0 == ~E_4~0); 20698#L1343-1 assume !(0 == ~E_5~0); 20798#L1348-1 assume !(0 == ~E_6~0); 21078#L1353-1 assume !(0 == ~E_7~0); 20429#L1358-1 assume !(0 == ~E_8~0); 20430#L1363-1 assume !(0 == ~E_9~0); 20719#L1368-1 assume !(0 == ~E_10~0); 19370#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 19371#L1378-1 assume !(0 == ~E_12~0); 19652#L1383-1 assume !(0 == ~E_13~0); 19653#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20434#L607 assume 1 == ~m_pc~0; 20435#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 19727#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20236#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20237#L1560 assume !(0 != activate_threads_~tmp~1#1); 20342#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19538#L626 assume !(1 == ~t1_pc~0); 19539#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19820#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19821#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20706#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 19442#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19443#L645 assume 1 == ~t2_pc~0; 19554#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19511#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19620#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19621#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 20316#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20317#L664 assume 1 == ~t3_pc~0; 21076#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19304#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19305#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19969#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 19970#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20991#L683 assume !(1 == ~t4_pc~0); 20546#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20499#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19328#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19329#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20654#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20259#L702 assume 1 == ~t5_pc~0; 20260#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20196#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20650#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20981#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 20889#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19340#L721 assume !(1 == ~t6_pc~0); 19321#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19322#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19466#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19605#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 19982#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20594#L740 assume 1 == ~t7_pc~0; 19386#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19221#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19222#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19211#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 19212#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19909#L759 assume !(1 == ~t8_pc~0); 19910#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19941#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21036#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20778#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 20779#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21058#L778 assume 1 == ~t9_pc~0; 20947#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19369#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19675#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19247#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 19248#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19550#L797 assume !(1 == ~t10_pc~0); 19551#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19685#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20924#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20092#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 20093#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20386#L816 assume 1 == ~t11_pc~0; 19282#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19283#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20225#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19988#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 19989#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20527#L835 assume 1 == ~t12_pc~0; 20401#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 19433#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19272#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19273#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 20145#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20146#L854 assume !(1 == ~t13_pc~0); 19765#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 19766#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 19815#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19464#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 19465#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20885#L1401 assume !(1 == ~M_E~0); 19975#L1401-2 assume !(1 == ~T1_E~0); 19976#L1406-1 assume !(1 == ~T2_E~0); 20583#L1411-1 assume !(1 == ~T3_E~0); 20584#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20235#L1421-1 assume !(1 == ~T5_E~0); 19761#L1426-1 assume !(1 == ~T6_E~0); 19762#L1431-1 assume !(1 == ~T7_E~0); 19319#L1436-1 assume !(1 == ~T8_E~0); 19320#L1441-1 assume !(1 == ~T9_E~0); 20083#L1446-1 assume !(1 == ~T10_E~0); 20084#L1451-1 assume !(1 == ~T11_E~0); 20795#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 20454#L1461-1 assume !(1 == ~T13_E~0); 20004#L1466-1 assume !(1 == ~E_1~0); 20005#L1471-1 assume !(1 == ~E_2~0); 20776#L1476-1 assume !(1 == ~E_3~0); 20777#L1481-1 assume !(1 == ~E_4~0); 20930#L1486-1 assume !(1 == ~E_5~0); 19590#L1491-1 assume !(1 == ~E_6~0); 19257#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19258#L1501-1 assume !(1 == ~E_8~0); 20079#L1506-1 assume !(1 == ~E_9~0); 20080#L1511-1 assume !(1 == ~E_10~0); 20034#L1516-1 assume !(1 == ~E_11~0); 19209#L1521-1 assume !(1 == ~E_12~0); 19210#L1526-1 assume !(1 == ~E_13~0); 19256#L1531-1 assume { :end_inline_reset_delta_events } true; 19787#L1892-2 [2022-12-13 12:58:12,072 INFO L750 eck$LassoCheckResult]: Loop: 19787#L1892-2 assume !false; 20837#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21035#L1233 assume !false; 21018#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20343#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20323#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20866#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 19298#L1046 assume !(0 != eval_~tmp~0#1); 19300#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19832#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19833#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21075#L1258-5 assume !(0 == ~T1_E~0); 19454#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19455#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21067#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21071#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21072#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19690#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19691#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20834#L1298-3 assume !(0 == ~T9_E~0); 20835#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 20998#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20833#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 20327#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 19456#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19457#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20922#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19601#L1338-3 assume !(0 == ~E_4~0); 19602#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20753#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20927#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20928#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20274#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19822#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19823#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 20614#L1378-3 assume !(0 == ~E_12~0); 20615#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 20792#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20793#L607-42 assume 1 == ~m_pc~0; 20411#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 20129#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19962#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19842#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19843#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20387#L626-42 assume 1 == ~t1_pc~0; 19933#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19934#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21022#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20808#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19490#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19491#L645-42 assume !(1 == ~t2_pc~0); 20733#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 20734#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20272#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19710#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19229#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19230#L664-42 assume !(1 == ~t3_pc~0); 19746#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 19747#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20673#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20560#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20561#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20726#L683-42 assume !(1 == ~t4_pc~0); 20437#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 20438#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20567#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20729#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20988#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20828#L702-42 assume 1 == ~t5_pc~0; 20304#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19924#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20228#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20337#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 19241#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19242#L721-42 assume 1 == ~t6_pc~0; 19381#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19402#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19581#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19582#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20060#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19897#L740-42 assume !(1 == ~t7_pc~0); 19616#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 19617#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20189#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20043#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20044#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20310#L759-42 assume 1 == ~t8_pc~0; 20165#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20102#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20103#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20174#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20175#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20264#L778-42 assume 1 == ~t9_pc~0; 20114#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20116#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20532#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20439#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20440#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20494#L797-42 assume 1 == ~t10_pc~0; 19624#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19625#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20512#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20513#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20533#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20534#L816-42 assume 1 == ~t11_pc~0; 19201#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19202#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21028#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20089#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 19801#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19802#L835-42 assume 1 == ~t12_pc~0; 20224#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20126#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20313#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20314#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 20888#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20671#L854-42 assume 1 == ~t13_pc~0; 20672#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 19723#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 19889#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19890#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 20000#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20001#L1401-3 assume !(1 == ~M_E~0); 20786#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19553#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19428#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19429#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20050#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20051#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19595#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19596#L1436-3 assume !(1 == ~T8_E~0); 19213#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19214#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 20812#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 20137#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 19769#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 19770#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21069#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19711#L1476-3 assume !(1 == ~E_3~0); 19712#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20134#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19739#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19740#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20171#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20172#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20610#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20598#L1516-3 assume !(1 == ~E_11~0); 20599#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 20277#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 20278#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20693#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 19528#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 19575#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 19576#L1911 assume !(0 == start_simulation_~tmp~3#1); 20106#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20632#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 19667#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 19251#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 19252#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19375#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20135#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 20941#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 19787#L1892-2 [2022-12-13 12:58:12,073 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:12,073 INFO L85 PathProgramCache]: Analyzing trace with hash 351114206, now seen corresponding path program 1 times [2022-12-13 12:58:12,073 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:12,073 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1445613291] [2022-12-13 12:58:12,073 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:12,074 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:12,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:12,122 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:12,123 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:12,123 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1445613291] [2022-12-13 12:58:12,123 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1445613291] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:12,123 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:12,123 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:12,123 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1221026487] [2022-12-13 12:58:12,123 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:12,124 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:58:12,124 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:12,124 INFO L85 PathProgramCache]: Analyzing trace with hash 199200465, now seen corresponding path program 1 times [2022-12-13 12:58:12,124 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:12,125 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1081588112] [2022-12-13 12:58:12,125 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:12,125 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:12,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:12,190 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:12,190 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:12,191 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1081588112] [2022-12-13 12:58:12,191 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1081588112] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:12,191 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:12,191 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:12,191 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [979471370] [2022-12-13 12:58:12,191 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:12,192 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:58:12,192 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:58:12,192 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:58:12,192 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:58:12,192 INFO L87 Difference]: Start difference. First operand 1914 states and 2831 transitions. cyclomatic complexity: 918 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:12,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:58:12,233 INFO L93 Difference]: Finished difference Result 1914 states and 2830 transitions. [2022-12-13 12:58:12,233 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2830 transitions. [2022-12-13 12:58:12,241 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 12:58:12,250 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2830 transitions. [2022-12-13 12:58:12,250 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-12-13 12:58:12,252 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-12-13 12:58:12,252 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2830 transitions. [2022-12-13 12:58:12,255 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:58:12,255 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2830 transitions. [2022-12-13 12:58:12,258 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2830 transitions. [2022-12-13 12:58:12,278 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-12-13 12:58:12,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4785788923719958) internal successors, (2830), 1913 states have internal predecessors, (2830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:12,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2830 transitions. [2022-12-13 12:58:12,286 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2830 transitions. [2022-12-13 12:58:12,287 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:58:12,287 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2830 transitions. [2022-12-13 12:58:12,287 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-12-13 12:58:12,287 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2830 transitions. [2022-12-13 12:58:12,294 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 12:58:12,294 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:58:12,294 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:58:12,296 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:12,296 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:12,297 INFO L748 eck$LassoCheckResult]: Stem: 23309#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 23310#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 24204#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24205#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24926#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 24602#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24603#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23534#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23535#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24008#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23846#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 23847#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23598#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 23599#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24016#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24195#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24363#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 24397#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 23614#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23615#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 24818#L1258-2 assume !(0 == ~T1_E~0); 23931#L1263-1 assume !(0 == ~T2_E~0); 23932#L1268-1 assume !(0 == ~T3_E~0); 24241#L1273-1 assume !(0 == ~T4_E~0); 24797#L1278-1 assume !(0 == ~T5_E~0); 24656#L1283-1 assume !(0 == ~T6_E~0); 24657#L1288-1 assume !(0 == ~T7_E~0); 24894#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24883#L1298-1 assume !(0 == ~T9_E~0); 24813#L1303-1 assume !(0 == ~T10_E~0); 23412#L1308-1 assume !(0 == ~T11_E~0); 23352#L1313-1 assume !(0 == ~T12_E~0); 23353#L1318-1 assume !(0 == ~T13_E~0); 23358#L1323-1 assume !(0 == ~E_1~0); 23359#L1328-1 assume !(0 == ~E_2~0); 23544#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 24532#L1338-1 assume !(0 == ~E_4~0); 24533#L1343-1 assume !(0 == ~E_5~0); 24633#L1348-1 assume !(0 == ~E_6~0); 24913#L1353-1 assume !(0 == ~E_7~0); 24264#L1358-1 assume !(0 == ~E_8~0); 24265#L1363-1 assume !(0 == ~E_9~0); 24554#L1368-1 assume !(0 == ~E_10~0); 23205#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 23206#L1378-1 assume !(0 == ~E_12~0); 23487#L1383-1 assume !(0 == ~E_13~0); 23488#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24269#L607 assume 1 == ~m_pc~0; 24270#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23562#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24071#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24072#L1560 assume !(0 != activate_threads_~tmp~1#1); 24177#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23373#L626 assume !(1 == ~t1_pc~0); 23374#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23655#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23656#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24541#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 23277#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23278#L645 assume 1 == ~t2_pc~0; 23389#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23346#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23455#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23456#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 24151#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24152#L664 assume 1 == ~t3_pc~0; 24911#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23139#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23140#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23804#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 23805#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24826#L683 assume !(1 == ~t4_pc~0); 24381#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24334#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23163#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23164#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24489#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24094#L702 assume 1 == ~t5_pc~0; 24095#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24031#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24485#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24816#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 24724#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23175#L721 assume !(1 == ~t6_pc~0); 23156#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 23157#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23301#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23440#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 23817#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24429#L740 assume 1 == ~t7_pc~0; 23221#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23056#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23057#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23046#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 23047#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23744#L759 assume !(1 == ~t8_pc~0); 23745#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 23776#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24871#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24613#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 24614#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24893#L778 assume 1 == ~t9_pc~0; 24782#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23204#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23510#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23082#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 23083#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23385#L797 assume !(1 == ~t10_pc~0); 23386#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 23520#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24759#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23927#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 23928#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24221#L816 assume 1 == ~t11_pc~0; 23117#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23118#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24060#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23823#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 23824#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24362#L835 assume 1 == ~t12_pc~0; 24236#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 23268#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 23107#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23108#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 23980#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 23981#L854 assume !(1 == ~t13_pc~0); 23600#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 23601#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 23650#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 23299#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 23300#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24720#L1401 assume !(1 == ~M_E~0); 23810#L1401-2 assume !(1 == ~T1_E~0); 23811#L1406-1 assume !(1 == ~T2_E~0); 24418#L1411-1 assume !(1 == ~T3_E~0); 24419#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24070#L1421-1 assume !(1 == ~T5_E~0); 23596#L1426-1 assume !(1 == ~T6_E~0); 23597#L1431-1 assume !(1 == ~T7_E~0); 23154#L1436-1 assume !(1 == ~T8_E~0); 23155#L1441-1 assume !(1 == ~T9_E~0); 23918#L1446-1 assume !(1 == ~T10_E~0); 23919#L1451-1 assume !(1 == ~T11_E~0); 24630#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 24289#L1461-1 assume !(1 == ~T13_E~0); 23839#L1466-1 assume !(1 == ~E_1~0); 23840#L1471-1 assume !(1 == ~E_2~0); 24611#L1476-1 assume !(1 == ~E_3~0); 24612#L1481-1 assume !(1 == ~E_4~0); 24765#L1486-1 assume !(1 == ~E_5~0); 23425#L1491-1 assume !(1 == ~E_6~0); 23092#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 23093#L1501-1 assume !(1 == ~E_8~0); 23914#L1506-1 assume !(1 == ~E_9~0); 23915#L1511-1 assume !(1 == ~E_10~0); 23869#L1516-1 assume !(1 == ~E_11~0); 23044#L1521-1 assume !(1 == ~E_12~0); 23045#L1526-1 assume !(1 == ~E_13~0); 23091#L1531-1 assume { :end_inline_reset_delta_events } true; 23622#L1892-2 [2022-12-13 12:58:12,297 INFO L750 eck$LassoCheckResult]: Loop: 23622#L1892-2 assume !false; 24672#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24870#L1233 assume !false; 24853#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24178#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24158#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24701#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 23133#L1046 assume !(0 != eval_~tmp~0#1); 23135#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23667#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23668#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 24910#L1258-5 assume !(0 == ~T1_E~0); 23289#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23290#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24902#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24906#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24907#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23525#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23526#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24669#L1298-3 assume !(0 == ~T9_E~0); 24670#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24833#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 24668#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 24162#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 23291#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23292#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24757#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23436#L1338-3 assume !(0 == ~E_4~0); 23437#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 24588#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24762#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24763#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24109#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 23657#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 23658#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24449#L1378-3 assume !(0 == ~E_12~0); 24450#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 24627#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24628#L607-42 assume 1 == ~m_pc~0; 24246#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23964#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23797#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23677#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 23678#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24222#L626-42 assume 1 == ~t1_pc~0; 23768#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23769#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24857#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24643#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23325#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23326#L645-42 assume !(1 == ~t2_pc~0); 24568#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 24569#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24107#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23545#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23064#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23065#L664-42 assume 1 == ~t3_pc~0; 23875#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23582#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24508#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24395#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24396#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24561#L683-42 assume !(1 == ~t4_pc~0); 24272#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 24273#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24402#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24564#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24823#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24663#L702-42 assume 1 == ~t5_pc~0; 24139#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23759#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24063#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24172#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 23076#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23077#L721-42 assume 1 == ~t6_pc~0; 23216#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23237#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23416#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23417#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23895#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23732#L740-42 assume 1 == ~t7_pc~0; 23733#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23452#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24024#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23878#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 23879#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24145#L759-42 assume 1 == ~t8_pc~0; 24000#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 23937#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23938#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24009#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24010#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24099#L778-42 assume 1 == ~t9_pc~0; 23949#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23951#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24367#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24274#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24275#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24329#L797-42 assume 1 == ~t10_pc~0; 23459#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 23460#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24347#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24348#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24368#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24369#L816-42 assume 1 == ~t11_pc~0; 23036#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23037#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24863#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23924#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 23636#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 23637#L835-42 assume !(1 == ~t12_pc~0); 23960#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 23961#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24148#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 24149#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 24723#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 24506#L854-42 assume !(1 == ~t13_pc~0); 23557#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 23558#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 23724#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 23725#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 23835#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23836#L1401-3 assume !(1 == ~M_E~0); 24621#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23388#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23263#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23264#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23885#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23886#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23430#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23431#L1436-3 assume !(1 == ~T8_E~0); 23048#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 23049#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 24647#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 23972#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 23604#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 23605#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24904#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23546#L1476-3 assume !(1 == ~E_3~0); 23547#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23969#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23574#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23575#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24006#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24007#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24445#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24433#L1516-3 assume !(1 == ~E_11~0); 24434#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 24112#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 24113#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24528#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 23363#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 23410#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 23411#L1911 assume !(0 == start_simulation_~tmp~3#1); 23941#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24467#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 23502#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 23086#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 23087#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23210#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23970#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 24776#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 23622#L1892-2 [2022-12-13 12:58:12,297 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:12,298 INFO L85 PathProgramCache]: Analyzing trace with hash 1274281632, now seen corresponding path program 1 times [2022-12-13 12:58:12,298 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:12,298 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [526261166] [2022-12-13 12:58:12,298 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:12,298 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:12,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:12,344 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:12,344 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:12,344 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [526261166] [2022-12-13 12:58:12,344 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [526261166] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:12,344 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:12,344 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:12,345 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1117223782] [2022-12-13 12:58:12,345 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:12,345 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:58:12,345 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:12,345 INFO L85 PathProgramCache]: Analyzing trace with hash -146866287, now seen corresponding path program 1 times [2022-12-13 12:58:12,346 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:12,346 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1362566797] [2022-12-13 12:58:12,346 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:12,346 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:12,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:12,407 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:12,407 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:12,407 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1362566797] [2022-12-13 12:58:12,407 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1362566797] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:12,407 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:12,407 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:12,407 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1264754046] [2022-12-13 12:58:12,408 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:12,408 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:58:12,408 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:58:12,408 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:58:12,408 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:58:12,409 INFO L87 Difference]: Start difference. First operand 1914 states and 2830 transitions. cyclomatic complexity: 917 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:12,452 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:58:12,452 INFO L93 Difference]: Finished difference Result 1914 states and 2829 transitions. [2022-12-13 12:58:12,453 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2829 transitions. [2022-12-13 12:58:12,462 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 12:58:12,471 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2829 transitions. [2022-12-13 12:58:12,471 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-12-13 12:58:12,472 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-12-13 12:58:12,473 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2829 transitions. [2022-12-13 12:58:12,476 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:58:12,476 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2829 transitions. [2022-12-13 12:58:12,479 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2829 transitions. [2022-12-13 12:58:12,503 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-12-13 12:58:12,506 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4780564263322884) internal successors, (2829), 1913 states have internal predecessors, (2829), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:12,510 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2829 transitions. [2022-12-13 12:58:12,511 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2829 transitions. [2022-12-13 12:58:12,511 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:58:12,511 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2829 transitions. [2022-12-13 12:58:12,512 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-12-13 12:58:12,512 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2829 transitions. [2022-12-13 12:58:12,517 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 12:58:12,517 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:58:12,517 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:58:12,520 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:12,520 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:12,520 INFO L748 eck$LassoCheckResult]: Stem: 27144#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 27145#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 28039#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28040#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28761#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 28437#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28438#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27369#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27370#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27843#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27681#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27682#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 27433#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 27434#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27851#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 28030#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 28198#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 28232#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 27449#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27450#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 28653#L1258-2 assume !(0 == ~T1_E~0); 27766#L1263-1 assume !(0 == ~T2_E~0); 27767#L1268-1 assume !(0 == ~T3_E~0); 28076#L1273-1 assume !(0 == ~T4_E~0); 28632#L1278-1 assume !(0 == ~T5_E~0); 28491#L1283-1 assume !(0 == ~T6_E~0); 28492#L1288-1 assume !(0 == ~T7_E~0); 28729#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28718#L1298-1 assume !(0 == ~T9_E~0); 28648#L1303-1 assume !(0 == ~T10_E~0); 27247#L1308-1 assume !(0 == ~T11_E~0); 27187#L1313-1 assume !(0 == ~T12_E~0); 27188#L1318-1 assume !(0 == ~T13_E~0); 27193#L1323-1 assume !(0 == ~E_1~0); 27194#L1328-1 assume !(0 == ~E_2~0); 27379#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 28367#L1338-1 assume !(0 == ~E_4~0); 28368#L1343-1 assume !(0 == ~E_5~0); 28468#L1348-1 assume !(0 == ~E_6~0); 28748#L1353-1 assume !(0 == ~E_7~0); 28099#L1358-1 assume !(0 == ~E_8~0); 28100#L1363-1 assume !(0 == ~E_9~0); 28389#L1368-1 assume !(0 == ~E_10~0); 27040#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 27041#L1378-1 assume !(0 == ~E_12~0); 27322#L1383-1 assume !(0 == ~E_13~0); 27323#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28104#L607 assume 1 == ~m_pc~0; 28105#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27397#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27906#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27907#L1560 assume !(0 != activate_threads_~tmp~1#1); 28012#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27208#L626 assume !(1 == ~t1_pc~0); 27209#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 27490#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27491#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28376#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 27112#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27113#L645 assume 1 == ~t2_pc~0; 27224#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27181#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27290#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27291#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 27986#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27987#L664 assume 1 == ~t3_pc~0; 28746#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26974#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26975#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27639#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 27640#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28661#L683 assume !(1 == ~t4_pc~0); 28216#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28169#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26998#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26999#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28324#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27929#L702 assume 1 == ~t5_pc~0; 27930#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27866#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28320#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28651#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 28559#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27010#L721 assume !(1 == ~t6_pc~0); 26991#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 26992#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27136#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27275#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 27652#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28264#L740 assume 1 == ~t7_pc~0; 27056#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26891#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26892#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26881#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 26882#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27579#L759 assume !(1 == ~t8_pc~0); 27580#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 27611#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28706#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28448#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 28449#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28728#L778 assume 1 == ~t9_pc~0; 28617#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27039#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27345#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26917#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 26918#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27220#L797 assume !(1 == ~t10_pc~0); 27221#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 27355#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28594#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 27762#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 27763#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28056#L816 assume 1 == ~t11_pc~0; 26952#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26953#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27895#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27658#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 27659#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28197#L835 assume 1 == ~t12_pc~0; 28071#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 27103#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 26942#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 26943#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 27815#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 27816#L854 assume !(1 == ~t13_pc~0); 27435#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 27436#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 27485#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 27134#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 27135#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28555#L1401 assume !(1 == ~M_E~0); 27645#L1401-2 assume !(1 == ~T1_E~0); 27646#L1406-1 assume !(1 == ~T2_E~0); 28253#L1411-1 assume !(1 == ~T3_E~0); 28254#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27905#L1421-1 assume !(1 == ~T5_E~0); 27431#L1426-1 assume !(1 == ~T6_E~0); 27432#L1431-1 assume !(1 == ~T7_E~0); 26989#L1436-1 assume !(1 == ~T8_E~0); 26990#L1441-1 assume !(1 == ~T9_E~0); 27753#L1446-1 assume !(1 == ~T10_E~0); 27754#L1451-1 assume !(1 == ~T11_E~0); 28465#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28124#L1461-1 assume !(1 == ~T13_E~0); 27674#L1466-1 assume !(1 == ~E_1~0); 27675#L1471-1 assume !(1 == ~E_2~0); 28446#L1476-1 assume !(1 == ~E_3~0); 28447#L1481-1 assume !(1 == ~E_4~0); 28600#L1486-1 assume !(1 == ~E_5~0); 27260#L1491-1 assume !(1 == ~E_6~0); 26927#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 26928#L1501-1 assume !(1 == ~E_8~0); 27749#L1506-1 assume !(1 == ~E_9~0); 27750#L1511-1 assume !(1 == ~E_10~0); 27704#L1516-1 assume !(1 == ~E_11~0); 26879#L1521-1 assume !(1 == ~E_12~0); 26880#L1526-1 assume !(1 == ~E_13~0); 26926#L1531-1 assume { :end_inline_reset_delta_events } true; 27457#L1892-2 [2022-12-13 12:58:12,521 INFO L750 eck$LassoCheckResult]: Loop: 27457#L1892-2 assume !false; 28507#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28705#L1233 assume !false; 28688#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28013#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27993#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28536#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 26968#L1046 assume !(0 != eval_~tmp~0#1); 26970#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27502#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27503#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28745#L1258-5 assume !(0 == ~T1_E~0); 27124#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27125#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28737#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28741#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28742#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27360#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27361#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28504#L1298-3 assume !(0 == ~T9_E~0); 28505#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28668#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 28503#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 27997#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 27126#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27127#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28592#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27271#L1338-3 assume !(0 == ~E_4~0); 27272#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28423#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28597#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28598#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27944#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 27492#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 27493#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28284#L1378-3 assume !(0 == ~E_12~0); 28285#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 28462#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28463#L607-42 assume 1 == ~m_pc~0; 28081#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27799#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27632#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27512#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27513#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28057#L626-42 assume 1 == ~t1_pc~0; 27603#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27604#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28692#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28478#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 27160#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27161#L645-42 assume !(1 == ~t2_pc~0); 28403#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 28404#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27942#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27380#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26899#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26900#L664-42 assume !(1 == ~t3_pc~0); 27416#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 27417#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28343#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28230#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28231#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28396#L683-42 assume 1 == ~t4_pc~0; 28753#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28108#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28237#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28399#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28658#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28498#L702-42 assume 1 == ~t5_pc~0; 27974#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27594#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27898#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28007#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 26911#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26912#L721-42 assume 1 == ~t6_pc~0; 27051#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27072#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27251#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27252#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27730#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27567#L740-42 assume 1 == ~t7_pc~0; 27568#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27287#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27859#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27713#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27714#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27980#L759-42 assume 1 == ~t8_pc~0; 27835#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27772#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27773#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27844#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27845#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27934#L778-42 assume 1 == ~t9_pc~0; 27784#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27786#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28202#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28109#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28110#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28164#L797-42 assume !(1 == ~t10_pc~0); 27296#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 27295#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28182#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28183#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28203#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28204#L816-42 assume 1 == ~t11_pc~0; 26871#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26872#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28698#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27759#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 27471#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 27472#L835-42 assume !(1 == ~t12_pc~0); 27795#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 27796#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 27983#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 27984#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 28558#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 28341#L854-42 assume !(1 == ~t13_pc~0); 27392#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 27393#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 27559#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 27560#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 27670#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27671#L1401-3 assume !(1 == ~M_E~0); 28456#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27223#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27098#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27099#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27720#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27721#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27265#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27266#L1436-3 assume !(1 == ~T8_E~0); 26883#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 26884#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28482#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 27807#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 27439#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 27440#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28739#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27381#L1476-3 assume !(1 == ~E_3~0); 27382#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27804#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27409#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27410#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27841#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27842#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28280#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 28268#L1516-3 assume !(1 == ~E_11~0); 28269#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 27947#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 27948#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28363#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27198#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 27245#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 27246#L1911 assume !(0 == start_simulation_~tmp~3#1); 27776#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28302#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27337#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 26921#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 26922#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27045#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27805#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 28611#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 27457#L1892-2 [2022-12-13 12:58:12,521 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:12,521 INFO L85 PathProgramCache]: Analyzing trace with hash 888419230, now seen corresponding path program 1 times [2022-12-13 12:58:12,521 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:12,522 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [290538739] [2022-12-13 12:58:12,522 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:12,522 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:12,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:12,565 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:12,565 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:12,566 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [290538739] [2022-12-13 12:58:12,566 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [290538739] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:12,566 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:12,566 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:12,566 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1134638624] [2022-12-13 12:58:12,566 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:12,567 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:58:12,567 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:12,567 INFO L85 PathProgramCache]: Analyzing trace with hash 1882431728, now seen corresponding path program 1 times [2022-12-13 12:58:12,567 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:12,567 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1086642020] [2022-12-13 12:58:12,568 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:12,568 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:12,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:12,610 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:12,611 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:12,611 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1086642020] [2022-12-13 12:58:12,611 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1086642020] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:12,611 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:12,611 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:12,611 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [14016036] [2022-12-13 12:58:12,611 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:12,612 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:58:12,612 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:58:12,612 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:58:12,612 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:58:12,612 INFO L87 Difference]: Start difference. First operand 1914 states and 2829 transitions. cyclomatic complexity: 916 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:12,638 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:58:12,638 INFO L93 Difference]: Finished difference Result 1914 states and 2828 transitions. [2022-12-13 12:58:12,638 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2828 transitions. [2022-12-13 12:58:12,644 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 12:58:12,648 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2828 transitions. [2022-12-13 12:58:12,648 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-12-13 12:58:12,650 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-12-13 12:58:12,650 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2828 transitions. [2022-12-13 12:58:12,652 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:58:12,652 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2828 transitions. [2022-12-13 12:58:12,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2828 transitions. [2022-12-13 12:58:12,668 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-12-13 12:58:12,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.477533960292581) internal successors, (2828), 1913 states have internal predecessors, (2828), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:12,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2828 transitions. [2022-12-13 12:58:12,673 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2828 transitions. [2022-12-13 12:58:12,673 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:58:12,674 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2828 transitions. [2022-12-13 12:58:12,674 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-12-13 12:58:12,674 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2828 transitions. [2022-12-13 12:58:12,680 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 12:58:12,680 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:58:12,681 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:58:12,682 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:12,682 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:12,683 INFO L748 eck$LassoCheckResult]: Stem: 30979#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 30980#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 31874#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31875#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32596#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 32272#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32273#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31204#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31205#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31678#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31516#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 31517#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 31268#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 31269#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 31686#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 31865#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 32033#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 32067#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 31284#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31285#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 32488#L1258-2 assume !(0 == ~T1_E~0); 31601#L1263-1 assume !(0 == ~T2_E~0); 31602#L1268-1 assume !(0 == ~T3_E~0); 31911#L1273-1 assume !(0 == ~T4_E~0); 32467#L1278-1 assume !(0 == ~T5_E~0); 32326#L1283-1 assume !(0 == ~T6_E~0); 32327#L1288-1 assume !(0 == ~T7_E~0); 32564#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32553#L1298-1 assume !(0 == ~T9_E~0); 32483#L1303-1 assume !(0 == ~T10_E~0); 31082#L1308-1 assume !(0 == ~T11_E~0); 31022#L1313-1 assume !(0 == ~T12_E~0); 31023#L1318-1 assume !(0 == ~T13_E~0); 31028#L1323-1 assume !(0 == ~E_1~0); 31029#L1328-1 assume !(0 == ~E_2~0); 31214#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 32202#L1338-1 assume !(0 == ~E_4~0); 32203#L1343-1 assume !(0 == ~E_5~0); 32303#L1348-1 assume !(0 == ~E_6~0); 32583#L1353-1 assume !(0 == ~E_7~0); 31934#L1358-1 assume !(0 == ~E_8~0); 31935#L1363-1 assume !(0 == ~E_9~0); 32224#L1368-1 assume !(0 == ~E_10~0); 30875#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 30876#L1378-1 assume !(0 == ~E_12~0); 31157#L1383-1 assume !(0 == ~E_13~0); 31158#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31939#L607 assume 1 == ~m_pc~0; 31940#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31232#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31741#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31742#L1560 assume !(0 != activate_threads_~tmp~1#1); 31847#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31043#L626 assume !(1 == ~t1_pc~0); 31044#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31325#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31326#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32211#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 30947#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30948#L645 assume 1 == ~t2_pc~0; 31059#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31016#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31125#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31126#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 31821#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31822#L664 assume 1 == ~t3_pc~0; 32581#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30809#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30810#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31474#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 31475#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32496#L683 assume !(1 == ~t4_pc~0); 32051#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 32004#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30833#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30834#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32159#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31764#L702 assume 1 == ~t5_pc~0; 31765#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31701#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32155#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32486#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 32394#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30845#L721 assume !(1 == ~t6_pc~0); 30826#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 30827#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30971#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31110#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 31487#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32099#L740 assume 1 == ~t7_pc~0; 30891#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30726#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30727#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30716#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 30717#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31414#L759 assume !(1 == ~t8_pc~0); 31415#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 31446#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32541#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32283#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 32284#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32563#L778 assume 1 == ~t9_pc~0; 32452#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30874#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31180#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30752#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 30753#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31055#L797 assume !(1 == ~t10_pc~0); 31056#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 31190#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32429#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 31597#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 31598#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 31891#L816 assume 1 == ~t11_pc~0; 30787#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 30788#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31730#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31493#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 31494#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32032#L835 assume 1 == ~t12_pc~0; 31906#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 30938#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30777#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 30778#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 31650#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 31651#L854 assume !(1 == ~t13_pc~0); 31270#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 31271#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 31320#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 30969#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 30970#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32390#L1401 assume !(1 == ~M_E~0); 31480#L1401-2 assume !(1 == ~T1_E~0); 31481#L1406-1 assume !(1 == ~T2_E~0); 32088#L1411-1 assume !(1 == ~T3_E~0); 32089#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31740#L1421-1 assume !(1 == ~T5_E~0); 31266#L1426-1 assume !(1 == ~T6_E~0); 31267#L1431-1 assume !(1 == ~T7_E~0); 30824#L1436-1 assume !(1 == ~T8_E~0); 30825#L1441-1 assume !(1 == ~T9_E~0); 31588#L1446-1 assume !(1 == ~T10_E~0); 31589#L1451-1 assume !(1 == ~T11_E~0); 32300#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 31959#L1461-1 assume !(1 == ~T13_E~0); 31509#L1466-1 assume !(1 == ~E_1~0); 31510#L1471-1 assume !(1 == ~E_2~0); 32281#L1476-1 assume !(1 == ~E_3~0); 32282#L1481-1 assume !(1 == ~E_4~0); 32435#L1486-1 assume !(1 == ~E_5~0); 31095#L1491-1 assume !(1 == ~E_6~0); 30762#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 30763#L1501-1 assume !(1 == ~E_8~0); 31584#L1506-1 assume !(1 == ~E_9~0); 31585#L1511-1 assume !(1 == ~E_10~0); 31539#L1516-1 assume !(1 == ~E_11~0); 30714#L1521-1 assume !(1 == ~E_12~0); 30715#L1526-1 assume !(1 == ~E_13~0); 30761#L1531-1 assume { :end_inline_reset_delta_events } true; 31292#L1892-2 [2022-12-13 12:58:12,683 INFO L750 eck$LassoCheckResult]: Loop: 31292#L1892-2 assume !false; 32342#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32540#L1233 assume !false; 32523#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 31848#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31828#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 32371#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30803#L1046 assume !(0 != eval_~tmp~0#1); 30805#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31337#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31338#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 32580#L1258-5 assume !(0 == ~T1_E~0); 30959#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30960#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32572#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32576#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32577#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 31195#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31196#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32339#L1298-3 assume !(0 == ~T9_E~0); 32340#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32503#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32338#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 31832#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 30961#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30962#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32427#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31106#L1338-3 assume !(0 == ~E_4~0); 31107#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32258#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32432#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 32433#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 31779#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 31327#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31328#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32119#L1378-3 assume !(0 == ~E_12~0); 32120#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 32297#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32298#L607-42 assume 1 == ~m_pc~0; 31916#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31634#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31467#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31347#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31348#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31892#L626-42 assume !(1 == ~t1_pc~0); 31440#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 31439#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32527#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32313#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30995#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30996#L645-42 assume !(1 == ~t2_pc~0); 32238#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 32239#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31777#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31215#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30734#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30735#L664-42 assume !(1 == ~t3_pc~0); 31251#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 31252#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32178#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32065#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32066#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32231#L683-42 assume !(1 == ~t4_pc~0); 31942#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 31943#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32072#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32234#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32493#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32333#L702-42 assume 1 == ~t5_pc~0; 31809#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31429#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31733#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31842#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 30746#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30747#L721-42 assume 1 == ~t6_pc~0; 30886#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30907#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31086#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31087#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 31565#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31402#L740-42 assume !(1 == ~t7_pc~0); 31121#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 31122#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31694#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 31548#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 31549#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31815#L759-42 assume 1 == ~t8_pc~0; 31670#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31607#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31608#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 31679#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 31680#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31769#L778-42 assume 1 == ~t9_pc~0; 31619#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31621#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32037#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31944#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 31945#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31999#L797-42 assume 1 == ~t10_pc~0; 31129#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 31130#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32017#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32018#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32038#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32039#L816-42 assume 1 == ~t11_pc~0; 30706#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 30707#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32533#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31594#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 31306#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 31307#L835-42 assume 1 == ~t12_pc~0; 31729#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 31631#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 31818#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 31819#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 32393#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 32176#L854-42 assume 1 == ~t13_pc~0; 32177#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 31228#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 31394#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 31395#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 31505#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31506#L1401-3 assume !(1 == ~M_E~0); 32291#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31058#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30933#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30934#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31555#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31556#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 31100#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 31101#L1436-3 assume !(1 == ~T8_E~0); 30718#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30719#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32317#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31642#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 31274#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 31275#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32574#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 31216#L1476-3 assume !(1 == ~E_3~0); 31217#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31639#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31244#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 31245#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 31676#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 31677#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32115#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32103#L1516-3 assume !(1 == ~E_11~0); 32104#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 31782#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 31783#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32198#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31033#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 31080#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 31081#L1911 assume !(0 == start_simulation_~tmp~3#1); 31611#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32137#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31172#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 30756#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 30757#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30880#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31640#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 32446#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 31292#L1892-2 [2022-12-13 12:58:12,683 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:12,683 INFO L85 PathProgramCache]: Analyzing trace with hash 1153066720, now seen corresponding path program 1 times [2022-12-13 12:58:12,683 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:12,683 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [896189662] [2022-12-13 12:58:12,684 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:12,684 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:12,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:12,722 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:12,722 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:12,722 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [896189662] [2022-12-13 12:58:12,722 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [896189662] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:12,722 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:12,723 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:12,723 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1958436668] [2022-12-13 12:58:12,723 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:12,723 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:58:12,723 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:12,723 INFO L85 PathProgramCache]: Analyzing trace with hash -678054352, now seen corresponding path program 1 times [2022-12-13 12:58:12,723 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:12,724 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [862220015] [2022-12-13 12:58:12,724 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:12,724 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:12,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:12,761 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:12,762 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:12,762 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [862220015] [2022-12-13 12:58:12,762 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [862220015] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:12,762 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:12,762 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:12,762 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1799544234] [2022-12-13 12:58:12,762 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:12,763 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:58:12,763 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:58:12,763 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:58:12,763 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:58:12,763 INFO L87 Difference]: Start difference. First operand 1914 states and 2828 transitions. cyclomatic complexity: 915 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:12,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:58:12,787 INFO L93 Difference]: Finished difference Result 1914 states and 2827 transitions. [2022-12-13 12:58:12,787 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2827 transitions. [2022-12-13 12:58:12,792 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 12:58:12,797 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2827 transitions. [2022-12-13 12:58:12,797 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-12-13 12:58:12,798 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-12-13 12:58:12,798 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2827 transitions. [2022-12-13 12:58:12,800 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:58:12,800 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2827 transitions. [2022-12-13 12:58:12,802 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2827 transitions. [2022-12-13 12:58:12,816 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-12-13 12:58:12,818 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4770114942528736) internal successors, (2827), 1913 states have internal predecessors, (2827), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:12,821 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2827 transitions. [2022-12-13 12:58:12,821 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2827 transitions. [2022-12-13 12:58:12,821 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:58:12,822 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2827 transitions. [2022-12-13 12:58:12,822 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-12-13 12:58:12,822 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2827 transitions. [2022-12-13 12:58:12,828 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 12:58:12,828 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:58:12,828 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:58:12,830 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:12,830 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:12,830 INFO L748 eck$LassoCheckResult]: Stem: 34814#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 34815#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 35710#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35711#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36431#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 36107#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36108#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35039#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35040#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35515#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35351#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35352#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35103#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 35104#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 35521#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 35700#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 35868#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 35903#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 35119#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35120#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 36323#L1258-2 assume !(0 == ~T1_E~0); 35436#L1263-1 assume !(0 == ~T2_E~0); 35437#L1268-1 assume !(0 == ~T3_E~0); 35746#L1273-1 assume !(0 == ~T4_E~0); 36302#L1278-1 assume !(0 == ~T5_E~0); 36161#L1283-1 assume !(0 == ~T6_E~0); 36162#L1288-1 assume !(0 == ~T7_E~0); 36400#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36388#L1298-1 assume !(0 == ~T9_E~0); 36318#L1303-1 assume !(0 == ~T10_E~0); 34917#L1308-1 assume !(0 == ~T11_E~0); 34860#L1313-1 assume !(0 == ~T12_E~0); 34861#L1318-1 assume !(0 == ~T13_E~0); 34865#L1323-1 assume !(0 == ~E_1~0); 34866#L1328-1 assume !(0 == ~E_2~0); 35049#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 36037#L1338-1 assume !(0 == ~E_4~0); 36038#L1343-1 assume !(0 == ~E_5~0); 36138#L1348-1 assume !(0 == ~E_6~0); 36418#L1353-1 assume !(0 == ~E_7~0); 35769#L1358-1 assume !(0 == ~E_8~0); 35770#L1363-1 assume !(0 == ~E_9~0); 36059#L1368-1 assume !(0 == ~E_10~0); 34710#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 34711#L1378-1 assume !(0 == ~E_12~0); 34994#L1383-1 assume !(0 == ~E_13~0); 34995#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35774#L607 assume 1 == ~m_pc~0; 35775#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35069#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35579#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35580#L1560 assume !(0 != activate_threads_~tmp~1#1); 35682#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34878#L626 assume !(1 == ~t1_pc~0); 34879#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 35162#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35163#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36046#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 34783#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34784#L645 assume 1 == ~t2_pc~0; 34896#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34851#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34962#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34963#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 35656#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35657#L664 assume 1 == ~t3_pc~0; 36416#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34648#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34649#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35309#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 35310#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36331#L683 assume !(1 == ~t4_pc~0); 35886#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 35839#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34668#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34669#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35994#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35603#L702 assume 1 == ~t5_pc~0; 35604#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35537#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35990#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36321#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 36230#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34684#L721 assume !(1 == ~t6_pc~0); 34661#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 34662#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34806#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34945#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 35322#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35934#L740 assume 1 == ~t7_pc~0; 34726#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34561#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34562#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34551#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 34552#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35250#L759 assume !(1 == ~t8_pc~0); 35251#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 35281#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36379#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36118#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 36119#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36398#L778 assume 1 == ~t9_pc~0; 36289#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34709#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35015#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34587#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 34588#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34891#L797 assume !(1 == ~t10_pc~0); 34892#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 35025#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36264#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35432#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 35433#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35726#L816 assume 1 == ~t11_pc~0; 34624#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34625#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35567#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35328#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 35329#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 35867#L835 assume 1 == ~t12_pc~0; 35741#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 34773#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34612#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34613#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 35485#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 35486#L854 assume !(1 == ~t13_pc~0); 35105#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 35106#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 35157#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34804#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 34805#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36225#L1401 assume !(1 == ~M_E~0); 35315#L1401-2 assume !(1 == ~T1_E~0); 35316#L1406-1 assume !(1 == ~T2_E~0); 35923#L1411-1 assume !(1 == ~T3_E~0); 35924#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35575#L1421-1 assume !(1 == ~T5_E~0); 35101#L1426-1 assume !(1 == ~T6_E~0); 35102#L1431-1 assume !(1 == ~T7_E~0); 34659#L1436-1 assume !(1 == ~T8_E~0); 34660#L1441-1 assume !(1 == ~T9_E~0); 35423#L1446-1 assume !(1 == ~T10_E~0); 35424#L1451-1 assume !(1 == ~T11_E~0); 36135#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35794#L1461-1 assume !(1 == ~T13_E~0); 35344#L1466-1 assume !(1 == ~E_1~0); 35345#L1471-1 assume !(1 == ~E_2~0); 36116#L1476-1 assume !(1 == ~E_3~0); 36117#L1481-1 assume !(1 == ~E_4~0); 36270#L1486-1 assume !(1 == ~E_5~0); 34930#L1491-1 assume !(1 == ~E_6~0); 34597#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 34598#L1501-1 assume !(1 == ~E_8~0); 35419#L1506-1 assume !(1 == ~E_9~0); 35420#L1511-1 assume !(1 == ~E_10~0); 35374#L1516-1 assume !(1 == ~E_11~0); 34549#L1521-1 assume !(1 == ~E_12~0); 34550#L1526-1 assume !(1 == ~E_13~0); 34596#L1531-1 assume { :end_inline_reset_delta_events } true; 35127#L1892-2 [2022-12-13 12:58:12,831 INFO L750 eck$LassoCheckResult]: Loop: 35127#L1892-2 assume !false; 36177#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36375#L1233 assume !false; 36358#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 35683#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35663#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 36206#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 34638#L1046 assume !(0 != eval_~tmp~0#1); 34640#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35172#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35173#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 36415#L1258-5 assume !(0 == ~T1_E~0); 34794#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34795#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36407#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36411#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36412#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35030#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 35031#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36174#L1298-3 assume !(0 == ~T9_E~0); 36175#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36338#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36173#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 35667#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 34796#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 34797#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36262#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34941#L1338-3 assume !(0 == ~E_4~0); 34942#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36093#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36267#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36268#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35614#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35160#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 35161#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 35954#L1378-3 assume !(0 == ~E_12~0); 35955#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 36132#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36133#L607-42 assume 1 == ~m_pc~0; 35751#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35469#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35302#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35182#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35183#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35727#L626-42 assume 1 == ~t1_pc~0; 35273#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35274#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36362#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36148#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34830#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34831#L645-42 assume !(1 == ~t2_pc~0); 36073#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 36074#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35612#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35050#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34569#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34570#L664-42 assume 1 == ~t3_pc~0; 35380#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 35087#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36013#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35900#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 35901#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36066#L683-42 assume !(1 == ~t4_pc~0); 35777#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 35778#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35907#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36069#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36328#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36168#L702-42 assume 1 == ~t5_pc~0; 35644#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35264#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35568#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35677#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 34581#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34582#L721-42 assume 1 == ~t6_pc~0; 34721#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 34742#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34921#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34922#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35400#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35237#L740-42 assume 1 == ~t7_pc~0; 35238#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34957#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35529#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35383#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35384#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35650#L759-42 assume 1 == ~t8_pc~0; 35505#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35442#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35443#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35513#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35514#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35602#L778-42 assume 1 == ~t9_pc~0; 35454#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35456#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35872#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35779#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35780#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35834#L797-42 assume 1 == ~t10_pc~0; 34964#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 34965#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35852#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35853#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35873#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35874#L816-42 assume 1 == ~t11_pc~0; 34541#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34542#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36368#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35429#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35141#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 35142#L835-42 assume !(1 == ~t12_pc~0); 35465#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 35466#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35653#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 35654#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 36228#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 36011#L854-42 assume !(1 == ~t13_pc~0); 35062#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 35063#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 35229#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 35230#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 35340#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35341#L1401-3 assume !(1 == ~M_E~0); 36126#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34890#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34768#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34769#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35390#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 35391#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34935#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34936#L1436-3 assume !(1 == ~T8_E~0); 34553#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34554#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36152#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35477#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35109#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 35110#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36409#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35051#L1476-3 assume !(1 == ~E_3~0); 35052#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 35474#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35079#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35080#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35511#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 35512#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 35950#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 35938#L1516-3 assume !(1 == ~E_11~0); 35939#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 35617#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 35618#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36033#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 34868#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 34915#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 34916#L1911 assume !(0 == start_simulation_~tmp~3#1); 35446#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 35972#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35007#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 34591#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 34592#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34715#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35475#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 36281#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 35127#L1892-2 [2022-12-13 12:58:12,831 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:12,831 INFO L85 PathProgramCache]: Analyzing trace with hash -778058914, now seen corresponding path program 1 times [2022-12-13 12:58:12,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:12,831 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [559670177] [2022-12-13 12:58:12,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:12,832 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:12,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:12,865 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:12,865 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:12,865 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [559670177] [2022-12-13 12:58:12,866 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [559670177] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:12,866 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:12,866 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:12,866 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1223890807] [2022-12-13 12:58:12,866 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:12,866 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:58:12,867 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:12,867 INFO L85 PathProgramCache]: Analyzing trace with hash -146866287, now seen corresponding path program 2 times [2022-12-13 12:58:12,867 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:12,867 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1024679611] [2022-12-13 12:58:12,867 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:12,867 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:12,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:12,906 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:12,907 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:12,907 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1024679611] [2022-12-13 12:58:12,907 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1024679611] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:12,907 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:12,907 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:12,907 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [808705237] [2022-12-13 12:58:12,907 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:12,908 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:58:12,908 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:58:12,908 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:58:12,908 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:58:12,909 INFO L87 Difference]: Start difference. First operand 1914 states and 2827 transitions. cyclomatic complexity: 914 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:12,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:58:12,933 INFO L93 Difference]: Finished difference Result 1914 states and 2826 transitions. [2022-12-13 12:58:12,933 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2826 transitions. [2022-12-13 12:58:12,938 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 12:58:12,942 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2826 transitions. [2022-12-13 12:58:12,942 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-12-13 12:58:12,943 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-12-13 12:58:12,943 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2826 transitions. [2022-12-13 12:58:12,945 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:58:12,945 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2826 transitions. [2022-12-13 12:58:12,947 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2826 transitions. [2022-12-13 12:58:12,964 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-12-13 12:58:12,966 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4764890282131662) internal successors, (2826), 1913 states have internal predecessors, (2826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:12,968 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2826 transitions. [2022-12-13 12:58:12,968 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2826 transitions. [2022-12-13 12:58:12,969 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:58:12,969 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2826 transitions. [2022-12-13 12:58:12,969 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-12-13 12:58:12,969 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2826 transitions. [2022-12-13 12:58:12,976 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 12:58:12,976 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:58:12,976 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:58:12,977 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:12,977 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:12,978 INFO L748 eck$LassoCheckResult]: Stem: 38649#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 38650#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 39545#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39546#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 40266#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 39942#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39943#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38874#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38875#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39350#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39186#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 39187#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38938#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 38939#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 39356#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 39535#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 39703#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 39738#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 38954#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38955#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 40158#L1258-2 assume !(0 == ~T1_E~0); 39271#L1263-1 assume !(0 == ~T2_E~0); 39272#L1268-1 assume !(0 == ~T3_E~0); 39581#L1273-1 assume !(0 == ~T4_E~0); 40137#L1278-1 assume !(0 == ~T5_E~0); 39996#L1283-1 assume !(0 == ~T6_E~0); 39997#L1288-1 assume !(0 == ~T7_E~0); 40235#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40223#L1298-1 assume !(0 == ~T9_E~0); 40153#L1303-1 assume !(0 == ~T10_E~0); 38752#L1308-1 assume !(0 == ~T11_E~0); 38692#L1313-1 assume !(0 == ~T12_E~0); 38693#L1318-1 assume !(0 == ~T13_E~0); 38700#L1323-1 assume !(0 == ~E_1~0); 38701#L1328-1 assume !(0 == ~E_2~0); 38884#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 39872#L1338-1 assume !(0 == ~E_4~0); 39873#L1343-1 assume !(0 == ~E_5~0); 39973#L1348-1 assume !(0 == ~E_6~0); 40253#L1353-1 assume !(0 == ~E_7~0); 39604#L1358-1 assume !(0 == ~E_8~0); 39605#L1363-1 assume !(0 == ~E_9~0); 39894#L1368-1 assume !(0 == ~E_10~0); 38545#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 38546#L1378-1 assume !(0 == ~E_12~0); 38829#L1383-1 assume !(0 == ~E_13~0); 38830#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39609#L607 assume 1 == ~m_pc~0; 39610#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 38904#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39414#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39415#L1560 assume !(0 != activate_threads_~tmp~1#1); 39517#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38713#L626 assume !(1 == ~t1_pc~0); 38714#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 38997#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38998#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39881#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 38617#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38618#L645 assume 1 == ~t2_pc~0; 38731#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38686#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38797#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38798#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 39491#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39492#L664 assume 1 == ~t3_pc~0; 40251#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38483#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38484#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39144#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 39145#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40166#L683 assume !(1 == ~t4_pc~0); 39721#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 39674#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38503#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38504#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 39829#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39438#L702 assume 1 == ~t5_pc~0; 39439#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39372#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39825#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40156#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 40065#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38519#L721 assume !(1 == ~t6_pc~0); 38496#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 38497#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38641#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38780#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 39157#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39769#L740 assume 1 == ~t7_pc~0; 38561#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38396#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38397#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38386#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 38387#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39085#L759 assume !(1 == ~t8_pc~0); 39086#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 39116#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40213#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39953#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 39954#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40233#L778 assume 1 == ~t9_pc~0; 40124#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38544#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38850#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38422#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 38423#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38726#L797 assume !(1 == ~t10_pc~0); 38727#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 38860#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40099#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39267#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 39268#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39561#L816 assume 1 == ~t11_pc~0; 38459#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38460#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39402#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39163#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 39164#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 39702#L835 assume 1 == ~t12_pc~0; 39576#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 38608#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38447#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38448#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 39320#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 39321#L854 assume !(1 == ~t13_pc~0); 38940#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 38941#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 38992#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38639#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 38640#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40060#L1401 assume !(1 == ~M_E~0); 39150#L1401-2 assume !(1 == ~T1_E~0); 39151#L1406-1 assume !(1 == ~T2_E~0); 39758#L1411-1 assume !(1 == ~T3_E~0); 39759#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39410#L1421-1 assume !(1 == ~T5_E~0); 38936#L1426-1 assume !(1 == ~T6_E~0); 38937#L1431-1 assume !(1 == ~T7_E~0); 38494#L1436-1 assume !(1 == ~T8_E~0); 38495#L1441-1 assume !(1 == ~T9_E~0); 39260#L1446-1 assume !(1 == ~T10_E~0); 39261#L1451-1 assume !(1 == ~T11_E~0); 39970#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 39629#L1461-1 assume !(1 == ~T13_E~0); 39179#L1466-1 assume !(1 == ~E_1~0); 39180#L1471-1 assume !(1 == ~E_2~0); 39951#L1476-1 assume !(1 == ~E_3~0); 39952#L1481-1 assume !(1 == ~E_4~0); 40105#L1486-1 assume !(1 == ~E_5~0); 38765#L1491-1 assume !(1 == ~E_6~0); 38432#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 38433#L1501-1 assume !(1 == ~E_8~0); 39254#L1506-1 assume !(1 == ~E_9~0); 39255#L1511-1 assume !(1 == ~E_10~0); 39209#L1516-1 assume !(1 == ~E_11~0); 38384#L1521-1 assume !(1 == ~E_12~0); 38385#L1526-1 assume !(1 == ~E_13~0); 38431#L1531-1 assume { :end_inline_reset_delta_events } true; 38962#L1892-2 [2022-12-13 12:58:12,978 INFO L750 eck$LassoCheckResult]: Loop: 38962#L1892-2 assume !false; 40012#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40210#L1233 assume !false; 40193#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 39518#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 39498#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 40041#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 38473#L1046 assume !(0 != eval_~tmp~0#1); 38475#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 39008#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 39009#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40250#L1258-5 assume !(0 == ~T1_E~0); 38631#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38632#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40242#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40246#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40247#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 38865#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 38866#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40009#L1298-3 assume !(0 == ~T9_E~0); 40010#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 40173#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 40008#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 39502#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 38633#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 38634#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40097#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38774#L1338-3 assume !(0 == ~E_4~0); 38775#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 39928#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 40102#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40103#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 39449#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 38995#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 38996#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 39789#L1378-3 assume !(0 == ~E_12~0); 39790#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 39967#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39968#L607-42 assume 1 == ~m_pc~0; 39586#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 39304#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39137#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39017#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39018#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39562#L626-42 assume 1 == ~t1_pc~0; 39108#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 39109#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40197#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39983#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38663#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38664#L645-42 assume !(1 == ~t2_pc~0); 39908#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 39909#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39447#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38885#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38404#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38405#L664-42 assume !(1 == ~t3_pc~0); 38921#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 38922#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39848#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39735#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 39736#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39901#L683-42 assume 1 == ~t4_pc~0; 40258#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39613#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39742#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39904#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40163#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40003#L702-42 assume 1 == ~t5_pc~0; 39479#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39099#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39403#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39512#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 38416#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38417#L721-42 assume 1 == ~t6_pc~0; 38556#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38577#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38756#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38757#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 39235#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39072#L740-42 assume 1 == ~t7_pc~0; 39073#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38792#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39364#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 39218#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 39219#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39485#L759-42 assume 1 == ~t8_pc~0; 39340#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 39277#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39278#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39348#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39349#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39437#L778-42 assume 1 == ~t9_pc~0; 39289#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39291#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39706#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39614#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 39615#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39669#L797-42 assume !(1 == ~t10_pc~0); 38801#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 38800#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39687#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39688#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 39708#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39709#L816-42 assume 1 == ~t11_pc~0; 38376#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38377#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40203#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39264#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 38976#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 38977#L835-42 assume !(1 == ~t12_pc~0); 39300#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 39301#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 39487#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39488#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 40063#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 39846#L854-42 assume 1 == ~t13_pc~0; 39847#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 38896#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 39064#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 39065#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 39175#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39176#L1401-3 assume !(1 == ~M_E~0); 39961#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38725#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38603#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38604#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39225#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 39226#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38770#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38771#L1436-3 assume !(1 == ~T8_E~0); 38388#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38389#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 39987#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 39312#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 38944#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 38945#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 40244#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38886#L1476-3 assume !(1 == ~E_3~0); 38887#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39309#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38914#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38915#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 39346#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 39347#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 39785#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 39773#L1516-3 assume !(1 == ~E_11~0); 39774#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 39452#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 39453#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 39868#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 38703#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 38750#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 38751#L1911 assume !(0 == start_simulation_~tmp~3#1); 39281#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 39807#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 38842#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 38426#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 38427#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38550#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 39310#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 40116#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 38962#L1892-2 [2022-12-13 12:58:12,978 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:12,978 INFO L85 PathProgramCache]: Analyzing trace with hash 1619928924, now seen corresponding path program 1 times [2022-12-13 12:58:12,978 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:12,979 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [271525437] [2022-12-13 12:58:12,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:12,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:12,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:13,007 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:13,008 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:13,008 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [271525437] [2022-12-13 12:58:13,008 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [271525437] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:13,008 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:13,008 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:13,008 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [233985020] [2022-12-13 12:58:13,008 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:13,009 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:58:13,009 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:13,009 INFO L85 PathProgramCache]: Analyzing trace with hash -1104530799, now seen corresponding path program 1 times [2022-12-13 12:58:13,009 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:13,009 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1505902727] [2022-12-13 12:58:13,009 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:13,010 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:13,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:13,045 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:13,045 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:13,045 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1505902727] [2022-12-13 12:58:13,046 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1505902727] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:13,046 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:13,046 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:13,046 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2091204606] [2022-12-13 12:58:13,046 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:13,046 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:58:13,046 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:58:13,047 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:58:13,047 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:58:13,047 INFO L87 Difference]: Start difference. First operand 1914 states and 2826 transitions. cyclomatic complexity: 913 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:13,069 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:58:13,069 INFO L93 Difference]: Finished difference Result 1914 states and 2825 transitions. [2022-12-13 12:58:13,070 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2825 transitions. [2022-12-13 12:58:13,074 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 12:58:13,078 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2825 transitions. [2022-12-13 12:58:13,079 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-12-13 12:58:13,079 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-12-13 12:58:13,080 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2825 transitions. [2022-12-13 12:58:13,081 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:58:13,081 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2825 transitions. [2022-12-13 12:58:13,083 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2825 transitions. [2022-12-13 12:58:13,096 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-12-13 12:58:13,098 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4759665621734588) internal successors, (2825), 1913 states have internal predecessors, (2825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:13,100 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2825 transitions. [2022-12-13 12:58:13,101 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2825 transitions. [2022-12-13 12:58:13,101 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:58:13,101 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2825 transitions. [2022-12-13 12:58:13,101 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-12-13 12:58:13,101 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2825 transitions. [2022-12-13 12:58:13,106 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 12:58:13,106 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:58:13,106 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:58:13,108 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:13,108 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:13,108 INFO L748 eck$LassoCheckResult]: Stem: 42484#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 42485#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 43379#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43380#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 44101#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 43777#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43778#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42709#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42710#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43185#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43021#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43022#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42773#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 42774#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 43191#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 43370#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 43538#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 43572#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 42789#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42790#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 43993#L1258-2 assume !(0 == ~T1_E~0); 43106#L1263-1 assume !(0 == ~T2_E~0); 43107#L1268-1 assume !(0 == ~T3_E~0); 43416#L1273-1 assume !(0 == ~T4_E~0); 43972#L1278-1 assume !(0 == ~T5_E~0); 43831#L1283-1 assume !(0 == ~T6_E~0); 43832#L1288-1 assume !(0 == ~T7_E~0); 44070#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44058#L1298-1 assume !(0 == ~T9_E~0); 43988#L1303-1 assume !(0 == ~T10_E~0); 42587#L1308-1 assume !(0 == ~T11_E~0); 42527#L1313-1 assume !(0 == ~T12_E~0); 42528#L1318-1 assume !(0 == ~T13_E~0); 42535#L1323-1 assume !(0 == ~E_1~0); 42536#L1328-1 assume !(0 == ~E_2~0); 42719#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 43707#L1338-1 assume !(0 == ~E_4~0); 43708#L1343-1 assume !(0 == ~E_5~0); 43808#L1348-1 assume !(0 == ~E_6~0); 44088#L1353-1 assume !(0 == ~E_7~0); 43439#L1358-1 assume !(0 == ~E_8~0); 43440#L1363-1 assume !(0 == ~E_9~0); 43729#L1368-1 assume !(0 == ~E_10~0); 42380#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 42381#L1378-1 assume !(0 == ~E_12~0); 42664#L1383-1 assume !(0 == ~E_13~0); 42665#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43444#L607 assume 1 == ~m_pc~0; 43445#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 42737#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43249#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43250#L1560 assume !(0 != activate_threads_~tmp~1#1); 43352#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42548#L626 assume !(1 == ~t1_pc~0); 42549#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 42830#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42831#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43716#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 42452#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42453#L645 assume 1 == ~t2_pc~0; 42566#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42521#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42632#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42633#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 43326#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43327#L664 assume 1 == ~t3_pc~0; 44086#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42318#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42319#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42979#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 42980#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44001#L683 assume !(1 == ~t4_pc~0); 43556#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 43509#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42338#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42339#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43664#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43273#L702 assume 1 == ~t5_pc~0; 43274#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43207#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43660#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43991#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 43900#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42354#L721 assume !(1 == ~t6_pc~0); 42331#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 42332#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42476#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42615#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 42992#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43604#L740 assume 1 == ~t7_pc~0; 42396#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42231#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42232#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42221#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 42222#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42920#L759 assume !(1 == ~t8_pc~0); 42921#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 42951#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44048#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43788#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 43789#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44068#L778 assume 1 == ~t9_pc~0; 43957#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 42379#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42685#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42257#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 42258#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42561#L797 assume !(1 == ~t10_pc~0); 42562#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 42695#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43934#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43102#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 43103#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43396#L816 assume 1 == ~t11_pc~0; 42294#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42295#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43237#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42998#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 42999#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43537#L835 assume 1 == ~t12_pc~0; 43411#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 42443#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42282#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42283#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 43155#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 43156#L854 assume !(1 == ~t13_pc~0); 42775#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 42776#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42825#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42474#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 42475#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43895#L1401 assume !(1 == ~M_E~0); 42985#L1401-2 assume !(1 == ~T1_E~0); 42986#L1406-1 assume !(1 == ~T2_E~0); 43593#L1411-1 assume !(1 == ~T3_E~0); 43594#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43245#L1421-1 assume !(1 == ~T5_E~0); 42771#L1426-1 assume !(1 == ~T6_E~0); 42772#L1431-1 assume !(1 == ~T7_E~0); 42329#L1436-1 assume !(1 == ~T8_E~0); 42330#L1441-1 assume !(1 == ~T9_E~0); 43095#L1446-1 assume !(1 == ~T10_E~0); 43096#L1451-1 assume !(1 == ~T11_E~0); 43805#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 43464#L1461-1 assume !(1 == ~T13_E~0); 43014#L1466-1 assume !(1 == ~E_1~0); 43015#L1471-1 assume !(1 == ~E_2~0); 43786#L1476-1 assume !(1 == ~E_3~0); 43787#L1481-1 assume !(1 == ~E_4~0); 43940#L1486-1 assume !(1 == ~E_5~0); 42600#L1491-1 assume !(1 == ~E_6~0); 42267#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 42268#L1501-1 assume !(1 == ~E_8~0); 43089#L1506-1 assume !(1 == ~E_9~0); 43090#L1511-1 assume !(1 == ~E_10~0); 43044#L1516-1 assume !(1 == ~E_11~0); 42219#L1521-1 assume !(1 == ~E_12~0); 42220#L1526-1 assume !(1 == ~E_13~0); 42266#L1531-1 assume { :end_inline_reset_delta_events } true; 42797#L1892-2 [2022-12-13 12:58:13,109 INFO L750 eck$LassoCheckResult]: Loop: 42797#L1892-2 assume !false; 43847#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44045#L1233 assume !false; 44028#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43353#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 43333#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 43876#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 42308#L1046 assume !(0 != eval_~tmp~0#1); 42310#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 42843#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 42844#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44085#L1258-5 assume !(0 == ~T1_E~0); 42466#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42467#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44077#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44081#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44082#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 42700#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 42701#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 43844#L1298-3 assume !(0 == ~T9_E~0); 43845#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 44008#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 43843#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 43337#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 42468#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 42469#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43932#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42611#L1338-3 assume !(0 == ~E_4~0); 42612#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 43763#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 43938#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 43939#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 43284#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 42832#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 42833#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43624#L1378-3 assume !(0 == ~E_12~0); 43625#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 43802#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43803#L607-42 assume 1 == ~m_pc~0; 43424#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 43139#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42972#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 42852#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42853#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43397#L626-42 assume !(1 == ~t1_pc~0); 42945#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 42944#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44032#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43818#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42498#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42499#L645-42 assume 1 == ~t2_pc~0; 44000#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43743#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43282#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42720#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42239#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42240#L664-42 assume !(1 == ~t3_pc~0); 42756#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 42757#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43683#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43570#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43571#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43736#L683-42 assume !(1 == ~t4_pc~0); 43447#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 43448#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43576#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43739#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43998#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43838#L702-42 assume 1 == ~t5_pc~0; 43314#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 42934#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43238#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43347#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 42251#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42252#L721-42 assume 1 == ~t6_pc~0; 42391#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 42412#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42591#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42592#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 43070#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42907#L740-42 assume !(1 == ~t7_pc~0); 42626#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 42627#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43199#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43053#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 43054#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43320#L759-42 assume 1 == ~t8_pc~0; 43175#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 43112#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43113#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43183#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43184#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43272#L778-42 assume 1 == ~t9_pc~0; 43124#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43126#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43541#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43449#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 43450#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43504#L797-42 assume 1 == ~t10_pc~0; 42634#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 42635#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43522#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43523#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 43543#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43544#L816-42 assume 1 == ~t11_pc~0; 42211#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42212#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44038#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43099#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 42811#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 42812#L835-42 assume 1 == ~t12_pc~0; 43234#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 43135#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 43322#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43323#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 43898#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 43681#L854-42 assume 1 == ~t13_pc~0; 43682#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 42731#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42899#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42900#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 43010#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43011#L1401-3 assume !(1 == ~M_E~0); 43796#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42560#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42438#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42439#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43060#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 43061#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42605#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42606#L1436-3 assume !(1 == ~T8_E~0); 42223#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42224#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43822#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43147#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 42779#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 42780#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44079#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42721#L1476-3 assume !(1 == ~E_3~0); 42722#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43144#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42749#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 42750#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 43180#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 43181#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43620#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 43608#L1516-3 assume !(1 == ~E_11~0); 43609#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 43287#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 43288#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43703#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 42538#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 42585#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 42586#L1911 assume !(0 == start_simulation_~tmp~3#1); 43116#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43642#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 42677#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 42261#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 42262#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42385#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43145#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 43951#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 42797#L1892-2 [2022-12-13 12:58:13,109 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:13,109 INFO L85 PathProgramCache]: Analyzing trace with hash 1281641374, now seen corresponding path program 1 times [2022-12-13 12:58:13,109 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:13,109 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [213180604] [2022-12-13 12:58:13,110 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:13,110 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:13,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:13,140 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:13,140 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:13,140 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [213180604] [2022-12-13 12:58:13,140 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [213180604] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:13,140 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:13,140 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:13,140 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1768476215] [2022-12-13 12:58:13,140 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:13,141 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:58:13,141 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:13,141 INFO L85 PathProgramCache]: Analyzing trace with hash -1680680047, now seen corresponding path program 1 times [2022-12-13 12:58:13,141 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:13,141 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1649167039] [2022-12-13 12:58:13,142 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:13,142 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:13,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:13,183 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:13,183 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:13,183 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1649167039] [2022-12-13 12:58:13,183 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1649167039] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:13,183 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:13,183 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:13,183 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1691847512] [2022-12-13 12:58:13,183 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:13,184 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:58:13,184 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:58:13,184 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:58:13,184 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:58:13,185 INFO L87 Difference]: Start difference. First operand 1914 states and 2825 transitions. cyclomatic complexity: 912 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:13,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:58:13,209 INFO L93 Difference]: Finished difference Result 1914 states and 2824 transitions. [2022-12-13 12:58:13,209 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2824 transitions. [2022-12-13 12:58:13,214 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 12:58:13,218 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2824 transitions. [2022-12-13 12:58:13,218 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-12-13 12:58:13,219 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-12-13 12:58:13,219 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2824 transitions. [2022-12-13 12:58:13,221 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:58:13,221 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2824 transitions. [2022-12-13 12:58:13,223 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2824 transitions. [2022-12-13 12:58:13,236 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-12-13 12:58:13,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4754440961337514) internal successors, (2824), 1913 states have internal predecessors, (2824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:13,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2824 transitions. [2022-12-13 12:58:13,241 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2824 transitions. [2022-12-13 12:58:13,241 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:58:13,241 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2824 transitions. [2022-12-13 12:58:13,241 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-12-13 12:58:13,242 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2824 transitions. [2022-12-13 12:58:13,248 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 12:58:13,248 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:58:13,248 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:58:13,250 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:13,250 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:13,250 INFO L748 eck$LassoCheckResult]: Stem: 46319#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 46320#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 47214#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 47215#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47936#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 47612#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47613#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46544#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46545#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47020#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46856#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46857#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46608#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 46609#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47026#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47205#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 47373#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 47407#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 46624#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46625#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 47828#L1258-2 assume !(0 == ~T1_E~0); 46941#L1263-1 assume !(0 == ~T2_E~0); 46942#L1268-1 assume !(0 == ~T3_E~0); 47251#L1273-1 assume !(0 == ~T4_E~0); 47807#L1278-1 assume !(0 == ~T5_E~0); 47666#L1283-1 assume !(0 == ~T6_E~0); 47667#L1288-1 assume !(0 == ~T7_E~0); 47904#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47893#L1298-1 assume !(0 == ~T9_E~0); 47823#L1303-1 assume !(0 == ~T10_E~0); 46422#L1308-1 assume !(0 == ~T11_E~0); 46362#L1313-1 assume !(0 == ~T12_E~0); 46363#L1318-1 assume !(0 == ~T13_E~0); 46370#L1323-1 assume !(0 == ~E_1~0); 46371#L1328-1 assume !(0 == ~E_2~0); 46554#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 47542#L1338-1 assume !(0 == ~E_4~0); 47543#L1343-1 assume !(0 == ~E_5~0); 47643#L1348-1 assume !(0 == ~E_6~0); 47923#L1353-1 assume !(0 == ~E_7~0); 47274#L1358-1 assume !(0 == ~E_8~0); 47275#L1363-1 assume !(0 == ~E_9~0); 47564#L1368-1 assume !(0 == ~E_10~0); 46215#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 46216#L1378-1 assume !(0 == ~E_12~0); 46499#L1383-1 assume !(0 == ~E_13~0); 46500#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47279#L607 assume 1 == ~m_pc~0; 47280#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 46572#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47084#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47085#L1560 assume !(0 != activate_threads_~tmp~1#1); 47187#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46383#L626 assume !(1 == ~t1_pc~0); 46384#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46665#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46666#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47551#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 46287#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46288#L645 assume 1 == ~t2_pc~0; 46401#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46356#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46467#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46468#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 47161#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47162#L664 assume 1 == ~t3_pc~0; 47921#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46151#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46152#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46814#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 46815#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47836#L683 assume !(1 == ~t4_pc~0); 47391#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 47344#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46173#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46174#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47499#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47108#L702 assume 1 == ~t5_pc~0; 47109#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47042#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47495#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47826#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 47735#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46189#L721 assume !(1 == ~t6_pc~0); 46166#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 46167#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46311#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46450#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 46827#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47439#L740 assume 1 == ~t7_pc~0; 46231#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46066#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46067#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46056#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 46057#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46755#L759 assume !(1 == ~t8_pc~0); 46756#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 46786#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47883#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47623#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 47624#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47903#L778 assume 1 == ~t9_pc~0; 47792#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46214#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46520#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46092#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 46093#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46396#L797 assume !(1 == ~t10_pc~0); 46397#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 46530#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47769#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46937#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 46938#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47231#L816 assume 1 == ~t11_pc~0; 46129#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46130#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47070#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46833#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 46834#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47372#L835 assume 1 == ~t12_pc~0; 47246#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 46278#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46117#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46118#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 46990#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 46991#L854 assume !(1 == ~t13_pc~0); 46610#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 46611#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46660#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46309#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46310#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47730#L1401 assume !(1 == ~M_E~0); 46820#L1401-2 assume !(1 == ~T1_E~0); 46821#L1406-1 assume !(1 == ~T2_E~0); 47428#L1411-1 assume !(1 == ~T3_E~0); 47429#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47080#L1421-1 assume !(1 == ~T5_E~0); 46606#L1426-1 assume !(1 == ~T6_E~0); 46607#L1431-1 assume !(1 == ~T7_E~0); 46164#L1436-1 assume !(1 == ~T8_E~0); 46165#L1441-1 assume !(1 == ~T9_E~0); 46930#L1446-1 assume !(1 == ~T10_E~0); 46931#L1451-1 assume !(1 == ~T11_E~0); 47640#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47299#L1461-1 assume !(1 == ~T13_E~0); 46849#L1466-1 assume !(1 == ~E_1~0); 46850#L1471-1 assume !(1 == ~E_2~0); 47621#L1476-1 assume !(1 == ~E_3~0); 47622#L1481-1 assume !(1 == ~E_4~0); 47775#L1486-1 assume !(1 == ~E_5~0); 46435#L1491-1 assume !(1 == ~E_6~0); 46102#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 46103#L1501-1 assume !(1 == ~E_8~0); 46924#L1506-1 assume !(1 == ~E_9~0); 46925#L1511-1 assume !(1 == ~E_10~0); 46879#L1516-1 assume !(1 == ~E_11~0); 46054#L1521-1 assume !(1 == ~E_12~0); 46055#L1526-1 assume !(1 == ~E_13~0); 46101#L1531-1 assume { :end_inline_reset_delta_events } true; 46632#L1892-2 [2022-12-13 12:58:13,250 INFO L750 eck$LassoCheckResult]: Loop: 46632#L1892-2 assume !false; 47682#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47880#L1233 assume !false; 47863#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47188#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 47168#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 47711#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 46143#L1046 assume !(0 != eval_~tmp~0#1); 46145#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46678#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46679#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 47920#L1258-5 assume !(0 == ~T1_E~0); 46301#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46302#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47912#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47916#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47917#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 46535#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 46536#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47679#L1298-3 assume !(0 == ~T9_E~0); 47680#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 47843#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 47678#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 47172#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 46303#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 46304#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47767#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46446#L1338-3 assume !(0 == ~E_4~0); 46447#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47598#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47773#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 47774#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 47119#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 46667#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 46668#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 47459#L1378-3 assume !(0 == ~E_12~0); 47460#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 47637#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47638#L607-42 assume 1 == ~m_pc~0; 47259#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 46974#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46809#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46687#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46688#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47235#L626-42 assume 1 == ~t1_pc~0; 46781#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 46782#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47867#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47653#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46335#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46336#L645-42 assume !(1 == ~t2_pc~0); 47578#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 47579#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47117#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46555#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46074#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46075#L664-42 assume 1 == ~t3_pc~0; 46885#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46589#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47518#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47405#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47406#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47571#L683-42 assume !(1 == ~t4_pc~0); 47281#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 47282#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47411#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47574#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47833#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47673#L702-42 assume 1 == ~t5_pc~0; 47149#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 46768#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47073#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47182#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 46086#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46087#L721-42 assume 1 == ~t6_pc~0; 46226#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46247#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46426#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46427#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46905#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46742#L740-42 assume 1 == ~t7_pc~0; 46743#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46462#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47034#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46888#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 46889#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47155#L759-42 assume 1 == ~t8_pc~0; 47010#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46947#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46948#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47018#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47019#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47107#L778-42 assume !(1 == ~t9_pc~0); 46960#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 46961#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47376#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47283#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 47284#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47339#L797-42 assume 1 == ~t10_pc~0; 46469#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 46470#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47357#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47358#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 47378#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47379#L816-42 assume !(1 == ~t11_pc~0); 46048#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 46047#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47873#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46934#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 46646#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 46647#L835-42 assume !(1 == ~t12_pc~0); 46967#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 46968#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 47157#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 47158#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 47733#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 47516#L854-42 assume !(1 == ~t13_pc~0); 46565#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 46566#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46734#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46735#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46845#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46846#L1401-3 assume !(1 == ~M_E~0); 47631#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46395#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46273#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46274#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46895#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 46896#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46440#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46441#L1436-3 assume !(1 == ~T8_E~0); 46058#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46059#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47657#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 46982#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 46614#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 46615#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 47914#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46556#L1476-3 assume !(1 == ~E_3~0); 46557#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 46979#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46584#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46585#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 47015#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 47016#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 47455#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 47443#L1516-3 assume !(1 == ~E_11~0); 47444#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 47122#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 47123#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47538#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 46373#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 46420#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 46421#L1911 assume !(0 == start_simulation_~tmp~3#1); 46951#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47477#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 46512#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 46096#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 46097#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46220#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46980#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 47786#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 46632#L1892-2 [2022-12-13 12:58:13,251 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:13,251 INFO L85 PathProgramCache]: Analyzing trace with hash 855086876, now seen corresponding path program 1 times [2022-12-13 12:58:13,251 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:13,251 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2107938275] [2022-12-13 12:58:13,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:13,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:13,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:13,285 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:13,285 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:13,285 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2107938275] [2022-12-13 12:58:13,285 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2107938275] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:13,285 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:13,285 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:13,285 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1038003279] [2022-12-13 12:58:13,285 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:13,286 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:58:13,286 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:13,286 INFO L85 PathProgramCache]: Analyzing trace with hash -381757233, now seen corresponding path program 1 times [2022-12-13 12:58:13,286 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:13,286 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1852540795] [2022-12-13 12:58:13,286 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:13,287 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:13,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:13,321 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:13,321 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:13,321 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1852540795] [2022-12-13 12:58:13,321 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1852540795] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:13,321 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:13,321 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:13,321 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1785922895] [2022-12-13 12:58:13,321 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:13,322 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:58:13,322 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:58:13,322 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:58:13,322 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:58:13,322 INFO L87 Difference]: Start difference. First operand 1914 states and 2824 transitions. cyclomatic complexity: 911 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:13,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:58:13,346 INFO L93 Difference]: Finished difference Result 1914 states and 2823 transitions. [2022-12-13 12:58:13,346 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2823 transitions. [2022-12-13 12:58:13,351 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 12:58:13,355 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2823 transitions. [2022-12-13 12:58:13,355 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-12-13 12:58:13,356 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-12-13 12:58:13,356 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2823 transitions. [2022-12-13 12:58:13,358 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:58:13,358 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2823 transitions. [2022-12-13 12:58:13,359 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2823 transitions. [2022-12-13 12:58:13,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-12-13 12:58:13,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.474921630094044) internal successors, (2823), 1913 states have internal predecessors, (2823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:13,387 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2823 transitions. [2022-12-13 12:58:13,387 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1914 states and 2823 transitions. [2022-12-13 12:58:13,388 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:58:13,388 INFO L428 stractBuchiCegarLoop]: Abstraction has 1914 states and 2823 transitions. [2022-12-13 12:58:13,389 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-12-13 12:58:13,389 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2823 transitions. [2022-12-13 12:58:13,395 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-12-13 12:58:13,395 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:58:13,395 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:58:13,396 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:13,397 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:13,397 INFO L748 eck$LassoCheckResult]: Stem: 50154#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 50155#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 51049#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 51050#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 51771#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 51447#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51448#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50379#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50380#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50855#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50691#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50692#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50443#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50444#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50861#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 51040#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 51208#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 51242#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 50459#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50460#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 51663#L1258-2 assume !(0 == ~T1_E~0); 50776#L1263-1 assume !(0 == ~T2_E~0); 50777#L1268-1 assume !(0 == ~T3_E~0); 51086#L1273-1 assume !(0 == ~T4_E~0); 51642#L1278-1 assume !(0 == ~T5_E~0); 51501#L1283-1 assume !(0 == ~T6_E~0); 51502#L1288-1 assume !(0 == ~T7_E~0); 51739#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51728#L1298-1 assume !(0 == ~T9_E~0); 51658#L1303-1 assume !(0 == ~T10_E~0); 50257#L1308-1 assume !(0 == ~T11_E~0); 50197#L1313-1 assume !(0 == ~T12_E~0); 50198#L1318-1 assume !(0 == ~T13_E~0); 50205#L1323-1 assume !(0 == ~E_1~0); 50206#L1328-1 assume !(0 == ~E_2~0); 50389#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 51377#L1338-1 assume !(0 == ~E_4~0); 51378#L1343-1 assume !(0 == ~E_5~0); 51478#L1348-1 assume !(0 == ~E_6~0); 51758#L1353-1 assume !(0 == ~E_7~0); 51109#L1358-1 assume !(0 == ~E_8~0); 51110#L1363-1 assume !(0 == ~E_9~0); 51399#L1368-1 assume !(0 == ~E_10~0); 50050#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 50051#L1378-1 assume !(0 == ~E_12~0); 50334#L1383-1 assume !(0 == ~E_13~0); 50335#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51114#L607 assume 1 == ~m_pc~0; 51115#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50407#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50916#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50917#L1560 assume !(0 != activate_threads_~tmp~1#1); 51022#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50218#L626 assume !(1 == ~t1_pc~0); 50219#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50500#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50501#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 51386#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 50122#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50123#L645 assume 1 == ~t2_pc~0; 50234#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50191#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50302#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50303#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 50996#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50997#L664 assume 1 == ~t3_pc~0; 51756#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49984#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49985#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50649#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 50650#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51671#L683 assume !(1 == ~t4_pc~0); 51226#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 51179#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50008#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50009#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51334#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50943#L702 assume 1 == ~t5_pc~0; 50944#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50877#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51330#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51661#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 51570#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50022#L721 assume !(1 == ~t6_pc~0); 50001#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 50002#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50146#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50285#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 50662#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51274#L740 assume 1 == ~t7_pc~0; 50066#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49901#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49902#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49891#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 49892#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50590#L759 assume !(1 == ~t8_pc~0); 50591#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 50621#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51716#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51458#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 51459#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51738#L778 assume 1 == ~t9_pc~0; 51627#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50049#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50355#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49927#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 49928#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50231#L797 assume !(1 == ~t10_pc~0); 50232#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 50365#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51604#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50772#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 50773#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51066#L816 assume 1 == ~t11_pc~0; 49964#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49965#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50905#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50668#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 50669#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 51207#L835 assume 1 == ~t12_pc~0; 51081#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 50113#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 49952#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 49953#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 50825#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 50826#L854 assume !(1 == ~t13_pc~0); 50445#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 50446#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50495#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50144#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50145#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51565#L1401 assume !(1 == ~M_E~0); 50655#L1401-2 assume !(1 == ~T1_E~0); 50656#L1406-1 assume !(1 == ~T2_E~0); 51263#L1411-1 assume !(1 == ~T3_E~0); 51264#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50915#L1421-1 assume !(1 == ~T5_E~0); 50441#L1426-1 assume !(1 == ~T6_E~0); 50442#L1431-1 assume !(1 == ~T7_E~0); 49999#L1436-1 assume !(1 == ~T8_E~0); 50000#L1441-1 assume !(1 == ~T9_E~0); 50765#L1446-1 assume !(1 == ~T10_E~0); 50766#L1451-1 assume !(1 == ~T11_E~0); 51475#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 51134#L1461-1 assume !(1 == ~T13_E~0); 50684#L1466-1 assume !(1 == ~E_1~0); 50685#L1471-1 assume !(1 == ~E_2~0); 51456#L1476-1 assume !(1 == ~E_3~0); 51457#L1481-1 assume !(1 == ~E_4~0); 51610#L1486-1 assume !(1 == ~E_5~0); 50270#L1491-1 assume !(1 == ~E_6~0); 49937#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 49938#L1501-1 assume !(1 == ~E_8~0); 50759#L1506-1 assume !(1 == ~E_9~0); 50760#L1511-1 assume !(1 == ~E_10~0); 50714#L1516-1 assume !(1 == ~E_11~0); 49889#L1521-1 assume !(1 == ~E_12~0); 49890#L1526-1 assume !(1 == ~E_13~0); 49936#L1531-1 assume { :end_inline_reset_delta_events } true; 50467#L1892-2 [2022-12-13 12:58:13,397 INFO L750 eck$LassoCheckResult]: Loop: 50467#L1892-2 assume !false; 51517#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 51715#L1233 assume !false; 51698#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51023#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 51003#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51546#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 49978#L1046 assume !(0 != eval_~tmp~0#1); 49980#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50513#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50514#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 51755#L1258-5 assume !(0 == ~T1_E~0); 50134#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50135#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 51747#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 51751#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51752#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50370#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50371#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51514#L1298-3 assume !(0 == ~T9_E~0); 51515#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 51678#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 51513#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 51007#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 50136#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 50137#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 51602#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50281#L1338-3 assume !(0 == ~E_4~0); 50282#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51433#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 51608#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 51609#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50954#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 50502#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 50503#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 51294#L1378-3 assume !(0 == ~E_12~0); 51295#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 51472#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51473#L607-42 assume 1 == ~m_pc~0; 51094#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50809#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50644#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50522#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50523#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51070#L626-42 assume 1 == ~t1_pc~0; 50616#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50617#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51702#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 51488#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50170#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50171#L645-42 assume !(1 == ~t2_pc~0); 51413#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 51414#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50952#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50390#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49909#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49910#L664-42 assume 1 == ~t3_pc~0; 50722#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50427#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51353#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51240#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51241#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51406#L683-42 assume 1 == ~t4_pc~0; 51763#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 51120#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51247#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51409#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51668#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51511#L702-42 assume !(1 == ~t5_pc~0); 50603#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 50604#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50910#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51017#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 49921#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49922#L721-42 assume 1 == ~t6_pc~0; 50060#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 50082#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50261#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50262#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50740#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50575#L740-42 assume 1 == ~t7_pc~0; 50576#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50294#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50869#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50723#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 50724#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50990#L759-42 assume 1 == ~t8_pc~0; 50845#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50782#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50783#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50853#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 50854#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50942#L778-42 assume 1 == ~t9_pc~0; 50794#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50796#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51209#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 51116#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 51117#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51174#L797-42 assume 1 == ~t10_pc~0; 50304#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 50305#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51192#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 51193#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 51213#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51214#L816-42 assume 1 == ~t11_pc~0; 49881#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49882#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 51708#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50769#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50481#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50482#L835-42 assume !(1 == ~t12_pc~0); 50802#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 50803#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50992#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50993#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 51568#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 51351#L854-42 assume !(1 == ~t13_pc~0); 50400#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 50401#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50569#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50570#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50680#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50681#L1401-3 assume !(1 == ~M_E~0); 51466#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50230#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50108#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50109#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50730#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50731#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50275#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50276#L1436-3 assume !(1 == ~T8_E~0); 49893#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49894#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 51492#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50817#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 50449#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 50450#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 51749#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50391#L1476-3 assume !(1 == ~E_3~0); 50392#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50814#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50419#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50420#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50850#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 50851#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 51290#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 51277#L1516-3 assume !(1 == ~E_11~0); 51278#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 50957#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 50958#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51373#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50208#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 50255#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 50256#L1911 assume !(0 == start_simulation_~tmp~3#1); 50784#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51312#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50347#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 49931#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 49932#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50055#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50815#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 51621#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 50467#L1892-2 [2022-12-13 12:58:13,398 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:13,398 INFO L85 PathProgramCache]: Analyzing trace with hash 1395516382, now seen corresponding path program 1 times [2022-12-13 12:58:13,398 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:13,398 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [769137768] [2022-12-13 12:58:13,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:13,398 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:13,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:13,449 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:13,449 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:13,449 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [769137768] [2022-12-13 12:58:13,449 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [769137768] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:13,449 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:13,450 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 12:58:13,450 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2000194324] [2022-12-13 12:58:13,450 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:13,450 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:58:13,451 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:13,451 INFO L85 PathProgramCache]: Analyzing trace with hash 1129186001, now seen corresponding path program 1 times [2022-12-13 12:58:13,451 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:13,451 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [758700542] [2022-12-13 12:58:13,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:13,451 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:13,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:13,498 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:13,498 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:13,498 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [758700542] [2022-12-13 12:58:13,498 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [758700542] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:13,499 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:13,499 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:13,499 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [670313839] [2022-12-13 12:58:13,499 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:13,499 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:58:13,500 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:58:13,500 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:58:13,500 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:58:13,500 INFO L87 Difference]: Start difference. First operand 1914 states and 2823 transitions. cyclomatic complexity: 910 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:13,630 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:58:13,630 INFO L93 Difference]: Finished difference Result 3555 states and 5213 transitions. [2022-12-13 12:58:13,631 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3555 states and 5213 transitions. [2022-12-13 12:58:13,642 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3382 [2022-12-13 12:58:13,650 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3555 states to 3555 states and 5213 transitions. [2022-12-13 12:58:13,650 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3555 [2022-12-13 12:58:13,652 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3555 [2022-12-13 12:58:13,652 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3555 states and 5213 transitions. [2022-12-13 12:58:13,655 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:58:13,656 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3555 states and 5213 transitions. [2022-12-13 12:58:13,659 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3555 states and 5213 transitions. [2022-12-13 12:58:13,691 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3555 to 3555. [2022-12-13 12:58:13,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3555 states, 3555 states have (on average 1.4663853727144867) internal successors, (5213), 3554 states have internal predecessors, (5213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:13,700 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3555 states to 3555 states and 5213 transitions. [2022-12-13 12:58:13,700 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3555 states and 5213 transitions. [2022-12-13 12:58:13,700 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:58:13,701 INFO L428 stractBuchiCegarLoop]: Abstraction has 3555 states and 5213 transitions. [2022-12-13 12:58:13,701 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-12-13 12:58:13,701 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3555 states and 5213 transitions. [2022-12-13 12:58:13,710 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3382 [2022-12-13 12:58:13,710 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:58:13,710 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:58:13,711 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:13,711 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:13,712 INFO L748 eck$LassoCheckResult]: Stem: 55632#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 55633#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 56533#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 56534#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 57330#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 56945#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 56946#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55858#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55859#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56333#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 56170#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 56171#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 55922#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 55923#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 56341#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 56524#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 56695#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 56730#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 55938#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55939#L1258 assume !(0 == ~M_E~0); 57188#L1258-2 assume !(0 == ~T1_E~0); 56256#L1263-1 assume !(0 == ~T2_E~0); 56257#L1268-1 assume !(0 == ~T3_E~0); 56571#L1273-1 assume !(0 == ~T4_E~0); 57163#L1278-1 assume !(0 == ~T5_E~0); 57005#L1283-1 assume !(0 == ~T6_E~0); 57006#L1288-1 assume !(0 == ~T7_E~0); 57286#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 57272#L1298-1 assume !(0 == ~T9_E~0); 57182#L1303-1 assume !(0 == ~T10_E~0); 55735#L1308-1 assume !(0 == ~T11_E~0); 55675#L1313-1 assume !(0 == ~T12_E~0); 55676#L1318-1 assume !(0 == ~T13_E~0); 55681#L1323-1 assume !(0 == ~E_1~0); 55682#L1328-1 assume !(0 == ~E_2~0); 55868#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 56868#L1338-1 assume !(0 == ~E_4~0); 56869#L1343-1 assume !(0 == ~E_5~0); 56981#L1348-1 assume !(0 == ~E_6~0); 57313#L1353-1 assume !(0 == ~E_7~0); 56594#L1358-1 assume !(0 == ~E_8~0); 56595#L1363-1 assume !(0 == ~E_9~0); 56891#L1368-1 assume !(0 == ~E_10~0); 55526#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 55527#L1378-1 assume !(0 == ~E_12~0); 55811#L1383-1 assume !(0 == ~E_13~0); 55812#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56598#L607 assume !(1 == ~m_pc~0); 55885#L607-2 is_master_triggered_~__retres1~0#1 := 0; 55886#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56397#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 56398#L1560 assume !(0 != activate_threads_~tmp~1#1); 56504#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55696#L626 assume !(1 == ~t1_pc~0); 55697#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 55979#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55980#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 56878#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 55600#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55601#L645 assume 1 == ~t2_pc~0; 55712#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 55669#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55778#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 55779#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 56478#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56479#L664 assume 1 == ~t3_pc~0; 57310#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 55460#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55461#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 56128#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 56129#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57201#L683 assume !(1 == ~t4_pc~0); 56713#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 56663#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55484#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 55485#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 56825#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56420#L702 assume 1 == ~t5_pc~0; 56421#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 56357#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 56821#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 57186#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 57077#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55496#L721 assume !(1 == ~t6_pc~0); 55477#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 55478#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 55624#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 55763#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 56141#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 56764#L740 assume 1 == ~t7_pc~0; 55542#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 55377#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55378#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 55367#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 55368#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 56068#L759 assume !(1 == ~t8_pc~0); 56069#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 56100#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 57254#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 56958#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 56959#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 57285#L778 assume 1 == ~t9_pc~0; 57146#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 55525#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 55834#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 55403#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 55404#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 55708#L797 assume !(1 == ~t10_pc~0); 55709#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 55844#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 57118#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 56252#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 56253#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 56551#L816 assume 1 == ~t11_pc~0; 55438#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 55439#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 56386#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 56147#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 56148#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 56694#L835 assume 1 == ~t12_pc~0; 56566#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 55591#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 55428#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 55429#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 56305#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 56306#L854 assume !(1 == ~t13_pc~0); 55924#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 55925#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 55974#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 55622#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 55623#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57072#L1401 assume !(1 == ~M_E~0); 56134#L1401-2 assume !(1 == ~T1_E~0); 56135#L1406-1 assume !(1 == ~T2_E~0); 56753#L1411-1 assume !(1 == ~T3_E~0); 56754#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56396#L1421-1 assume !(1 == ~T5_E~0); 55920#L1426-1 assume !(1 == ~T6_E~0); 55921#L1431-1 assume !(1 == ~T7_E~0); 55475#L1436-1 assume !(1 == ~T8_E~0); 55476#L1441-1 assume !(1 == ~T9_E~0); 56242#L1446-1 assume !(1 == ~T10_E~0); 56243#L1451-1 assume !(1 == ~T11_E~0); 56978#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 56618#L1461-1 assume !(1 == ~T13_E~0); 56163#L1466-1 assume !(1 == ~E_1~0); 56164#L1471-1 assume !(1 == ~E_2~0); 56956#L1476-1 assume !(1 == ~E_3~0); 56957#L1481-1 assume !(1 == ~E_4~0); 57124#L1486-1 assume !(1 == ~E_5~0); 55748#L1491-1 assume !(1 == ~E_6~0); 55413#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 55414#L1501-1 assume !(1 == ~E_8~0); 56238#L1506-1 assume !(1 == ~E_9~0); 56239#L1511-1 assume !(1 == ~E_10~0); 56193#L1516-1 assume !(1 == ~E_11~0); 55365#L1521-1 assume !(1 == ~E_12~0); 55366#L1526-1 assume !(1 == ~E_13~0); 55412#L1531-1 assume { :end_inline_reset_delta_events } true; 55946#L1892-2 [2022-12-13 12:58:13,712 INFO L750 eck$LassoCheckResult]: Loop: 55946#L1892-2 assume !false; 57403#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57253#L1233 assume !false; 57232#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 56505#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 56485#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 57053#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 55454#L1046 assume !(0 != eval_~tmp~0#1); 55456#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 55991#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 55992#L1258-3 assume !(0 == ~M_E~0); 57309#L1258-5 assume !(0 == ~T1_E~0); 55612#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 55613#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 57298#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 57304#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 57305#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 55849#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 55850#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 57018#L1298-3 assume !(0 == ~T9_E~0); 57019#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 57211#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 57017#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 56489#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 55614#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 55615#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 57116#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 55759#L1338-3 assume !(0 == ~E_4~0); 55760#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 56930#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 57121#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 57122#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 56435#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 55981#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 55982#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 56786#L1378-3 assume !(0 == ~E_12~0); 56787#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 56975#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56976#L607-42 assume !(1 == ~m_pc~0); 56577#L607-44 is_master_triggered_~__retres1~0#1 := 0; 56289#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56121#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 56001#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 56002#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56552#L626-42 assume 1 == ~t1_pc~0; 56092#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 56093#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 57236#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 56992#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 55648#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55649#L645-42 assume !(1 == ~t2_pc~0); 56905#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 56906#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56433#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 55869#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 55385#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55386#L664-42 assume !(1 == ~t3_pc~0); 55905#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 55906#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 56844#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 56728#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 56729#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 56898#L683-42 assume 1 == ~t4_pc~0; 57319#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 56602#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56735#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 56901#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 57196#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 57012#L702-42 assume !(1 == ~t5_pc~0); 56082#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 56083#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 56389#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 56499#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 55397#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55398#L721-42 assume 1 == ~t6_pc~0; 55537#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 58829#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58828#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 58827#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 58826#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58825#L740-42 assume 1 == ~t7_pc~0; 58823#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 58822#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 58821#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 58820#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 58819#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 57348#L759-42 assume 1 == ~t8_pc~0; 56325#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 56262#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 56263#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 56689#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 58812#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 58811#L778-42 assume !(1 == ~t9_pc~0); 58809#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 58808#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58807#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 58806#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 58805#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 58804#L797-42 assume 1 == ~t10_pc~0; 58802#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 58801#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 58800#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 58799#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 58798#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 58797#L816-42 assume !(1 == ~t11_pc~0); 58795#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 58794#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 58793#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58792#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 58791#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 58790#L835-42 assume 1 == ~t12_pc~0; 58788#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 58787#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58786#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 58544#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 58543#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 58542#L854-42 assume !(1 == ~t13_pc~0); 58540#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 58539#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 58538#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 58537#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 58536#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57345#L1401-3 assume !(1 == ~M_E~0); 57346#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 57782#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 57780#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 57778#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 57775#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 57773#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 57771#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 57769#L1436-3 assume !(1 == ~T8_E~0); 57767#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 57765#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 57764#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 57761#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 57759#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 57757#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 57755#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 57753#L1476-3 assume !(1 == ~E_3~0); 57751#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 57750#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 57747#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 57745#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 57743#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 57741#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 57739#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 57737#L1516-3 assume !(1 == ~E_11~0); 57734#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 57732#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 57731#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 57441#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 57437#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 57435#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 57434#L1911 assume !(0 == start_simulation_~tmp~3#1); 57432#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 57431#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 57417#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 57416#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 57415#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 57414#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 57413#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 57411#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 55946#L1892-2 [2022-12-13 12:58:13,712 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:13,712 INFO L85 PathProgramCache]: Analyzing trace with hash -1486214853, now seen corresponding path program 1 times [2022-12-13 12:58:13,712 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:13,713 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [703655459] [2022-12-13 12:58:13,713 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:13,713 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:13,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:13,781 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:13,781 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:13,781 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [703655459] [2022-12-13 12:58:13,781 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [703655459] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:13,781 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:13,782 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:13,782 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [202166349] [2022-12-13 12:58:13,782 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:13,782 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:58:13,782 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:13,783 INFO L85 PathProgramCache]: Analyzing trace with hash 1121718444, now seen corresponding path program 1 times [2022-12-13 12:58:13,783 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:13,783 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [924289807] [2022-12-13 12:58:13,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:13,783 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:13,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:13,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:13,823 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:13,823 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [924289807] [2022-12-13 12:58:13,823 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [924289807] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:13,823 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:13,823 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:13,823 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [912419276] [2022-12-13 12:58:13,823 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:13,824 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:58:13,824 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:58:13,824 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:58:13,824 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:58:13,824 INFO L87 Difference]: Start difference. First operand 3555 states and 5213 transitions. cyclomatic complexity: 1659 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:13,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:58:13,958 INFO L93 Difference]: Finished difference Result 6962 states and 10199 transitions. [2022-12-13 12:58:13,959 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6962 states and 10199 transitions. [2022-12-13 12:58:13,985 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6764 [2022-12-13 12:58:14,007 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6962 states to 6962 states and 10199 transitions. [2022-12-13 12:58:14,007 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6962 [2022-12-13 12:58:14,013 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6962 [2022-12-13 12:58:14,013 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6962 states and 10199 transitions. [2022-12-13 12:58:14,021 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:58:14,022 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6962 states and 10199 transitions. [2022-12-13 12:58:14,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6962 states and 10199 transitions. [2022-12-13 12:58:14,084 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6962 to 6962. [2022-12-13 12:58:14,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6962 states, 6962 states have (on average 1.4649525998276358) internal successors, (10199), 6961 states have internal predecessors, (10199), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:14,100 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6962 states to 6962 states and 10199 transitions. [2022-12-13 12:58:14,101 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6962 states and 10199 transitions. [2022-12-13 12:58:14,101 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:58:14,101 INFO L428 stractBuchiCegarLoop]: Abstraction has 6962 states and 10199 transitions. [2022-12-13 12:58:14,101 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-12-13 12:58:14,102 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6962 states and 10199 transitions. [2022-12-13 12:58:14,122 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6764 [2022-12-13 12:58:14,123 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:58:14,123 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:58:14,134 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:14,134 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:14,134 INFO L748 eck$LassoCheckResult]: Stem: 66157#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 66158#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 67062#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 67063#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 67827#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 67466#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 67467#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 66383#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 66384#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 66864#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 66699#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 66700#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 66448#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 66449#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 66872#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 67053#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 67220#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 67255#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 66464#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 66465#L1258 assume !(0 == ~M_E~0); 67699#L1258-2 assume !(0 == ~T1_E~0); 66785#L1263-1 assume !(0 == ~T2_E~0); 66786#L1268-1 assume !(0 == ~T3_E~0); 67099#L1273-1 assume !(0 == ~T4_E~0); 67677#L1278-1 assume !(0 == ~T5_E~0); 67526#L1283-1 assume !(0 == ~T6_E~0); 67527#L1288-1 assume !(0 == ~T7_E~0); 67781#L1293-1 assume !(0 == ~T8_E~0); 67769#L1298-1 assume !(0 == ~T9_E~0); 67694#L1303-1 assume !(0 == ~T10_E~0); 66260#L1308-1 assume !(0 == ~T11_E~0); 66200#L1313-1 assume !(0 == ~T12_E~0); 66201#L1318-1 assume !(0 == ~T13_E~0); 66206#L1323-1 assume !(0 == ~E_1~0); 66207#L1328-1 assume !(0 == ~E_2~0); 66393#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 67394#L1338-1 assume !(0 == ~E_4~0); 67395#L1343-1 assume !(0 == ~E_5~0); 67500#L1348-1 assume !(0 == ~E_6~0); 67803#L1353-1 assume !(0 == ~E_7~0); 67122#L1358-1 assume !(0 == ~E_8~0); 67123#L1363-1 assume !(0 == ~E_9~0); 67416#L1368-1 assume !(0 == ~E_10~0); 66053#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 66054#L1378-1 assume !(0 == ~E_12~0); 66336#L1383-1 assume !(0 == ~E_13~0); 66337#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67126#L607 assume !(1 == ~m_pc~0); 66410#L607-2 is_master_triggered_~__retres1~0#1 := 0; 66411#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 66927#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 66928#L1560 assume !(0 != activate_threads_~tmp~1#1); 67034#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66221#L626 assume !(1 == ~t1_pc~0); 66222#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 66506#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66507#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 67403#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 66125#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66126#L645 assume 1 == ~t2_pc~0; 66237#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 66194#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66304#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 66305#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 67007#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67008#L664 assume 1 == ~t3_pc~0; 67798#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 65987#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65988#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 66657#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 66658#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67707#L683 assume !(1 == ~t4_pc~0); 67238#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 67190#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66012#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 66013#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 67351#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66950#L702 assume 1 == ~t5_pc~0; 66951#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 66887#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 67347#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 67697#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 67597#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 66023#L721 assume !(1 == ~t6_pc~0); 66005#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 66006#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 66149#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 66289#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 66670#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 67289#L740 assume 1 == ~t7_pc~0; 66069#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 65904#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 65905#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 65894#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 65895#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 66597#L759 assume !(1 == ~t8_pc~0); 66598#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 66629#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 67756#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 67477#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 67478#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 67780#L778 assume 1 == ~t9_pc~0; 67661#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 66052#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66359#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 65930#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 65931#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 66234#L797 assume !(1 == ~t10_pc~0); 66235#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 66369#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 67637#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 66781#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 66782#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 67079#L816 assume 1 == ~t11_pc~0; 65965#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 65966#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 66916#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 66676#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 66677#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 67219#L835 assume 1 == ~t12_pc~0; 67094#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 66116#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 65955#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 65956#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 66836#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 66837#L854 assume !(1 == ~t13_pc~0); 66450#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 66451#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 66501#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 66147#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 66148#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 67592#L1401 assume !(1 == ~M_E~0); 66663#L1401-2 assume !(1 == ~T1_E~0); 66664#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 67599#L1411-1 assume !(1 == ~T3_E~0); 67971#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 67970#L1421-1 assume !(1 == ~T5_E~0); 67969#L1426-1 assume !(1 == ~T6_E~0); 67968#L1431-1 assume !(1 == ~T7_E~0); 67967#L1436-1 assume !(1 == ~T8_E~0); 66003#L1441-1 assume !(1 == ~T9_E~0); 67966#L1446-1 assume !(1 == ~T10_E~0); 67965#L1451-1 assume !(1 == ~T11_E~0); 67964#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 67963#L1461-1 assume !(1 == ~T13_E~0); 67962#L1466-1 assume !(1 == ~E_1~0); 67961#L1471-1 assume !(1 == ~E_2~0); 67960#L1476-1 assume !(1 == ~E_3~0); 67959#L1481-1 assume !(1 == ~E_4~0); 67958#L1486-1 assume !(1 == ~E_5~0); 67957#L1491-1 assume !(1 == ~E_6~0); 67956#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 67955#L1501-1 assume !(1 == ~E_8~0); 67954#L1506-1 assume !(1 == ~E_9~0); 67953#L1511-1 assume !(1 == ~E_10~0); 67952#L1516-1 assume !(1 == ~E_11~0); 65892#L1521-1 assume !(1 == ~E_12~0); 65893#L1526-1 assume !(1 == ~E_13~0); 65939#L1531-1 assume { :end_inline_reset_delta_events } true; 67905#L1892-2 [2022-12-13 12:58:14,134 INFO L750 eck$LassoCheckResult]: Loop: 67905#L1892-2 assume !false; 67895#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 67893#L1233 assume !false; 67892#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 67877#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 67862#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 67860#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 67857#L1046 assume !(0 != eval_~tmp~0#1); 67854#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 67852#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 67849#L1258-3 assume !(0 == ~M_E~0); 67850#L1258-5 assume !(0 == ~T1_E~0); 70316#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 70314#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 70312#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 70310#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 70307#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 70305#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 70303#L1293-3 assume !(0 == ~T8_E~0); 70301#L1298-3 assume !(0 == ~T9_E~0); 70299#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 70297#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 70294#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 70292#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 70290#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 70288#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 70286#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 70284#L1338-3 assume !(0 == ~E_4~0); 70281#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 70279#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 70277#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 70275#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 70273#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 70271#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 70268#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 70266#L1378-3 assume !(0 == ~E_12~0); 70264#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 70262#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 70260#L607-42 assume !(1 == ~m_pc~0); 70254#L607-44 is_master_triggered_~__retres1~0#1 := 0; 70253#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 70252#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 70251#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 70250#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 70249#L626-42 assume 1 == ~t1_pc~0; 70247#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 70246#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 70243#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 70241#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 70239#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 70237#L645-42 assume 1 == ~t2_pc~0; 70235#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 70232#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 70230#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 70227#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 70225#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 70223#L664-42 assume !(1 == ~t3_pc~0); 70221#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 70218#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70216#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 70213#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 70211#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 70209#L683-42 assume 1 == ~t4_pc~0; 70207#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 70204#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70202#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 70199#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 70197#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 70195#L702-42 assume !(1 == ~t5_pc~0); 70193#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 70190#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 70188#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 70185#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 70183#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 70181#L721-42 assume !(1 == ~t6_pc~0); 70179#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 70176#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 70174#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 70171#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 70169#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 70167#L740-42 assume !(1 == ~t7_pc~0); 70165#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 70162#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 70160#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 70157#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 70155#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 70153#L759-42 assume !(1 == ~t8_pc~0); 70151#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 70148#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 70146#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 70143#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 70141#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 70139#L778-42 assume 1 == ~t9_pc~0; 70137#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 70134#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 70132#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 70129#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 70127#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 70125#L797-42 assume !(1 == ~t10_pc~0); 70123#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 70120#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 70118#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 70115#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 70113#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 70111#L816-42 assume 1 == ~t11_pc~0; 70109#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 70106#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 70104#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 70101#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 70099#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 70097#L835-42 assume !(1 == ~t12_pc~0); 70095#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 70092#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 70090#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 70089#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 70088#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 70085#L854-42 assume 1 == ~t13_pc~0; 70083#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 70080#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 70078#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 70076#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 70074#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70069#L1401-3 assume !(1 == ~M_E~0); 70067#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 70065#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 70061#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 70059#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 70056#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 70054#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 70052#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 70047#L1436-3 assume !(1 == ~T8_E~0); 70045#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 70042#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 70040#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 70038#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 70036#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 70034#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 70032#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 70031#L1476-3 assume !(1 == ~E_3~0); 70028#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 70026#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 70024#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 70022#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 70020#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 70018#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 69998#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 69989#L1516-3 assume !(1 == ~E_11~0); 69981#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 69975#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 68723#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68592#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68588#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68573#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 68567#L1911 assume !(0 == start_simulation_~tmp~3#1); 68559#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68147#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68130#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68128#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 67949#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 67948#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 67946#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 67917#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 67905#L1892-2 [2022-12-13 12:58:14,135 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:14,135 INFO L85 PathProgramCache]: Analyzing trace with hash -1259435077, now seen corresponding path program 1 times [2022-12-13 12:58:14,135 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:14,135 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [585480590] [2022-12-13 12:58:14,135 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:14,135 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:14,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:14,192 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:14,192 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:14,192 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [585480590] [2022-12-13 12:58:14,192 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [585480590] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:14,192 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:14,192 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:14,192 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1550303374] [2022-12-13 12:58:14,192 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:14,193 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:58:14,193 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:14,193 INFO L85 PathProgramCache]: Analyzing trace with hash 1300109961, now seen corresponding path program 1 times [2022-12-13 12:58:14,193 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:14,193 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2132913217] [2022-12-13 12:58:14,193 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:14,194 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:14,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:14,228 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:14,228 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:14,228 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2132913217] [2022-12-13 12:58:14,228 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2132913217] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:14,228 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:14,228 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:14,228 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [717024364] [2022-12-13 12:58:14,228 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:14,229 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:58:14,229 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:58:14,229 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:58:14,229 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:58:14,229 INFO L87 Difference]: Start difference. First operand 6962 states and 10199 transitions. cyclomatic complexity: 3239 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:14,390 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:58:14,390 INFO L93 Difference]: Finished difference Result 13360 states and 19568 transitions. [2022-12-13 12:58:14,390 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13360 states and 19568 transitions. [2022-12-13 12:58:14,429 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13128 [2022-12-13 12:58:14,488 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13360 states to 13360 states and 19568 transitions. [2022-12-13 12:58:14,488 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13360 [2022-12-13 12:58:14,498 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13360 [2022-12-13 12:58:14,498 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13360 states and 19568 transitions. [2022-12-13 12:58:14,509 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:58:14,509 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13360 states and 19568 transitions. [2022-12-13 12:58:14,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13360 states and 19568 transitions. [2022-12-13 12:58:14,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13360 to 13356. [2022-12-13 12:58:14,669 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13356 states, 13356 states have (on average 1.4648098233003894) internal successors, (19564), 13355 states have internal predecessors, (19564), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:14,720 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13356 states to 13356 states and 19564 transitions. [2022-12-13 12:58:14,720 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13356 states and 19564 transitions. [2022-12-13 12:58:14,720 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:58:14,720 INFO L428 stractBuchiCegarLoop]: Abstraction has 13356 states and 19564 transitions. [2022-12-13 12:58:14,721 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-12-13 12:58:14,721 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13356 states and 19564 transitions. [2022-12-13 12:58:14,755 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13128 [2022-12-13 12:58:14,755 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:58:14,755 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:58:14,757 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:14,757 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:14,757 INFO L748 eck$LassoCheckResult]: Stem: 86491#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 86492#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 87414#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 87415#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 88306#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 87856#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 87857#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 86719#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 86720#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 87206#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 87036#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 87037#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 86785#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 86786#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 87214#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 87405#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 87579#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 87614#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 86801#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86802#L1258 assume !(0 == ~M_E~0); 88124#L1258-2 assume !(0 == ~T1_E~0); 87125#L1263-1 assume !(0 == ~T2_E~0); 87126#L1268-1 assume !(0 == ~T3_E~0); 87452#L1273-1 assume !(0 == ~T4_E~0); 88098#L1278-1 assume !(0 == ~T5_E~0); 87927#L1283-1 assume !(0 == ~T6_E~0); 87928#L1288-1 assume !(0 == ~T7_E~0); 88236#L1293-1 assume !(0 == ~T8_E~0); 88218#L1298-1 assume !(0 == ~T9_E~0); 88117#L1303-1 assume !(0 == ~T10_E~0); 86595#L1308-1 assume !(0 == ~T11_E~0); 86534#L1313-1 assume !(0 == ~T12_E~0); 86535#L1318-1 assume !(0 == ~T13_E~0); 86540#L1323-1 assume !(0 == ~E_1~0); 86541#L1328-1 assume !(0 == ~E_2~0); 86729#L1333-1 assume !(0 == ~E_3~0); 87769#L1338-1 assume !(0 == ~E_4~0); 87770#L1343-1 assume !(0 == ~E_5~0); 87897#L1348-1 assume !(0 == ~E_6~0); 88277#L1353-1 assume !(0 == ~E_7~0); 87475#L1358-1 assume !(0 == ~E_8~0); 87476#L1363-1 assume !(0 == ~E_9~0); 87794#L1368-1 assume !(0 == ~E_10~0); 86385#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 86386#L1378-1 assume !(0 == ~E_12~0); 86672#L1383-1 assume !(0 == ~E_13~0); 86673#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 87479#L607 assume !(1 == ~m_pc~0); 86746#L607-2 is_master_triggered_~__retres1~0#1 := 0; 86747#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87271#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 87272#L1560 assume !(0 != activate_threads_~tmp~1#1); 87383#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 86555#L626 assume !(1 == ~t1_pc~0); 86556#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 86842#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86843#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 87778#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 86459#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86460#L645 assume 1 == ~t2_pc~0; 86572#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 86528#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 86639#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 86640#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 87356#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 87357#L664 assume 1 == ~t3_pc~0; 88270#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 86319#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86320#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 86994#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 86995#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88135#L683 assume !(1 == ~t4_pc~0); 87598#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 87549#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86343#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 86344#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 87721#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 87295#L702 assume 1 == ~t5_pc~0; 87296#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 87229#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 87715#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 88122#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 88006#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 86355#L721 assume !(1 == ~t6_pc~0); 86336#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 86337#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 86483#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 86624#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 87007#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 87653#L740 assume 1 == ~t7_pc~0; 86401#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 86236#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86237#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 86226#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 86227#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 86934#L759 assume !(1 == ~t8_pc~0); 86935#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 86966#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 88202#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 87868#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 87869#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 88235#L778 assume 1 == ~t9_pc~0; 88078#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 86384#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 86695#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 86262#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 86263#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 86567#L797 assume !(1 == ~t10_pc~0); 86568#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 86705#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 88054#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 87121#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 87122#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 87431#L816 assume 1 == ~t11_pc~0; 86297#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 86298#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 87259#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 87013#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 87014#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 87578#L835 assume 1 == ~t12_pc~0; 87447#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 86450#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 86287#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 86288#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 87178#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 87179#L854 assume !(1 == ~t13_pc~0); 86787#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 86788#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86837#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 86481#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 86482#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 88002#L1401 assume !(1 == ~M_E~0); 87000#L1401-2 assume !(1 == ~T1_E~0); 87001#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 88009#L1411-1 assume !(1 == ~T3_E~0); 88258#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 88259#L1421-1 assume !(1 == ~T5_E~0); 86783#L1426-1 assume !(1 == ~T6_E~0); 86784#L1431-1 assume !(1 == ~T7_E~0); 86334#L1436-1 assume !(1 == ~T8_E~0); 86335#L1441-1 assume !(1 == ~T9_E~0); 87502#L1446-1 assume !(1 == ~T10_E~0); 88319#L1451-1 assume !(1 == ~T11_E~0); 88320#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 87499#L1461-1 assume !(1 == ~T13_E~0); 87500#L1466-1 assume !(1 == ~E_1~0); 88315#L1471-1 assume !(1 == ~E_2~0); 88316#L1476-1 assume !(1 == ~E_3~0); 90085#L1481-1 assume !(1 == ~E_4~0); 90082#L1486-1 assume !(1 == ~E_5~0); 90080#L1491-1 assume !(1 == ~E_6~0); 90078#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 90076#L1501-1 assume !(1 == ~E_8~0); 90074#L1506-1 assume !(1 == ~E_9~0); 90070#L1511-1 assume !(1 == ~E_10~0); 90068#L1516-1 assume !(1 == ~E_11~0); 90067#L1521-1 assume !(1 == ~E_12~0); 90065#L1526-1 assume !(1 == ~E_13~0); 90057#L1531-1 assume { :end_inline_reset_delta_events } true; 90050#L1892-2 [2022-12-13 12:58:14,758 INFO L750 eck$LassoCheckResult]: Loop: 90050#L1892-2 assume !false; 90045#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 90044#L1233 assume !false; 90043#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 90029#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 90028#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 90027#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 90025#L1046 assume !(0 != eval_~tmp~0#1); 90024#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 90023#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 90022#L1258-3 assume !(0 == ~M_E~0); 90021#L1258-5 assume !(0 == ~T1_E~0); 90018#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 90019#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 92570#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 92568#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 92566#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 92565#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 92564#L1293-3 assume !(0 == ~T8_E~0); 92563#L1298-3 assume !(0 == ~T9_E~0); 92562#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 92561#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 92560#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 92559#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 92558#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 92557#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 92556#L1333-3 assume !(0 == ~E_3~0); 92555#L1338-3 assume !(0 == ~E_4~0); 92554#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 92552#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 92550#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 92547#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 92545#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 92543#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 92541#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 92356#L1378-3 assume !(0 == ~E_12~0); 92354#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 92353#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 92352#L607-42 assume !(1 == ~m_pc~0); 92348#L607-44 is_master_triggered_~__retres1~0#1 := 0; 92346#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 92344#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 92229#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 92227#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 92226#L626-42 assume 1 == ~t1_pc~0; 92123#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 92121#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 92119#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 92117#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 92114#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 92113#L645-42 assume 1 == ~t2_pc~0; 92112#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 92110#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 92109#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 92108#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 92106#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 89969#L664-42 assume !(1 == ~t3_pc~0); 89968#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 88266#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 87743#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 87612#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 87613#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 87806#L683-42 assume 1 == ~t4_pc~0; 88291#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 87483#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 87619#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 91918#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 91916#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 91913#L702-42 assume !(1 == ~t5_pc~0); 86948#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 86949#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 87262#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 87377#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 86256#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 86257#L721-42 assume !(1 == ~t6_pc~0); 86397#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 91764#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 91762#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 91760#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 91759#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 91758#L740-42 assume !(1 == ~t7_pc~0); 89791#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 89788#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 87397#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 87071#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 87072#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 87349#L759-42 assume !(1 == ~t8_pc~0); 87199#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 87131#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 87132#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 87207#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 87208#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 87300#L778-42 assume 1 == ~t9_pc~0; 87143#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 87145#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 87583#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 87484#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 87485#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 87544#L797-42 assume 1 == ~t10_pc~0; 86643#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 86644#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 89614#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 89613#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 87584#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 87585#L816-42 assume 1 == ~t11_pc~0; 86216#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 86217#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 91387#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 91385#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 91383#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 91381#L835-42 assume 1 == ~t12_pc~0; 91323#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 91321#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 91319#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 91317#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 91314#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 91313#L854-42 assume 1 == ~t13_pc~0; 91312#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 91264#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 91261#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 91203#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 91201#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 91197#L1401-3 assume !(1 == ~M_E~0); 91149#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 91147#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 86571#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 91144#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 91142#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 91108#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 91080#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 91078#L1436-3 assume !(1 == ~T8_E~0); 86762#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 91034#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 91032#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 91030#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 91005#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 90959#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 90954#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 90948#L1476-3 assume !(1 == ~E_3~0); 90945#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 90942#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 90939#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 90936#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 90933#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 90932#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 90931#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 90930#L1516-3 assume !(1 == ~E_11~0); 90929#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 90928#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 90927#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 90912#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 90907#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 90904#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 90900#L1911 assume !(0 == start_simulation_~tmp~3#1); 90897#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 90895#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 90881#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 90333#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 90310#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 90288#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 90064#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 90056#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 90050#L1892-2 [2022-12-13 12:58:14,758 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:14,758 INFO L85 PathProgramCache]: Analyzing trace with hash -312397191, now seen corresponding path program 1 times [2022-12-13 12:58:14,758 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:14,758 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1821785925] [2022-12-13 12:58:14,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:14,759 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:14,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:14,821 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:14,821 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:14,821 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1821785925] [2022-12-13 12:58:14,821 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1821785925] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:14,821 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:14,821 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:14,822 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [571656806] [2022-12-13 12:58:14,822 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:14,822 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:58:14,822 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:14,823 INFO L85 PathProgramCache]: Analyzing trace with hash 1714648201, now seen corresponding path program 1 times [2022-12-13 12:58:14,823 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:14,823 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [553808465] [2022-12-13 12:58:14,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:14,823 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:14,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:14,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:14,869 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:14,869 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [553808465] [2022-12-13 12:58:14,869 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [553808465] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:14,869 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:14,870 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:14,870 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [396288182] [2022-12-13 12:58:14,870 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:14,870 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:58:14,870 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:58:14,871 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:58:14,871 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:58:14,871 INFO L87 Difference]: Start difference. First operand 13356 states and 19564 transitions. cyclomatic complexity: 6212 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:15,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:58:15,126 INFO L93 Difference]: Finished difference Result 25712 states and 37649 transitions. [2022-12-13 12:58:15,126 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25712 states and 37649 transitions. [2022-12-13 12:58:15,193 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 25456 [2022-12-13 12:58:15,245 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25712 states to 25712 states and 37649 transitions. [2022-12-13 12:58:15,245 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25712 [2022-12-13 12:58:15,255 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25712 [2022-12-13 12:58:15,255 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25712 states and 37649 transitions. [2022-12-13 12:58:15,270 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:58:15,270 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25712 states and 37649 transitions. [2022-12-13 12:58:15,287 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25712 states and 37649 transitions. [2022-12-13 12:58:15,513 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25712 to 25704. [2022-12-13 12:58:15,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25704 states, 25704 states have (on average 1.4644024276377217) internal successors, (37641), 25703 states have internal predecessors, (37641), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:15,618 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25704 states to 25704 states and 37641 transitions. [2022-12-13 12:58:15,618 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25704 states and 37641 transitions. [2022-12-13 12:58:15,619 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:58:15,619 INFO L428 stractBuchiCegarLoop]: Abstraction has 25704 states and 37641 transitions. [2022-12-13 12:58:15,619 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-12-13 12:58:15,619 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25704 states and 37641 transitions. [2022-12-13 12:58:15,687 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 25456 [2022-12-13 12:58:15,687 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:58:15,687 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:58:15,689 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:15,689 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:15,690 INFO L748 eck$LassoCheckResult]: Stem: 125567#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 125568#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 126491#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 126492#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 127348#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 126918#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 126919#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 125798#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 125799#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 126284#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 126115#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 126116#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 125862#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 125863#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 126292#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 126482#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 126655#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 126694#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 125878#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 125879#L1258 assume !(0 == ~M_E~0); 127189#L1258-2 assume !(0 == ~T1_E~0); 126203#L1263-1 assume !(0 == ~T2_E~0); 126204#L1268-1 assume !(0 == ~T3_E~0); 126530#L1273-1 assume !(0 == ~T4_E~0); 127163#L1278-1 assume !(0 == ~T5_E~0); 126986#L1283-1 assume !(0 == ~T6_E~0); 126987#L1288-1 assume !(0 == ~T7_E~0); 127283#L1293-1 assume !(0 == ~T8_E~0); 127270#L1298-1 assume !(0 == ~T9_E~0); 127183#L1303-1 assume !(0 == ~T10_E~0); 125671#L1308-1 assume !(0 == ~T11_E~0); 125610#L1313-1 assume !(0 == ~T12_E~0); 125611#L1318-1 assume !(0 == ~T13_E~0); 125616#L1323-1 assume !(0 == ~E_1~0); 125617#L1328-1 assume !(0 == ~E_2~0); 125808#L1333-1 assume !(0 == ~E_3~0); 126836#L1338-1 assume !(0 == ~E_4~0); 126837#L1343-1 assume !(0 == ~E_5~0); 126959#L1348-1 assume !(0 == ~E_6~0); 127322#L1353-1 assume !(0 == ~E_7~0); 126553#L1358-1 assume !(0 == ~E_8~0); 126554#L1363-1 assume !(0 == ~E_9~0); 126858#L1368-1 assume !(0 == ~E_10~0); 125463#L1373-1 assume !(0 == ~E_11~0); 125464#L1378-1 assume !(0 == ~E_12~0); 125749#L1383-1 assume !(0 == ~E_13~0); 125750#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 126557#L607 assume !(1 == ~m_pc~0); 125825#L607-2 is_master_triggered_~__retres1~0#1 := 0; 125826#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 126348#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 126349#L1560 assume !(0 != activate_threads_~tmp~1#1); 126460#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 125631#L626 assume !(1 == ~t1_pc~0); 125632#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 125919#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 125920#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 126845#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 125535#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 125536#L645 assume 1 == ~t2_pc~0; 125648#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 125604#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 125716#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 125717#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 126433#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 126434#L664 assume 1 == ~t3_pc~0; 127314#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 125397#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 125398#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 126072#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 126073#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 127198#L683 assume !(1 == ~t4_pc~0); 126676#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 126624#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 125422#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 125423#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 126792#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 126371#L702 assume 1 == ~t5_pc~0; 126372#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 126307#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 126788#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 127187#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 127062#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 125433#L721 assume !(1 == ~t6_pc~0); 125415#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 125416#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 125559#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 125701#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 126085#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 126731#L740 assume 1 == ~t7_pc~0; 125479#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 125314#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 125315#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 125304#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 125305#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 126010#L759 assume !(1 == ~t8_pc~0); 126011#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 126043#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 127256#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 126930#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 126931#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 127282#L778 assume 1 == ~t9_pc~0; 127141#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 125462#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 125772#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 125340#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 125341#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 125643#L797 assume !(1 == ~t10_pc~0); 125644#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 125784#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 127114#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 126199#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 126200#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 126509#L816 assume 1 == ~t11_pc~0; 125375#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 125376#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 126336#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 126091#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 126092#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 126654#L835 assume 1 == ~t12_pc~0; 126525#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 125526#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 125365#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 125366#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 126254#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 126255#L854 assume !(1 == ~t13_pc~0); 125864#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 125865#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 125914#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 125557#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 125558#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 127057#L1401 assume !(1 == ~M_E~0); 126078#L1401-2 assume !(1 == ~T1_E~0); 126079#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 126719#L1411-1 assume !(1 == ~T3_E~0); 126720#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 126347#L1421-1 assume !(1 == ~T5_E~0); 125860#L1426-1 assume !(1 == ~T6_E~0); 125861#L1431-1 assume !(1 == ~T7_E~0); 126866#L1436-1 assume !(1 == ~T8_E~0); 128819#L1441-1 assume !(1 == ~T9_E~0); 128818#L1446-1 assume !(1 == ~T10_E~0); 128817#L1451-1 assume !(1 == ~T11_E~0); 128816#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 128815#L1461-1 assume !(1 == ~T13_E~0); 128814#L1466-1 assume !(1 == ~E_1~0); 128813#L1471-1 assume !(1 == ~E_2~0); 128812#L1476-1 assume !(1 == ~E_3~0); 128811#L1481-1 assume !(1 == ~E_4~0); 128810#L1486-1 assume !(1 == ~E_5~0); 128809#L1491-1 assume !(1 == ~E_6~0); 128808#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 128807#L1501-1 assume !(1 == ~E_8~0); 128806#L1506-1 assume !(1 == ~E_9~0); 128805#L1511-1 assume !(1 == ~E_10~0); 128804#L1516-1 assume !(1 == ~E_11~0); 128758#L1521-1 assume !(1 == ~E_12~0); 128730#L1526-1 assume !(1 == ~E_13~0); 128714#L1531-1 assume { :end_inline_reset_delta_events } true; 128702#L1892-2 [2022-12-13 12:58:15,690 INFO L750 eck$LassoCheckResult]: Loop: 128702#L1892-2 assume !false; 128696#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 128695#L1233 assume !false; 128694#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 128679#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 128664#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 128662#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 128659#L1046 assume !(0 != eval_~tmp~0#1); 128656#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 128654#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 128652#L1258-3 assume !(0 == ~M_E~0); 128649#L1258-5 assume !(0 == ~T1_E~0); 128648#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 127298#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 127299#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 127306#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 127307#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 125789#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 125790#L1293-3 assume !(0 == ~T8_E~0); 127000#L1298-3 assume !(0 == ~T9_E~0); 127001#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 127206#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 126999#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 126444#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 125549#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 125550#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 127110#L1333-3 assume !(0 == ~E_3~0); 127329#L1338-3 assume !(0 == ~E_4~0); 126903#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 126904#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 127117#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 127118#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 127146#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 150968#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 150967#L1373-3 assume !(0 == ~E_11~0); 150966#L1378-3 assume !(0 == ~E_12~0); 150965#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 150964#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 150963#L607-42 assume !(1 == ~m_pc~0); 150961#L607-44 is_master_triggered_~__retres1~0#1 := 0; 150960#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 150959#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 150958#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 150957#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 150956#L626-42 assume 1 == ~t1_pc~0; 150954#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 150953#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 150952#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 150951#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 150950#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 150949#L645-42 assume !(1 == ~t2_pc~0); 150947#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 150946#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 150945#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 150713#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 150712#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 150711#L664-42 assume 1 == ~t3_pc~0; 126146#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 125846#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 126811#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 126692#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 126693#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 126867#L683-42 assume !(1 == ~t4_pc~0); 126560#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 126561#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 126699#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 126870#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 127195#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 126994#L702-42 assume 1 == ~t5_pc~0; 126420#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 126026#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 150361#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 150359#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 150358#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 150356#L721-42 assume !(1 == ~t6_pc~0); 150354#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 150351#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 150349#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 150347#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 150345#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 150344#L740-42 assume 1 == ~t7_pc~0; 150342#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 150341#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 150340#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 150339#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 150338#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 127388#L759-42 assume 1 == ~t8_pc~0; 127389#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 126209#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 126210#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 148405#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 148401#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 148402#L778-42 assume !(1 == ~t9_pc~0); 148395#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 148396#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 148391#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 148392#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 148387#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 148388#L797-42 assume !(1 == ~t10_pc~0); 148383#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 148382#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 148377#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 148378#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 148408#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 128608#L816-42 assume !(1 == ~t11_pc~0); 128609#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 128600#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 128601#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 128593#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 128594#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 132120#L835-42 assume !(1 == ~t12_pc~0); 132118#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 132114#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 132112#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 132110#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 132108#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 132106#L854-42 assume !(1 == ~t13_pc~0); 132103#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 132100#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 132098#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 132096#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 132094#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 131967#L1401-3 assume !(1 == ~M_E~0); 131963#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 131961#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 125647#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 131958#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 131956#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 131954#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 131952#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 131948#L1436-3 assume !(1 == ~T8_E~0); 131947#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 131946#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 131945#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 131944#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 131943#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 131942#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 131941#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 131813#L1476-3 assume !(1 == ~E_3~0); 131810#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 131808#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 131806#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 131804#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 131802#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 131800#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 131799#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 131795#L1516-3 assume !(1 == ~E_11~0); 131793#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 131791#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 131788#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 128935#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 128931#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 128929#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 128889#L1911 assume !(0 == start_simulation_~tmp~3#1); 128822#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 128776#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 128761#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 128760#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 128759#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 128731#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 128729#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 128713#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 128702#L1892-2 [2022-12-13 12:58:15,690 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:15,690 INFO L85 PathProgramCache]: Analyzing trace with hash -645040329, now seen corresponding path program 1 times [2022-12-13 12:58:15,691 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:15,691 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1693073429] [2022-12-13 12:58:15,691 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:15,691 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:15,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:15,782 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:15,782 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:15,782 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1693073429] [2022-12-13 12:58:15,782 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1693073429] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:15,782 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:15,782 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:15,783 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [332200168] [2022-12-13 12:58:15,783 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:15,783 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:58:15,783 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:15,784 INFO L85 PathProgramCache]: Analyzing trace with hash 901293092, now seen corresponding path program 1 times [2022-12-13 12:58:15,784 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:15,784 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1375953475] [2022-12-13 12:58:15,784 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:15,784 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:15,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:15,832 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:15,832 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:15,832 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1375953475] [2022-12-13 12:58:15,832 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1375953475] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:15,832 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:15,832 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:15,832 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [435261224] [2022-12-13 12:58:15,832 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:15,833 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:58:15,833 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:58:15,833 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:58:15,833 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:58:15,833 INFO L87 Difference]: Start difference. First operand 25704 states and 37641 transitions. cyclomatic complexity: 11945 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:16,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:58:16,279 INFO L93 Difference]: Finished difference Result 74990 states and 108892 transitions. [2022-12-13 12:58:16,279 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 74990 states and 108892 transitions. [2022-12-13 12:58:16,479 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 73032 [2022-12-13 12:58:16,700 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 74990 states to 74990 states and 108892 transitions. [2022-12-13 12:58:16,700 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 74990 [2022-12-13 12:58:16,719 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 74990 [2022-12-13 12:58:16,719 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74990 states and 108892 transitions. [2022-12-13 12:58:16,749 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:58:16,749 INFO L218 hiAutomatonCegarLoop]: Abstraction has 74990 states and 108892 transitions. [2022-12-13 12:58:16,778 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74990 states and 108892 transitions. [2022-12-13 12:58:17,262 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74990 to 72678. [2022-12-13 12:58:17,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72678 states, 72678 states have (on average 1.454140179971931) internal successors, (105684), 72677 states have internal predecessors, (105684), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:17,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72678 states to 72678 states and 105684 transitions. [2022-12-13 12:58:17,436 INFO L240 hiAutomatonCegarLoop]: Abstraction has 72678 states and 105684 transitions. [2022-12-13 12:58:17,437 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:58:17,437 INFO L428 stractBuchiCegarLoop]: Abstraction has 72678 states and 105684 transitions. [2022-12-13 12:58:17,437 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2022-12-13 12:58:17,437 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72678 states and 105684 transitions. [2022-12-13 12:58:17,641 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 72352 [2022-12-13 12:58:17,641 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:58:17,641 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:58:17,643 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:17,643 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:17,644 INFO L748 eck$LassoCheckResult]: Stem: 226270#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 226271#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 227176#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 227177#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 228013#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 227609#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 227610#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 226496#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 226497#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 226978#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 226808#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 226809#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 226560#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 226561#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 226986#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 227166#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 227341#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 227377#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 226576#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 226577#L1258 assume !(0 == ~M_E~0); 227852#L1258-2 assume !(0 == ~T1_E~0); 226897#L1263-1 assume !(0 == ~T2_E~0); 226898#L1268-1 assume !(0 == ~T3_E~0); 227213#L1273-1 assume !(0 == ~T4_E~0); 227826#L1278-1 assume !(0 == ~T5_E~0); 227663#L1283-1 assume !(0 == ~T6_E~0); 227664#L1288-1 assume !(0 == ~T7_E~0); 227952#L1293-1 assume !(0 == ~T8_E~0); 227937#L1298-1 assume !(0 == ~T9_E~0); 227847#L1303-1 assume !(0 == ~T10_E~0); 226372#L1308-1 assume !(0 == ~T11_E~0); 226313#L1313-1 assume !(0 == ~T12_E~0); 226314#L1318-1 assume !(0 == ~T13_E~0); 226319#L1323-1 assume !(0 == ~E_1~0); 226320#L1328-1 assume !(0 == ~E_2~0); 226506#L1333-1 assume !(0 == ~E_3~0); 227528#L1338-1 assume !(0 == ~E_4~0); 227529#L1343-1 assume !(0 == ~E_5~0); 227639#L1348-1 assume !(0 == ~E_6~0); 227989#L1353-1 assume !(0 == ~E_7~0); 227235#L1358-1 assume !(0 == ~E_8~0); 227236#L1363-1 assume !(0 == ~E_9~0); 227552#L1368-1 assume !(0 == ~E_10~0); 226166#L1373-1 assume !(0 == ~E_11~0); 226167#L1378-1 assume !(0 == ~E_12~0); 226448#L1383-1 assume !(0 == ~E_13~0); 226449#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 227239#L607 assume !(1 == ~m_pc~0); 226523#L607-2 is_master_triggered_~__retres1~0#1 := 0; 226524#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 227041#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 227042#L1560 assume !(0 != activate_threads_~tmp~1#1); 227147#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 226334#L626 assume !(1 == ~t1_pc~0); 226335#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 226618#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 226619#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 227537#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 226238#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 226239#L645 assume !(1 == ~t2_pc~0); 226306#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 226307#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 226416#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 226417#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 227121#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 227122#L664 assume 1 == ~t3_pc~0; 227981#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 226102#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 226103#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 226767#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 226768#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 227866#L683 assume !(1 == ~t4_pc~0); 227361#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 227312#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 226126#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 226127#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 227479#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 227064#L702 assume 1 == ~t5_pc~0; 227065#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 227001#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 227475#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 227850#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 227736#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 226136#L721 assume !(1 == ~t6_pc~0); 226119#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 226120#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 226262#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 226401#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 226780#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 227414#L740 assume 1 == ~t7_pc~0; 226182#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 226018#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 226019#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 226008#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 226009#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 226707#L759 assume !(1 == ~t8_pc~0); 226708#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 226739#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 227924#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 227619#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 227620#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 227951#L778 assume 1 == ~t9_pc~0; 227809#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 226165#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 226471#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 226044#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 226045#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 226346#L797 assume !(1 == ~t10_pc~0); 226347#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 226482#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 227780#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 226893#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 226894#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 227193#L816 assume 1 == ~t11_pc~0; 226080#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 226081#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 227030#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 226786#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 226787#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 227340#L835 assume 1 == ~t12_pc~0; 227208#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 226229#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 226070#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 226071#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 226950#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 226951#L854 assume !(1 == ~t13_pc~0); 226562#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 226563#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 226613#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 226260#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 226261#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 227731#L1401 assume !(1 == ~M_E~0); 226773#L1401-2 assume !(1 == ~T1_E~0); 226774#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 227402#L1411-1 assume !(1 == ~T3_E~0); 227403#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 227040#L1421-1 assume !(1 == ~T5_E~0); 226558#L1426-1 assume !(1 == ~T6_E~0); 226559#L1431-1 assume !(1 == ~T7_E~0); 226117#L1436-1 assume !(1 == ~T8_E~0); 226118#L1441-1 assume !(1 == ~T9_E~0); 227259#L1446-1 assume !(1 == ~T10_E~0); 228026#L1451-1 assume !(1 == ~T11_E~0); 227636#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 227257#L1461-1 assume !(1 == ~T13_E~0); 226802#L1466-1 assume !(1 == ~E_1~0); 226803#L1471-1 assume !(1 == ~E_2~0); 227617#L1476-1 assume !(1 == ~E_3~0); 227618#L1481-1 assume !(1 == ~E_4~0); 227965#L1486-1 assume !(1 == ~E_5~0); 226385#L1491-1 assume !(1 == ~E_6~0); 226055#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 226056#L1501-1 assume !(1 == ~E_8~0); 226876#L1506-1 assume !(1 == ~E_9~0); 226877#L1511-1 assume !(1 == ~E_10~0); 226830#L1516-1 assume !(1 == ~E_11~0); 226006#L1521-1 assume !(1 == ~E_12~0); 226007#L1526-1 assume !(1 == ~E_13~0); 226584#L1531-1 assume { :end_inline_reset_delta_events } true; 226585#L1892-2 [2022-12-13 12:58:17,644 INFO L750 eck$LassoCheckResult]: Loop: 226585#L1892-2 assume !false; 294589#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 294588#L1233 assume !false; 294587#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 294573#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 294572#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 227712#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 226096#L1046 assume !(0 != eval_~tmp~0#1); 226098#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 226630#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 226631#L1258-3 assume !(0 == ~M_E~0); 227979#L1258-5 assume !(0 == ~T1_E~0); 226250#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 226251#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 227969#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 227975#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 227976#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 226487#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 226488#L1293-3 assume !(0 == ~T8_E~0); 227675#L1298-3 assume !(0 == ~T9_E~0); 227676#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 227877#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 227674#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 227132#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 226252#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 226253#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 227777#L1333-3 assume !(0 == ~E_3~0); 226396#L1338-3 assume !(0 == ~E_4~0); 226397#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 227595#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 227784#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 227785#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 227079#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 226620#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 226621#L1373-3 assume !(0 == ~E_11~0); 227435#L1378-3 assume !(0 == ~E_12~0); 227436#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 227633#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 227634#L607-42 assume !(1 == ~m_pc~0); 228023#L607-44 is_master_triggered_~__retres1~0#1 := 0; 298343#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 298342#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 298341#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 298340#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 298339#L626-42 assume 1 == ~t1_pc~0; 298337#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 298336#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 298335#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 298334#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 298333#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 298332#L645-42 assume !(1 == ~t2_pc~0); 298331#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 298330#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 298329#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 298328#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 298327#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 298326#L664-42 assume 1 == ~t3_pc~0; 298324#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 298323#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 298322#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 298321#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 298320#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 298319#L683-42 assume !(1 == ~t4_pc~0); 298317#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 298316#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 298315#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 298314#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 298313#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 298312#L702-42 assume 1 == ~t5_pc~0; 298310#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 298309#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 298308#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 298307#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 298306#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 298305#L721-42 assume !(1 == ~t6_pc~0); 298304#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 298302#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 298301#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 298300#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 298299#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 298298#L740-42 assume 1 == ~t7_pc~0; 298296#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 298295#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 298294#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 298293#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 298292#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 298291#L759-42 assume !(1 == ~t8_pc~0); 226971#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 226903#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 226904#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 226979#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 226980#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 227069#L778-42 assume !(1 == ~t9_pc~0); 226917#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 226918#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 227345#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 227243#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 227244#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 227303#L797-42 assume !(1 == ~t10_pc~0); 227305#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 298278#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 298277#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 298276#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 298275#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 298274#L816-42 assume !(1 == ~t11_pc~0); 298272#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 298271#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 298270#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 298269#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 226599#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 226600#L835-42 assume 1 == ~t12_pc~0; 227029#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 226928#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 298225#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 298223#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 298220#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 298219#L854-42 assume !(1 == ~t13_pc~0); 298217#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 226878#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 226879#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 226938#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 226939#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 294442#L1401-3 assume !(1 == ~M_E~0); 294443#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 294437#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 253614#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 294431#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 294432#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 294425#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 294426#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 294420#L1436-3 assume !(1 == ~T8_E~0); 282951#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 294414#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 294415#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 294408#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 294409#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 294402#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 294403#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 294394#L1476-3 assume !(1 == ~E_3~0); 271134#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 294389#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 294390#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 294383#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 294384#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 294378#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 294379#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 294353#L1516-3 assume !(1 == ~E_11~0); 291776#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 294347#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 294348#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 294271#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 294267#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 294264#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 294265#L1911 assume !(0 == start_simulation_~tmp~3#1); 294671#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 294669#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 294654#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 294635#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 294624#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 294614#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 294606#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 294599#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 226585#L1892-2 [2022-12-13 12:58:17,645 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:17,645 INFO L85 PathProgramCache]: Analyzing trace with hash -1648097194, now seen corresponding path program 1 times [2022-12-13 12:58:17,645 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:17,645 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1696001419] [2022-12-13 12:58:17,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:17,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:17,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:17,711 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:17,711 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:17,711 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1696001419] [2022-12-13 12:58:17,711 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1696001419] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:17,711 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:17,711 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:17,711 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1072419034] [2022-12-13 12:58:17,712 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:17,712 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:58:17,712 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:17,712 INFO L85 PathProgramCache]: Analyzing trace with hash 1681979172, now seen corresponding path program 1 times [2022-12-13 12:58:17,713 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:17,713 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [312790622] [2022-12-13 12:58:17,713 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:17,713 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:17,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:17,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:17,772 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:17,772 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [312790622] [2022-12-13 12:58:17,773 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [312790622] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:17,773 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:17,773 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:17,773 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [399191138] [2022-12-13 12:58:17,773 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:17,774 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:58:17,774 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:58:17,774 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:58:17,774 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:58:17,774 INFO L87 Difference]: Start difference. First operand 72678 states and 105684 transitions. cyclomatic complexity: 33022 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:18,596 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:58:18,597 INFO L93 Difference]: Finished difference Result 210029 states and 303417 transitions. [2022-12-13 12:58:18,597 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 210029 states and 303417 transitions. [2022-12-13 12:58:19,341 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 206072 [2022-12-13 12:58:19,756 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 210029 states to 210029 states and 303417 transitions. [2022-12-13 12:58:19,757 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 210029 [2022-12-13 12:58:19,832 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 210029 [2022-12-13 12:58:19,832 INFO L73 IsDeterministic]: Start isDeterministic. Operand 210029 states and 303417 transitions. [2022-12-13 12:58:19,924 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:58:19,924 INFO L218 hiAutomatonCegarLoop]: Abstraction has 210029 states and 303417 transitions. [2022-12-13 12:58:20,075 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 210029 states and 303417 transitions. [2022-12-13 12:58:21,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 210029 to 202813. [2022-12-13 12:58:21,564 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 202813 states, 202813 states have (on average 1.4468944298442408) internal successors, (293449), 202812 states have internal predecessors, (293449), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:22,051 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 202813 states to 202813 states and 293449 transitions. [2022-12-13 12:58:22,051 INFO L240 hiAutomatonCegarLoop]: Abstraction has 202813 states and 293449 transitions. [2022-12-13 12:58:22,052 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:58:22,052 INFO L428 stractBuchiCegarLoop]: Abstraction has 202813 states and 293449 transitions. [2022-12-13 12:58:22,052 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2022-12-13 12:58:22,052 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 202813 states and 293449 transitions. [2022-12-13 12:58:22,522 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 202328 [2022-12-13 12:58:22,522 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:58:22,522 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:58:22,523 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:22,523 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:22,524 INFO L748 eck$LassoCheckResult]: Stem: 508991#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 508992#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 509911#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 509912#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 510835#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 510364#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 510365#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 509219#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 509220#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 509704#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 509532#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 509533#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 509285#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 509286#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 509714#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 509902#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 510076#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 510111#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 509301#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 509302#L1258 assume !(0 == ~M_E~0); 510632#L1258-2 assume !(0 == ~T1_E~0); 509621#L1263-1 assume !(0 == ~T2_E~0); 509622#L1268-1 assume !(0 == ~T3_E~0); 509948#L1273-1 assume !(0 == ~T4_E~0); 510605#L1278-1 assume !(0 == ~T5_E~0); 510424#L1283-1 assume !(0 == ~T6_E~0); 510425#L1288-1 assume !(0 == ~T7_E~0); 510751#L1293-1 assume !(0 == ~T8_E~0); 510732#L1298-1 assume !(0 == ~T9_E~0); 510626#L1303-1 assume !(0 == ~T10_E~0); 509094#L1308-1 assume !(0 == ~T11_E~0); 509034#L1313-1 assume !(0 == ~T12_E~0); 509035#L1318-1 assume !(0 == ~T13_E~0); 509041#L1323-1 assume !(0 == ~E_1~0); 509042#L1328-1 assume !(0 == ~E_2~0); 509229#L1333-1 assume !(0 == ~E_3~0); 510269#L1338-1 assume !(0 == ~E_4~0); 510270#L1343-1 assume !(0 == ~E_5~0); 510397#L1348-1 assume !(0 == ~E_6~0); 510791#L1353-1 assume !(0 == ~E_7~0); 509971#L1358-1 assume !(0 == ~E_8~0); 509972#L1363-1 assume !(0 == ~E_9~0); 510300#L1368-1 assume !(0 == ~E_10~0); 508886#L1373-1 assume !(0 == ~E_11~0); 508887#L1378-1 assume !(0 == ~E_12~0); 509172#L1383-1 assume !(0 == ~E_13~0); 509173#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 509976#L607 assume !(1 == ~m_pc~0); 509247#L607-2 is_master_triggered_~__retres1~0#1 := 0; 509248#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 509772#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 509773#L1560 assume !(0 != activate_threads_~tmp~1#1); 509882#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 509056#L626 assume !(1 == ~t1_pc~0); 509057#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 509342#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 509343#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 510279#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 508959#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 508960#L645 assume !(1 == ~t2_pc~0); 509027#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 509028#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 509139#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 509140#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 509855#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 509856#L664 assume !(1 == ~t3_pc~0); 510327#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 508818#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 508819#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 509491#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 509492#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 510646#L683 assume !(1 == ~t4_pc~0); 510094#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 510043#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 508842#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 508843#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 510218#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 509796#L702 assume 1 == ~t5_pc~0; 509797#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 509731#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 510214#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 510630#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 510509#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 508854#L721 assume !(1 == ~t6_pc~0); 508835#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 508836#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 508983#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 509125#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 509504#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 510149#L740 assume 1 == ~t7_pc~0; 508902#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 508735#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 508736#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 508725#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 508726#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 509431#L759 assume !(1 == ~t8_pc~0); 509432#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 509463#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 510717#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 510374#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 510375#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 510750#L778 assume 1 == ~t9_pc~0; 510585#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 508885#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 509195#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 508760#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 508761#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 509068#L797 assume !(1 == ~t10_pc~0); 509069#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 509205#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 510556#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 509617#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 509618#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 509928#L816 assume 1 == ~t11_pc~0; 508796#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 508797#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 509760#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 509510#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 509511#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 510075#L835 assume 1 == ~t12_pc~0; 509943#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 508949#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 508786#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 508787#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 509671#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 509672#L854 assume !(1 == ~t13_pc~0); 509287#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 509288#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 509337#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 508981#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 508982#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 510501#L1401 assume !(1 == ~M_E~0); 509497#L1401-2 assume !(1 == ~T1_E~0); 509498#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 510511#L1411-1 assume !(1 == ~T3_E~0); 510778#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 510779#L1421-1 assume !(1 == ~T5_E~0); 509283#L1426-1 assume !(1 == ~T6_E~0); 509284#L1431-1 assume !(1 == ~T7_E~0); 508833#L1436-1 assume !(1 == ~T8_E~0); 508834#L1441-1 assume !(1 == ~T9_E~0); 509607#L1446-1 assume !(1 == ~T10_E~0); 509608#L1451-1 assume !(1 == ~T11_E~0); 510394#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 509994#L1461-1 assume !(1 == ~T13_E~0); 509526#L1466-1 assume !(1 == ~E_1~0); 509527#L1471-1 assume !(1 == ~E_2~0); 510372#L1476-1 assume !(1 == ~E_3~0); 510373#L1481-1 assume !(1 == ~E_4~0); 510565#L1486-1 assume !(1 == ~E_5~0); 509107#L1491-1 assume !(1 == ~E_6~0); 508771#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 508772#L1501-1 assume !(1 == ~E_8~0); 509603#L1506-1 assume !(1 == ~E_9~0); 509604#L1511-1 assume !(1 == ~E_10~0); 509556#L1516-1 assume !(1 == ~E_11~0); 508723#L1521-1 assume !(1 == ~E_12~0); 508724#L1526-1 assume !(1 == ~E_13~0); 508770#L1531-1 assume { :end_inline_reset_delta_events } true; 509309#L1892-2 [2022-12-13 12:58:22,524 INFO L750 eck$LassoCheckResult]: Loop: 509309#L1892-2 assume !false; 660220#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 660219#L1233 assume !false; 660218#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 660204#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 660203#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 660202#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 660200#L1046 assume !(0 != eval_~tmp~0#1); 660199#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 660198#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 660197#L1258-3 assume !(0 == ~M_E~0); 660196#L1258-5 assume !(0 == ~T1_E~0); 660195#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 660194#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 660193#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 660192#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 660191#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 660190#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 660189#L1293-3 assume !(0 == ~T8_E~0); 660188#L1298-3 assume !(0 == ~T9_E~0); 660187#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 660186#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 660185#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 660184#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 660183#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 660182#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 660181#L1333-3 assume !(0 == ~E_3~0); 660180#L1338-3 assume !(0 == ~E_4~0); 660179#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 660176#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 660175#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 660174#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 660173#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 660172#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 660170#L1373-3 assume !(0 == ~E_11~0); 660168#L1378-3 assume !(0 == ~E_12~0); 660166#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 660164#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 660162#L607-42 assume !(1 == ~m_pc~0); 660160#L607-44 is_master_triggered_~__retres1~0#1 := 0; 660158#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 660155#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 660153#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 660151#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 660149#L626-42 assume 1 == ~t1_pc~0; 660146#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 660144#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 660142#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 660140#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 660138#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 660136#L645-42 assume !(1 == ~t2_pc~0); 660134#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 660132#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 660130#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 660128#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 660126#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 660124#L664-42 assume !(1 == ~t3_pc~0); 660121#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 660118#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 660114#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 660110#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 660106#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 660101#L683-42 assume !(1 == ~t4_pc~0); 660095#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 660089#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 660083#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 660078#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 660072#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 660067#L702-42 assume 1 == ~t5_pc~0; 660060#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 660055#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 660049#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 660044#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 660039#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 660035#L721-42 assume 1 == ~t6_pc~0; 660030#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 660026#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 660021#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 660017#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 660013#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 660008#L740-42 assume !(1 == ~t7_pc~0); 660002#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 659995#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 659988#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 659982#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 659975#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 659969#L759-42 assume 1 == ~t8_pc~0; 659960#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 659953#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 659946#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 659940#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 659933#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 659927#L778-42 assume !(1 == ~t9_pc~0); 659919#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 659913#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 659906#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 659900#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 659893#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 659887#L797-42 assume !(1 == ~t10_pc~0); 659880#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 659873#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 659866#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 659860#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 659853#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 659847#L816-42 assume !(1 == ~t11_pc~0); 659838#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 659831#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 659824#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 659818#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 659812#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 659807#L835-42 assume !(1 == ~t12_pc~0); 659800#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 659794#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 659787#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 659782#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 659776#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 659770#L854-42 assume 1 == ~t13_pc~0; 659762#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 659755#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 659749#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 659743#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 659736#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 659730#L1401-3 assume !(1 == ~M_E~0); 659184#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 659716#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 588025#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 659705#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 659698#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 659692#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 659684#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 659678#L1436-3 assume !(1 == ~T8_E~0); 628643#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 659667#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 659660#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 659655#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 659646#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 659641#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 659636#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 659630#L1476-3 assume !(1 == ~E_3~0); 649451#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 659619#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 659610#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 659605#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 659600#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 659594#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 659586#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 659581#L1516-3 assume !(1 == ~E_11~0); 647310#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 659575#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 659572#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 659465#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 659455#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 659447#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 659439#L1911 assume !(0 == start_simulation_~tmp~3#1); 659440#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 660331#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 660282#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 660266#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 660255#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 660245#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 660237#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 660230#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 509309#L1892-2 [2022-12-13 12:58:22,524 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:22,524 INFO L85 PathProgramCache]: Analyzing trace with hash -1375101771, now seen corresponding path program 1 times [2022-12-13 12:58:22,524 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:22,524 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1375628233] [2022-12-13 12:58:22,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:22,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:22,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:22,575 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:22,576 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:22,576 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1375628233] [2022-12-13 12:58:22,576 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1375628233] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:22,576 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:22,576 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:58:22,576 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1859016354] [2022-12-13 12:58:22,576 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:22,577 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:58:22,577 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:22,577 INFO L85 PathProgramCache]: Analyzing trace with hash -656402716, now seen corresponding path program 1 times [2022-12-13 12:58:22,577 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:22,577 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1392478040] [2022-12-13 12:58:22,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:22,578 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:22,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:22,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:22,618 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:22,618 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1392478040] [2022-12-13 12:58:22,618 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1392478040] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:22,618 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:22,618 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:58:22,619 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [735307182] [2022-12-13 12:58:22,619 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:22,619 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:58:22,619 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:58:22,619 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-13 12:58:22,620 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-13 12:58:22,620 INFO L87 Difference]: Start difference. First operand 202813 states and 293449 transitions. cyclomatic complexity: 90668 Second operand has 5 states, 5 states have (on average 31.8) internal successors, (159), 5 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:24,289 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:58:24,289 INFO L93 Difference]: Finished difference Result 547726 states and 795256 transitions. [2022-12-13 12:58:24,289 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 547726 states and 795256 transitions. [2022-12-13 12:58:26,044 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 546472 [2022-12-13 12:58:26,989 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 547726 states to 547726 states and 795256 transitions. [2022-12-13 12:58:26,989 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 547726 [2022-12-13 12:58:27,182 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 547726 [2022-12-13 12:58:27,182 INFO L73 IsDeterministic]: Start isDeterministic. Operand 547726 states and 795256 transitions. [2022-12-13 12:58:27,354 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:58:27,354 INFO L218 hiAutomatonCegarLoop]: Abstraction has 547726 states and 795256 transitions. [2022-12-13 12:58:27,685 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 547726 states and 795256 transitions. [2022-12-13 12:58:29,966 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 547726 to 207976. [2022-12-13 12:58:30,051 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 207976 states, 207976 states have (on average 1.4358002846482287) internal successors, (298612), 207975 states have internal predecessors, (298612), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:30,368 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207976 states to 207976 states and 298612 transitions. [2022-12-13 12:58:30,369 INFO L240 hiAutomatonCegarLoop]: Abstraction has 207976 states and 298612 transitions. [2022-12-13 12:58:30,369 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-12-13 12:58:30,370 INFO L428 stractBuchiCegarLoop]: Abstraction has 207976 states and 298612 transitions. [2022-12-13 12:58:30,370 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2022-12-13 12:58:30,370 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 207976 states and 298612 transitions. [2022-12-13 12:58:30,948 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 207488 [2022-12-13 12:58:30,949 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:58:30,949 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:58:30,950 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:30,950 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:30,950 INFO L748 eck$LassoCheckResult]: Stem: 1259541#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1259542#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1260459#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1260460#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1261373#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 1260914#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1260915#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1259770#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1259771#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1260258#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1260087#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1260088#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1259836#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1259837#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1260264#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1260449#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1260627#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1260667#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1259854#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1259855#L1258 assume !(0 == ~M_E~0); 1261177#L1258-2 assume !(0 == ~T1_E~0); 1260177#L1263-1 assume !(0 == ~T2_E~0); 1260178#L1268-1 assume !(0 == ~T3_E~0); 1260496#L1273-1 assume !(0 == ~T4_E~0); 1261153#L1278-1 assume !(0 == ~T5_E~0); 1260969#L1283-1 assume !(0 == ~T6_E~0); 1260970#L1288-1 assume !(0 == ~T7_E~0); 1261301#L1293-1 assume !(0 == ~T8_E~0); 1261281#L1298-1 assume !(0 == ~T9_E~0); 1261171#L1303-1 assume !(0 == ~T10_E~0); 1259643#L1308-1 assume !(0 == ~T11_E~0); 1259584#L1313-1 assume !(0 == ~T12_E~0); 1259585#L1318-1 assume !(0 == ~T13_E~0); 1259592#L1323-1 assume !(0 == ~E_1~0); 1259593#L1328-1 assume !(0 == ~E_2~0); 1259780#L1333-1 assume !(0 == ~E_3~0); 1260821#L1338-1 assume !(0 == ~E_4~0); 1260822#L1343-1 assume !(0 == ~E_5~0); 1260945#L1348-1 assume !(0 == ~E_6~0); 1261333#L1353-1 assume !(0 == ~E_7~0); 1260519#L1358-1 assume !(0 == ~E_8~0); 1260520#L1363-1 assume !(0 == ~E_9~0); 1260851#L1368-1 assume !(0 == ~E_10~0); 1259437#L1373-1 assume !(0 == ~E_11~0); 1259438#L1378-1 assume !(0 == ~E_12~0); 1259723#L1383-1 assume !(0 == ~E_13~0); 1259724#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1260523#L607 assume !(1 == ~m_pc~0); 1259801#L607-2 is_master_triggered_~__retres1~0#1 := 0; 1259802#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1260323#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1260324#L1560 assume !(0 != activate_threads_~tmp~1#1); 1260429#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1259605#L626 assume !(1 == ~t1_pc~0); 1259606#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1259897#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1259898#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1260832#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 1259510#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1259511#L645 assume !(1 == ~t2_pc~0); 1259577#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1259578#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1259688#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1259689#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 1260403#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1260404#L664 assume !(1 == ~t3_pc~0); 1260877#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1259376#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1259377#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1260045#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 1260046#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1261193#L683 assume !(1 == ~t4_pc~0); 1260648#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1260597#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1260598#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1261354#L1592 assume !(0 != activate_threads_~tmp___3~0#1); 1260770#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1260347#L702 assume 1 == ~t5_pc~0; 1260348#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1260280#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1260766#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1261175#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 1261054#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1259410#L721 assume !(1 == ~t6_pc~0); 1259389#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1259390#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1259533#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1259674#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 1260058#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1260703#L740 assume 1 == ~t7_pc~0; 1259453#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1259289#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1259290#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1259279#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 1259280#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1259984#L759 assume !(1 == ~t8_pc~0); 1259985#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1260015#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1261269#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1260925#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 1260926#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1261299#L778 assume 1 == ~t9_pc~0; 1261133#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1259436#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1259744#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1259314#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 1259315#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1259618#L797 assume !(1 == ~t10_pc~0); 1259619#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1259756#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1261100#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1260173#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 1260174#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1260475#L816 assume 1 == ~t11_pc~0; 1259352#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1259353#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1260311#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1260064#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 1260065#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1260626#L835 assume 1 == ~t12_pc~0; 1260490#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1259500#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1259340#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1259341#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 1260227#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1260228#L854 assume !(1 == ~t13_pc~0); 1259838#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 1259839#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1259892#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1259531#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1259532#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1261045#L1401 assume !(1 == ~M_E~0); 1260051#L1401-2 assume !(1 == ~T1_E~0); 1260052#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1260692#L1411-1 assume !(1 == ~T3_E~0); 1260693#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1260319#L1421-1 assume !(1 == ~T5_E~0); 1259834#L1426-1 assume !(1 == ~T6_E~0); 1259835#L1431-1 assume !(1 == ~T7_E~0); 1259387#L1436-1 assume !(1 == ~T8_E~0); 1259388#L1441-1 assume !(1 == ~T9_E~0); 1343995#L1446-1 assume !(1 == ~T10_E~0); 1343981#L1451-1 assume !(1 == ~T11_E~0); 1343969#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1260545#L1461-1 assume !(1 == ~T13_E~0); 1260081#L1466-1 assume !(1 == ~E_1~0); 1260082#L1471-1 assume !(1 == ~E_2~0); 1260923#L1476-1 assume !(1 == ~E_3~0); 1260924#L1481-1 assume !(1 == ~E_4~0); 1261107#L1486-1 assume !(1 == ~E_5~0); 1430087#L1491-1 assume !(1 == ~E_6~0); 1259325#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1259326#L1501-1 assume !(1 == ~E_8~0); 1260159#L1506-1 assume !(1 == ~E_9~0); 1260160#L1511-1 assume !(1 == ~E_10~0); 1260110#L1516-1 assume !(1 == ~E_11~0); 1260111#L1521-1 assume !(1 == ~E_12~0); 1259323#L1526-1 assume !(1 == ~E_13~0); 1259324#L1531-1 assume { :end_inline_reset_delta_events } true; 1259862#L1892-2 [2022-12-13 12:58:30,950 INFO L750 eck$LassoCheckResult]: Loop: 1259862#L1892-2 assume !false; 1465345#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1465294#L1233 assume !false; 1461993#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1418499#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1418500#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1418493#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1418494#L1046 assume !(0 != eval_~tmp~0#1); 1453703#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1453699#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1453694#L1258-3 assume !(0 == ~M_E~0); 1453690#L1258-5 assume !(0 == ~T1_E~0); 1453684#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1453680#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1453676#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1453672#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1453667#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1453663#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1453657#L1293-3 assume !(0 == ~T8_E~0); 1453653#L1298-3 assume !(0 == ~T9_E~0); 1453649#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1453645#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1453640#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1453636#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1453630#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1453626#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1453622#L1333-3 assume !(0 == ~E_3~0); 1453618#L1338-3 assume !(0 == ~E_4~0); 1453613#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1453609#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1453603#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1453599#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1453595#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1453591#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1453586#L1373-3 assume !(0 == ~E_11~0); 1453582#L1378-3 assume !(0 == ~E_12~0); 1453576#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1453572#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1453571#L607-42 assume !(1 == ~m_pc~0); 1453570#L607-44 is_master_triggered_~__retres1~0#1 := 0; 1453569#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1453568#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1453567#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1453566#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1453565#L626-42 assume !(1 == ~t1_pc~0); 1453564#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 1453562#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1453561#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1453560#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1453559#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1453558#L645-42 assume !(1 == ~t2_pc~0); 1453557#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1453556#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1453555#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1453554#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1453553#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1453552#L664-42 assume !(1 == ~t3_pc~0); 1453551#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 1453550#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1453549#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1453548#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1453547#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1453546#L683-42 assume 1 == ~t4_pc~0; 1453544#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1453542#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1453540#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1453538#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1453535#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1453532#L702-42 assume 1 == ~t5_pc~0; 1453527#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1453504#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1453499#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1453495#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 1453490#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1453486#L721-42 assume 1 == ~t6_pc~0; 1453480#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1453476#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1453471#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1453467#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1453462#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1453425#L740-42 assume 1 == ~t7_pc~0; 1453418#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1453413#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1453373#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1453369#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1453365#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1452924#L759-42 assume 1 == ~t8_pc~0; 1452920#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1452918#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1452916#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1452914#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1452912#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1452910#L778-42 assume 1 == ~t9_pc~0; 1452906#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1452903#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1452901#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1452899#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1452897#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1452894#L797-42 assume !(1 == ~t10_pc~0); 1452892#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 1452889#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1452887#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1452885#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1452883#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1452880#L816-42 assume 1 == ~t11_pc~0; 1452878#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1452875#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1452873#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1452871#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1452869#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1452868#L835-42 assume !(1 == ~t12_pc~0); 1452866#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 1452863#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1452681#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1452678#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1452676#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1452674#L854-42 assume 1 == ~t13_pc~0; 1452672#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1452666#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1452659#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1452651#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1452642#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1452636#L1401-3 assume !(1 == ~M_E~0); 1448120#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1452554#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1321766#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1452545#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1452540#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1452499#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1452465#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1452463#L1436-3 assume !(1 == ~T8_E~0); 1414718#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1452459#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1452457#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1452455#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1452453#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1452451#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1452449#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1452446#L1476-3 assume !(1 == ~E_3~0); 1442708#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1452423#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1452419#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1452417#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1452381#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1452379#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1452377#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1452374#L1516-3 assume !(1 == ~E_11~0); 1428758#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1452371#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1452369#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1452318#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1452314#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1452312#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1452309#L1911 assume !(0 == start_simulation_~tmp~3#1); 1452310#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1465405#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1465390#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1465387#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1465385#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1465383#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1465381#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1465379#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 1259862#L1892-2 [2022-12-13 12:58:30,951 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:30,951 INFO L85 PathProgramCache]: Analyzing trace with hash 1040734579, now seen corresponding path program 1 times [2022-12-13 12:58:30,951 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:30,951 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [16110213] [2022-12-13 12:58:30,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:30,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:30,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:30,992 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:30,992 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:30,993 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [16110213] [2022-12-13 12:58:30,993 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [16110213] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:30,993 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:30,993 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-13 12:58:30,993 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [791677243] [2022-12-13 12:58:30,993 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:30,993 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:58:30,994 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:30,994 INFO L85 PathProgramCache]: Analyzing trace with hash 1689118983, now seen corresponding path program 1 times [2022-12-13 12:58:30,994 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:30,994 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [876515089] [2022-12-13 12:58:30,994 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:30,994 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:31,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:31,029 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:31,030 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:31,030 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [876515089] [2022-12-13 12:58:31,030 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [876515089] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:31,030 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:31,030 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:31,030 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1913784074] [2022-12-13 12:58:31,030 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:31,031 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:58:31,031 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:58:31,031 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-12-13 12:58:31,031 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-12-13 12:58:31,031 INFO L87 Difference]: Start difference. First operand 207976 states and 298612 transitions. cyclomatic complexity: 90668 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:32,235 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:58:32,235 INFO L93 Difference]: Finished difference Result 399423 states and 571771 transitions. [2022-12-13 12:58:32,236 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 399423 states and 571771 transitions. [2022-12-13 12:58:33,682 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 398408 [2022-12-13 12:58:34,292 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 399423 states to 399423 states and 571771 transitions. [2022-12-13 12:58:34,292 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 399423 [2022-12-13 12:58:34,424 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 399423 [2022-12-13 12:58:34,424 INFO L73 IsDeterministic]: Start isDeterministic. Operand 399423 states and 571771 transitions. [2022-12-13 12:58:34,658 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:58:34,658 INFO L218 hiAutomatonCegarLoop]: Abstraction has 399423 states and 571771 transitions. [2022-12-13 12:58:34,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 399423 states and 571771 transitions. [2022-12-13 12:58:37,541 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 399423 to 399135. [2022-12-13 12:58:37,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 399135 states, 399135 states have (on average 1.4318037756648754) internal successors, (571483), 399134 states have internal predecessors, (571483), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:38,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399135 states to 399135 states and 571483 transitions. [2022-12-13 12:58:38,615 INFO L240 hiAutomatonCegarLoop]: Abstraction has 399135 states and 571483 transitions. [2022-12-13 12:58:38,615 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-12-13 12:58:38,616 INFO L428 stractBuchiCegarLoop]: Abstraction has 399135 states and 571483 transitions. [2022-12-13 12:58:38,616 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2022-12-13 12:58:38,616 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 399135 states and 571483 transitions. [2022-12-13 12:58:39,482 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 398120 [2022-12-13 12:58:39,482 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:58:39,482 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:58:39,483 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:39,483 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:58:39,484 INFO L748 eck$LassoCheckResult]: Stem: 1866945#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1866946#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1867871#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1867872#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1868810#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 1868338#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1868339#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1867173#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1867174#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1867662#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1867492#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1867493#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1867238#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1867239#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1867672#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1867859#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1868042#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1868080#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1867254#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1867255#L1258 assume !(0 == ~M_E~0); 1868610#L1258-2 assume !(0 == ~T1_E~0); 1867578#L1263-1 assume !(0 == ~T2_E~0); 1867579#L1268-1 assume !(0 == ~T3_E~0); 1867910#L1273-1 assume !(0 == ~T4_E~0); 1868580#L1278-1 assume !(0 == ~T5_E~0); 1868397#L1283-1 assume !(0 == ~T6_E~0); 1868398#L1288-1 assume !(0 == ~T7_E~0); 1868729#L1293-1 assume !(0 == ~T8_E~0); 1868710#L1298-1 assume !(0 == ~T9_E~0); 1868604#L1303-1 assume !(0 == ~T10_E~0); 1867049#L1308-1 assume !(0 == ~T11_E~0); 1866988#L1313-1 assume !(0 == ~T12_E~0); 1866989#L1318-1 assume !(0 == ~T13_E~0); 1866994#L1323-1 assume !(0 == ~E_1~0); 1866995#L1328-1 assume !(0 == ~E_2~0); 1867183#L1333-1 assume !(0 == ~E_3~0); 1868240#L1338-1 assume !(0 == ~E_4~0); 1868241#L1343-1 assume !(0 == ~E_5~0); 1868371#L1348-1 assume !(0 == ~E_6~0); 1868775#L1353-1 assume !(0 == ~E_7~0); 1867935#L1358-1 assume !(0 == ~E_8~0); 1867936#L1363-1 assume !(0 == ~E_9~0); 1868269#L1368-1 assume !(0 == ~E_10~0); 1866840#L1373-1 assume !(0 == ~E_11~0); 1866841#L1378-1 assume !(0 == ~E_12~0); 1867125#L1383-1 assume !(0 == ~E_13~0); 1867126#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1867939#L607 assume !(1 == ~m_pc~0); 1867201#L607-2 is_master_triggered_~__retres1~0#1 := 0; 1867202#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1867730#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1867731#L1560 assume !(0 != activate_threads_~tmp~1#1); 1867840#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1867009#L626 assume !(1 == ~t1_pc~0); 1867010#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1867294#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1867295#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1868250#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 1866913#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1866914#L645 assume !(1 == ~t2_pc~0); 1866981#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1866982#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1867093#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1867094#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 1867812#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1867813#L664 assume !(1 == ~t3_pc~0); 1868296#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1866775#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1866776#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1867450#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 1867451#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1868623#L683 assume !(1 == ~t4_pc~0); 1868064#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1868012#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1866799#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1866800#L1592 assume !(0 != activate_threads_~tmp___3~0#1); 1868190#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1867753#L702 assume !(1 == ~t5_pc~0); 1867687#L702-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1867688#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1868184#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1868608#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 1868480#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1866810#L721 assume !(1 == ~t6_pc~0); 1866792#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1866793#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1866937#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1867079#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 1867463#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1868117#L740 assume 1 == ~t7_pc~0; 1866857#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1866695#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1866696#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1866685#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 1866686#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1867385#L759 assume !(1 == ~t8_pc~0); 1867386#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1867420#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1868694#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1868349#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 1868350#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1868728#L778 assume 1 == ~t9_pc~0; 1868560#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1866839#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1867148#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1866718#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 1866719#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1867021#L797 assume !(1 == ~t10_pc~0); 1867022#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1867159#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1868528#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1867574#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 1867575#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1867889#L816 assume 1 == ~t11_pc~0; 1866753#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1866754#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1867718#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1867469#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 1867470#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1868041#L835 assume 1 == ~t12_pc~0; 1867904#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1866904#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1866743#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1866744#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 1867632#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1867633#L854 assume !(1 == ~t13_pc~0); 1867240#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 1867241#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1867289#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1866935#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1866936#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1868473#L1401 assume !(1 == ~M_E~0); 1867456#L1401-2 assume !(1 == ~T1_E~0); 1867457#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1868107#L1411-1 assume !(1 == ~T3_E~0); 1868108#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1868755#L1421-1 assume !(1 == ~T5_E~0); 1867236#L1426-1 assume !(1 == ~T6_E~0); 1867237#L1431-1 assume !(1 == ~T7_E~0); 1866790#L1436-1 assume !(1 == ~T8_E~0); 1866791#L1441-1 assume !(1 == ~T9_E~0); 1867564#L1446-1 assume !(1 == ~T10_E~0); 1867565#L1451-1 assume !(1 == ~T11_E~0); 1868368#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1867959#L1461-1 assume !(1 == ~T13_E~0); 1867486#L1466-1 assume !(1 == ~E_1~0); 1867487#L1471-1 assume !(1 == ~E_2~0); 1868347#L1476-1 assume !(1 == ~E_3~0); 1868348#L1481-1 assume !(1 == ~E_4~0); 1868536#L1486-1 assume !(1 == ~E_5~0); 1867063#L1491-1 assume !(1 == ~E_6~0); 1866728#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1866729#L1501-1 assume !(1 == ~E_8~0); 1867560#L1506-1 assume !(1 == ~E_9~0); 1867561#L1511-1 assume !(1 == ~E_10~0); 1867515#L1516-1 assume !(1 == ~E_11~0); 1866683#L1521-1 assume !(1 == ~E_12~0); 1866684#L1526-1 assume !(1 == ~E_13~0); 1866727#L1531-1 assume { :end_inline_reset_delta_events } true; 1867262#L1892-2 [2022-12-13 12:58:39,484 INFO L750 eck$LassoCheckResult]: Loop: 1867262#L1892-2 assume !false; 2188148#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2188144#L1233 assume !false; 2188143#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 2183190#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 2183188#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 2183186#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2183182#L1046 assume !(0 != eval_~tmp~0#1); 2183184#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2189942#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2189941#L1258-3 assume !(0 == ~M_E~0); 2189940#L1258-5 assume !(0 == ~T1_E~0); 2189939#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2189938#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2189936#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2189935#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2189934#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2189933#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2189932#L1293-3 assume !(0 == ~T8_E~0); 2189930#L1298-3 assume !(0 == ~T9_E~0); 2189929#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 2189928#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 2189927#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 2189926#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 2189925#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2189923#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2189921#L1333-3 assume !(0 == ~E_3~0); 2189919#L1338-3 assume !(0 == ~E_4~0); 2189917#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2189915#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2189913#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2189911#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2189908#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2189906#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 2189904#L1373-3 assume !(0 == ~E_11~0); 2189902#L1378-3 assume !(0 == ~E_12~0); 2189900#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 2189898#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2189896#L607-42 assume !(1 == ~m_pc~0); 2189894#L607-44 is_master_triggered_~__retres1~0#1 := 0; 2189892#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2189890#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2189888#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2189886#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2189884#L626-42 assume 1 == ~t1_pc~0; 2189881#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2189879#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2189877#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2189875#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2189871#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2189869#L645-42 assume !(1 == ~t2_pc~0); 2189867#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 2189865#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2189862#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2189860#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2189858#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2189856#L664-42 assume !(1 == ~t3_pc~0); 2189854#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 2189852#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2189850#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2189848#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2189846#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2189843#L683-42 assume 1 == ~t4_pc~0; 2189841#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2189842#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2189937#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2189830#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2189828#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2189825#L702-42 assume !(1 == ~t5_pc~0); 2189823#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 2189821#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2189819#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2189817#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 2189815#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2189811#L721-42 assume !(1 == ~t6_pc~0); 2189809#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 2189805#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2189803#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2189801#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2189799#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2189796#L740-42 assume 1 == ~t7_pc~0; 2189793#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2189791#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2189789#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2189787#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2189785#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2189782#L759-42 assume 1 == ~t8_pc~0; 2189779#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2189777#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2189775#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2189773#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2189771#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2189768#L778-42 assume !(1 == ~t9_pc~0); 2189765#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 2189763#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2189761#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2189759#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2189757#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2189754#L797-42 assume 1 == ~t10_pc~0; 2189751#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 2189749#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2189747#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 2189745#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2189743#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2189740#L816-42 assume !(1 == ~t11_pc~0); 2189737#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 2189735#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2189733#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 2189731#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2189727#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 2189726#L835-42 assume !(1 == ~t12_pc~0); 2189725#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 2189723#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 2189722#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 2189721#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 2189720#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 2189719#L854-42 assume 1 == ~t13_pc~0; 2189717#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 2189715#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 2189713#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 2189711#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 2189709#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2189309#L1401-3 assume !(1 == ~M_E~0); 2189306#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2189303#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2061454#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2189296#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2189293#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2189290#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2189287#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2189284#L1436-3 assume !(1 == ~T8_E~0); 2084133#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2189277#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2189274#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 2189271#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 2189268#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 2188312#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2188310#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2188307#L1476-3 assume !(1 == ~E_3~0); 2149220#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2188302#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2188300#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2188295#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2188296#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2194712#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2194710#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2194708#L1516-3 assume !(1 == ~E_11~0); 2174903#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 2194705#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 2194703#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 2188246#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 2188242#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 2188240#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 2188236#L1911 assume !(0 == start_simulation_~tmp~3#1); 2188237#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 2195726#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 2195712#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 2195711#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 2195710#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2195709#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2195708#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 2195707#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 1867262#L1892-2 [2022-12-13 12:58:39,484 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:39,485 INFO L85 PathProgramCache]: Analyzing trace with hash -944094126, now seen corresponding path program 1 times [2022-12-13 12:58:39,485 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:39,485 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [847555998] [2022-12-13 12:58:39,485 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:39,485 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:39,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:39,528 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:39,528 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:39,529 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [847555998] [2022-12-13 12:58:39,529 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [847555998] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:39,529 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:39,529 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:58:39,529 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1835119169] [2022-12-13 12:58:39,529 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:39,529 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:58:39,530 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:58:39,530 INFO L85 PathProgramCache]: Analyzing trace with hash -1193213371, now seen corresponding path program 1 times [2022-12-13 12:58:39,530 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:58:39,530 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1615275505] [2022-12-13 12:58:39,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:58:39,530 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:58:39,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:58:39,565 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:58:39,566 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:58:39,566 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1615275505] [2022-12-13 12:58:39,566 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1615275505] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:58:39,566 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:58:39,566 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:58:39,566 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1470028263] [2022-12-13 12:58:39,566 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:58:39,567 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:58:39,567 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:58:39,567 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:58:39,567 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:58:39,567 INFO L87 Difference]: Start difference. First operand 399135 states and 571483 transitions. cyclomatic complexity: 172412 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:58:42,970 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:58:42,970 INFO L93 Difference]: Finished difference Result 1144622 states and 1630592 transitions. [2022-12-13 12:58:42,970 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1144622 states and 1630592 transitions. [2022-12-13 12:58:47,096 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 1127544 [2022-12-13 12:58:49,271 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1144622 states to 1144622 states and 1630592 transitions. [2022-12-13 12:58:49,271 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1144622 [2022-12-13 12:58:49,592 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1144622 [2022-12-13 12:58:49,593 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1144622 states and 1630592 transitions. [2022-12-13 12:58:49,871 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-12-13 12:58:49,872 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1144622 states and 1630592 transitions. [2022-12-13 12:58:50,307 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1144622 states and 1630592 transitions. [2022-12-13 12:58:58,099 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1144622 to 1115374. [2022-12-13 12:58:58,998 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1115374 states, 1115374 states have (on average 1.426348471454418) internal successors, (1590912), 1115373 states have internal predecessors, (1590912), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:59:01,508 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1115374 states to 1115374 states and 1590912 transitions. [2022-12-13 12:59:01,508 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1115374 states and 1590912 transitions. [2022-12-13 12:59:01,509 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-13 12:59:01,509 INFO L428 stractBuchiCegarLoop]: Abstraction has 1115374 states and 1590912 transitions. [2022-12-13 12:59:01,509 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2022-12-13 12:59:01,509 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1115374 states and 1590912 transitions. [2022-12-13 12:59:03,946 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 1113144 [2022-12-13 12:59:03,946 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-12-13 12:59:03,946 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-12-13 12:59:03,948 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:59:03,948 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-13 12:59:03,948 INFO L748 eck$LassoCheckResult]: Stem: 3410713#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 3410714#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 3411648#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3411649#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3412601#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 3412109#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3412110#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3410944#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3410945#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3411436#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3411261#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3411262#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3411008#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3411009#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3411446#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3411638#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 3411816#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 3411852#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 3411024#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3411025#L1258 assume !(0 == ~M_E~0); 3412382#L1258-2 assume !(0 == ~T1_E~0); 3411353#L1263-1 assume !(0 == ~T2_E~0); 3411354#L1268-1 assume !(0 == ~T3_E~0); 3411688#L1273-1 assume !(0 == ~T4_E~0); 3412352#L1278-1 assume !(0 == ~T5_E~0); 3412179#L1283-1 assume !(0 == ~T6_E~0); 3412180#L1288-1 assume !(0 == ~T7_E~0); 3412510#L1293-1 assume !(0 == ~T8_E~0); 3412484#L1298-1 assume !(0 == ~T9_E~0); 3412371#L1303-1 assume !(0 == ~T10_E~0); 3410817#L1308-1 assume !(0 == ~T11_E~0); 3410756#L1313-1 assume !(0 == ~T12_E~0); 3410757#L1318-1 assume !(0 == ~T13_E~0); 3410763#L1323-1 assume !(0 == ~E_1~0); 3410764#L1328-1 assume !(0 == ~E_2~0); 3410954#L1333-1 assume !(0 == ~E_3~0); 3412015#L1338-1 assume !(0 == ~E_4~0); 3412016#L1343-1 assume !(0 == ~E_5~0); 3412144#L1348-1 assume !(0 == ~E_6~0); 3412556#L1353-1 assume !(0 == ~E_7~0); 3411710#L1358-1 assume !(0 == ~E_8~0); 3411711#L1363-1 assume !(0 == ~E_9~0); 3412040#L1368-1 assume !(0 == ~E_10~0); 3410610#L1373-1 assume !(0 == ~E_11~0); 3410611#L1378-1 assume !(0 == ~E_12~0); 3410894#L1383-1 assume !(0 == ~E_13~0); 3410895#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3411714#L607 assume !(1 == ~m_pc~0); 3410971#L607-2 is_master_triggered_~__retres1~0#1 := 0; 3410972#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3411505#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3411506#L1560 assume !(0 != activate_threads_~tmp~1#1); 3411615#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3410778#L626 assume !(1 == ~t1_pc~0); 3410779#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3411065#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3411066#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3412024#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 3410680#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3410681#L645 assume !(1 == ~t2_pc~0); 3410749#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3410750#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3410863#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3410864#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 3411589#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3411590#L664 assume !(1 == ~t3_pc~0); 3412068#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3410546#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3410547#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3411219#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 3411220#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3412400#L683 assume !(1 == ~t4_pc~0); 3411835#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3412026#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3410570#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3410571#L1592 assume !(0 != activate_threads_~tmp___3~0#1); 3411961#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3411531#L702 assume !(1 == ~t5_pc~0); 3411460#L702-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3411461#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3411956#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3412375#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 3412256#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3410581#L721 assume !(1 == ~t6_pc~0); 3410563#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3410564#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3410705#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3410849#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 3411232#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3411890#L740 assume !(1 == ~t7_pc~0); 3411891#L740-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3410464#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3410465#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3410454#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 3410455#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3411156#L759 assume !(1 == ~t8_pc~0); 3411157#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3411188#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3412469#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3412120#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 3412121#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3412509#L778 assume 1 == ~t9_pc~0; 3412331#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3410609#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3410918#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3410489#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 3410490#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3410790#L797 assume !(1 == ~t10_pc~0); 3410791#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3410930#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3412301#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3411349#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 3411350#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3411666#L816 assume 1 == ~t11_pc~0; 3410524#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3410525#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3411493#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3411238#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 3411239#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 3411815#L835 assume 1 == ~t12_pc~0; 3411683#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 3410671#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3410514#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3410515#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 3411405#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 3411406#L854 assume !(1 == ~t13_pc~0); 3411010#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 3411011#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 3411060#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3410703#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 3410704#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3412250#L1401 assume !(1 == ~M_E~0); 3411225#L1401-2 assume !(1 == ~T1_E~0); 3411226#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3412258#L1411-1 assume !(1 == ~T3_E~0); 3412542#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3412543#L1421-1 assume !(1 == ~T5_E~0); 3411006#L1426-1 assume !(1 == ~T6_E~0); 3411007#L1431-1 assume !(1 == ~T7_E~0); 3410561#L1436-1 assume !(1 == ~T8_E~0); 3410562#L1441-1 assume !(1 == ~T9_E~0); 4005217#L1446-1 assume !(1 == ~T10_E~0); 4005216#L1451-1 assume !(1 == ~T11_E~0); 4005215#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4005214#L1461-1 assume !(1 == ~T13_E~0); 4005213#L1466-1 assume !(1 == ~E_1~0); 4005212#L1471-1 assume !(1 == ~E_2~0); 4005211#L1476-1 assume !(1 == ~E_3~0); 4005210#L1481-1 assume !(1 == ~E_4~0); 4005208#L1486-1 assume !(1 == ~E_5~0); 4005206#L1491-1 assume !(1 == ~E_6~0); 4005204#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 4005202#L1501-1 assume !(1 == ~E_8~0); 4005200#L1506-1 assume !(1 == ~E_9~0); 4005198#L1511-1 assume !(1 == ~E_10~0); 4005197#L1516-1 assume !(1 == ~E_11~0); 4005195#L1521-1 assume !(1 == ~E_12~0); 4005194#L1526-1 assume !(1 == ~E_13~0); 3993952#L1531-1 assume { :end_inline_reset_delta_events } true; 3993953#L1892-2 [2022-12-13 12:59:03,949 INFO L750 eck$LassoCheckResult]: Loop: 3993953#L1892-2 assume !false; 4089991#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4089990#L1233 assume !false; 4089989#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 3993058#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 3993056#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 3993055#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3993053#L1046 assume !(0 != eval_~tmp~0#1); 3993054#eval_returnLabel#1 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4070736#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4070726#L1258-3 assume !(0 == ~M_E~0); 4070727#L1258-5 assume !(0 == ~T1_E~0); 4070718#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4070719#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4070708#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4070709#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4070697#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4070698#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4070686#L1293-3 assume !(0 == ~T8_E~0); 4070687#L1298-3 assume !(0 == ~T9_E~0); 4070675#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4070676#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4070665#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4070666#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4070655#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4070656#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4070646#L1333-3 assume !(0 == ~E_3~0); 4070647#L1338-3 assume !(0 == ~E_4~0); 4070635#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4070636#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4070624#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4070625#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4070614#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4070615#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4070603#L1373-3 assume !(0 == ~E_11~0); 4070604#L1378-3 assume !(0 == ~E_12~0); 4070589#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 4070590#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4070573#L607-42 assume !(1 == ~m_pc~0); 4070574#L607-44 is_master_triggered_~__retres1~0#1 := 0; 4070555#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4070556#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4070542#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4070543#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4070527#L626-42 assume 1 == ~t1_pc~0; 4070528#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4070511#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4070512#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4070495#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4070496#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4070479#L645-42 assume !(1 == ~t2_pc~0); 4070480#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 4070467#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4070468#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4070454#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4070455#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4070441#L664-42 assume !(1 == ~t3_pc~0); 4070442#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 4070426#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4070427#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4070412#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4070413#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4070372#L683-42 assume !(1 == ~t4_pc~0); 4070374#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 4070364#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4070365#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4070359#L1592-42 assume !(0 != activate_threads_~tmp___3~0#1); 4070358#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4070351#L702-42 assume !(1 == ~t5_pc~0); 4070352#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 4070345#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4070346#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4070338#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 4070339#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4070331#L721-42 assume 1 == ~t6_pc~0; 4070332#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4070323#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4070324#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4070316#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4070317#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4070310#L740-42 assume !(1 == ~t7_pc~0); 4070311#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 4070304#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4070305#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4070297#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4070298#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4070290#L759-42 assume !(1 == ~t8_pc~0); 4070292#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 4070269#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4070270#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4070263#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4070264#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4070255#L778-42 assume !(1 == ~t9_pc~0); 4070256#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 4070248#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4070249#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4070242#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4070243#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4070236#L797-42 assume !(1 == ~t10_pc~0); 4070238#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 4066480#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4066481#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4065174#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4065175#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4065167#L816-42 assume !(1 == ~t11_pc~0); 4065168#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 4065160#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4065161#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4065154#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4065155#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4065147#L835-42 assume 1 == ~t12_pc~0; 4065148#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4065138#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4065139#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4065132#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4065133#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4065125#L854-42 assume 1 == ~t13_pc~0; 4065126#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4065118#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4065119#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4065112#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4065113#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4065103#L1401-3 assume !(1 == ~M_E~0); 4065104#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4065097#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4053365#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4065087#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4065088#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4065078#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4065079#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4064994#L1436-3 assume !(1 == ~T8_E~0); 4064995#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4064986#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4064987#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4064978#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4064979#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 4064971#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4064972#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4064964#L1476-3 assume !(1 == ~E_3~0); 3995617#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4064956#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4064957#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4064936#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4064937#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4064930#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4064931#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3994155#L1516-3 assume !(1 == ~E_11~0); 3994156#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 3994149#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 3994150#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 3994116#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 3994112#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 3994109#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 3994110#L1911 assume !(0 == start_simulation_~tmp~3#1); 4090018#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4090017#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4090003#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4090002#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 4090001#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4090000#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4089999#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 4089998#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 3993953#L1892-2 [2022-12-13 12:59:03,949 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:59:03,949 INFO L85 PathProgramCache]: Analyzing trace with hash -37337679, now seen corresponding path program 1 times [2022-12-13 12:59:03,949 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:59:03,949 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [60510695] [2022-12-13 12:59:03,950 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:59:03,950 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:59:03,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:59:04,012 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:59:04,012 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:59:04,013 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [60510695] [2022-12-13 12:59:04,013 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [60510695] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:59:04,013 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:59:04,013 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-13 12:59:04,013 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [598037854] [2022-12-13 12:59:04,013 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:59:04,013 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-12-13 12:59:04,014 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-13 12:59:04,014 INFO L85 PathProgramCache]: Analyzing trace with hash -659452415, now seen corresponding path program 1 times [2022-12-13 12:59:04,014 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-12-13 12:59:04,014 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [551619327] [2022-12-13 12:59:04,014 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-13 12:59:04,014 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-13 12:59:04,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-13 12:59:04,068 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-13 12:59:04,069 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-12-13 12:59:04,069 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [551619327] [2022-12-13 12:59:04,069 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [551619327] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-13 12:59:04,069 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-13 12:59:04,069 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-13 12:59:04,069 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1465429423] [2022-12-13 12:59:04,069 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-13 12:59:04,070 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-12-13 12:59:04,070 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-12-13 12:59:04,070 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-13 12:59:04,070 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-13 12:59:04,070 INFO L87 Difference]: Start difference. First operand 1115374 states and 1590912 transitions. cyclomatic complexity: 475666 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-12-13 12:59:13,295 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-13 12:59:13,295 INFO L93 Difference]: Finished difference Result 3181181 states and 4518021 transitions. [2022-12-13 12:59:13,295 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3181181 states and 4518021 transitions.