/usr/bin/java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerCInline.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Overflow-32bit-Automizer_Default.epf -i ../sv-benchmarks/c/array-fpi/pcompf.c -------------------------------------------------------------------------------- This is Ultimate 0.2.2-dev-05d3305-m [2022-10-16 10:44:17,569 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-10-16 10:44:17,572 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-10-16 10:44:17,633 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-10-16 10:44:17,634 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-10-16 10:44:17,635 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-10-16 10:44:17,637 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-10-16 10:44:17,639 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-10-16 10:44:17,641 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-10-16 10:44:17,642 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-10-16 10:44:17,643 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-10-16 10:44:17,645 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-10-16 10:44:17,645 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-10-16 10:44:17,646 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-10-16 10:44:17,648 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-10-16 10:44:17,649 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-10-16 10:44:17,650 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-10-16 10:44:17,651 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-10-16 10:44:17,653 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-10-16 10:44:17,655 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-10-16 10:44:17,657 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-10-16 10:44:17,664 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-10-16 10:44:17,665 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-10-16 10:44:17,666 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-10-16 10:44:17,671 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2022-10-16 10:44:17,680 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-10-16 10:44:17,681 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-10-16 10:44:17,682 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-10-16 10:44:17,683 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Overflow-32bit-Automizer_Default.epf [2022-10-16 10:44:17,710 INFO L113 SettingsManager]: Loading preferences was successful [2022-10-16 10:44:17,710 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-10-16 10:44:17,711 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-10-16 10:44:17,711 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-10-16 10:44:17,712 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-10-16 10:44:17,712 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-10-16 10:44:17,713 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-10-16 10:44:17,713 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-10-16 10:44:17,713 INFO L138 SettingsManager]: * Use SBE=true [2022-10-16 10:44:17,714 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-10-16 10:44:17,714 INFO L138 SettingsManager]: * sizeof long=4 [2022-10-16 10:44:17,714 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-10-16 10:44:17,714 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-10-16 10:44:17,715 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-10-16 10:44:17,715 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-10-16 10:44:17,715 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-10-16 10:44:17,715 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-10-16 10:44:17,716 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-10-16 10:44:17,716 INFO L138 SettingsManager]: * Check absence of signed integer overflows=true [2022-10-16 10:44:17,716 INFO L138 SettingsManager]: * sizeof long double=12 [2022-10-16 10:44:17,716 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-10-16 10:44:17,717 INFO L138 SettingsManager]: * Use constant arrays=true [2022-10-16 10:44:17,717 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-10-16 10:44:17,717 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-10-16 10:44:17,717 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-10-16 10:44:17,718 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-10-16 10:44:17,718 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-10-16 10:44:17,718 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-10-16 10:44:17,718 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-10-16 10:44:17,719 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-10-16 10:44:17,719 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-10-16 10:44:17,719 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-10-16 10:44:17,719 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-10-16 10:44:17,720 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release [2022-10-16 10:44:18,060 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-10-16 10:44:18,103 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-10-16 10:44:18,107 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-10-16 10:44:18,108 INFO L271 PluginConnector]: Initializing CDTParser... [2022-10-16 10:44:18,109 INFO L275 PluginConnector]: CDTParser initialized [2022-10-16 10:44:18,111 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/array-fpi/pcompf.c [2022-10-16 10:44:18,181 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/99b6c6f6d/fa89248b0fce441395bbe0c65f21758f/FLAG8fc0d621f [2022-10-16 10:44:18,752 INFO L306 CDTParser]: Found 1 translation units. [2022-10-16 10:44:18,753 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/array-fpi/pcompf.c [2022-10-16 10:44:18,763 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/99b6c6f6d/fa89248b0fce441395bbe0c65f21758f/FLAG8fc0d621f [2022-10-16 10:44:19,117 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/99b6c6f6d/fa89248b0fce441395bbe0c65f21758f [2022-10-16 10:44:19,120 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-10-16 10:44:19,128 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2022-10-16 10:44:19,132 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-10-16 10:44:19,132 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-10-16 10:44:19,136 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-10-16 10:44:19,138 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.10 10:44:19" (1/1) ... [2022-10-16 10:44:19,140 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2ec32caa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.10 10:44:19, skipping insertion in model container [2022-10-16 10:44:19,140 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.10 10:44:19" (1/1) ... [2022-10-16 10:44:19,148 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-10-16 10:44:19,167 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-10-16 10:44:19,332 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/array-fpi/pcompf.c[589,602] [2022-10-16 10:44:19,356 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-16 10:44:19,366 INFO L203 MainTranslator]: Completed pre-run [2022-10-16 10:44:19,381 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/array-fpi/pcompf.c[589,602] [2022-10-16 10:44:19,392 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-16 10:44:19,408 INFO L208 MainTranslator]: Completed translation [2022-10-16 10:44:19,409 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.10 10:44:19 WrapperNode [2022-10-16 10:44:19,409 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-10-16 10:44:19,411 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-10-16 10:44:19,411 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-10-16 10:44:19,411 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-10-16 10:44:19,419 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.10 10:44:19" (1/1) ... [2022-10-16 10:44:19,428 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.10 10:44:19" (1/1) ... [2022-10-16 10:44:19,455 INFO L138 Inliner]: procedures = 16, calls = 24, calls flagged for inlining = 4, calls inlined = 4, statements flattened = 115 [2022-10-16 10:44:19,455 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-10-16 10:44:19,456 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-10-16 10:44:19,456 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-10-16 10:44:19,457 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-10-16 10:44:19,468 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.10 10:44:19" (1/1) ... [2022-10-16 10:44:19,468 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.10 10:44:19" (1/1) ... [2022-10-16 10:44:19,471 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.10 10:44:19" (1/1) ... [2022-10-16 10:44:19,471 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.10 10:44:19" (1/1) ... [2022-10-16 10:44:19,478 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.10 10:44:19" (1/1) ... [2022-10-16 10:44:19,483 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.10 10:44:19" (1/1) ... [2022-10-16 10:44:19,484 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.10 10:44:19" (1/1) ... [2022-10-16 10:44:19,485 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.10 10:44:19" (1/1) ... [2022-10-16 10:44:19,488 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-10-16 10:44:19,489 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-10-16 10:44:19,489 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-10-16 10:44:19,489 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-10-16 10:44:19,490 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.10 10:44:19" (1/1) ... [2022-10-16 10:44:19,497 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-10-16 10:44:19,510 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-10-16 10:44:19,529 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-10-16 10:44:19,544 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-10-16 10:44:19,593 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-10-16 10:44:19,593 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-10-16 10:44:19,593 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-10-16 10:44:19,594 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2022-10-16 10:44:19,594 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-10-16 10:44:19,594 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-10-16 10:44:19,594 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-10-16 10:44:19,684 INFO L235 CfgBuilder]: Building ICFG [2022-10-16 10:44:19,688 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-10-16 10:44:20,114 INFO L276 CfgBuilder]: Performing block encoding [2022-10-16 10:44:20,125 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-10-16 10:44:20,126 INFO L300 CfgBuilder]: Removed 4 assume(true) statements. [2022-10-16 10:44:20,128 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.10 10:44:20 BoogieIcfgContainer [2022-10-16 10:44:20,128 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-10-16 10:44:20,131 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-10-16 10:44:20,131 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-10-16 10:44:20,135 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-10-16 10:44:20,135 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 16.10 10:44:19" (1/3) ... [2022-10-16 10:44:20,136 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6181c50 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 16.10 10:44:20, skipping insertion in model container [2022-10-16 10:44:20,136 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.10 10:44:19" (2/3) ... [2022-10-16 10:44:20,137 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6181c50 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 16.10 10:44:20, skipping insertion in model container [2022-10-16 10:44:20,137 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.10 10:44:20" (3/3) ... [2022-10-16 10:44:20,139 INFO L112 eAbstractionObserver]: Analyzing ICFG pcompf.c [2022-10-16 10:44:20,160 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-10-16 10:44:20,161 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 26 error locations. [2022-10-16 10:44:20,271 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-10-16 10:44:20,284 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@3ec08d3c, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-10-16 10:44:20,286 INFO L358 AbstractCegarLoop]: Starting to check reachability of 26 error locations. [2022-10-16 10:44:20,293 INFO L276 IsEmpty]: Start isEmpty. Operand has 75 states, 48 states have (on average 1.7708333333333333) internal successors, (85), 74 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:20,302 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2022-10-16 10:44:20,302 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:44:20,303 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:44:20,304 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:44:20,313 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:44:20,314 INFO L85 PathProgramCache]: Analyzing trace with hash 1806845353, now seen corresponding path program 1 times [2022-10-16 10:44:20,326 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:44:20,327 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1055776887] [2022-10-16 10:44:20,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:20,329 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:44:20,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:44:20,586 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:44:20,587 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:44:20,587 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1055776887] [2022-10-16 10:44:20,588 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1055776887] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-16 10:44:20,588 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-16 10:44:20,589 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-16 10:44:20,591 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [894738361] [2022-10-16 10:44:20,592 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-16 10:44:20,597 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2022-10-16 10:44:20,597 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:44:20,631 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-10-16 10:44:20,632 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-10-16 10:44:20,635 INFO L87 Difference]: Start difference. First operand has 75 states, 48 states have (on average 1.7708333333333333) internal successors, (85), 74 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 3.5) internal successors, (7), 2 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:20,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:44:20,659 INFO L93 Difference]: Finished difference Result 145 states and 164 transitions. [2022-10-16 10:44:20,660 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-10-16 10:44:20,662 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 3.5) internal successors, (7), 2 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 7 [2022-10-16 10:44:20,662 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:44:20,671 INFO L225 Difference]: With dead ends: 145 [2022-10-16 10:44:20,675 INFO L226 Difference]: Without dead ends: 69 [2022-10-16 10:44:20,678 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-10-16 10:44:20,684 INFO L413 NwaCegarLoop]: 78 mSDtfsCounter, 0 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 0 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 78 SdHoareTripleChecker+Invalid, 0 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 0 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-10-16 10:44:20,688 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 78 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 0 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-10-16 10:44:20,707 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2022-10-16 10:44:20,731 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 69. [2022-10-16 10:44:20,733 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 69 states, 44 states have (on average 1.6363636363636365) internal successors, (72), 68 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:20,738 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 72 transitions. [2022-10-16 10:44:20,741 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 72 transitions. Word has length 7 [2022-10-16 10:44:20,741 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:44:20,741 INFO L495 AbstractCegarLoop]: Abstraction has 69 states and 72 transitions. [2022-10-16 10:44:20,742 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 3.5) internal successors, (7), 2 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:20,742 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 72 transitions. [2022-10-16 10:44:20,743 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2022-10-16 10:44:20,743 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:44:20,743 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:44:20,743 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-10-16 10:44:20,745 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:44:20,746 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:44:20,746 INFO L85 PathProgramCache]: Analyzing trace with hash 1806904935, now seen corresponding path program 1 times [2022-10-16 10:44:20,747 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:44:20,747 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1241369789] [2022-10-16 10:44:20,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:20,749 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:44:20,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:44:20,917 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:44:20,917 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:44:20,918 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1241369789] [2022-10-16 10:44:20,918 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1241369789] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-16 10:44:20,918 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-16 10:44:20,918 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-16 10:44:20,919 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [520679730] [2022-10-16 10:44:20,919 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-16 10:44:20,920 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-10-16 10:44:20,921 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:44:20,921 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-16 10:44:20,921 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-16 10:44:20,925 INFO L87 Difference]: Start difference. First operand 69 states and 72 transitions. Second operand has 3 states, 2 states have (on average 3.5) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:21,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:44:21,048 INFO L93 Difference]: Finished difference Result 122 states and 128 transitions. [2022-10-16 10:44:21,049 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-16 10:44:21,049 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 2 states have (on average 3.5) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 7 [2022-10-16 10:44:21,049 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:44:21,051 INFO L225 Difference]: With dead ends: 122 [2022-10-16 10:44:21,051 INFO L226 Difference]: Without dead ends: 112 [2022-10-16 10:44:21,052 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-16 10:44:21,054 INFO L413 NwaCegarLoop]: 50 mSDtfsCounter, 39 mSDsluCounter, 26 mSDsCounter, 0 mSdLazyCounter, 65 mSolverCounterSat, 13 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 39 SdHoareTripleChecker+Valid, 76 SdHoareTripleChecker+Invalid, 78 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 13 IncrementalHoareTripleChecker+Valid, 65 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-10-16 10:44:21,054 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [39 Valid, 76 Invalid, 78 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [13 Valid, 65 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-10-16 10:44:21,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2022-10-16 10:44:21,073 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 82. [2022-10-16 10:44:21,074 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 82 states, 57 states have (on average 1.543859649122807) internal successors, (88), 81 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:21,075 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 88 transitions. [2022-10-16 10:44:21,076 INFO L78 Accepts]: Start accepts. Automaton has 82 states and 88 transitions. Word has length 7 [2022-10-16 10:44:21,081 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:44:21,081 INFO L495 AbstractCegarLoop]: Abstraction has 82 states and 88 transitions. [2022-10-16 10:44:21,081 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 2 states have (on average 3.5) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:21,082 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states and 88 transitions. [2022-10-16 10:44:21,082 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 10 [2022-10-16 10:44:21,082 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:44:21,082 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:44:21,083 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-10-16 10:44:21,083 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:44:21,084 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:44:21,084 INFO L85 PathProgramCache]: Analyzing trace with hash 1268856745, now seen corresponding path program 1 times [2022-10-16 10:44:21,084 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:44:21,085 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1164831697] [2022-10-16 10:44:21,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:21,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:44:21,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:44:21,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:44:21,784 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:44:21,784 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1164831697] [2022-10-16 10:44:21,784 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1164831697] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-16 10:44:21,785 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-16 10:44:21,785 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-16 10:44:21,785 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1183080960] [2022-10-16 10:44:21,785 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-16 10:44:21,786 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-10-16 10:44:21,786 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:44:21,800 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-16 10:44:21,800 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-16 10:44:21,801 INFO L87 Difference]: Start difference. First operand 82 states and 88 transitions. Second operand has 4 states, 3 states have (on average 3.0) internal successors, (9), 4 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:21,976 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:44:21,976 INFO L93 Difference]: Finished difference Result 112 states and 120 transitions. [2022-10-16 10:44:21,977 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-16 10:44:21,977 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 3 states have (on average 3.0) internal successors, (9), 4 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 9 [2022-10-16 10:44:21,978 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:44:21,981 INFO L225 Difference]: With dead ends: 112 [2022-10-16 10:44:21,981 INFO L226 Difference]: Without dead ends: 110 [2022-10-16 10:44:21,981 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-10-16 10:44:21,985 INFO L413 NwaCegarLoop]: 51 mSDtfsCounter, 26 mSDsluCounter, 73 mSDsCounter, 0 mSdLazyCounter, 91 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 26 SdHoareTripleChecker+Valid, 124 SdHoareTripleChecker+Invalid, 95 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 91 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-10-16 10:44:21,986 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [26 Valid, 124 Invalid, 95 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 91 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-10-16 10:44:21,990 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110 states. [2022-10-16 10:44:22,009 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110 to 84. [2022-10-16 10:44:22,010 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84 states, 59 states have (on average 1.5254237288135593) internal successors, (90), 83 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:22,013 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 90 transitions. [2022-10-16 10:44:22,013 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 90 transitions. Word has length 9 [2022-10-16 10:44:22,014 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:44:22,014 INFO L495 AbstractCegarLoop]: Abstraction has 84 states and 90 transitions. [2022-10-16 10:44:22,014 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 3 states have (on average 3.0) internal successors, (9), 4 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:22,014 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 90 transitions. [2022-10-16 10:44:22,018 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2022-10-16 10:44:22,018 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:44:22,018 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:44:22,019 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2022-10-16 10:44:22,019 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr4ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:44:22,023 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:44:22,023 INFO L85 PathProgramCache]: Analyzing trace with hash 504177845, now seen corresponding path program 1 times [2022-10-16 10:44:22,023 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:44:22,024 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [309525302] [2022-10-16 10:44:22,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:22,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:44:22,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:44:22,131 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:44:22,132 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:44:22,136 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [309525302] [2022-10-16 10:44:22,136 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [309525302] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-16 10:44:22,137 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-16 10:44:22,137 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-16 10:44:22,138 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1647624962] [2022-10-16 10:44:22,138 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-16 10:44:22,138 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-10-16 10:44:22,139 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:44:22,139 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-16 10:44:22,140 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-16 10:44:22,140 INFO L87 Difference]: Start difference. First operand 84 states and 90 transitions. Second operand has 4 states, 3 states have (on average 4.0) internal successors, (12), 4 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:22,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:44:22,287 INFO L93 Difference]: Finished difference Result 110 states and 116 transitions. [2022-10-16 10:44:22,287 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-16 10:44:22,287 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 3 states have (on average 4.0) internal successors, (12), 4 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 12 [2022-10-16 10:44:22,290 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:44:22,294 INFO L225 Difference]: With dead ends: 110 [2022-10-16 10:44:22,294 INFO L226 Difference]: Without dead ends: 108 [2022-10-16 10:44:22,295 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-10-16 10:44:22,305 INFO L413 NwaCegarLoop]: 48 mSDtfsCounter, 32 mSDsluCounter, 71 mSDsCounter, 0 mSdLazyCounter, 94 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 32 SdHoareTripleChecker+Valid, 119 SdHoareTripleChecker+Invalid, 99 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 94 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-10-16 10:44:22,305 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [32 Valid, 119 Invalid, 99 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 94 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-10-16 10:44:22,309 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108 states. [2022-10-16 10:44:22,328 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108 to 87. [2022-10-16 10:44:22,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 87 states, 62 states have (on average 1.5) internal successors, (93), 86 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:22,333 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 93 transitions. [2022-10-16 10:44:22,333 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 93 transitions. Word has length 12 [2022-10-16 10:44:22,333 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:44:22,334 INFO L495 AbstractCegarLoop]: Abstraction has 87 states and 93 transitions. [2022-10-16 10:44:22,334 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 3 states have (on average 4.0) internal successors, (12), 4 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:22,334 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 93 transitions. [2022-10-16 10:44:22,337 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2022-10-16 10:44:22,337 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:44:22,337 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:44:22,337 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2022-10-16 10:44:22,338 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:44:22,338 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:44:22,338 INFO L85 PathProgramCache]: Analyzing trace with hash 1224983743, now seen corresponding path program 1 times [2022-10-16 10:44:22,339 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:44:22,339 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1623664379] [2022-10-16 10:44:22,339 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:22,339 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:44:22,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:44:22,453 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:44:22,454 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:44:22,454 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1623664379] [2022-10-16 10:44:22,455 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1623664379] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-16 10:44:22,455 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-16 10:44:22,456 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-16 10:44:22,457 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [318312234] [2022-10-16 10:44:22,457 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-16 10:44:22,458 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-10-16 10:44:22,458 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:44:22,458 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-16 10:44:22,459 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-10-16 10:44:22,459 INFO L87 Difference]: Start difference. First operand 87 states and 93 transitions. Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:22,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:44:22,614 INFO L93 Difference]: Finished difference Result 179 states and 190 transitions. [2022-10-16 10:44:22,615 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-10-16 10:44:22,615 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 13 [2022-10-16 10:44:22,615 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:44:22,616 INFO L225 Difference]: With dead ends: 179 [2022-10-16 10:44:22,617 INFO L226 Difference]: Without dead ends: 121 [2022-10-16 10:44:22,617 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-10-16 10:44:22,619 INFO L413 NwaCegarLoop]: 49 mSDtfsCounter, 48 mSDsluCounter, 95 mSDsCounter, 0 mSdLazyCounter, 140 mSolverCounterSat, 9 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 48 SdHoareTripleChecker+Valid, 144 SdHoareTripleChecker+Invalid, 149 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 9 IncrementalHoareTripleChecker+Valid, 140 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-10-16 10:44:22,619 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [48 Valid, 144 Invalid, 149 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [9 Valid, 140 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-10-16 10:44:22,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121 states. [2022-10-16 10:44:22,628 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121 to 91. [2022-10-16 10:44:22,628 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 91 states, 66 states have (on average 1.4696969696969697) internal successors, (97), 90 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:22,629 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 97 transitions. [2022-10-16 10:44:22,630 INFO L78 Accepts]: Start accepts. Automaton has 91 states and 97 transitions. Word has length 13 [2022-10-16 10:44:22,630 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:44:22,630 INFO L495 AbstractCegarLoop]: Abstraction has 91 states and 97 transitions. [2022-10-16 10:44:22,630 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:22,630 INFO L276 IsEmpty]: Start isEmpty. Operand 91 states and 97 transitions. [2022-10-16 10:44:22,631 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2022-10-16 10:44:22,631 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:44:22,631 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:44:22,632 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2022-10-16 10:44:22,632 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:44:22,632 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:44:22,632 INFO L85 PathProgramCache]: Analyzing trace with hash 1186956715, now seen corresponding path program 1 times [2022-10-16 10:44:22,633 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:44:22,633 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1996070587] [2022-10-16 10:44:22,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:22,633 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:44:22,649 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-10-16 10:44:22,649 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [2056342732] [2022-10-16 10:44:22,650 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:22,650 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:44:22,650 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-10-16 10:44:22,652 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-16 10:44:22,677 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-10-16 10:44:22,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:44:22,731 INFO L263 TraceCheckSpWp]: Trace formula consists of 110 conjuncts, 3 conjunts are in the unsatisfiable core [2022-10-16 10:44:22,736 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-16 10:44:22,749 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:44:22,750 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-10-16 10:44:22,750 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:44:22,750 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1996070587] [2022-10-16 10:44:22,751 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-10-16 10:44:22,751 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2056342732] [2022-10-16 10:44:22,751 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2056342732] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-16 10:44:22,751 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-16 10:44:22,751 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-16 10:44:22,751 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [239675066] [2022-10-16 10:44:22,752 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-16 10:44:22,752 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-10-16 10:44:22,752 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:44:22,753 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-16 10:44:22,753 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-16 10:44:22,753 INFO L87 Difference]: Start difference. First operand 91 states and 97 transitions. Second operand has 3 states, 2 states have (on average 6.5) internal successors, (13), 3 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:22,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:44:22,806 INFO L93 Difference]: Finished difference Result 102 states and 108 transitions. [2022-10-16 10:44:22,807 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-16 10:44:22,807 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 2 states have (on average 6.5) internal successors, (13), 3 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 13 [2022-10-16 10:44:22,807 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:44:22,808 INFO L225 Difference]: With dead ends: 102 [2022-10-16 10:44:22,808 INFO L226 Difference]: Without dead ends: 101 [2022-10-16 10:44:22,808 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 11 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-16 10:44:22,809 INFO L413 NwaCegarLoop]: 68 mSDtfsCounter, 8 mSDsluCounter, 26 mSDsCounter, 0 mSdLazyCounter, 49 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 8 SdHoareTripleChecker+Valid, 94 SdHoareTripleChecker+Invalid, 49 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 49 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-10-16 10:44:22,810 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [8 Valid, 94 Invalid, 49 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 49 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-10-16 10:44:22,811 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101 states. [2022-10-16 10:44:22,817 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101 to 93. [2022-10-16 10:44:22,818 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 93 states, 68 states have (on average 1.4558823529411764) internal successors, (99), 92 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:22,819 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 99 transitions. [2022-10-16 10:44:22,819 INFO L78 Accepts]: Start accepts. Automaton has 93 states and 99 transitions. Word has length 13 [2022-10-16 10:44:22,819 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:44:22,820 INFO L495 AbstractCegarLoop]: Abstraction has 93 states and 99 transitions. [2022-10-16 10:44:22,820 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 2 states have (on average 6.5) internal successors, (13), 3 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:22,820 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states and 99 transitions. [2022-10-16 10:44:22,821 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2022-10-16 10:44:22,821 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:44:22,821 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:44:22,858 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2022-10-16 10:44:23,036 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable5 [2022-10-16 10:44:23,037 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:44:23,038 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:44:23,038 INFO L85 PathProgramCache]: Analyzing trace with hash 461611375, now seen corresponding path program 1 times [2022-10-16 10:44:23,038 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:44:23,038 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1619217194] [2022-10-16 10:44:23,039 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:23,039 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:44:23,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:44:23,104 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:44:23,105 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:44:23,105 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1619217194] [2022-10-16 10:44:23,105 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1619217194] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-16 10:44:23,105 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [449163523] [2022-10-16 10:44:23,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:23,106 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:44:23,106 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-10-16 10:44:23,107 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-16 10:44:23,109 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-10-16 10:44:23,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:44:23,172 INFO L263 TraceCheckSpWp]: Trace formula consists of 116 conjuncts, 4 conjunts are in the unsatisfiable core [2022-10-16 10:44:23,174 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-16 10:44:23,236 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:44:23,236 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-16 10:44:23,283 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:44:23,284 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [449163523] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-16 10:44:23,284 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-16 10:44:23,284 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 9 [2022-10-16 10:44:23,284 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1597143866] [2022-10-16 10:44:23,284 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-16 10:44:23,285 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-10-16 10:44:23,285 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:44:23,285 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-10-16 10:44:23,286 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2022-10-16 10:44:23,286 INFO L87 Difference]: Start difference. First operand 93 states and 99 transitions. Second operand has 10 states, 9 states have (on average 3.888888888888889) internal successors, (35), 10 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:23,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:44:23,472 INFO L93 Difference]: Finished difference Result 133 states and 142 transitions. [2022-10-16 10:44:23,472 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-10-16 10:44:23,472 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 9 states have (on average 3.888888888888889) internal successors, (35), 10 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 15 [2022-10-16 10:44:23,473 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:44:23,474 INFO L225 Difference]: With dead ends: 133 [2022-10-16 10:44:23,498 INFO L226 Difference]: Without dead ends: 130 [2022-10-16 10:44:23,499 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 24 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=71, Invalid=139, Unknown=0, NotChecked=0, Total=210 [2022-10-16 10:44:23,501 INFO L413 NwaCegarLoop]: 34 mSDtfsCounter, 154 mSDsluCounter, 77 mSDsCounter, 0 mSdLazyCounter, 156 mSolverCounterSat, 36 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 154 SdHoareTripleChecker+Valid, 111 SdHoareTripleChecker+Invalid, 192 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 36 IncrementalHoareTripleChecker+Valid, 156 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-10-16 10:44:23,503 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [154 Valid, 111 Invalid, 192 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [36 Valid, 156 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-10-16 10:44:23,504 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130 states. [2022-10-16 10:44:23,520 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130 to 90. [2022-10-16 10:44:23,523 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 90 states, 68 states have (on average 1.411764705882353) internal successors, (96), 89 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:23,525 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 96 transitions. [2022-10-16 10:44:23,525 INFO L78 Accepts]: Start accepts. Automaton has 90 states and 96 transitions. Word has length 15 [2022-10-16 10:44:23,526 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:44:23,526 INFO L495 AbstractCegarLoop]: Abstraction has 90 states and 96 transitions. [2022-10-16 10:44:23,526 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 9 states have (on average 3.888888888888889) internal successors, (35), 10 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:23,526 INFO L276 IsEmpty]: Start isEmpty. Operand 90 states and 96 transitions. [2022-10-16 10:44:23,527 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-10-16 10:44:23,527 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:44:23,528 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:44:23,567 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2022-10-16 10:44:23,741 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable6 [2022-10-16 10:44:23,742 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:44:23,743 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:44:23,744 INFO L85 PathProgramCache]: Analyzing trace with hash 1425050793, now seen corresponding path program 1 times [2022-10-16 10:44:23,744 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:44:23,745 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [763301838] [2022-10-16 10:44:23,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:23,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:44:23,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:44:23,809 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:44:23,809 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:44:23,809 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [763301838] [2022-10-16 10:44:23,810 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [763301838] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-16 10:44:23,810 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [24412058] [2022-10-16 10:44:23,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:23,810 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:44:23,810 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-10-16 10:44:23,811 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-16 10:44:23,836 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-10-16 10:44:23,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:44:23,885 INFO L263 TraceCheckSpWp]: Trace formula consists of 117 conjuncts, 4 conjunts are in the unsatisfiable core [2022-10-16 10:44:23,887 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-16 10:44:23,921 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:44:23,922 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-10-16 10:44:23,922 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [24412058] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-16 10:44:23,922 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-10-16 10:44:23,922 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 6 [2022-10-16 10:44:23,923 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1531936876] [2022-10-16 10:44:23,923 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-16 10:44:23,923 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-10-16 10:44:23,923 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:44:23,924 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-16 10:44:23,924 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2022-10-16 10:44:23,924 INFO L87 Difference]: Start difference. First operand 90 states and 96 transitions. Second operand has 5 states, 4 states have (on average 4.0) internal successors, (16), 5 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:24,040 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:44:24,040 INFO L93 Difference]: Finished difference Result 109 states and 115 transitions. [2022-10-16 10:44:24,040 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-10-16 10:44:24,041 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 4 states have (on average 4.0) internal successors, (16), 5 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 16 [2022-10-16 10:44:24,041 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:44:24,042 INFO L225 Difference]: With dead ends: 109 [2022-10-16 10:44:24,042 INFO L226 Difference]: Without dead ends: 107 [2022-10-16 10:44:24,042 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 14 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2022-10-16 10:44:24,043 INFO L413 NwaCegarLoop]: 44 mSDtfsCounter, 41 mSDsluCounter, 84 mSDsCounter, 0 mSdLazyCounter, 133 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 41 SdHoareTripleChecker+Valid, 128 SdHoareTripleChecker+Invalid, 140 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 133 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-10-16 10:44:24,043 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [41 Valid, 128 Invalid, 140 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 133 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-10-16 10:44:24,044 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states. [2022-10-16 10:44:24,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 87. [2022-10-16 10:44:24,049 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 87 states, 67 states have (on average 1.3880597014925373) internal successors, (93), 86 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:24,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 93 transitions. [2022-10-16 10:44:24,049 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 93 transitions. Word has length 16 [2022-10-16 10:44:24,050 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:44:24,050 INFO L495 AbstractCegarLoop]: Abstraction has 87 states and 93 transitions. [2022-10-16 10:44:24,050 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 4 states have (on average 4.0) internal successors, (16), 5 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:24,050 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 93 transitions. [2022-10-16 10:44:24,051 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-10-16 10:44:24,051 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:44:24,051 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:44:24,085 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2022-10-16 10:44:24,265 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7,4 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:44:24,266 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:44:24,267 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:44:24,267 INFO L85 PathProgramCache]: Analyzing trace with hash 1226901681, now seen corresponding path program 1 times [2022-10-16 10:44:24,267 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:44:24,268 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1907019191] [2022-10-16 10:44:24,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:24,268 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:44:24,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:44:24,885 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:44:24,885 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:44:24,885 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1907019191] [2022-10-16 10:44:24,886 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1907019191] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-16 10:44:24,886 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1871182785] [2022-10-16 10:44:24,886 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:24,886 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:44:24,886 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-10-16 10:44:24,891 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-16 10:44:24,898 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-10-16 10:44:24,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:44:24,960 INFO L263 TraceCheckSpWp]: Trace formula consists of 120 conjuncts, 26 conjunts are in the unsatisfiable core [2022-10-16 10:44:24,963 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-16 10:44:25,027 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 17 [2022-10-16 10:44:25,042 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:44:25,044 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:44:25,045 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:44:25,047 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 3 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2022-10-16 10:44:25,062 INFO L356 Elim1Store]: treesize reduction 7, result has 12.5 percent of original size [2022-10-16 10:44:25,062 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 19 [2022-10-16 10:44:25,163 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:44:25,165 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:44:25,167 INFO L356 Elim1Store]: treesize reduction 2, result has 33.3 percent of original size [2022-10-16 10:44:25,168 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 37 treesize of output 39 [2022-10-16 10:44:25,314 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-10-16 10:44:25,314 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 12 [2022-10-16 10:44:25,320 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:44:25,320 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-16 10:44:25,449 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:44:25,450 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1871182785] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-16 10:44:25,450 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-16 10:44:25,450 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 18 [2022-10-16 10:44:25,450 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [81918568] [2022-10-16 10:44:25,450 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-16 10:44:25,451 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 19 states [2022-10-16 10:44:25,451 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:44:25,451 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-10-16 10:44:25,452 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=71, Invalid=271, Unknown=0, NotChecked=0, Total=342 [2022-10-16 10:44:25,452 INFO L87 Difference]: Start difference. First operand 87 states and 93 transitions. Second operand has 19 states, 18 states have (on average 2.3333333333333335) internal successors, (42), 19 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:25,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:44:25,975 INFO L93 Difference]: Finished difference Result 136 states and 146 transitions. [2022-10-16 10:44:25,975 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-10-16 10:44:25,976 INFO L78 Accepts]: Start accepts. Automaton has has 19 states, 18 states have (on average 2.3333333333333335) internal successors, (42), 19 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 17 [2022-10-16 10:44:25,976 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:44:25,977 INFO L225 Difference]: With dead ends: 136 [2022-10-16 10:44:25,977 INFO L226 Difference]: Without dead ends: 135 [2022-10-16 10:44:25,978 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 47 GetRequests, 22 SyntacticMatches, 0 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 144 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=149, Invalid=553, Unknown=0, NotChecked=0, Total=702 [2022-10-16 10:44:25,979 INFO L413 NwaCegarLoop]: 47 mSDtfsCounter, 99 mSDsluCounter, 199 mSDsCounter, 0 mSdLazyCounter, 380 mSolverCounterSat, 22 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 99 SdHoareTripleChecker+Valid, 246 SdHoareTripleChecker+Invalid, 402 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 22 IncrementalHoareTripleChecker+Valid, 380 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-10-16 10:44:25,979 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [99 Valid, 246 Invalid, 402 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [22 Valid, 380 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-10-16 10:44:25,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states. [2022-10-16 10:44:25,985 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 100. [2022-10-16 10:44:25,985 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100 states, 80 states have (on average 1.375) internal successors, (110), 99 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:25,986 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 110 transitions. [2022-10-16 10:44:25,986 INFO L78 Accepts]: Start accepts. Automaton has 100 states and 110 transitions. Word has length 17 [2022-10-16 10:44:25,986 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:44:25,987 INFO L495 AbstractCegarLoop]: Abstraction has 100 states and 110 transitions. [2022-10-16 10:44:25,987 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 19 states, 18 states have (on average 2.3333333333333335) internal successors, (42), 19 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:25,987 INFO L276 IsEmpty]: Start isEmpty. Operand 100 states and 110 transitions. [2022-10-16 10:44:25,988 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-10-16 10:44:25,988 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:44:25,988 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:44:26,028 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2022-10-16 10:44:26,201 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8,5 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:44:26,202 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr24ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:44:26,203 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:44:26,203 INFO L85 PathProgramCache]: Analyzing trace with hash 957307911, now seen corresponding path program 1 times [2022-10-16 10:44:26,203 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:44:26,204 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [302464961] [2022-10-16 10:44:26,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:26,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:44:26,218 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-10-16 10:44:26,219 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1253774684] [2022-10-16 10:44:26,219 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:26,219 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:44:26,219 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-10-16 10:44:26,220 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-16 10:44:26,242 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-10-16 10:44:26,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:44:26,288 INFO L263 TraceCheckSpWp]: Trace formula consists of 120 conjuncts, 3 conjunts are in the unsatisfiable core [2022-10-16 10:44:26,290 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-16 10:44:26,304 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:44:26,304 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-10-16 10:44:26,304 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:44:26,304 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [302464961] [2022-10-16 10:44:26,304 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-10-16 10:44:26,305 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1253774684] [2022-10-16 10:44:26,305 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1253774684] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-16 10:44:26,305 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-16 10:44:26,305 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-16 10:44:26,305 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [686135122] [2022-10-16 10:44:26,305 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-16 10:44:26,306 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-10-16 10:44:26,306 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:44:26,306 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-16 10:44:26,307 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-16 10:44:26,307 INFO L87 Difference]: Start difference. First operand 100 states and 110 transitions. Second operand has 4 states, 3 states have (on average 6.0) internal successors, (18), 4 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:26,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:44:26,369 INFO L93 Difference]: Finished difference Result 108 states and 118 transitions. [2022-10-16 10:44:26,369 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-10-16 10:44:26,369 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 3 states have (on average 6.0) internal successors, (18), 4 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 18 [2022-10-16 10:44:26,370 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:44:26,370 INFO L225 Difference]: With dead ends: 108 [2022-10-16 10:44:26,370 INFO L226 Difference]: Without dead ends: 107 [2022-10-16 10:44:26,371 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 15 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-10-16 10:44:26,372 INFO L413 NwaCegarLoop]: 60 mSDtfsCounter, 5 mSDsluCounter, 83 mSDsCounter, 0 mSdLazyCounter, 52 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 5 SdHoareTripleChecker+Valid, 143 SdHoareTripleChecker+Invalid, 57 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 52 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-10-16 10:44:26,372 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [5 Valid, 143 Invalid, 57 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 52 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-10-16 10:44:26,373 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states. [2022-10-16 10:44:26,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 105. [2022-10-16 10:44:26,378 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 105 states, 85 states have (on average 1.3529411764705883) internal successors, (115), 104 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:26,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 115 transitions. [2022-10-16 10:44:26,379 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 115 transitions. Word has length 18 [2022-10-16 10:44:26,379 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:44:26,379 INFO L495 AbstractCegarLoop]: Abstraction has 105 states and 115 transitions. [2022-10-16 10:44:26,380 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 3 states have (on average 6.0) internal successors, (18), 4 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:26,380 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 115 transitions. [2022-10-16 10:44:26,380 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-10-16 10:44:26,381 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:44:26,381 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:44:26,418 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2022-10-16 10:44:26,595 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable9 [2022-10-16 10:44:26,596 INFO L420 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr3ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:44:26,597 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:44:26,597 INFO L85 PathProgramCache]: Analyzing trace with hash -620753493, now seen corresponding path program 1 times [2022-10-16 10:44:26,597 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:44:26,598 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1280503917] [2022-10-16 10:44:26,599 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:26,599 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:44:26,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:44:26,783 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:44:26,783 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:44:26,783 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1280503917] [2022-10-16 10:44:26,783 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1280503917] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-16 10:44:26,784 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1604783838] [2022-10-16 10:44:26,784 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:26,784 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:44:26,784 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-10-16 10:44:26,785 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-16 10:44:26,805 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2022-10-16 10:44:26,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:44:26,853 INFO L263 TraceCheckSpWp]: Trace formula consists of 121 conjuncts, 10 conjunts are in the unsatisfiable core [2022-10-16 10:44:26,856 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-16 10:44:26,876 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-10-16 10:44:26,912 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 9 [2022-10-16 10:44:26,916 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:44:26,917 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-10-16 10:44:26,917 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1604783838] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-16 10:44:26,917 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-10-16 10:44:26,917 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [6] total 8 [2022-10-16 10:44:26,917 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1317920749] [2022-10-16 10:44:26,917 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-16 10:44:26,918 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-10-16 10:44:26,918 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:44:26,918 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-10-16 10:44:26,919 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2022-10-16 10:44:26,919 INFO L87 Difference]: Start difference. First operand 105 states and 115 transitions. Second operand has 6 states, 5 states have (on average 3.6) internal successors, (18), 6 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:27,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:44:27,056 INFO L93 Difference]: Finished difference Result 105 states and 115 transitions. [2022-10-16 10:44:27,057 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-10-16 10:44:27,057 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 3.6) internal successors, (18), 6 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 18 [2022-10-16 10:44:27,057 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:44:27,058 INFO L225 Difference]: With dead ends: 105 [2022-10-16 10:44:27,058 INFO L226 Difference]: Without dead ends: 104 [2022-10-16 10:44:27,059 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 17 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=32, Invalid=100, Unknown=0, NotChecked=0, Total=132 [2022-10-16 10:44:27,059 INFO L413 NwaCegarLoop]: 55 mSDtfsCounter, 12 mSDsluCounter, 137 mSDsCounter, 0 mSdLazyCounter, 116 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 12 SdHoareTripleChecker+Valid, 192 SdHoareTripleChecker+Invalid, 118 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 116 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-10-16 10:44:27,060 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [12 Valid, 192 Invalid, 118 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 116 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-10-16 10:44:27,060 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104 states. [2022-10-16 10:44:27,066 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104 to 104. [2022-10-16 10:44:27,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 104 states, 85 states have (on average 1.3294117647058823) internal successors, (113), 103 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:27,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104 states to 104 states and 113 transitions. [2022-10-16 10:44:27,067 INFO L78 Accepts]: Start accepts. Automaton has 104 states and 113 transitions. Word has length 18 [2022-10-16 10:44:27,067 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:44:27,067 INFO L495 AbstractCegarLoop]: Abstraction has 104 states and 113 transitions. [2022-10-16 10:44:27,068 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 3.6) internal successors, (18), 6 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:27,068 INFO L276 IsEmpty]: Start isEmpty. Operand 104 states and 113 transitions. [2022-10-16 10:44:27,068 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2022-10-16 10:44:27,068 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:44:27,069 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:44:27,106 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2022-10-16 10:44:27,279 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10,7 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:44:27,280 INFO L420 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr25ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:44:27,281 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:44:27,282 INFO L85 PathProgramCache]: Analyzing trace with hash -388225674, now seen corresponding path program 1 times [2022-10-16 10:44:27,282 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:44:27,282 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [290878954] [2022-10-16 10:44:27,283 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:27,283 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:44:27,301 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-10-16 10:44:27,302 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [515578960] [2022-10-16 10:44:27,302 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:27,302 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:44:27,302 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-10-16 10:44:27,303 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-16 10:44:27,321 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2022-10-16 10:44:27,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:44:27,371 INFO L263 TraceCheckSpWp]: Trace formula consists of 121 conjuncts, 3 conjunts are in the unsatisfiable core [2022-10-16 10:44:27,372 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-16 10:44:27,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:44:27,389 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-10-16 10:44:27,389 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:44:27,390 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [290878954] [2022-10-16 10:44:27,390 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-10-16 10:44:27,390 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [515578960] [2022-10-16 10:44:27,390 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [515578960] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-16 10:44:27,390 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-16 10:44:27,390 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-16 10:44:27,391 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1661408615] [2022-10-16 10:44:27,391 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-16 10:44:27,391 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-10-16 10:44:27,392 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:44:27,392 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-16 10:44:27,392 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-16 10:44:27,392 INFO L87 Difference]: Start difference. First operand 104 states and 113 transitions. Second operand has 4 states, 3 states have (on average 6.333333333333333) internal successors, (19), 4 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:27,491 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:44:27,491 INFO L93 Difference]: Finished difference Result 123 states and 132 transitions. [2022-10-16 10:44:27,492 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-16 10:44:27,492 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 3 states have (on average 6.333333333333333) internal successors, (19), 4 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 19 [2022-10-16 10:44:27,492 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:44:27,493 INFO L225 Difference]: With dead ends: 123 [2022-10-16 10:44:27,493 INFO L226 Difference]: Without dead ends: 122 [2022-10-16 10:44:27,494 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 16 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-10-16 10:44:27,494 INFO L413 NwaCegarLoop]: 35 mSDtfsCounter, 41 mSDsluCounter, 53 mSDsCounter, 0 mSdLazyCounter, 88 mSolverCounterSat, 8 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 41 SdHoareTripleChecker+Valid, 88 SdHoareTripleChecker+Invalid, 96 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 8 IncrementalHoareTripleChecker+Valid, 88 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-10-16 10:44:27,495 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [41 Valid, 88 Invalid, 96 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [8 Valid, 88 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-10-16 10:44:27,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122 states. [2022-10-16 10:44:27,503 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122 to 103. [2022-10-16 10:44:27,503 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 103 states, 85 states have (on average 1.3176470588235294) internal successors, (112), 102 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:27,504 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 112 transitions. [2022-10-16 10:44:27,504 INFO L78 Accepts]: Start accepts. Automaton has 103 states and 112 transitions. Word has length 19 [2022-10-16 10:44:27,504 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:44:27,504 INFO L495 AbstractCegarLoop]: Abstraction has 103 states and 112 transitions. [2022-10-16 10:44:27,505 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 3 states have (on average 6.333333333333333) internal successors, (19), 4 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:27,505 INFO L276 IsEmpty]: Start isEmpty. Operand 103 states and 112 transitions. [2022-10-16 10:44:27,506 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2022-10-16 10:44:27,506 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:44:27,507 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:44:27,534 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2022-10-16 10:44:27,720 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11,8 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:44:27,721 INFO L420 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr4ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:44:27,722 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:44:27,722 INFO L85 PathProgramCache]: Analyzing trace with hash 456349357, now seen corresponding path program 1 times [2022-10-16 10:44:27,722 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:44:27,723 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1278991865] [2022-10-16 10:44:27,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:27,724 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:44:27,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:44:27,828 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:44:27,829 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:44:27,829 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1278991865] [2022-10-16 10:44:27,829 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1278991865] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-16 10:44:27,829 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [234115228] [2022-10-16 10:44:27,830 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:27,830 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:44:27,830 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-10-16 10:44:27,831 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-16 10:44:27,847 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2022-10-16 10:44:27,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:44:27,917 INFO L263 TraceCheckSpWp]: Trace formula consists of 128 conjuncts, 5 conjunts are in the unsatisfiable core [2022-10-16 10:44:27,918 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-16 10:44:27,952 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:44:27,952 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-16 10:44:27,993 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:44:27,993 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [234115228] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-16 10:44:27,993 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-16 10:44:27,993 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 11 [2022-10-16 10:44:27,994 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [447256234] [2022-10-16 10:44:27,994 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-16 10:44:27,994 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 12 states [2022-10-16 10:44:27,995 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:44:27,995 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2022-10-16 10:44:27,995 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=91, Unknown=0, NotChecked=0, Total=132 [2022-10-16 10:44:27,996 INFO L87 Difference]: Start difference. First operand 103 states and 112 transitions. Second operand has 12 states, 11 states have (on average 4.090909090909091) internal successors, (45), 12 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:28,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:44:28,178 INFO L93 Difference]: Finished difference Result 140 states and 151 transitions. [2022-10-16 10:44:28,178 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-10-16 10:44:28,179 INFO L78 Accepts]: Start accepts. Automaton has has 12 states, 11 states have (on average 4.090909090909091) internal successors, (45), 12 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 20 [2022-10-16 10:44:28,179 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:44:28,181 INFO L225 Difference]: With dead ends: 140 [2022-10-16 10:44:28,181 INFO L226 Difference]: Without dead ends: 139 [2022-10-16 10:44:28,182 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 47 GetRequests, 33 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 40 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=77, Invalid=163, Unknown=0, NotChecked=0, Total=240 [2022-10-16 10:44:28,183 INFO L413 NwaCegarLoop]: 37 mSDtfsCounter, 139 mSDsluCounter, 176 mSDsCounter, 0 mSdLazyCounter, 217 mSolverCounterSat, 40 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 139 SdHoareTripleChecker+Valid, 213 SdHoareTripleChecker+Invalid, 257 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 40 IncrementalHoareTripleChecker+Valid, 217 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-10-16 10:44:28,183 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [139 Valid, 213 Invalid, 257 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [40 Valid, 217 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-10-16 10:44:28,184 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states. [2022-10-16 10:44:28,190 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 114. [2022-10-16 10:44:28,191 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 114 states, 96 states have (on average 1.2916666666666667) internal successors, (124), 113 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:28,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 124 transitions. [2022-10-16 10:44:28,191 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 124 transitions. Word has length 20 [2022-10-16 10:44:28,192 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:44:28,192 INFO L495 AbstractCegarLoop]: Abstraction has 114 states and 124 transitions. [2022-10-16 10:44:28,192 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 12 states, 11 states have (on average 4.090909090909091) internal successors, (45), 12 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:28,192 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 124 transitions. [2022-10-16 10:44:28,193 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2022-10-16 10:44:28,193 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:44:28,193 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:44:28,227 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2022-10-16 10:44:28,407 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable12 [2022-10-16 10:44:28,408 INFO L420 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:44:28,409 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:44:28,409 INFO L85 PathProgramCache]: Analyzing trace with hash 577286456, now seen corresponding path program 1 times [2022-10-16 10:44:28,410 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:44:28,410 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1636615214] [2022-10-16 10:44:28,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:28,411 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:44:28,423 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-10-16 10:44:28,424 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1984974660] [2022-10-16 10:44:28,424 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:28,424 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:44:28,424 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-10-16 10:44:28,425 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-16 10:44:28,446 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2022-10-16 10:44:28,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:44:28,497 INFO L263 TraceCheckSpWp]: Trace formula consists of 127 conjuncts, 6 conjunts are in the unsatisfiable core [2022-10-16 10:44:28,498 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-16 10:44:28,562 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:44:28,562 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-10-16 10:44:28,563 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:44:28,563 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1636615214] [2022-10-16 10:44:28,563 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-10-16 10:44:28,563 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1984974660] [2022-10-16 10:44:28,563 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1984974660] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-16 10:44:28,563 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-16 10:44:28,563 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-10-16 10:44:28,564 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [103756547] [2022-10-16 10:44:28,564 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-16 10:44:28,564 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-10-16 10:44:28,564 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:44:28,565 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-10-16 10:44:28,565 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2022-10-16 10:44:28,565 INFO L87 Difference]: Start difference. First operand 114 states and 124 transitions. Second operand has 7 states, 7 states have (on average 3.0) internal successors, (21), 7 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:28,718 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:44:28,718 INFO L93 Difference]: Finished difference Result 155 states and 165 transitions. [2022-10-16 10:44:28,719 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-10-16 10:44:28,719 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 3.0) internal successors, (21), 7 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 21 [2022-10-16 10:44:28,719 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:44:28,720 INFO L225 Difference]: With dead ends: 155 [2022-10-16 10:44:28,720 INFO L226 Difference]: Without dead ends: 129 [2022-10-16 10:44:28,720 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 15 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=41, Invalid=69, Unknown=0, NotChecked=0, Total=110 [2022-10-16 10:44:28,721 INFO L413 NwaCegarLoop]: 37 mSDtfsCounter, 65 mSDsluCounter, 113 mSDsCounter, 0 mSdLazyCounter, 174 mSolverCounterSat, 22 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 65 SdHoareTripleChecker+Valid, 150 SdHoareTripleChecker+Invalid, 196 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 22 IncrementalHoareTripleChecker+Valid, 174 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-10-16 10:44:28,721 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [65 Valid, 150 Invalid, 196 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [22 Valid, 174 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-10-16 10:44:28,722 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 129 states. [2022-10-16 10:44:28,727 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 129 to 110. [2022-10-16 10:44:28,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 110 states, 92 states have (on average 1.2717391304347827) internal successors, (117), 109 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:28,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 117 transitions. [2022-10-16 10:44:28,728 INFO L78 Accepts]: Start accepts. Automaton has 110 states and 117 transitions. Word has length 21 [2022-10-16 10:44:28,729 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:44:28,729 INFO L495 AbstractCegarLoop]: Abstraction has 110 states and 117 transitions. [2022-10-16 10:44:28,729 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 3.0) internal successors, (21), 7 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:28,729 INFO L276 IsEmpty]: Start isEmpty. Operand 110 states and 117 transitions. [2022-10-16 10:44:28,730 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2022-10-16 10:44:28,730 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:44:28,730 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:44:28,765 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Forceful destruction successful, exit code 0 [2022-10-16 10:44:28,943 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable13 [2022-10-16 10:44:28,944 INFO L420 AbstractCegarLoop]: === Iteration 15 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:44:28,944 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:44:28,945 INFO L85 PathProgramCache]: Analyzing trace with hash -257699385, now seen corresponding path program 1 times [2022-10-16 10:44:28,945 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:44:28,945 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [699361361] [2022-10-16 10:44:28,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:28,946 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:44:28,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:44:29,544 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:44:29,544 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:44:29,544 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [699361361] [2022-10-16 10:44:29,545 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [699361361] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-16 10:44:29,545 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1402853989] [2022-10-16 10:44:29,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:29,545 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:44:29,545 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-10-16 10:44:29,546 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-16 10:44:29,565 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2022-10-16 10:44:29,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:44:29,617 INFO L263 TraceCheckSpWp]: Trace formula consists of 127 conjuncts, 24 conjunts are in the unsatisfiable core [2022-10-16 10:44:29,620 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-16 10:44:29,640 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:44:29,644 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:44:29,645 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:44:29,657 INFO L356 Elim1Store]: treesize reduction 11, result has 45.0 percent of original size [2022-10-16 10:44:29,657 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 17 treesize of output 23 [2022-10-16 10:44:29,675 INFO L356 Elim1Store]: treesize reduction 7, result has 12.5 percent of original size [2022-10-16 10:44:29,675 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 108 treesize of output 102 [2022-10-16 10:44:29,705 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2022-10-16 10:44:29,828 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:44:29,830 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 30 [2022-10-16 10:44:30,036 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 13 [2022-10-16 10:44:30,055 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:44:30,055 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-16 10:44:31,677 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:44:31,677 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1402853989] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-16 10:44:31,677 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-16 10:44:31,678 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 7, 8] total 19 [2022-10-16 10:44:31,678 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1215069666] [2022-10-16 10:44:31,678 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-16 10:44:31,678 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 20 states [2022-10-16 10:44:31,679 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:44:31,679 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2022-10-16 10:44:31,679 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=305, Unknown=0, NotChecked=0, Total=380 [2022-10-16 10:44:31,680 INFO L87 Difference]: Start difference. First operand 110 states and 117 transitions. Second operand has 20 states, 19 states have (on average 2.8947368421052633) internal successors, (55), 20 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:32,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:44:32,172 INFO L93 Difference]: Finished difference Result 147 states and 155 transitions. [2022-10-16 10:44:32,172 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-10-16 10:44:32,172 INFO L78 Accepts]: Start accepts. Automaton has has 20 states, 19 states have (on average 2.8947368421052633) internal successors, (55), 20 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 21 [2022-10-16 10:44:32,172 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:44:32,173 INFO L225 Difference]: With dead ends: 147 [2022-10-16 10:44:32,173 INFO L226 Difference]: Without dead ends: 145 [2022-10-16 10:44:32,174 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 28 SyntacticMatches, 3 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 117 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=131, Invalid=421, Unknown=0, NotChecked=0, Total=552 [2022-10-16 10:44:32,175 INFO L413 NwaCegarLoop]: 45 mSDtfsCounter, 128 mSDsluCounter, 386 mSDsCounter, 0 mSdLazyCounter, 340 mSolverCounterSat, 10 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 128 SdHoareTripleChecker+Valid, 431 SdHoareTripleChecker+Invalid, 525 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 10 IncrementalHoareTripleChecker+Valid, 340 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 175 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-10-16 10:44:32,175 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [128 Valid, 431 Invalid, 525 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [10 Valid, 340 Invalid, 0 Unknown, 175 Unchecked, 0.3s Time] [2022-10-16 10:44:32,176 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145 states. [2022-10-16 10:44:32,181 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145 to 118. [2022-10-16 10:44:32,182 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 118 states, 100 states have (on average 1.25) internal successors, (125), 117 states have internal predecessors, (125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:32,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 125 transitions. [2022-10-16 10:44:32,183 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 125 transitions. Word has length 21 [2022-10-16 10:44:32,183 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:44:32,183 INFO L495 AbstractCegarLoop]: Abstraction has 118 states and 125 transitions. [2022-10-16 10:44:32,183 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 20 states, 19 states have (on average 2.8947368421052633) internal successors, (55), 20 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:32,183 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 125 transitions. [2022-10-16 10:44:32,184 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2022-10-16 10:44:32,184 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:44:32,184 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:44:32,222 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Forceful destruction successful, exit code 0 [2022-10-16 10:44:32,385 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable14 [2022-10-16 10:44:32,388 INFO L420 AbstractCegarLoop]: === Iteration 16 === Targeting ULTIMATE.startErr12ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:44:32,389 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:44:32,389 INFO L85 PathProgramCache]: Analyzing trace with hash -2015731147, now seen corresponding path program 1 times [2022-10-16 10:44:32,389 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:44:32,389 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [11946169] [2022-10-16 10:44:32,389 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:32,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:44:32,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:44:32,442 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-10-16 10:44:32,442 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:44:32,443 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [11946169] [2022-10-16 10:44:32,443 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [11946169] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-16 10:44:32,443 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-16 10:44:32,443 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-16 10:44:32,443 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [667044667] [2022-10-16 10:44:32,443 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-16 10:44:32,444 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-10-16 10:44:32,444 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:44:32,444 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-16 10:44:32,444 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-16 10:44:32,445 INFO L87 Difference]: Start difference. First operand 118 states and 125 transitions. Second operand has 4 states, 3 states have (on average 8.0) internal successors, (24), 4 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:32,532 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:44:32,533 INFO L93 Difference]: Finished difference Result 136 states and 143 transitions. [2022-10-16 10:44:32,533 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-16 10:44:32,533 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 3 states have (on average 8.0) internal successors, (24), 4 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 24 [2022-10-16 10:44:32,534 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:44:32,534 INFO L225 Difference]: With dead ends: 136 [2022-10-16 10:44:32,535 INFO L226 Difference]: Without dead ends: 134 [2022-10-16 10:44:32,535 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-10-16 10:44:32,536 INFO L413 NwaCegarLoop]: 44 mSDtfsCounter, 25 mSDsluCounter, 64 mSDsCounter, 0 mSdLazyCounter, 84 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 25 SdHoareTripleChecker+Valid, 108 SdHoareTripleChecker+Invalid, 87 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 84 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-10-16 10:44:32,536 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [25 Valid, 108 Invalid, 87 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 84 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-10-16 10:44:32,537 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states. [2022-10-16 10:44:32,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 123. [2022-10-16 10:44:32,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 123 states, 105 states have (on average 1.2571428571428571) internal successors, (132), 122 states have internal predecessors, (132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:32,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123 states to 123 states and 132 transitions. [2022-10-16 10:44:32,544 INFO L78 Accepts]: Start accepts. Automaton has 123 states and 132 transitions. Word has length 24 [2022-10-16 10:44:32,544 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:44:32,544 INFO L495 AbstractCegarLoop]: Abstraction has 123 states and 132 transitions. [2022-10-16 10:44:32,544 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 3 states have (on average 8.0) internal successors, (24), 4 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:32,544 INFO L276 IsEmpty]: Start isEmpty. Operand 123 states and 132 transitions. [2022-10-16 10:44:32,545 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2022-10-16 10:44:32,545 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:44:32,545 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:44:32,545 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable15 [2022-10-16 10:44:32,546 INFO L420 AbstractCegarLoop]: === Iteration 17 === Targeting ULTIMATE.startErr6ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:44:32,546 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:44:32,546 INFO L85 PathProgramCache]: Analyzing trace with hash 1586227149, now seen corresponding path program 1 times [2022-10-16 10:44:32,546 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:44:32,546 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1814139701] [2022-10-16 10:44:32,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:32,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:44:32,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:44:32,611 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-10-16 10:44:32,612 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:44:32,612 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1814139701] [2022-10-16 10:44:32,612 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1814139701] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-16 10:44:32,612 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [873257210] [2022-10-16 10:44:32,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:32,613 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:44:32,613 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-10-16 10:44:32,614 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-16 10:44:32,632 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2022-10-16 10:44:32,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:44:32,690 INFO L263 TraceCheckSpWp]: Trace formula consists of 140 conjuncts, 4 conjunts are in the unsatisfiable core [2022-10-16 10:44:32,692 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-16 10:44:32,716 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-10-16 10:44:32,716 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-16 10:44:32,750 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-10-16 10:44:32,751 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [873257210] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-16 10:44:32,751 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-16 10:44:32,751 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 9 [2022-10-16 10:44:32,751 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1714355664] [2022-10-16 10:44:32,751 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-16 10:44:32,752 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-10-16 10:44:32,752 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:44:32,752 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-10-16 10:44:32,752 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2022-10-16 10:44:32,753 INFO L87 Difference]: Start difference. First operand 123 states and 132 transitions. Second operand has 10 states, 9 states have (on average 5.666666666666667) internal successors, (51), 10 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:32,923 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:44:32,924 INFO L93 Difference]: Finished difference Result 150 states and 161 transitions. [2022-10-16 10:44:32,924 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-10-16 10:44:32,924 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 9 states have (on average 5.666666666666667) internal successors, (51), 10 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 27 [2022-10-16 10:44:32,924 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:44:32,925 INFO L225 Difference]: With dead ends: 150 [2022-10-16 10:44:32,925 INFO L226 Difference]: Without dead ends: 149 [2022-10-16 10:44:32,926 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 48 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=71, Invalid=139, Unknown=0, NotChecked=0, Total=210 [2022-10-16 10:44:32,927 INFO L413 NwaCegarLoop]: 32 mSDtfsCounter, 142 mSDsluCounter, 70 mSDsCounter, 0 mSdLazyCounter, 151 mSolverCounterSat, 27 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 142 SdHoareTripleChecker+Valid, 102 SdHoareTripleChecker+Invalid, 178 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 27 IncrementalHoareTripleChecker+Valid, 151 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-10-16 10:44:32,927 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [142 Valid, 102 Invalid, 178 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [27 Valid, 151 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-10-16 10:44:32,928 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 149 states. [2022-10-16 10:44:32,933 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 149 to 122. [2022-10-16 10:44:32,934 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 122 states, 105 states have (on average 1.2476190476190476) internal successors, (131), 121 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:32,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122 states to 122 states and 131 transitions. [2022-10-16 10:44:32,934 INFO L78 Accepts]: Start accepts. Automaton has 122 states and 131 transitions. Word has length 27 [2022-10-16 10:44:32,935 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:44:32,935 INFO L495 AbstractCegarLoop]: Abstraction has 122 states and 131 transitions. [2022-10-16 10:44:32,935 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 9 states have (on average 5.666666666666667) internal successors, (51), 10 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:32,935 INFO L276 IsEmpty]: Start isEmpty. Operand 122 states and 131 transitions. [2022-10-16 10:44:32,935 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2022-10-16 10:44:32,936 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:44:32,936 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:44:32,975 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Forceful destruction successful, exit code 0 [2022-10-16 10:44:33,149 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable16 [2022-10-16 10:44:33,150 INFO L420 AbstractCegarLoop]: === Iteration 18 === Targeting ULTIMATE.startErr7ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:44:33,150 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:44:33,151 INFO L85 PathProgramCache]: Analyzing trace with hash 1928401445, now seen corresponding path program 1 times [2022-10-16 10:44:33,151 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:44:33,151 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [210147919] [2022-10-16 10:44:33,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:33,152 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:44:33,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:44:33,227 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-10-16 10:44:33,227 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:44:33,227 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [210147919] [2022-10-16 10:44:33,227 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [210147919] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-16 10:44:33,227 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1805967954] [2022-10-16 10:44:33,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:33,228 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:44:33,228 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-10-16 10:44:33,229 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-16 10:44:33,248 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2022-10-16 10:44:33,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:44:33,306 INFO L263 TraceCheckSpWp]: Trace formula consists of 141 conjuncts, 4 conjunts are in the unsatisfiable core [2022-10-16 10:44:33,308 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-16 10:44:33,334 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-10-16 10:44:33,334 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-10-16 10:44:33,334 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1805967954] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-16 10:44:33,334 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-10-16 10:44:33,334 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 6 [2022-10-16 10:44:33,335 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [682167354] [2022-10-16 10:44:33,335 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-16 10:44:33,335 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-10-16 10:44:33,335 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:44:33,336 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-16 10:44:33,336 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2022-10-16 10:44:33,336 INFO L87 Difference]: Start difference. First operand 122 states and 131 transitions. Second operand has 5 states, 4 states have (on average 7.0) internal successors, (28), 5 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:33,447 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:44:33,447 INFO L93 Difference]: Finished difference Result 133 states and 140 transitions. [2022-10-16 10:44:33,448 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-10-16 10:44:33,448 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 4 states have (on average 7.0) internal successors, (28), 5 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 28 [2022-10-16 10:44:33,448 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:44:33,449 INFO L225 Difference]: With dead ends: 133 [2022-10-16 10:44:33,449 INFO L226 Difference]: Without dead ends: 130 [2022-10-16 10:44:33,450 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 26 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2022-10-16 10:44:33,450 INFO L413 NwaCegarLoop]: 41 mSDtfsCounter, 36 mSDsluCounter, 77 mSDsCounter, 0 mSdLazyCounter, 123 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 36 SdHoareTripleChecker+Valid, 118 SdHoareTripleChecker+Invalid, 129 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 123 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-10-16 10:44:33,451 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [36 Valid, 118 Invalid, 129 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 123 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-10-16 10:44:33,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130 states. [2022-10-16 10:44:33,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130 to 118. [2022-10-16 10:44:33,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 118 states, 104 states have (on average 1.2211538461538463) internal successors, (127), 117 states have internal predecessors, (127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:33,458 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 127 transitions. [2022-10-16 10:44:33,458 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 127 transitions. Word has length 28 [2022-10-16 10:44:33,458 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:44:33,458 INFO L495 AbstractCegarLoop]: Abstraction has 118 states and 127 transitions. [2022-10-16 10:44:33,459 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 4 states have (on average 7.0) internal successors, (28), 5 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:33,459 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 127 transitions. [2022-10-16 10:44:33,459 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2022-10-16 10:44:33,459 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:44:33,459 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:44:33,496 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Forceful destruction successful, exit code 0 [2022-10-16 10:44:33,675 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable17 [2022-10-16 10:44:33,676 INFO L420 AbstractCegarLoop]: === Iteration 19 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:44:33,677 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:44:33,677 INFO L85 PathProgramCache]: Analyzing trace with hash 336221903, now seen corresponding path program 2 times [2022-10-16 10:44:33,677 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:44:33,677 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [630985594] [2022-10-16 10:44:33,678 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:44:33,678 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:44:33,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:44:34,302 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:44:34,302 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:44:34,302 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [630985594] [2022-10-16 10:44:34,302 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [630985594] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-16 10:44:34,303 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1825860318] [2022-10-16 10:44:34,303 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-10-16 10:44:34,303 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:44:34,303 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-10-16 10:44:34,306 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-16 10:44:34,308 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2022-10-16 10:44:34,390 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-10-16 10:44:34,390 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-16 10:44:34,392 INFO L263 TraceCheckSpWp]: Trace formula consists of 144 conjuncts, 30 conjunts are in the unsatisfiable core [2022-10-16 10:44:34,395 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-16 10:44:34,420 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:44:34,425 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:44:34,427 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 26 [2022-10-16 10:44:34,438 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:44:34,439 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 26 [2022-10-16 10:44:34,450 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2022-10-16 10:44:34,460 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2022-10-16 10:44:34,475 INFO L356 Elim1Store]: treesize reduction 7, result has 12.5 percent of original size [2022-10-16 10:44:34,476 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 19 [2022-10-16 10:44:34,489 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 26 [2022-10-16 10:44:34,595 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:44:34,596 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 32 [2022-10-16 10:44:34,765 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:44:34,766 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 32 [2022-10-16 10:44:34,995 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 13 [2022-10-16 10:44:35,014 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 5 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:44:35,014 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-16 10:44:37,398 WARN L833 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_63| Int)) (or (forall ((v_ArrVal_828 Int)) (< (let ((.cse0 (store (select |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base|) (+ |c_ULTIMATE.start_main_~a~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_63| 8)) v_ArrVal_828))) (+ (select .cse0 |c_ULTIMATE.start_main_~a~0#1.offset|) (select (select (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| .cse0) |c_ULTIMATE.start_main_~b~0#1.base|) |c_ULTIMATE.start_main_~b~0#1.offset|))) 9223372036854775808)) (not (<= (+ |c_ULTIMATE.start_main_#t~post8#1| 1) |v_ULTIMATE.start_main_~i~0#1_63|)))) is different from false [2022-10-16 10:44:52,835 WARN L833 $PredicateComparison]: unable to prove that (forall ((v_ArrVal_828 Int) (v_ArrVal_826 Int) (|v_ULTIMATE.start_main_~i~0#1_63| Int)) (or (< (let ((.cse0 (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base|) (+ (* 8 |c_ULTIMATE.start_main_~i~0#1|) |c_ULTIMATE.start_main_~a~0#1.offset|) v_ArrVal_826) (+ |c_ULTIMATE.start_main_~a~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_63| 8)) v_ArrVal_828))) (+ (select (select (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| .cse0) |c_ULTIMATE.start_main_~b~0#1.base|) |c_ULTIMATE.start_main_~b~0#1.offset|) (select .cse0 |c_ULTIMATE.start_main_~a~0#1.offset|))) 9223372036854775808) (< |v_ULTIMATE.start_main_~i~0#1_63| (+ |c_ULTIMATE.start_main_~i~0#1| 1)))) is different from false [2022-10-16 10:44:52,919 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 8 not checked. [2022-10-16 10:44:52,920 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1825860318] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-16 10:44:52,920 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-16 10:44:52,920 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 8, 9] total 22 [2022-10-16 10:44:52,920 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1417144808] [2022-10-16 10:44:52,920 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-16 10:44:52,921 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 23 states [2022-10-16 10:44:52,921 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:44:52,922 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2022-10-16 10:44:52,922 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=86, Invalid=328, Unknown=14, NotChecked=78, Total=506 [2022-10-16 10:44:52,922 INFO L87 Difference]: Start difference. First operand 118 states and 127 transitions. Second operand has 23 states, 22 states have (on average 3.590909090909091) internal successors, (79), 23 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:44:54,989 WARN L833 $PredicateComparison]: unable to prove that (let ((.cse1 (select |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base|))) (and (= |c_ULTIMATE.start_main_#t~post8#1| 1) (= 0 |c_ULTIMATE.start_main_~b~0#1.offset|) (= (select (select |c_#memory_int| |c_ULTIMATE.start_main_~b~0#1.base|) |c_ULTIMATE.start_main_~b~0#1.offset|) 1) (forall ((|v_ULTIMATE.start_main_~i~0#1_63| Int)) (or (forall ((v_ArrVal_828 Int)) (< (let ((.cse0 (store .cse1 (+ |c_ULTIMATE.start_main_~a~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_63| 8)) v_ArrVal_828))) (+ (select .cse0 |c_ULTIMATE.start_main_~a~0#1.offset|) (select (select (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| .cse0) |c_ULTIMATE.start_main_~b~0#1.base|) |c_ULTIMATE.start_main_~b~0#1.offset|))) 9223372036854775808)) (not (<= (+ |c_ULTIMATE.start_main_#t~post8#1| 1) |v_ULTIMATE.start_main_~i~0#1_63|)))) (= 6 (select .cse1 |c_ULTIMATE.start_main_~a~0#1.offset|)) (= |c_ULTIMATE.start_main_~a~0#1.offset| 0) (= |c_ULTIMATE.start_main_~i~0#1| 1))) is different from false [2022-10-16 10:44:57,001 WARN L833 $PredicateComparison]: unable to prove that (let ((.cse1 (select |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base|))) (and (= |c_ULTIMATE.start_main_#t~post8#1| 1) (= 0 |c_ULTIMATE.start_main_~b~0#1.offset|) (= (select (select |c_#memory_int| |c_ULTIMATE.start_main_~b~0#1.base|) |c_ULTIMATE.start_main_~b~0#1.offset|) 1) (forall ((|v_ULTIMATE.start_main_~i~0#1_63| Int)) (or (forall ((v_ArrVal_828 Int)) (< (let ((.cse0 (store .cse1 (+ |c_ULTIMATE.start_main_~a~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_63| 8)) v_ArrVal_828))) (+ (select .cse0 |c_ULTIMATE.start_main_~a~0#1.offset|) (select (select (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| .cse0) |c_ULTIMATE.start_main_~b~0#1.base|) |c_ULTIMATE.start_main_~b~0#1.offset|))) 9223372036854775808)) (not (<= (+ |c_ULTIMATE.start_main_#t~post8#1| 1) |v_ULTIMATE.start_main_~i~0#1_63|)))) (= 6 (select .cse1 |c_ULTIMATE.start_main_~a~0#1.offset|)) (= |c_ULTIMATE.start_main_~a~0#1.offset| 0))) is different from false [2022-10-16 10:44:59,135 WARN L833 $PredicateComparison]: unable to prove that (let ((.cse3 (select |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base|))) (let ((.cse0 (select .cse3 |c_ULTIMATE.start_main_~a~0#1.offset|)) (.cse1 (select (select |c_#memory_int| |c_ULTIMATE.start_main_~b~0#1.base|) |c_ULTIMATE.start_main_~b~0#1.offset|))) (and (not (= (* 8 |c_ULTIMATE.start_main_~i~0#1|) 0)) (<= 1 |c_ULTIMATE.start_main_#t~post8#1|) (<= .cse0 6) (<= 2 |c_ULTIMATE.start_main_~i~0#1|) (= 0 |c_ULTIMATE.start_main_~b~0#1.offset|) (= .cse1 1) (forall ((|v_ULTIMATE.start_main_~i~0#1_63| Int)) (or (forall ((v_ArrVal_828 Int)) (< (let ((.cse2 (store .cse3 (+ |c_ULTIMATE.start_main_~a~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_63| 8)) v_ArrVal_828))) (+ (select .cse2 |c_ULTIMATE.start_main_~a~0#1.offset|) (select (select (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| .cse2) |c_ULTIMATE.start_main_~b~0#1.base|) |c_ULTIMATE.start_main_~b~0#1.offset|))) 9223372036854775808)) (not (<= (+ |c_ULTIMATE.start_main_#t~post8#1| 1) |v_ULTIMATE.start_main_~i~0#1_63|)))) (= 6 .cse0) (not (= |c_ULTIMATE.start_main_~b~0#1.base| |c_ULTIMATE.start_main_~a~0#1.base|)) (= |c_ULTIMATE.start_main_~a~0#1.offset| 0) (<= .cse1 1)))) is different from false [2022-10-16 10:45:01,179 WARN L833 $PredicateComparison]: unable to prove that (let ((.cse3 (select |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base|))) (let ((.cse0 (select .cse3 |c_ULTIMATE.start_main_~a~0#1.offset|)) (.cse1 (select (select |c_#memory_int| |c_ULTIMATE.start_main_~b~0#1.base|) |c_ULTIMATE.start_main_~b~0#1.offset|))) (and (<= 1 |c_ULTIMATE.start_main_#t~post8#1|) (<= .cse0 6) (= 0 |c_ULTIMATE.start_main_~b~0#1.offset|) (= .cse1 1) (forall ((|v_ULTIMATE.start_main_~i~0#1_63| Int)) (or (forall ((v_ArrVal_828 Int)) (< (let ((.cse2 (store .cse3 (+ |c_ULTIMATE.start_main_~a~0#1.offset| (* |v_ULTIMATE.start_main_~i~0#1_63| 8)) v_ArrVal_828))) (+ (select .cse2 |c_ULTIMATE.start_main_~a~0#1.offset|) (select (select (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| .cse2) |c_ULTIMATE.start_main_~b~0#1.base|) |c_ULTIMATE.start_main_~b~0#1.offset|))) 9223372036854775808)) (not (<= (+ |c_ULTIMATE.start_main_#t~post8#1| 1) |v_ULTIMATE.start_main_~i~0#1_63|)))) (= 6 .cse0) (not (= |c_ULTIMATE.start_main_~b~0#1.base| |c_ULTIMATE.start_main_~a~0#1.base|)) (= |c_ULTIMATE.start_main_~a~0#1.offset| 0) (<= .cse1 1)))) is different from false [2022-10-16 10:45:02,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:45:02,405 INFO L93 Difference]: Finished difference Result 140 states and 148 transitions. [2022-10-16 10:45:02,406 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-10-16 10:45:02,406 INFO L78 Accepts]: Start accepts. Automaton has has 23 states, 22 states have (on average 3.590909090909091) internal successors, (79), 23 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 29 [2022-10-16 10:45:02,406 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:45:02,407 INFO L225 Difference]: With dead ends: 140 [2022-10-16 10:45:02,407 INFO L226 Difference]: Without dead ends: 138 [2022-10-16 10:45:02,408 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 78 GetRequests, 45 SyntacticMatches, 4 SemanticMatches, 29 ConstructedPredicates, 6 IntricatePredicates, 0 DeprecatedPredicates, 102 ImplicationChecksByTransitivity, 27.1s TimeCoverageRelationStatistics Valid=145, Invalid=460, Unknown=19, NotChecked=306, Total=930 [2022-10-16 10:45:02,409 INFO L413 NwaCegarLoop]: 38 mSDtfsCounter, 122 mSDsluCounter, 297 mSDsCounter, 0 mSdLazyCounter, 294 mSolverCounterSat, 20 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 122 SdHoareTripleChecker+Valid, 335 SdHoareTripleChecker+Invalid, 460 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 20 IncrementalHoareTripleChecker+Valid, 294 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 146 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-10-16 10:45:02,409 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [122 Valid, 335 Invalid, 460 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [20 Valid, 294 Invalid, 0 Unknown, 146 Unchecked, 0.3s Time] [2022-10-16 10:45:02,410 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138 states. [2022-10-16 10:45:02,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138 to 110. [2022-10-16 10:45:02,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 110 states, 96 states have (on average 1.21875) internal successors, (117), 109 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:45:02,418 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 117 transitions. [2022-10-16 10:45:02,418 INFO L78 Accepts]: Start accepts. Automaton has 110 states and 117 transitions. Word has length 29 [2022-10-16 10:45:02,418 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:45:02,418 INFO L495 AbstractCegarLoop]: Abstraction has 110 states and 117 transitions. [2022-10-16 10:45:02,419 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 23 states, 22 states have (on average 3.590909090909091) internal successors, (79), 23 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:45:02,419 INFO L276 IsEmpty]: Start isEmpty. Operand 110 states and 117 transitions. [2022-10-16 10:45:02,419 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-10-16 10:45:02,419 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:45:02,419 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:45:02,458 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Forceful destruction successful, exit code 0 [2022-10-16 10:45:02,633 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable18,14 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:45:02,633 INFO L420 AbstractCegarLoop]: === Iteration 20 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:45:02,634 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:45:02,634 INFO L85 PathProgramCache]: Analyzing trace with hash -475019823, now seen corresponding path program 1 times [2022-10-16 10:45:02,634 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:45:02,634 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [372579851] [2022-10-16 10:45:02,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:45:02,635 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:45:02,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:45:02,769 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:45:02,769 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:45:02,769 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [372579851] [2022-10-16 10:45:02,769 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [372579851] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-16 10:45:02,769 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [924596950] [2022-10-16 10:45:02,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:45:02,770 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:45:02,770 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-10-16 10:45:02,771 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-16 10:45:02,795 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2022-10-16 10:45:02,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:45:02,858 INFO L263 TraceCheckSpWp]: Trace formula consists of 148 conjuncts, 8 conjunts are in the unsatisfiable core [2022-10-16 10:45:02,860 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-16 10:45:02,978 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 6 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:45:02,979 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-16 10:45:03,071 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 6 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:45:03,072 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [924596950] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-16 10:45:03,072 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-16 10:45:03,072 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9] total 16 [2022-10-16 10:45:03,072 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1587669650] [2022-10-16 10:45:03,072 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-16 10:45:03,073 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 16 states [2022-10-16 10:45:03,073 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:45:03,073 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2022-10-16 10:45:03,074 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=189, Unknown=0, NotChecked=0, Total=240 [2022-10-16 10:45:03,074 INFO L87 Difference]: Start difference. First operand 110 states and 117 transitions. Second operand has 16 states, 16 states have (on average 3.9375) internal successors, (63), 16 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:45:03,432 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:45:03,432 INFO L93 Difference]: Finished difference Result 236 states and 248 transitions. [2022-10-16 10:45:03,432 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2022-10-16 10:45:03,433 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 3.9375) internal successors, (63), 16 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 31 [2022-10-16 10:45:03,433 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:45:03,434 INFO L225 Difference]: With dead ends: 236 [2022-10-16 10:45:03,434 INFO L226 Difference]: Without dead ends: 182 [2022-10-16 10:45:03,435 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 75 GetRequests, 50 SyntacticMatches, 5 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 134 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=100, Invalid=362, Unknown=0, NotChecked=0, Total=462 [2022-10-16 10:45:03,436 INFO L413 NwaCegarLoop]: 28 mSDtfsCounter, 255 mSDsluCounter, 186 mSDsCounter, 0 mSdLazyCounter, 335 mSolverCounterSat, 41 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 255 SdHoareTripleChecker+Valid, 214 SdHoareTripleChecker+Invalid, 376 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 41 IncrementalHoareTripleChecker+Valid, 335 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-10-16 10:45:03,436 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [255 Valid, 214 Invalid, 376 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [41 Valid, 335 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-10-16 10:45:03,437 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 182 states. [2022-10-16 10:45:03,446 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 182 to 138. [2022-10-16 10:45:03,447 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 138 states, 124 states have (on average 1.2258064516129032) internal successors, (152), 137 states have internal predecessors, (152), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:45:03,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138 states to 138 states and 152 transitions. [2022-10-16 10:45:03,448 INFO L78 Accepts]: Start accepts. Automaton has 138 states and 152 transitions. Word has length 31 [2022-10-16 10:45:03,448 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:45:03,448 INFO L495 AbstractCegarLoop]: Abstraction has 138 states and 152 transitions. [2022-10-16 10:45:03,448 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 16 states, 16 states have (on average 3.9375) internal successors, (63), 16 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:45:03,448 INFO L276 IsEmpty]: Start isEmpty. Operand 138 states and 152 transitions. [2022-10-16 10:45:03,449 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2022-10-16 10:45:03,449 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:45:03,449 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:45:03,489 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Forceful destruction successful, exit code 0 [2022-10-16 10:45:03,662 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable19,15 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:45:03,663 INFO L420 AbstractCegarLoop]: === Iteration 21 === Targeting ULTIMATE.startErr18ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:45:03,664 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:45:03,664 INFO L85 PathProgramCache]: Analyzing trace with hash 921207273, now seen corresponding path program 1 times [2022-10-16 10:45:03,665 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:45:03,665 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1939107513] [2022-10-16 10:45:03,665 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:45:03,666 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:45:03,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:45:04,515 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-10-16 10:45:04,516 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:45:04,516 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1939107513] [2022-10-16 10:45:04,516 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1939107513] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-16 10:45:04,516 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [408419772] [2022-10-16 10:45:04,516 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:45:04,516 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:45:04,517 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-10-16 10:45:04,518 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-16 10:45:04,543 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2022-10-16 10:45:04,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:45:04,611 INFO L263 TraceCheckSpWp]: Trace formula consists of 151 conjuncts, 28 conjunts are in the unsatisfiable core [2022-10-16 10:45:04,614 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-16 10:45:04,628 INFO L356 Elim1Store]: treesize reduction 7, result has 12.5 percent of original size [2022-10-16 10:45:04,629 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 19 [2022-10-16 10:45:04,638 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:45:04,639 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:45:04,640 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:45:04,643 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 22 [2022-10-16 10:45:04,647 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2022-10-16 10:45:04,654 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2022-10-16 10:45:04,767 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 26 [2022-10-16 10:45:04,991 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:45:04,992 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 30 [2022-10-16 10:45:05,180 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 13 [2022-10-16 10:45:05,203 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:45:05,204 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-16 10:45:05,531 WARN L833 $PredicateComparison]: unable to prove that (forall ((v_ArrVal_950 Int) (v_ArrVal_948 (Array Int Int))) (< (let ((.cse1 (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_ArrVal_948))) (let ((.cse0 (select .cse1 |c_ULTIMATE.start_main_~b~0#1.base|))) (+ (select .cse0 |c_ULTIMATE.start_main_~b~0#1.offset|) (select (select (store .cse1 |c_ULTIMATE.start_main_~b~0#1.base| (store .cse0 (+ 8 |c_ULTIMATE.start_main_~b~0#1.offset|) v_ArrVal_950)) |c_ULTIMATE.start_main_~c~0#1.base|) |c_ULTIMATE.start_main_~c~0#1.offset|)))) 9223372036854775808)) is different from false [2022-10-16 10:45:05,580 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 1 not checked. [2022-10-16 10:45:05,581 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [408419772] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-16 10:45:05,581 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-16 10:45:05,581 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 8] total 19 [2022-10-16 10:45:05,581 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1278460762] [2022-10-16 10:45:05,582 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-16 10:45:05,582 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 20 states [2022-10-16 10:45:05,582 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:45:05,583 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2022-10-16 10:45:05,583 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=79, Invalid=266, Unknown=1, NotChecked=34, Total=380 [2022-10-16 10:45:05,585 INFO L87 Difference]: Start difference. First operand 138 states and 152 transitions. Second operand has 20 states, 19 states have (on average 4.7894736842105265) internal successors, (91), 20 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:45:05,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:45:05,915 INFO L93 Difference]: Finished difference Result 205 states and 230 transitions. [2022-10-16 10:45:05,916 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-10-16 10:45:05,916 INFO L78 Accepts]: Start accepts. Automaton has has 20 states, 19 states have (on average 4.7894736842105265) internal successors, (91), 20 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 33 [2022-10-16 10:45:05,916 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:45:05,917 INFO L225 Difference]: With dead ends: 205 [2022-10-16 10:45:05,918 INFO L226 Difference]: Without dead ends: 203 [2022-10-16 10:45:05,918 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 78 GetRequests, 55 SyntacticMatches, 2 SemanticMatches, 21 ConstructedPredicates, 1 IntricatePredicates, 0 DeprecatedPredicates, 84 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=125, Invalid=340, Unknown=1, NotChecked=40, Total=506 [2022-10-16 10:45:05,919 INFO L413 NwaCegarLoop]: 39 mSDtfsCounter, 146 mSDsluCounter, 219 mSDsCounter, 0 mSdLazyCounter, 170 mSolverCounterSat, 15 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 146 SdHoareTripleChecker+Valid, 258 SdHoareTripleChecker+Invalid, 355 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 15 IncrementalHoareTripleChecker+Valid, 170 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 170 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-10-16 10:45:05,922 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [146 Valid, 258 Invalid, 355 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [15 Valid, 170 Invalid, 0 Unknown, 170 Unchecked, 0.2s Time] [2022-10-16 10:45:05,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 203 states. [2022-10-16 10:45:05,933 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 203 to 150. [2022-10-16 10:45:05,933 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 150 states, 136 states have (on average 1.213235294117647) internal successors, (165), 149 states have internal predecessors, (165), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:45:05,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 165 transitions. [2022-10-16 10:45:05,934 INFO L78 Accepts]: Start accepts. Automaton has 150 states and 165 transitions. Word has length 33 [2022-10-16 10:45:05,934 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:45:05,934 INFO L495 AbstractCegarLoop]: Abstraction has 150 states and 165 transitions. [2022-10-16 10:45:05,935 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 20 states, 19 states have (on average 4.7894736842105265) internal successors, (91), 20 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:45:05,935 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states and 165 transitions. [2022-10-16 10:45:05,936 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2022-10-16 10:45:05,936 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:45:05,936 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1] [2022-10-16 10:45:05,971 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Forceful destruction successful, exit code 0 [2022-10-16 10:45:06,150 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable20,16 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:45:06,150 INFO L420 AbstractCegarLoop]: === Iteration 22 === Targeting ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:45:06,151 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:45:06,151 INFO L85 PathProgramCache]: Analyzing trace with hash 728765121, now seen corresponding path program 2 times [2022-10-16 10:45:06,151 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:45:06,151 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1071707665] [2022-10-16 10:45:06,151 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:45:06,151 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:45:06,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:45:07,257 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:45:07,257 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:45:07,257 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1071707665] [2022-10-16 10:45:07,258 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1071707665] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-16 10:45:07,258 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1929287567] [2022-10-16 10:45:07,258 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-10-16 10:45:07,258 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:45:07,258 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-10-16 10:45:07,259 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-16 10:45:07,261 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2022-10-16 10:45:07,346 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-10-16 10:45:07,346 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-16 10:45:07,348 INFO L263 TraceCheckSpWp]: Trace formula consists of 154 conjuncts, 45 conjunts are in the unsatisfiable core [2022-10-16 10:45:07,351 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-16 10:45:07,364 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 17 [2022-10-16 10:45:07,369 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:45:07,370 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:45:07,371 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:45:07,372 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 3 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2022-10-16 10:45:07,377 INFO L356 Elim1Store]: treesize reduction 7, result has 12.5 percent of original size [2022-10-16 10:45:07,377 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 19 [2022-10-16 10:45:07,447 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 42 treesize of output 32 [2022-10-16 10:45:07,635 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:45:07,636 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:45:07,638 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:45:07,639 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:45:07,640 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:45:07,643 INFO L356 Elim1Store]: treesize reduction 2, result has 33.3 percent of original size [2022-10-16 10:45:07,643 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 46 treesize of output 51 [2022-10-16 10:45:07,946 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:45:07,947 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:45:07,948 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:45:07,949 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:45:07,950 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:45:07,951 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:45:07,952 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:45:07,955 INFO L356 Elim1Store]: treesize reduction 2, result has 33.3 percent of original size [2022-10-16 10:45:07,955 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 4 select indices, 4 select index equivalence classes, 6 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 69 treesize of output 68 [2022-10-16 10:45:08,234 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-10-16 10:45:08,234 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 4 select indices, 4 select index equivalence classes, 6 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 48 treesize of output 20 [2022-10-16 10:45:08,239 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:45:08,239 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-16 10:45:08,754 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:45:08,754 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1929287567] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-16 10:45:08,754 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-16 10:45:08,754 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15] total 41 [2022-10-16 10:45:08,755 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1621582949] [2022-10-16 10:45:08,755 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-16 10:45:08,756 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 42 states [2022-10-16 10:45:08,756 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:45:08,756 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2022-10-16 10:45:08,757 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=281, Invalid=1441, Unknown=0, NotChecked=0, Total=1722 [2022-10-16 10:45:08,758 INFO L87 Difference]: Start difference. First operand 150 states and 165 transitions. Second operand has 42 states, 41 states have (on average 2.1219512195121952) internal successors, (87), 42 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:45:10,132 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:45:10,133 INFO L93 Difference]: Finished difference Result 191 states and 211 transitions. [2022-10-16 10:45:10,135 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2022-10-16 10:45:10,135 INFO L78 Accepts]: Start accepts. Automaton has has 42 states, 41 states have (on average 2.1219512195121952) internal successors, (87), 42 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 33 [2022-10-16 10:45:10,135 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:45:10,136 INFO L225 Difference]: With dead ends: 191 [2022-10-16 10:45:10,137 INFO L226 Difference]: Without dead ends: 190 [2022-10-16 10:45:10,139 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 93 GetRequests, 38 SyntacticMatches, 1 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1004 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=496, Invalid=2584, Unknown=0, NotChecked=0, Total=3080 [2022-10-16 10:45:10,140 INFO L413 NwaCegarLoop]: 47 mSDtfsCounter, 138 mSDsluCounter, 432 mSDsCounter, 0 mSdLazyCounter, 879 mSolverCounterSat, 40 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 138 SdHoareTripleChecker+Valid, 479 SdHoareTripleChecker+Invalid, 919 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 40 IncrementalHoareTripleChecker+Valid, 879 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2022-10-16 10:45:10,140 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [138 Valid, 479 Invalid, 919 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [40 Valid, 879 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2022-10-16 10:45:10,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 190 states. [2022-10-16 10:45:10,151 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 190 to 171. [2022-10-16 10:45:10,151 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 171 states, 157 states have (on average 1.2101910828025477) internal successors, (190), 170 states have internal predecessors, (190), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:45:10,152 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 171 states to 171 states and 190 transitions. [2022-10-16 10:45:10,152 INFO L78 Accepts]: Start accepts. Automaton has 171 states and 190 transitions. Word has length 33 [2022-10-16 10:45:10,152 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:45:10,152 INFO L495 AbstractCegarLoop]: Abstraction has 171 states and 190 transitions. [2022-10-16 10:45:10,153 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 42 states, 41 states have (on average 2.1219512195121952) internal successors, (87), 42 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:45:10,153 INFO L276 IsEmpty]: Start isEmpty. Operand 171 states and 190 transitions. [2022-10-16 10:45:10,153 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-10-16 10:45:10,153 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:45:10,154 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:45:10,191 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Forceful destruction successful, exit code 0 [2022-10-16 10:45:10,367 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 17 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable21 [2022-10-16 10:45:10,368 INFO L420 AbstractCegarLoop]: === Iteration 23 === Targeting ULTIMATE.startErr20ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:45:10,369 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:45:10,369 INFO L85 PathProgramCache]: Analyzing trace with hash -1155032271, now seen corresponding path program 1 times [2022-10-16 10:45:10,370 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:45:10,370 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [961319663] [2022-10-16 10:45:10,370 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:45:10,371 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:45:10,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:45:10,428 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-10-16 10:45:10,429 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:45:10,429 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [961319663] [2022-10-16 10:45:10,429 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [961319663] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-16 10:45:10,429 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-16 10:45:10,429 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-16 10:45:10,429 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1264567125] [2022-10-16 10:45:10,429 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-16 10:45:10,430 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-10-16 10:45:10,430 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:45:10,430 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-16 10:45:10,431 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-16 10:45:10,431 INFO L87 Difference]: Start difference. First operand 171 states and 190 transitions. Second operand has 4 states, 3 states have (on average 12.0) internal successors, (36), 4 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:45:10,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:45:10,526 INFO L93 Difference]: Finished difference Result 183 states and 204 transitions. [2022-10-16 10:45:10,526 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-16 10:45:10,526 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 3 states have (on average 12.0) internal successors, (36), 4 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-10-16 10:45:10,526 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:45:10,527 INFO L225 Difference]: With dead ends: 183 [2022-10-16 10:45:10,527 INFO L226 Difference]: Without dead ends: 181 [2022-10-16 10:45:10,528 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-10-16 10:45:10,528 INFO L413 NwaCegarLoop]: 42 mSDtfsCounter, 21 mSDsluCounter, 61 mSDsCounter, 0 mSdLazyCounter, 81 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 21 SdHoareTripleChecker+Valid, 103 SdHoareTripleChecker+Invalid, 84 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 81 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-10-16 10:45:10,529 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [21 Valid, 103 Invalid, 84 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 81 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-10-16 10:45:10,530 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 181 states. [2022-10-16 10:45:10,540 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 181 to 179. [2022-10-16 10:45:10,540 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 179 states, 165 states have (on average 1.2121212121212122) internal successors, (200), 178 states have internal predecessors, (200), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:45:10,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 200 transitions. [2022-10-16 10:45:10,541 INFO L78 Accepts]: Start accepts. Automaton has 179 states and 200 transitions. Word has length 36 [2022-10-16 10:45:10,541 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:45:10,541 INFO L495 AbstractCegarLoop]: Abstraction has 179 states and 200 transitions. [2022-10-16 10:45:10,542 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 3 states have (on average 12.0) internal successors, (36), 4 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:45:10,542 INFO L276 IsEmpty]: Start isEmpty. Operand 179 states and 200 transitions. [2022-10-16 10:45:10,542 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2022-10-16 10:45:10,542 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:45:10,542 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:45:10,543 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable22 [2022-10-16 10:45:10,543 INFO L420 AbstractCegarLoop]: === Iteration 24 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:45:10,543 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:45:10,543 INFO L85 PathProgramCache]: Analyzing trace with hash -140926759, now seen corresponding path program 2 times [2022-10-16 10:45:10,543 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:45:10,544 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [111239116] [2022-10-16 10:45:10,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:45:10,544 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:45:10,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:45:12,290 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:45:12,291 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:45:12,291 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [111239116] [2022-10-16 10:45:12,292 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [111239116] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-16 10:45:12,292 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [983151219] [2022-10-16 10:45:12,292 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-10-16 10:45:12,292 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:45:12,293 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-10-16 10:45:12,294 INFO L229 MonitoredProcess]: Starting monitored process 18 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-16 10:45:12,297 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2022-10-16 10:45:12,395 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-10-16 10:45:12,396 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-16 10:45:12,397 INFO L263 TraceCheckSpWp]: Trace formula consists of 165 conjuncts, 47 conjunts are in the unsatisfiable core [2022-10-16 10:45:12,401 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-16 10:45:12,419 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:45:12,422 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:45:12,423 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 26 [2022-10-16 10:45:12,429 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:45:12,430 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 26 [2022-10-16 10:45:12,438 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2022-10-16 10:45:12,442 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:45:12,450 INFO L356 Elim1Store]: treesize reduction 7, result has 12.5 percent of original size [2022-10-16 10:45:12,450 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 19 treesize of output 15 [2022-10-16 10:45:12,459 INFO L356 Elim1Store]: treesize reduction 7, result has 12.5 percent of original size [2022-10-16 10:45:12,460 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 22 treesize of output 27 [2022-10-16 10:45:12,463 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2022-10-16 10:45:12,618 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:45:12,619 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:45:12,623 INFO L356 Elim1Store]: treesize reduction 19, result has 5.0 percent of original size [2022-10-16 10:45:12,624 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 1 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 44 treesize of output 49 [2022-10-16 10:45:12,939 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:45:12,941 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:45:12,944 INFO L356 Elim1Store]: treesize reduction 7, result has 12.5 percent of original size [2022-10-16 10:45:12,944 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 43 treesize of output 44 [2022-10-16 10:45:13,413 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:45:13,414 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:45:13,415 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:45:13,416 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:45:13,417 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:45:13,433 INFO L356 Elim1Store]: treesize reduction 59, result has 15.7 percent of original size [2022-10-16 10:45:13,434 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 5 select indices, 5 select index equivalence classes, 1 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 11 case distinctions, treesize of input 75 treesize of output 77 [2022-10-16 10:45:13,905 INFO L356 Elim1Store]: treesize reduction 13, result has 23.5 percent of original size [2022-10-16 10:45:13,906 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 4 select indices, 4 select index equivalence classes, 1 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 59 treesize of output 27 [2022-10-16 10:45:13,950 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:45:13,950 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-16 10:45:35,902 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:45:35,902 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [983151219] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-16 10:45:35,902 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-16 10:45:35,902 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 14, 15] total 42 [2022-10-16 10:45:35,903 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [420627733] [2022-10-16 10:45:35,903 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-16 10:45:35,903 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 43 states [2022-10-16 10:45:35,904 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:45:35,904 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2022-10-16 10:45:35,905 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=196, Invalid=1601, Unknown=9, NotChecked=0, Total=1806 [2022-10-16 10:45:35,905 INFO L87 Difference]: Start difference. First operand 179 states and 200 transitions. Second operand has 43 states, 42 states have (on average 2.5952380952380953) internal successors, (109), 43 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:45:45,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:45:45,445 INFO L93 Difference]: Finished difference Result 227 states and 251 transitions. [2022-10-16 10:45:45,446 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2022-10-16 10:45:45,446 INFO L78 Accepts]: Start accepts. Automaton has has 43 states, 42 states have (on average 2.5952380952380953) internal successors, (109), 43 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 39 [2022-10-16 10:45:45,446 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:45:45,447 INFO L225 Difference]: With dead ends: 227 [2022-10-16 10:45:45,447 INFO L226 Difference]: Without dead ends: 226 [2022-10-16 10:45:45,449 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 121 GetRequests, 54 SyntacticMatches, 3 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 930 ImplicationChecksByTransitivity, 31.3s TimeCoverageRelationStatistics Valid=505, Invalid=3776, Unknown=9, NotChecked=0, Total=4290 [2022-10-16 10:45:45,450 INFO L413 NwaCegarLoop]: 34 mSDtfsCounter, 171 mSDsluCounter, 535 mSDsCounter, 0 mSdLazyCounter, 924 mSolverCounterSat, 23 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 171 SdHoareTripleChecker+Valid, 569 SdHoareTripleChecker+Invalid, 1792 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 23 IncrementalHoareTripleChecker+Valid, 924 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 845 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2022-10-16 10:45:45,450 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [171 Valid, 569 Invalid, 1792 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [23 Valid, 924 Invalid, 0 Unknown, 845 Unchecked, 0.8s Time] [2022-10-16 10:45:45,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 226 states. [2022-10-16 10:45:45,463 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 226 to 196. [2022-10-16 10:45:45,463 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 196 states, 182 states have (on average 1.1978021978021978) internal successors, (218), 195 states have internal predecessors, (218), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:45:45,464 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 196 states to 196 states and 218 transitions. [2022-10-16 10:45:45,464 INFO L78 Accepts]: Start accepts. Automaton has 196 states and 218 transitions. Word has length 39 [2022-10-16 10:45:45,464 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:45:45,465 INFO L495 AbstractCegarLoop]: Abstraction has 196 states and 218 transitions. [2022-10-16 10:45:45,465 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 43 states, 42 states have (on average 2.5952380952380953) internal successors, (109), 43 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:45:45,465 INFO L276 IsEmpty]: Start isEmpty. Operand 196 states and 218 transitions. [2022-10-16 10:45:45,465 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2022-10-16 10:45:45,466 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:45:45,466 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:45:45,491 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Forceful destruction successful, exit code 0 [2022-10-16 10:45:45,675 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable23,18 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:45:45,676 INFO L420 AbstractCegarLoop]: === Iteration 25 === Targeting ULTIMATE.startErr15ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:45:45,676 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:45:45,677 INFO L85 PathProgramCache]: Analyzing trace with hash 1523549345, now seen corresponding path program 1 times [2022-10-16 10:45:45,677 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:45:45,677 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [555749226] [2022-10-16 10:45:45,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:45:45,678 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:45:45,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:45:45,753 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-10-16 10:45:45,754 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:45:45,754 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [555749226] [2022-10-16 10:45:45,754 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [555749226] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-16 10:45:45,754 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [82503126] [2022-10-16 10:45:45,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:45:45,755 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:45:45,755 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-10-16 10:45:45,756 INFO L229 MonitoredProcess]: Starting monitored process 19 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-16 10:45:45,774 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2022-10-16 10:45:45,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:45:45,869 INFO L263 TraceCheckSpWp]: Trace formula consists of 165 conjuncts, 4 conjunts are in the unsatisfiable core [2022-10-16 10:45:45,871 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-16 10:45:45,913 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-10-16 10:45:45,913 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-10-16 10:45:45,913 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [82503126] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-16 10:45:45,914 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-10-16 10:45:45,914 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 6 [2022-10-16 10:45:45,914 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1243665448] [2022-10-16 10:45:45,914 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-16 10:45:45,914 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-10-16 10:45:45,915 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:45:45,915 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-16 10:45:45,915 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2022-10-16 10:45:45,915 INFO L87 Difference]: Start difference. First operand 196 states and 218 transitions. Second operand has 5 states, 4 states have (on average 10.0) internal successors, (40), 5 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:45:46,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:45:46,084 INFO L93 Difference]: Finished difference Result 198 states and 218 transitions. [2022-10-16 10:45:46,084 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-10-16 10:45:46,084 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 4 states have (on average 10.0) internal successors, (40), 5 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 40 [2022-10-16 10:45:46,085 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:45:46,086 INFO L225 Difference]: With dead ends: 198 [2022-10-16 10:45:46,086 INFO L226 Difference]: Without dead ends: 195 [2022-10-16 10:45:46,086 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 38 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2022-10-16 10:45:46,087 INFO L413 NwaCegarLoop]: 35 mSDtfsCounter, 33 mSDsluCounter, 69 mSDsCounter, 0 mSdLazyCounter, 121 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 33 SdHoareTripleChecker+Valid, 104 SdHoareTripleChecker+Invalid, 126 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 121 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-10-16 10:45:46,087 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [33 Valid, 104 Invalid, 126 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 121 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-10-16 10:45:46,088 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195 states. [2022-10-16 10:45:46,099 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195 to 191. [2022-10-16 10:45:46,100 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 191 states, 180 states have (on average 1.1666666666666667) internal successors, (210), 190 states have internal predecessors, (210), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:45:46,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191 states to 191 states and 210 transitions. [2022-10-16 10:45:46,101 INFO L78 Accepts]: Start accepts. Automaton has 191 states and 210 transitions. Word has length 40 [2022-10-16 10:45:46,101 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:45:46,101 INFO L495 AbstractCegarLoop]: Abstraction has 191 states and 210 transitions. [2022-10-16 10:45:46,102 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 4 states have (on average 10.0) internal successors, (40), 5 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:45:46,102 INFO L276 IsEmpty]: Start isEmpty. Operand 191 states and 210 transitions. [2022-10-16 10:45:46,102 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2022-10-16 10:45:46,102 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:45:46,102 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:45:46,143 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Forceful destruction successful, exit code 0 [2022-10-16 10:45:46,317 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable24,19 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:45:46,318 INFO L420 AbstractCegarLoop]: === Iteration 26 === Targeting ULTIMATE.startErr11ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:45:46,318 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:45:46,319 INFO L85 PathProgramCache]: Analyzing trace with hash -73762143, now seen corresponding path program 1 times [2022-10-16 10:45:46,319 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:45:46,319 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1074285747] [2022-10-16 10:45:46,320 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:45:46,320 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:45:46,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:45:47,391 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 17 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:45:47,391 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:45:47,392 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1074285747] [2022-10-16 10:45:47,392 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1074285747] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-16 10:45:47,392 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1891022323] [2022-10-16 10:45:47,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:45:47,392 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:45:47,392 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-10-16 10:45:47,396 INFO L229 MonitoredProcess]: Starting monitored process 20 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-16 10:45:47,402 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2022-10-16 10:45:47,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:45:47,500 INFO L263 TraceCheckSpWp]: Trace formula consists of 166 conjuncts, 40 conjunts are in the unsatisfiable core [2022-10-16 10:45:47,503 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-16 10:45:47,548 INFO L356 Elim1Store]: treesize reduction 13, result has 58.1 percent of original size [2022-10-16 10:45:47,548 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 3 new quantified variables, introduced 2 case distinctions, treesize of input 112 treesize of output 104 [2022-10-16 10:45:47,659 INFO L356 Elim1Store]: treesize reduction 141, result has 25.4 percent of original size [2022-10-16 10:45:47,660 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 3 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 5 new quantified variables, introduced 7 case distinctions, treesize of input 96 treesize of output 196 [2022-10-16 10:45:47,679 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2022-10-16 10:45:47,697 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2022-10-16 10:45:47,744 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2022-10-16 10:45:47,793 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:45:47,796 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:45:47,798 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 2 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 53 [2022-10-16 10:45:47,807 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 7 [2022-10-16 10:45:47,883 INFO L356 Elim1Store]: treesize reduction 25, result has 24.2 percent of original size [2022-10-16 10:45:47,884 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 2 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 5 case distinctions, treesize of input 77 treesize of output 78 [2022-10-16 10:45:47,928 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 7 [2022-10-16 10:45:47,948 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 7 [2022-10-16 10:45:47,959 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 2 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 62 [2022-10-16 10:45:47,985 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:45:47,986 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 7 [2022-10-16 10:45:48,035 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 3 [2022-10-16 10:45:48,450 INFO L356 Elim1Store]: treesize reduction 25, result has 16.7 percent of original size [2022-10-16 10:45:48,451 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 2 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 2 case distinctions, treesize of input 73 treesize of output 45 [2022-10-16 10:45:48,456 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 31 [2022-10-16 10:45:48,498 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 7 [2022-10-16 10:45:48,803 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 8 [2022-10-16 10:45:49,698 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:45:49,737 INFO L356 Elim1Store]: treesize reduction 25, result has 41.9 percent of original size [2022-10-16 10:45:49,738 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 1 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 137 treesize of output 142 [2022-10-16 10:45:49,745 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:45:49,749 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 89 [2022-10-16 10:45:49,756 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 89 treesize of output 83 [2022-10-16 10:45:49,765 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 83 treesize of output 79 [2022-10-16 10:45:49,816 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 5 [2022-10-16 10:45:49,822 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2022-10-16 10:45:49,834 WARN L234 Elim1Store]: Array PQE input equivalent to false [2022-10-16 10:45:49,840 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:45:49,841 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:45:49,842 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 32 [2022-10-16 10:45:50,139 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:45:50,140 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:45:50,141 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 4 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 34 [2022-10-16 10:45:50,430 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 50 treesize of output 43 [2022-10-16 10:45:50,908 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 2 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 20 [2022-10-16 10:45:50,976 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 17 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:45:50,976 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-16 10:45:54,813 WARN L833 $PredicateComparison]: unable to prove that (forall ((|ULTIMATE.start_main_~b~0#1.offset| Int) (v_ArrVal_1255 Int) (v_ArrVal_1254 Int)) (or (< 0 (+ 9223372036854775809 v_ArrVal_1255 (select (select (let ((.cse0 (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| (store (select |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base|) (+ (* 8 |c_ULTIMATE.start_main_~i~0#1|) |c_ULTIMATE.start_main_~a~0#1.offset|) v_ArrVal_1254)))) (store .cse0 |c_ULTIMATE.start_main_~b~0#1.base| (store (select .cse0 |c_ULTIMATE.start_main_~b~0#1.base|) (+ |ULTIMATE.start_main_~b~0#1.offset| 8) v_ArrVal_1255))) |c_ULTIMATE.start_main_~a~0#1.base|) (+ 8 |c_ULTIMATE.start_main_~a~0#1.offset|)))) (< (+ 9223372036854775808 v_ArrVal_1255) 0))) is different from false [2022-10-16 10:46:00,735 WARN L833 $PredicateComparison]: unable to prove that (forall ((|ULTIMATE.start_main_~b~0#1.offset| Int) (v_ArrVal_1255 Int) (v_ArrVal_1254 Int)) (or (< (+ 9223372036854775808 v_ArrVal_1255) 0) (< 0 (+ 9223372036854775809 v_ArrVal_1255 (select (select (let ((.cse0 (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| (store (select |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base|) (+ (* 8 |c_ULTIMATE.start_main_~i~0#1|) 8 |c_ULTIMATE.start_main_~a~0#1.offset|) v_ArrVal_1254)))) (store .cse0 |c_ULTIMATE.start_main_~b~0#1.base| (store (select .cse0 |c_ULTIMATE.start_main_~b~0#1.base|) (+ |ULTIMATE.start_main_~b~0#1.offset| 8) v_ArrVal_1255))) |c_ULTIMATE.start_main_~a~0#1.base|) (+ 8 |c_ULTIMATE.start_main_~a~0#1.offset|)))))) is different from false [2022-10-16 10:46:08,468 WARN L833 $PredicateComparison]: unable to prove that (forall ((|ULTIMATE.start_main_~b~0#1.offset| Int) (v_ArrVal_1252 Int) (v_ArrVal_1255 Int) (v_ArrVal_1254 Int)) (let ((.cse0 (select |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base|)) (.cse1 (* 8 |c_ULTIMATE.start_main_~i~0#1|))) (or (< v_ArrVal_1252 (+ (select .cse0 (+ .cse1 |c_ULTIMATE.start_main_~a~0#1.offset| (- 8))) 6)) (< 0 (+ 9223372036854775809 v_ArrVal_1255 (select (select (let ((.cse2 (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| (store (store .cse0 (+ .cse1 |c_ULTIMATE.start_main_~a~0#1.offset|) v_ArrVal_1252) (+ .cse1 8 |c_ULTIMATE.start_main_~a~0#1.offset|) v_ArrVal_1254)))) (store .cse2 |c_ULTIMATE.start_main_~b~0#1.base| (store (select .cse2 |c_ULTIMATE.start_main_~b~0#1.base|) (+ |ULTIMATE.start_main_~b~0#1.offset| 8) v_ArrVal_1255))) |c_ULTIMATE.start_main_~a~0#1.base|) (+ 8 |c_ULTIMATE.start_main_~a~0#1.offset|)))) (< (+ 9223372036854775808 v_ArrVal_1255) 0)))) is different from false [2022-10-16 10:46:08,571 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 8 not checked. [2022-10-16 10:46:08,571 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1891022323] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-16 10:46:08,571 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-16 10:46:08,572 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 13] total 35 [2022-10-16 10:46:08,572 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [699523179] [2022-10-16 10:46:08,572 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-16 10:46:08,572 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 36 states [2022-10-16 10:46:08,573 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:46:08,573 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2022-10-16 10:46:08,574 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=112, Invalid=937, Unknown=19, NotChecked=192, Total=1260 [2022-10-16 10:46:08,574 INFO L87 Difference]: Start difference. First operand 191 states and 210 transitions. Second operand has 36 states, 35 states have (on average 3.2) internal successors, (112), 36 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:46:09,053 WARN L855 $PredicateComparison]: unable to prove that (let ((.cse0 (select |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base|))) (and (= 0 |c_ULTIMATE.start_main_~b~0#1.offset|) (= |c_ULTIMATE.start_main_#t~mem9#1| 6) (<= (select .cse0 (+ (* 8 |c_ULTIMATE.start_main_~i~0#1|) |c_ULTIMATE.start_main_~a~0#1.offset| (- 8))) |c_ULTIMATE.start_main_#t~mem9#1|) (not (= |c_ULTIMATE.start_main_~b~0#1.base| |c_ULTIMATE.start_main_~a~0#1.base|)) (= |c_ULTIMATE.start_main_~a~0#1.offset| 0) (let ((.cse3 (select |c_#memory_int| |c_ULTIMATE.start_main_~b~0#1.base|)) (.cse4 (select .cse0 0))) (or (exists ((v_DerPreprocessor_10 (Array Int Int)) (v_DerPreprocessor_5 (Array Int Int)) (v_DerPreprocessor_6 (Array Int Int)) (v_DerPreprocessor_9 (Array Int Int))) (let ((.cse6 (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_9) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_10) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_9) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_10))) (let ((.cse1 (select v_DerPreprocessor_10 0)) (.cse5 (select v_DerPreprocessor_10 |c_ULTIMATE.start_main_~a~0#1.offset|)) (.cse2 (select (store (store (store (store .cse6 |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_5) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_6) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_5) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_6) |c_ULTIMATE.start_main_~b~0#1.base|))) (and (= (select v_DerPreprocessor_6 |c_ULTIMATE.start_main_~a~0#1.offset|) .cse1) (= .cse2 .cse3) (= .cse4 .cse1) (<= 6 .cse5) (= (store (store v_DerPreprocessor_6 0 .cse1) |c_ULTIMATE.start_main_~a~0#1.offset| .cse5) v_DerPreprocessor_10) (= .cse2 (select .cse6 |c_ULTIMATE.start_main_~b~0#1.base|)))))) (exists ((v_ArrVal_1250 Int) (v_DerPreprocessor_5 (Array Int Int)) (v_DerPreprocessor_6 (Array Int Int)) (v_DerPreprocessor_11 (Array Int Int)) (v_DerPreprocessor_3 Int) (v_DerPreprocessor_12 (Array Int Int))) (let ((.cse9 (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_11) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_12) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_11) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_12))) (let ((.cse7 (select (store (store (store (store .cse9 |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_5) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_6) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_5) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_6) |c_ULTIMATE.start_main_~b~0#1.base|)) (.cse8 (select v_DerPreprocessor_12 0))) (and (= .cse3 .cse7) (= .cse8 .cse4) (<= 6 v_ArrVal_1250) (<= 0 .cse8) (= (select .cse9 |c_ULTIMATE.start_main_~b~0#1.base|) .cse7) (= .cse8 (select v_DerPreprocessor_6 |c_ULTIMATE.start_main_~a~0#1.offset|)) (= (select (store (store v_DerPreprocessor_6 0 v_DerPreprocessor_3) |c_ULTIMATE.start_main_~a~0#1.offset| v_ArrVal_1250) 0) v_DerPreprocessor_3))))) (and (exists ((|ULTIMATE.start_main_~c~0#1.base| Int)) (and (<= 0 (select (select |c_#memory_int| |ULTIMATE.start_main_~c~0#1.base|) 0)) (not (= |ULTIMATE.start_main_~c~0#1.base| |c_ULTIMATE.start_main_~a~0#1.base|)))) (<= 6 (select .cse0 |c_ULTIMATE.start_main_~a~0#1.offset|))))) (= |c_ULTIMATE.start_main_~i~0#1| 1))) is different from true [2022-10-16 10:46:14,719 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:46:14,719 INFO L93 Difference]: Finished difference Result 227 states and 248 transitions. [2022-10-16 10:46:14,720 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2022-10-16 10:46:14,720 INFO L78 Accepts]: Start accepts. Automaton has has 36 states, 35 states have (on average 3.2) internal successors, (112), 36 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 40 [2022-10-16 10:46:14,720 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:46:14,722 INFO L225 Difference]: With dead ends: 227 [2022-10-16 10:46:14,722 INFO L226 Difference]: Without dead ends: 226 [2022-10-16 10:46:14,723 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 118 GetRequests, 60 SyntacticMatches, 4 SemanticMatches, 54 ConstructedPredicates, 4 IntricatePredicates, 1 DeprecatedPredicates, 367 ImplicationChecksByTransitivity, 24.0s TimeCoverageRelationStatistics Valid=301, Invalid=2341, Unknown=26, NotChecked=412, Total=3080 [2022-10-16 10:46:14,724 INFO L413 NwaCegarLoop]: 34 mSDtfsCounter, 166 mSDsluCounter, 418 mSDsCounter, 0 mSdLazyCounter, 537 mSolverCounterSat, 22 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 166 SdHoareTripleChecker+Valid, 452 SdHoareTripleChecker+Invalid, 1075 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 22 IncrementalHoareTripleChecker+Valid, 537 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 516 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-10-16 10:46:14,724 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [166 Valid, 452 Invalid, 1075 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [22 Valid, 537 Invalid, 0 Unknown, 516 Unchecked, 0.6s Time] [2022-10-16 10:46:14,725 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 226 states. [2022-10-16 10:46:14,738 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 226 to 192. [2022-10-16 10:46:14,738 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 192 states, 181 states have (on average 1.1657458563535912) internal successors, (211), 191 states have internal predecessors, (211), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:46:14,739 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 192 states to 192 states and 211 transitions. [2022-10-16 10:46:14,739 INFO L78 Accepts]: Start accepts. Automaton has 192 states and 211 transitions. Word has length 40 [2022-10-16 10:46:14,740 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:46:14,740 INFO L495 AbstractCegarLoop]: Abstraction has 192 states and 211 transitions. [2022-10-16 10:46:14,740 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 36 states, 35 states have (on average 3.2) internal successors, (112), 36 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:46:14,740 INFO L276 IsEmpty]: Start isEmpty. Operand 192 states and 211 transitions. [2022-10-16 10:46:14,741 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2022-10-16 10:46:14,741 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:46:14,741 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:46:14,773 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Forceful destruction successful, exit code 0 [2022-10-16 10:46:14,956 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable25,20 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:46:14,956 INFO L420 AbstractCegarLoop]: === Iteration 27 === Targeting ULTIMATE.startErr12ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:46:14,957 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:46:14,957 INFO L85 PathProgramCache]: Analyzing trace with hash 2129027555, now seen corresponding path program 1 times [2022-10-16 10:46:14,958 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:46:14,958 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [647407574] [2022-10-16 10:46:14,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:46:14,959 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:46:14,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:46:15,044 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2022-10-16 10:46:15,044 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:46:15,044 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [647407574] [2022-10-16 10:46:15,044 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [647407574] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-16 10:46:15,045 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1495645758] [2022-10-16 10:46:15,045 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:46:15,045 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:46:15,045 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-10-16 10:46:15,046 INFO L229 MonitoredProcess]: Starting monitored process 21 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-16 10:46:15,078 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2022-10-16 10:46:15,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:46:15,162 INFO L263 TraceCheckSpWp]: Trace formula consists of 173 conjuncts, 5 conjunts are in the unsatisfiable core [2022-10-16 10:46:15,163 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-16 10:46:15,207 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2022-10-16 10:46:15,207 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-16 10:46:15,270 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2022-10-16 10:46:15,270 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1495645758] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-16 10:46:15,270 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-16 10:46:15,270 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 11 [2022-10-16 10:46:15,271 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [71787145] [2022-10-16 10:46:15,271 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-16 10:46:15,271 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 12 states [2022-10-16 10:46:15,271 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:46:15,272 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2022-10-16 10:46:15,272 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=91, Unknown=0, NotChecked=0, Total=132 [2022-10-16 10:46:15,273 INFO L87 Difference]: Start difference. First operand 192 states and 211 transitions. Second operand has 12 states, 11 states have (on average 5.909090909090909) internal successors, (65), 12 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:46:15,501 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:46:15,501 INFO L93 Difference]: Finished difference Result 235 states and 256 transitions. [2022-10-16 10:46:15,501 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-10-16 10:46:15,501 INFO L78 Accepts]: Start accepts. Automaton has has 12 states, 11 states have (on average 5.909090909090909) internal successors, (65), 12 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 42 [2022-10-16 10:46:15,502 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:46:15,503 INFO L225 Difference]: With dead ends: 235 [2022-10-16 10:46:15,503 INFO L226 Difference]: Without dead ends: 234 [2022-10-16 10:46:15,503 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 91 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 40 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=77, Invalid=163, Unknown=0, NotChecked=0, Total=240 [2022-10-16 10:46:15,504 INFO L413 NwaCegarLoop]: 36 mSDtfsCounter, 82 mSDsluCounter, 126 mSDsCounter, 0 mSdLazyCounter, 189 mSolverCounterSat, 18 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 82 SdHoareTripleChecker+Valid, 162 SdHoareTripleChecker+Invalid, 207 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 18 IncrementalHoareTripleChecker+Valid, 189 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-10-16 10:46:15,504 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [82 Valid, 162 Invalid, 207 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [18 Valid, 189 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-10-16 10:46:15,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 234 states. [2022-10-16 10:46:15,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 234 to 220. [2022-10-16 10:46:15,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 220 states, 209 states have (on average 1.1818181818181819) internal successors, (247), 219 states have internal predecessors, (247), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:46:15,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 247 transitions. [2022-10-16 10:46:15,527 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 247 transitions. Word has length 42 [2022-10-16 10:46:15,528 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:46:15,528 INFO L495 AbstractCegarLoop]: Abstraction has 220 states and 247 transitions. [2022-10-16 10:46:15,528 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 12 states, 11 states have (on average 5.909090909090909) internal successors, (65), 12 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:46:15,528 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 247 transitions. [2022-10-16 10:46:15,528 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2022-10-16 10:46:15,528 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:46:15,529 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:46:15,560 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Forceful destruction successful, exit code 0 [2022-10-16 10:46:15,743 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 21 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable26 [2022-10-16 10:46:15,743 INFO L420 AbstractCegarLoop]: === Iteration 28 === Targeting ULTIMATE.startErr18ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:46:15,744 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:46:15,745 INFO L85 PathProgramCache]: Analyzing trace with hash -1155733965, now seen corresponding path program 1 times [2022-10-16 10:46:15,745 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:46:15,745 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1392922850] [2022-10-16 10:46:15,746 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:46:15,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:46:15,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:46:15,917 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-10-16 10:46:15,918 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:46:15,918 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1392922850] [2022-10-16 10:46:15,918 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1392922850] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-16 10:46:15,918 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1202874314] [2022-10-16 10:46:15,918 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:46:15,919 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:46:15,919 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-10-16 10:46:15,920 INFO L229 MonitoredProcess]: Starting monitored process 22 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-16 10:46:15,939 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2022-10-16 10:46:16,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:46:16,021 INFO L263 TraceCheckSpWp]: Trace formula consists of 172 conjuncts, 8 conjunts are in the unsatisfiable core [2022-10-16 10:46:16,022 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-16 10:46:16,159 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 6 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-10-16 10:46:16,159 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-16 10:46:16,286 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 6 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-10-16 10:46:16,286 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1202874314] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-16 10:46:16,286 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-16 10:46:16,286 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9] total 16 [2022-10-16 10:46:16,287 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1533351462] [2022-10-16 10:46:16,287 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-16 10:46:16,287 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 16 states [2022-10-16 10:46:16,287 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:46:16,288 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2022-10-16 10:46:16,288 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=189, Unknown=0, NotChecked=0, Total=240 [2022-10-16 10:46:16,288 INFO L87 Difference]: Start difference. First operand 220 states and 247 transitions. Second operand has 16 states, 16 states have (on average 4.6875) internal successors, (75), 16 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:46:16,740 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:46:16,740 INFO L93 Difference]: Finished difference Result 265 states and 288 transitions. [2022-10-16 10:46:16,740 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2022-10-16 10:46:16,741 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 4.6875) internal successors, (75), 16 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 43 [2022-10-16 10:46:16,741 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:46:16,742 INFO L225 Difference]: With dead ends: 265 [2022-10-16 10:46:16,742 INFO L226 Difference]: Without dead ends: 234 [2022-10-16 10:46:16,743 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 99 GetRequests, 74 SyntacticMatches, 5 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 132 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=100, Invalid=362, Unknown=0, NotChecked=0, Total=462 [2022-10-16 10:46:16,743 INFO L413 NwaCegarLoop]: 27 mSDtfsCounter, 130 mSDsluCounter, 198 mSDsCounter, 0 mSdLazyCounter, 372 mSolverCounterSat, 21 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 130 SdHoareTripleChecker+Valid, 225 SdHoareTripleChecker+Invalid, 393 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 21 IncrementalHoareTripleChecker+Valid, 372 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-10-16 10:46:16,744 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [130 Valid, 225 Invalid, 393 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [21 Valid, 372 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-10-16 10:46:16,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 234 states. [2022-10-16 10:46:16,759 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 234 to 212. [2022-10-16 10:46:16,759 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 212 states, 201 states have (on average 1.1691542288557213) internal successors, (235), 211 states have internal predecessors, (235), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:46:16,760 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 212 states to 212 states and 235 transitions. [2022-10-16 10:46:16,760 INFO L78 Accepts]: Start accepts. Automaton has 212 states and 235 transitions. Word has length 43 [2022-10-16 10:46:16,761 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:46:16,761 INFO L495 AbstractCegarLoop]: Abstraction has 212 states and 235 transitions. [2022-10-16 10:46:16,761 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 16 states, 16 states have (on average 4.6875) internal successors, (75), 16 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:46:16,761 INFO L276 IsEmpty]: Start isEmpty. Operand 212 states and 235 transitions. [2022-10-16 10:46:16,762 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2022-10-16 10:46:16,762 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:46:16,762 INFO L195 NwaCegarLoop]: trace histogram [5, 5, 5, 5, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1] [2022-10-16 10:46:16,803 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Forceful destruction successful, exit code 0 [2022-10-16 10:46:16,968 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 22 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable27 [2022-10-16 10:46:16,968 INFO L420 AbstractCegarLoop]: === Iteration 29 === Targeting ULTIMATE.startErr4ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:46:16,969 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:46:16,969 INFO L85 PathProgramCache]: Analyzing trace with hash -1614472043, now seen corresponding path program 2 times [2022-10-16 10:46:16,970 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:46:16,970 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1685345793] [2022-10-16 10:46:16,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:46:16,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:46:16,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:46:17,169 INFO L134 CoverageAnalysis]: Checked inductivity of 76 backedges. 0 proven. 76 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:46:17,169 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:46:17,169 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1685345793] [2022-10-16 10:46:17,170 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1685345793] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-16 10:46:17,170 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [476042291] [2022-10-16 10:46:17,170 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-10-16 10:46:17,170 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:46:17,170 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-10-16 10:46:17,172 INFO L229 MonitoredProcess]: Starting monitored process 23 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-16 10:46:17,195 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2022-10-16 10:46:17,275 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2022-10-16 10:46:17,275 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-16 10:46:17,276 INFO L263 TraceCheckSpWp]: Trace formula consists of 111 conjuncts, 4 conjunts are in the unsatisfiable core [2022-10-16 10:46:17,278 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-16 10:46:17,385 INFO L134 CoverageAnalysis]: Checked inductivity of 76 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2022-10-16 10:46:17,385 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-16 10:46:17,484 INFO L134 CoverageAnalysis]: Checked inductivity of 76 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2022-10-16 10:46:17,485 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [476042291] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-16 10:46:17,485 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-16 10:46:17,485 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 4, 4] total 14 [2022-10-16 10:46:17,485 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1465265483] [2022-10-16 10:46:17,485 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-16 10:46:17,486 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 15 states [2022-10-16 10:46:17,486 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:46:17,486 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2022-10-16 10:46:17,487 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=153, Unknown=0, NotChecked=0, Total=210 [2022-10-16 10:46:17,487 INFO L87 Difference]: Start difference. First operand 212 states and 235 transitions. Second operand has 15 states, 14 states have (on average 4.5) internal successors, (63), 15 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:46:17,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:46:17,953 INFO L93 Difference]: Finished difference Result 219 states and 240 transitions. [2022-10-16 10:46:17,953 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2022-10-16 10:46:17,953 INFO L78 Accepts]: Start accepts. Automaton has has 15 states, 14 states have (on average 4.5) internal successors, (63), 15 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 44 [2022-10-16 10:46:17,953 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:46:17,954 INFO L225 Difference]: With dead ends: 219 [2022-10-16 10:46:17,954 INFO L226 Difference]: Without dead ends: 217 [2022-10-16 10:46:17,955 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 109 GetRequests, 82 SyntacticMatches, 2 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 119 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=207, Invalid=495, Unknown=0, NotChecked=0, Total=702 [2022-10-16 10:46:17,955 INFO L413 NwaCegarLoop]: 25 mSDtfsCounter, 186 mSDsluCounter, 174 mSDsCounter, 0 mSdLazyCounter, 319 mSolverCounterSat, 26 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 186 SdHoareTripleChecker+Valid, 199 SdHoareTripleChecker+Invalid, 345 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 26 IncrementalHoareTripleChecker+Valid, 319 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-10-16 10:46:17,957 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [186 Valid, 199 Invalid, 345 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [26 Valid, 319 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-10-16 10:46:17,957 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 217 states. [2022-10-16 10:46:17,980 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 217 to 210. [2022-10-16 10:46:17,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 210 states, 201 states have (on average 1.1492537313432836) internal successors, (231), 209 states have internal predecessors, (231), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:46:17,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 210 states to 210 states and 231 transitions. [2022-10-16 10:46:17,982 INFO L78 Accepts]: Start accepts. Automaton has 210 states and 231 transitions. Word has length 44 [2022-10-16 10:46:17,982 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:46:17,983 INFO L495 AbstractCegarLoop]: Abstraction has 210 states and 231 transitions. [2022-10-16 10:46:17,983 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 15 states, 14 states have (on average 4.5) internal successors, (63), 15 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:46:17,983 INFO L276 IsEmpty]: Start isEmpty. Operand 210 states and 231 transitions. [2022-10-16 10:46:17,983 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2022-10-16 10:46:17,983 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:46:17,984 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:46:18,010 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Forceful destruction successful, exit code 0 [2022-10-16 10:46:18,184 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 23 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable28 [2022-10-16 10:46:18,185 INFO L420 AbstractCegarLoop]: === Iteration 30 === Targeting ULTIMATE.startErr22ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:46:18,188 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:46:18,188 INFO L85 PathProgramCache]: Analyzing trace with hash -918944492, now seen corresponding path program 1 times [2022-10-16 10:46:18,188 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:46:18,188 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1772916966] [2022-10-16 10:46:18,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:46:18,189 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:46:18,203 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-10-16 10:46:18,203 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [767585881] [2022-10-16 10:46:18,203 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:46:18,203 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:46:18,204 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-10-16 10:46:18,205 INFO L229 MonitoredProcess]: Starting monitored process 24 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-16 10:46:18,223 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2022-10-16 10:46:18,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:46:18,325 INFO L263 TraceCheckSpWp]: Trace formula consists of 186 conjuncts, 7 conjunts are in the unsatisfiable core [2022-10-16 10:46:18,327 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-16 10:46:18,354 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-10-16 10:46:18,355 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-16 10:46:18,422 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-10-16 10:46:18,422 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:46:18,423 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1772916966] [2022-10-16 10:46:18,423 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-10-16 10:46:18,423 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [767585881] [2022-10-16 10:46:18,423 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [767585881] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-16 10:46:18,423 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-10-16 10:46:18,423 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 7 [2022-10-16 10:46:18,423 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [166152965] [2022-10-16 10:46:18,424 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-10-16 10:46:18,424 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-10-16 10:46:18,424 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:46:18,425 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-10-16 10:46:18,425 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2022-10-16 10:46:18,425 INFO L87 Difference]: Start difference. First operand 210 states and 231 transitions. Second operand has 8 states, 7 states have (on average 8.571428571428571) internal successors, (60), 8 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:46:18,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:46:18,694 INFO L93 Difference]: Finished difference Result 226 states and 246 transitions. [2022-10-16 10:46:18,694 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-10-16 10:46:18,694 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 8.571428571428571) internal successors, (60), 8 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 49 [2022-10-16 10:46:18,694 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:46:18,695 INFO L225 Difference]: With dead ends: 226 [2022-10-16 10:46:18,696 INFO L226 Difference]: Without dead ends: 224 [2022-10-16 10:46:18,696 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 98 GetRequests, 90 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=31, Invalid=59, Unknown=0, NotChecked=0, Total=90 [2022-10-16 10:46:18,697 INFO L413 NwaCegarLoop]: 33 mSDtfsCounter, 75 mSDsluCounter, 119 mSDsCounter, 0 mSdLazyCounter, 197 mSolverCounterSat, 10 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 75 SdHoareTripleChecker+Valid, 152 SdHoareTripleChecker+Invalid, 207 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 10 IncrementalHoareTripleChecker+Valid, 197 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-10-16 10:46:18,697 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [75 Valid, 152 Invalid, 207 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [10 Valid, 197 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-10-16 10:46:18,698 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 224 states. [2022-10-16 10:46:18,716 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 224 to 221. [2022-10-16 10:46:18,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 221 states, 212 states have (on average 1.1415094339622642) internal successors, (242), 220 states have internal predecessors, (242), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:46:18,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 221 states to 221 states and 242 transitions. [2022-10-16 10:46:18,718 INFO L78 Accepts]: Start accepts. Automaton has 221 states and 242 transitions. Word has length 49 [2022-10-16 10:46:18,718 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:46:18,718 INFO L495 AbstractCegarLoop]: Abstraction has 221 states and 242 transitions. [2022-10-16 10:46:18,719 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 7 states have (on average 8.571428571428571) internal successors, (60), 8 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:46:18,719 INFO L276 IsEmpty]: Start isEmpty. Operand 221 states and 242 transitions. [2022-10-16 10:46:18,719 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2022-10-16 10:46:18,719 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:46:18,719 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:46:18,754 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Forceful destruction successful, exit code 0 [2022-10-16 10:46:18,921 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable29,24 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:46:18,921 INFO L420 AbstractCegarLoop]: === Iteration 31 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:46:18,922 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:46:18,922 INFO L85 PathProgramCache]: Analyzing trace with hash -519870877, now seen corresponding path program 3 times [2022-10-16 10:46:18,922 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:46:18,922 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [95100262] [2022-10-16 10:46:18,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:46:18,923 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:46:18,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:46:19,183 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 11 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:46:19,183 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:46:19,183 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [95100262] [2022-10-16 10:46:19,184 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [95100262] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-16 10:46:19,184 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [898013790] [2022-10-16 10:46:19,184 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-10-16 10:46:19,184 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:46:19,184 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-10-16 10:46:19,185 INFO L229 MonitoredProcess]: Starting monitored process 25 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-16 10:46:19,203 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2022-10-16 10:46:19,305 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2022-10-16 10:46:19,306 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-16 10:46:19,307 INFO L263 TraceCheckSpWp]: Trace formula consists of 186 conjuncts, 12 conjunts are in the unsatisfiable core [2022-10-16 10:46:19,308 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-16 10:46:19,545 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 22 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:46:19,545 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-16 10:46:19,749 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 22 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:46:19,749 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [898013790] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-16 10:46:19,749 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-16 10:46:19,749 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 22 [2022-10-16 10:46:19,750 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1744124669] [2022-10-16 10:46:19,750 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-16 10:46:19,750 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 22 states [2022-10-16 10:46:19,750 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:46:19,751 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2022-10-16 10:46:19,751 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=82, Invalid=380, Unknown=0, NotChecked=0, Total=462 [2022-10-16 10:46:19,751 INFO L87 Difference]: Start difference. First operand 221 states and 242 transitions. Second operand has 22 states, 22 states have (on average 4.136363636363637) internal successors, (91), 22 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:46:20,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:46:20,496 INFO L93 Difference]: Finished difference Result 395 states and 426 transitions. [2022-10-16 10:46:20,497 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2022-10-16 10:46:20,497 INFO L78 Accepts]: Start accepts. Automaton has has 22 states, 22 states have (on average 4.136363636363637) internal successors, (91), 22 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 49 [2022-10-16 10:46:20,497 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:46:20,502 INFO L225 Difference]: With dead ends: 395 [2022-10-16 10:46:20,503 INFO L226 Difference]: Without dead ends: 312 [2022-10-16 10:46:20,503 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 122 GetRequests, 80 SyntacticMatches, 9 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 402 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=224, Invalid=966, Unknown=0, NotChecked=0, Total=1190 [2022-10-16 10:46:20,504 INFO L413 NwaCegarLoop]: 27 mSDtfsCounter, 290 mSDsluCounter, 296 mSDsCounter, 0 mSdLazyCounter, 625 mSolverCounterSat, 35 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 290 SdHoareTripleChecker+Valid, 323 SdHoareTripleChecker+Invalid, 660 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 35 IncrementalHoareTripleChecker+Valid, 625 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-10-16 10:46:20,504 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [290 Valid, 323 Invalid, 660 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [35 Valid, 625 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2022-10-16 10:46:20,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 312 states. [2022-10-16 10:46:20,537 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 312 to 243. [2022-10-16 10:46:20,538 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 243 states, 234 states have (on average 1.1324786324786325) internal successors, (265), 242 states have internal predecessors, (265), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:46:20,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 243 states to 243 states and 265 transitions. [2022-10-16 10:46:20,539 INFO L78 Accepts]: Start accepts. Automaton has 243 states and 265 transitions. Word has length 49 [2022-10-16 10:46:20,539 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:46:20,539 INFO L495 AbstractCegarLoop]: Abstraction has 243 states and 265 transitions. [2022-10-16 10:46:20,539 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 22 states, 22 states have (on average 4.136363636363637) internal successors, (91), 22 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:46:20,540 INFO L276 IsEmpty]: Start isEmpty. Operand 243 states and 265 transitions. [2022-10-16 10:46:20,540 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2022-10-16 10:46:20,540 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:46:20,540 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:46:20,576 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Forceful destruction successful, exit code 0 [2022-10-16 10:46:20,755 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable30,25 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:46:20,756 INFO L420 AbstractCegarLoop]: === Iteration 32 === Targeting ULTIMATE.startErr18ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:46:20,756 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:46:20,757 INFO L85 PathProgramCache]: Analyzing trace with hash 769017339, now seen corresponding path program 2 times [2022-10-16 10:46:20,757 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:46:20,757 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1815201849] [2022-10-16 10:46:20,758 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:46:20,758 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:46:20,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:46:21,877 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2022-10-16 10:46:21,877 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:46:21,877 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1815201849] [2022-10-16 10:46:21,880 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1815201849] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-16 10:46:21,880 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [136730432] [2022-10-16 10:46:21,881 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-10-16 10:46:21,881 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:46:21,881 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-10-16 10:46:21,884 INFO L229 MonitoredProcess]: Starting monitored process 26 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-16 10:46:21,902 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2022-10-16 10:46:22,009 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-10-16 10:46:22,009 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-16 10:46:22,011 INFO L263 TraceCheckSpWp]: Trace formula consists of 189 conjuncts, 38 conjunts are in the unsatisfiable core [2022-10-16 10:46:22,014 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-16 10:46:22,699 INFO L356 Elim1Store]: treesize reduction 252, result has 37.8 percent of original size [2022-10-16 10:46:22,700 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 6 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 8 new quantified variables, introduced 19 case distinctions, treesize of input 226 treesize of output 790 [2022-10-16 10:46:22,756 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 15 [2022-10-16 10:46:22,833 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 33 [2022-10-16 10:46:22,926 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 19 [2022-10-16 10:46:23,107 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 19 [2022-10-16 10:46:26,906 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 34 [2022-10-16 10:46:26,989 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 3 [2022-10-16 10:46:27,041 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 34 [2022-10-16 10:46:27,191 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 3 [2022-10-16 10:46:27,309 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 5 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 5 new quantified variables, introduced 0 case distinctions, treesize of input 3627 treesize of output 3667 [2022-10-16 10:46:32,404 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:32,411 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 37 [2022-10-16 10:46:32,758 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:32,764 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2022-10-16 10:46:32,863 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:32,871 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 800 treesize of output 792 [2022-10-16 10:46:33,628 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:33,636 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 29 [2022-10-16 10:46:37,256 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:46:37,258 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:46:37,260 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:46:37,269 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 113 treesize of output 66 [2022-10-16 10:46:37,276 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 7 [2022-10-16 10:46:37,317 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:46:37,318 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:46:37,319 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:37,334 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:37,336 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 2 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 225 treesize of output 254 [2022-10-16 10:46:37,446 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:46:37,447 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:46:37,449 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:46:37,463 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 102 treesize of output 57 [2022-10-16 10:46:37,471 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 7 [2022-10-16 10:46:37,680 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:46:37,681 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:46:37,683 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:37,696 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:37,698 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 1 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 367 treesize of output 290 [2022-10-16 10:46:37,838 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:37,858 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:37,989 INFO L356 Elim1Store]: treesize reduction 55, result has 32.9 percent of original size [2022-10-16 10:46:37,989 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 4 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 5 new quantified variables, introduced 9 case distinctions, treesize of input 931 treesize of output 1131 [2022-10-16 10:46:39,808 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:46:39,808 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:39,818 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:39,834 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:39,840 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 2 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 656 treesize of output 1107 [2022-10-16 10:46:39,924 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:46:39,925 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:39,934 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:39,942 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:39,945 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:39,948 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 2 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 656 treesize of output 1107 [2022-10-16 10:46:40,020 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:40,022 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:40,028 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:40,029 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:40,034 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:40,035 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:40,036 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 2 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 410 treesize of output 165 [2022-10-16 10:46:40,065 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:40,066 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:40,074 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:40,075 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:40,079 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:40,080 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:40,081 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 2 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 410 treesize of output 165 [2022-10-16 10:46:40,702 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:40,765 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:40,874 INFO L356 Elim1Store]: treesize reduction 36, result has 42.9 percent of original size [2022-10-16 10:46:40,876 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 3 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 4 new quantified variables, introduced 8 case distinctions, treesize of input 4600 treesize of output 4314 [2022-10-16 10:46:42,898 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:42,898 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:42,902 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:42,903 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:42,905 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 2 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 404 treesize of output 159 [2022-10-16 10:46:42,994 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:42,994 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:43,002 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:43,002 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:43,004 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 2 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 404 treesize of output 159 [2022-10-16 10:46:43,105 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:46:43,106 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:43,118 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:43,120 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 79 treesize of output 14 [2022-10-16 10:46:43,473 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:46:43,474 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:46:43,475 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:43,481 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 507 treesize of output 105 [2022-10-16 10:46:43,495 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-10-16 10:46:43,503 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 18 [2022-10-16 10:46:43,835 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:46:43,836 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:46:43,836 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:43,846 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 506 treesize of output 100 [2022-10-16 10:46:43,859 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 40 treesize of output 25 [2022-10-16 10:46:44,467 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:46:44,468 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:44,471 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 122 treesize of output 78 [2022-10-16 10:46:44,478 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 5 [2022-10-16 10:46:44,481 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-10-16 10:46:44,768 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:46:44,769 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:44,777 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:46:44,779 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 214 treesize of output 151 [2022-10-16 10:46:44,791 WARN L234 Elim1Store]: Array PQE input equivalent to false [2022-10-16 10:46:44,798 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-10-16 10:46:45,307 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 77 treesize of output 34 [2022-10-16 10:46:45,312 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-10-16 10:46:45,322 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-10-16 10:46:45,360 INFO L356 Elim1Store]: treesize reduction 7, result has 12.5 percent of original size [2022-10-16 10:46:45,361 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 108 treesize of output 102 [2022-10-16 10:46:45,439 WARN L855 $PredicateComparison]: unable to prove that (let ((.cse48 (= |c_ULTIMATE.start_main_~b~0#1.base| |c_ULTIMATE.start_main_~c~0#1.base|)) (.cse23 (= |c_ULTIMATE.start_main_~b~0#1.base| |c_ULTIMATE.start_main_~a~0#1.base|))) (let ((.cse0 (not .cse23)) (.cse1 (not .cse48))) (and (= 0 |c_ULTIMATE.start_main_~b~0#1.offset|) (= |c_ULTIMATE.start_main_~c~0#1.offset| 0) .cse0 (= |c_ULTIMATE.start_main_~a~0#1.offset| 0) .cse1 (let ((.cse7 (select |c_#memory_int| |c_ULTIMATE.start_main_~b~0#1.base|)) (.cse14 (select |c_#memory_int| |c_ULTIMATE.start_main_~c~0#1.base|))) (let ((.cse5 (select .cse14 |c_ULTIMATE.start_main_~c~0#1.offset|)) (.cse101 (select .cse7 |c_ULTIMATE.start_main_~c~0#1.offset|)) (.cse30 (= |c_ULTIMATE.start_main_~a~0#1.base| |c_ULTIMATE.start_main_~c~0#1.base|)) (.cse21 (select .cse7 |c_ULTIMATE.start_main_~b~0#1.offset|))) (let ((.cse12 (select |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base|)) (.cse24 (<= .cse21 1)) (.cse25 (not .cse30)) (.cse2 (<= .cse101 1)) (.cse3 (<= .cse5 0)) (.cse54 (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| .cse14) |c_ULTIMATE.start_main_~b~0#1.base| .cse14) |c_ULTIMATE.start_main_~c~0#1.base| .cse14) |c_ULTIMATE.start_main_~a~0#1.base| .cse14) |c_ULTIMATE.start_main_~b~0#1.base| .cse14) |c_ULTIMATE.start_main_~c~0#1.base| .cse14))) (or (and (or (and (or (and .cse2 .cse0 .cse3) (and (or (exists ((v_DerPreprocessor_140 (Array Int Int))) (let ((.cse4 (select v_DerPreprocessor_140 |c_ULTIMATE.start_main_~c~0#1.offset|))) (and (= .cse4 .cse5) (<= .cse4 0) (exists ((v_DerPreprocessor_138 (Array Int Int)) (v_DerPreprocessor_139 (Array Int Int))) (let ((.cse6 (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_138) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_139) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_140) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_138) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_139) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_140))) (and (= (select .cse6 |c_ULTIMATE.start_main_~a~0#1.base|) v_DerPreprocessor_138) (= .cse7 (select .cse6 |c_ULTIMATE.start_main_~b~0#1.base|)) (exists ((v_prenex_61 (Array Int Int)) (v_prenex_60 (Array Int Int)) (v_prenex_120 (Array Int Int)) (v_prenex_62 (Array Int Int)) (v_prenex_121 (Array Int Int)) (v_prenex_122 (Array Int Int)) (v_DerPreprocessor_55 (Array Int Int)) (v_DerPreprocessor_56 (Array Int Int)) (v_prenex_59 (Array Int Int))) (let ((.cse11 (store (store (store (store (store (store .cse6 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_55) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_56) |c_ULTIMATE.start_main_~c~0#1.base| .cse14) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_55) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_56) |c_ULTIMATE.start_main_~c~0#1.base| .cse14))) (let ((.cse8 (select .cse11 |c_ULTIMATE.start_main_~a~0#1.base|)) (.cse9 (select (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_59) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_60) |c_ULTIMATE.start_main_~c~0#1.base| v_prenex_122) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_59) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_60) |c_ULTIMATE.start_main_~c~0#1.base| v_prenex_122) |c_ULTIMATE.start_main_~a~0#1.base|)) (.cse10 (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_120) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_121) |c_ULTIMATE.start_main_~c~0#1.base| v_prenex_122) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_120) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_121) |c_ULTIMATE.start_main_~c~0#1.base| v_prenex_122)) (.cse13 (select (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_61) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_62) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_140) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_61) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_62) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_140) |c_ULTIMATE.start_main_~a~0#1.base|))) (and (= .cse8 .cse9) (= (select .cse10 |c_ULTIMATE.start_main_~b~0#1.base|) (select .cse11 |c_ULTIMATE.start_main_~b~0#1.base|)) (= v_prenex_59 .cse9) (= .cse12 .cse9) (= .cse8 v_DerPreprocessor_55) (= .cse9 .cse13) (= v_prenex_120 (select .cse10 |c_ULTIMATE.start_main_~a~0#1.base|)) (= v_prenex_61 .cse13) (= .cse4 (select v_prenex_122 |c_ULTIMATE.start_main_~c~0#1.offset|)))))))))))) (exists ((v_DerPreprocessor_140 (Array Int Int))) (let ((.cse15 (select v_DerPreprocessor_140 |c_ULTIMATE.start_main_~c~0#1.offset|))) (and (= .cse15 .cse5) (<= .cse15 0) (exists ((v_DerPreprocessor_138 (Array Int Int)) (v_DerPreprocessor_139 (Array Int Int))) (let ((.cse22 (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_138) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_139) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_140) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_138) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_139) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_140))) (and (exists ((v_prenex_636 (Array Int Int)) (v_prenex_637 (Array Int Int)) (v_prenex_32 (Array Int Int)) (v_prenex_31 (Array Int Int)) (v_prenex_58 (Array Int Int)) (v_prenex_57 (Array Int Int)) (v_DerPreprocessor_34 (Array Int Int)) (v_DerPreprocessor_35 (Array Int Int)) (v_DerPreprocessor_36 (Array Int Int))) (let ((.cse16 (store (store (store (store (store (store .cse22 |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_636) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_637) |c_ULTIMATE.start_main_~c~0#1.base| .cse14) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_636) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_637) |c_ULTIMATE.start_main_~c~0#1.base| .cse14))) (let ((.cse18 (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_31) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_32) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_140) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_31) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_32) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_140)) (.cse17 (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_34) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_35) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_36) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_34) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_35) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_36)) (.cse20 (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_57) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_58) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_36) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_57) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_58) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_36)) (.cse19 (select .cse16 |c_ULTIMATE.start_main_~b~0#1.base|))) (and (= .cse15 (select v_DerPreprocessor_36 |c_ULTIMATE.start_main_~c~0#1.offset|)) (= v_prenex_636 (select .cse16 |c_ULTIMATE.start_main_~a~0#1.base|)) (= (select .cse17 |c_ULTIMATE.start_main_~a~0#1.base|) v_DerPreprocessor_34) (= (select .cse18 |c_ULTIMATE.start_main_~b~0#1.base|) .cse19) (= v_prenex_31 (select .cse18 |c_ULTIMATE.start_main_~a~0#1.base|)) (= .cse19 (select .cse17 |c_ULTIMATE.start_main_~b~0#1.base|)) (= (select .cse20 |c_ULTIMATE.start_main_~a~0#1.base|) v_prenex_57) (= .cse7 (select .cse20 |c_ULTIMATE.start_main_~b~0#1.base|)) (= (select .cse19 |c_ULTIMATE.start_main_~c~0#1.offset|) .cse21))))) (= (select .cse22 |c_ULTIMATE.start_main_~a~0#1.base|) v_DerPreprocessor_138) (= .cse7 (select .cse22 |c_ULTIMATE.start_main_~b~0#1.base|))))))))) .cse23 .cse24)) .cse25) (and (exists ((v_DerPreprocessor_52 (Array Int Int)) (v_DerPreprocessor_136 (Array Int Int)) (v_DerPreprocessor_53 (Array Int Int)) (v_DerPreprocessor_134 (Array Int Int)) (v_DerPreprocessor_135 (Array Int Int)) (v_arrayElimCell_123 (Array Int Int)) (v_DerPreprocessor_25 (Array Int Int))) (let ((.cse28 (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_25) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_134) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_25) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_25) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_134) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_25) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_135) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_136) |c_ULTIMATE.start_main_~c~0#1.base| .cse14) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_135) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_136) |c_ULTIMATE.start_main_~c~0#1.base| .cse14) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_135) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_136) |c_ULTIMATE.start_main_~c~0#1.base| .cse14) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_135) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_136) |c_ULTIMATE.start_main_~c~0#1.base| .cse14))) (let ((.cse29 (store (store (store (store (store (store .cse28 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_52) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_53) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_123) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_52) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_53) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_123))) (let ((.cse27 (select (select .cse28 |c_ULTIMATE.start_main_~b~0#1.base|) |c_ULTIMATE.start_main_~b~0#1.offset|)) (.cse26 (select .cse29 |c_ULTIMATE.start_main_~b~0#1.base|))) (and (= (select .cse26 |c_ULTIMATE.start_main_~c~0#1.offset|) .cse27) (= v_DerPreprocessor_134 .cse26) (= (select v_DerPreprocessor_25 |c_ULTIMATE.start_main_~c~0#1.offset|) .cse5) (= v_DerPreprocessor_135 (select .cse28 |c_ULTIMATE.start_main_~a~0#1.base|)) (= v_DerPreprocessor_52 (select .cse29 |c_ULTIMATE.start_main_~a~0#1.base|)) (<= .cse27 1) (= .cse7 .cse26) (= .cse5 (select v_arrayElimCell_123 |c_ULTIMATE.start_main_~c~0#1.offset|))))))) .cse30 .cse3)) .cse1) (and (or (and (or (exists ((v_DerPreprocessor_121 (Array Int Int))) (let ((.cse31 (select v_DerPreprocessor_121 |c_ULTIMATE.start_main_~c~0#1.offset|))) (and (<= .cse31 0) (exists ((v_DerPreprocessor_120 (Array Int Int)) (v_DerPreprocessor_119 (Array Int Int))) (let ((.cse32 (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_119) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_120) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_121) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_119) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_120) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_121))) (and (= (select .cse32 |c_ULTIMATE.start_main_~a~0#1.base|) v_DerPreprocessor_119) (exists ((v_prenex_61 (Array Int Int)) (v_prenex_60 (Array Int Int)) (v_prenex_591 (Array Int Int)) (v_prenex_592 (Array Int Int)) (v_prenex_120 (Array Int Int)) (v_prenex_62 (Array Int Int)) (v_prenex_121 (Array Int Int)) (v_prenex_122 (Array Int Int)) (v_prenex_593 Int) (v_prenex_59 (Array Int Int))) (let ((.cse38 (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_120) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_121) |c_ULTIMATE.start_main_~c~0#1.base| v_prenex_122) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_120) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_121) |c_ULTIMATE.start_main_~c~0#1.base| v_prenex_122)) (.cse39 (store (store (store (store (store (store .cse32 |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_592) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_591) |c_ULTIMATE.start_main_~c~0#1.base| .cse14) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_592) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_591) |c_ULTIMATE.start_main_~c~0#1.base| .cse14))) (let ((.cse33 (select (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_61) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_62) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_121) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_61) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_62) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_121) |c_ULTIMATE.start_main_~a~0#1.base|)) (.cse34 (select (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_59) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_60) |c_ULTIMATE.start_main_~c~0#1.base| v_prenex_122) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_59) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_60) |c_ULTIMATE.start_main_~c~0#1.base| v_prenex_122) |c_ULTIMATE.start_main_~a~0#1.base|)) (.cse37 (select .cse39 |c_ULTIMATE.start_main_~b~0#1.base|)) (.cse35 (select .cse38 |c_ULTIMATE.start_main_~a~0#1.base|))) (and (= .cse33 .cse34) (= v_prenex_61 .cse33) (= v_prenex_59 .cse34) (= .cse34 .cse35) (= .cse12 .cse34) (let ((.cse36 (store .cse37 |c_ULTIMATE.start_main_~b~0#1.offset| v_prenex_593))) (= .cse36 (store (store .cse14 |c_ULTIMATE.start_main_~c~0#1.offset| (select .cse36 |c_ULTIMATE.start_main_~c~0#1.offset|)) |c_ULTIMATE.start_main_~b~0#1.offset| v_prenex_593))) (= (select .cse38 |c_ULTIMATE.start_main_~b~0#1.base|) .cse37) (= v_prenex_592 (select .cse39 |c_ULTIMATE.start_main_~a~0#1.base|)) (= v_prenex_120 .cse35) (= .cse31 (select v_prenex_122 |c_ULTIMATE.start_main_~c~0#1.offset|)))))) (= .cse7 (select .cse32 |c_ULTIMATE.start_main_~b~0#1.base|))))) (= .cse31 .cse5)))) (exists ((v_DerPreprocessor_121 (Array Int Int))) (let ((.cse44 (select v_DerPreprocessor_121 |c_ULTIMATE.start_main_~c~0#1.offset|))) (and (exists ((v_DerPreprocessor_120 (Array Int Int)) (v_DerPreprocessor_119 (Array Int Int))) (let ((.cse40 (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_119) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_120) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_121) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_119) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_120) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_121))) (and (= (select .cse40 |c_ULTIMATE.start_main_~a~0#1.base|) v_DerPreprocessor_119) (= .cse7 (select .cse40 |c_ULTIMATE.start_main_~b~0#1.base|)) (exists ((v_DerPreprocessor_62 (Array Int Int)) (v_prenex_32 (Array Int Int)) (v_prenex_31 (Array Int Int)) (v_DerPreprocessor_61 (Array Int Int)) (v_prenex_58 (Array Int Int)) (v_prenex_57 (Array Int Int)) (v_DerPreprocessor_34 (Array Int Int)) (v_DerPreprocessor_51 Int) (v_DerPreprocessor_35 (Array Int Int)) (v_DerPreprocessor_36 (Array Int Int))) (let ((.cse46 (store (store (store (store (store (store .cse40 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_61) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_62) |c_ULTIMATE.start_main_~c~0#1.base| .cse14) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_61) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_62) |c_ULTIMATE.start_main_~c~0#1.base| .cse14))) (let ((.cse43 (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_34) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_35) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_36) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_34) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_35) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_36)) (.cse42 (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_31) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_32) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_121) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_31) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_32) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_121)) (.cse41 (select .cse46 |c_ULTIMATE.start_main_~b~0#1.base|)) (.cse45 (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_57) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_58) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_36) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_57) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_58) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_36))) (and (= (select .cse41 |c_ULTIMATE.start_main_~c~0#1.offset|) .cse21) (= (select .cse42 |c_ULTIMATE.start_main_~b~0#1.base|) .cse41) (= (select .cse43 |c_ULTIMATE.start_main_~a~0#1.base|) v_DerPreprocessor_34) (= .cse44 (select v_DerPreprocessor_36 |c_ULTIMATE.start_main_~c~0#1.offset|)) (= .cse41 (select .cse43 |c_ULTIMATE.start_main_~b~0#1.base|)) (= v_prenex_31 (select .cse42 |c_ULTIMATE.start_main_~a~0#1.base|)) (= (select .cse45 |c_ULTIMATE.start_main_~a~0#1.base|) v_prenex_57) (= v_DerPreprocessor_61 (select .cse46 |c_ULTIMATE.start_main_~a~0#1.base|)) (let ((.cse47 (store .cse41 |c_ULTIMATE.start_main_~b~0#1.offset| v_DerPreprocessor_51))) (= (store (store .cse14 |c_ULTIMATE.start_main_~c~0#1.offset| (select .cse47 |c_ULTIMATE.start_main_~c~0#1.offset|)) |c_ULTIMATE.start_main_~b~0#1.offset| v_DerPreprocessor_51) .cse47)) (= .cse7 (select .cse45 |c_ULTIMATE.start_main_~b~0#1.base|))))))))) (<= .cse44 0) (= .cse44 .cse5))))) .cse23 .cse24) (and .cse48 .cse3)) .cse25) (and .cse48 (let ((.cse49 (exists ((v_DerPreprocessor_43 Int)) (= (select (store .cse14 |c_ULTIMATE.start_main_~b~0#1.offset| v_DerPreprocessor_43) |c_ULTIMATE.start_main_~c~0#1.offset|) (select .cse14 |c_ULTIMATE.start_main_~b~0#1.offset|))))) (or (and .cse23 (or (and .cse49 (exists ((v_DerPreprocessor_128 (Array Int Int)) (v_DerPreprocessor_45 Int) (v_arrayElimCell_137 (Array Int Int)) (v_DerPreprocessor_39 Int) (v_DerPreprocessor_130 (Array Int Int)) (v_prenex_433 (Array Int Int)) (v_prenex_434 (Array Int Int)) (v_DerPreprocessor_129 (Array Int Int))) (let ((.cse52 (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_128) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_129) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_130) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_128) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_129) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_130) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_128) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_129) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_130) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_128) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_129) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_130) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_128) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_129) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_130) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_128) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_129) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_130) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_128) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_129) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_130) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_128) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_129) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_130))) (let ((.cse50 (select v_DerPreprocessor_130 |c_ULTIMATE.start_main_~c~0#1.offset|)) (.cse51 (store (store (store (store (store (store .cse52 |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_434) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_433) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_137) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_434) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_433) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_137))) (and (= (select (store .cse14 |c_ULTIMATE.start_main_~b~0#1.offset| v_DerPreprocessor_39) |c_ULTIMATE.start_main_~c~0#1.offset|) (select v_arrayElimCell_137 |c_ULTIMATE.start_main_~b~0#1.offset|)) (<= .cse50 0) (= (select v_arrayElimCell_137 |c_ULTIMATE.start_main_~c~0#1.offset|) .cse50) (= (select .cse51 |c_ULTIMATE.start_main_~b~0#1.base|) v_prenex_433) (= v_DerPreprocessor_128 (select .cse52 |c_ULTIMATE.start_main_~a~0#1.base|)) (let ((.cse53 (store .cse14 |c_ULTIMATE.start_main_~b~0#1.offset| v_DerPreprocessor_45))) (= (store (store v_arrayElimCell_137 |c_ULTIMATE.start_main_~c~0#1.offset| (select .cse53 |c_ULTIMATE.start_main_~c~0#1.offset|)) |c_ULTIMATE.start_main_~b~0#1.offset| v_DerPreprocessor_45) .cse53)) (= (select .cse52 |c_ULTIMATE.start_main_~b~0#1.base|) v_DerPreprocessor_129) (= .cse5 .cse50) (= (select .cse51 |c_ULTIMATE.start_main_~a~0#1.base|) v_prenex_434)))))) (and (exists ((v_DerPreprocessor_46 Int) (v_DerPreprocessor_47 Int) (v_arrayElimCell_137 (Array Int Int)) (v_DerPreprocessor_132 (Array Int Int)) (v_DerPreprocessor_133 (Array Int Int)) (v_DerPreprocessor_131 (Array Int Int)) (v_prenex_433 (Array Int Int)) (v_prenex_434 (Array Int Int))) (let ((.cse56 (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_131) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_132) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_133) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_131) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_132) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_133) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_131) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_132) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_133) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_131) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_132) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_133))) (let ((.cse55 (select v_DerPreprocessor_133 |c_ULTIMATE.start_main_~c~0#1.offset|)) (.cse57 (store (store (store (store (store (store .cse56 |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_434) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_433) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_137) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_434) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_433) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_137))) (and (<= .cse55 0) (= .cse5 .cse55) (= v_DerPreprocessor_132 (select .cse56 |c_ULTIMATE.start_main_~b~0#1.base|)) (= (select .cse56 |c_ULTIMATE.start_main_~a~0#1.base|) v_DerPreprocessor_131) (= (select v_arrayElimCell_137 |c_ULTIMATE.start_main_~c~0#1.offset|) .cse55) (= (select .cse57 |c_ULTIMATE.start_main_~b~0#1.base|) v_prenex_433) (= (select .cse57 |c_ULTIMATE.start_main_~a~0#1.base|) v_prenex_434) (= v_DerPreprocessor_46 (select (store (store v_arrayElimCell_137 |c_ULTIMATE.start_main_~c~0#1.offset| v_DerPreprocessor_46) |c_ULTIMATE.start_main_~b~0#1.offset| v_DerPreprocessor_47) |c_ULTIMATE.start_main_~c~0#1.offset|)))))) (exists ((v_DerPreprocessor_91 (Array Int Int)) (v_DerPreprocessor_90 (Array Int Int)) (v_DerPreprocessor_89 (Array Int Int))) (let ((.cse59 (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_89) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_90) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_91) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_89) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_90) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_91) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_89) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_90) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_91) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_89) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_90) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_91))) (let ((.cse58 (select .cse59 |c_ULTIMATE.start_main_~b~0#1.base|))) (and (= v_DerPreprocessor_90 .cse58) (= .cse14 .cse58) (= (select .cse59 |c_ULTIMATE.start_main_~a~0#1.base|) v_DerPreprocessor_89)))))))) (and .cse30 (or (and .cse49 (exists ((v_DerPreprocessor_127 (Array Int Int)) (v_DerPreprocessor_125 (Array Int Int)) (v_DerPreprocessor_126 (Array Int Int)) (v_DerPreprocessor_45 Int) (v_arrayElimCell_137 (Array Int Int)) (v_DerPreprocessor_39 Int) (v_prenex_433 (Array Int Int)) (v_prenex_434 (Array Int Int))) (let ((.cse62 (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_125) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_126) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_127) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_125) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_126) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_127) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_125) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_126) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_127) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_125) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_126) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_127) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_125) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_126) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_127) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_125) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_126) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_127) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_125) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_126) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_127) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_125) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_126) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_127))) (let ((.cse60 (store (store (store (store (store (store .cse62 |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_434) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_433) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_137) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_434) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_433) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_137)) (.cse61 (select v_DerPreprocessor_127 |c_ULTIMATE.start_main_~c~0#1.offset|))) (and (= (select (store .cse14 |c_ULTIMATE.start_main_~b~0#1.offset| v_DerPreprocessor_39) |c_ULTIMATE.start_main_~c~0#1.offset|) (select v_arrayElimCell_137 |c_ULTIMATE.start_main_~b~0#1.offset|)) (= (select .cse60 |c_ULTIMATE.start_main_~b~0#1.base|) v_prenex_433) (= v_prenex_434 (select .cse60 |c_ULTIMATE.start_main_~a~0#1.base|)) (<= .cse61 0) (= v_DerPreprocessor_125 (select .cse62 |c_ULTIMATE.start_main_~a~0#1.base|)) (= (select v_arrayElimCell_137 |c_ULTIMATE.start_main_~c~0#1.offset|) .cse61) (let ((.cse63 (store .cse14 |c_ULTIMATE.start_main_~b~0#1.offset| v_DerPreprocessor_45))) (= (store (store v_arrayElimCell_137 |c_ULTIMATE.start_main_~c~0#1.offset| (select .cse63 |c_ULTIMATE.start_main_~c~0#1.offset|)) |c_ULTIMATE.start_main_~b~0#1.offset| v_DerPreprocessor_45) .cse63)) (= .cse61 .cse5) (= (select .cse62 |c_ULTIMATE.start_main_~b~0#1.base|) v_DerPreprocessor_126)))))) (and (exists ((v_DerPreprocessor_46 Int) (v_DerPreprocessor_47 Int) (v_DerPreprocessor_123 (Array Int Int)) (v_arrayElimCell_137 (Array Int Int)) (v_DerPreprocessor_124 (Array Int Int)) (v_DerPreprocessor_122 (Array Int Int)) (v_prenex_433 (Array Int Int)) (v_prenex_434 (Array Int Int))) (let ((.cse66 (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_122) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_123) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_124) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_122) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_123) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_124) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_122) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_123) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_124) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_122) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_123) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_124))) (let ((.cse65 (store (store (store (store (store (store .cse66 |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_434) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_433) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_137) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_434) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_433) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_137)) (.cse64 (select v_DerPreprocessor_124 |c_ULTIMATE.start_main_~c~0#1.offset|))) (and (= .cse64 .cse5) (= (select v_arrayElimCell_137 |c_ULTIMATE.start_main_~c~0#1.offset|) .cse64) (= (select .cse65 |c_ULTIMATE.start_main_~b~0#1.base|) v_prenex_433) (= v_prenex_434 (select .cse65 |c_ULTIMATE.start_main_~a~0#1.base|)) (<= .cse64 0) (= (select .cse66 |c_ULTIMATE.start_main_~b~0#1.base|) v_DerPreprocessor_123) (= (select .cse66 |c_ULTIMATE.start_main_~a~0#1.base|) v_DerPreprocessor_122) (= v_DerPreprocessor_46 (select (store (store v_arrayElimCell_137 |c_ULTIMATE.start_main_~c~0#1.offset| v_DerPreprocessor_46) |c_ULTIMATE.start_main_~b~0#1.offset| v_DerPreprocessor_47) |c_ULTIMATE.start_main_~c~0#1.offset|)))))) (exists ((v_DerPreprocessor_92 (Array Int Int)) (v_DerPreprocessor_93 (Array Int Int)) (v_DerPreprocessor_94 (Array Int Int))) (let ((.cse67 (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_92) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_93) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_94) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_92) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_93) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_94) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_92) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_93) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_94) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_92) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_93) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_94))) (let ((.cse68 (select .cse67 |c_ULTIMATE.start_main_~b~0#1.base|))) (and (= v_DerPreprocessor_92 (select .cse67 |c_ULTIMATE.start_main_~a~0#1.base|)) (= .cse14 .cse68) (= v_DerPreprocessor_93 .cse68))))))))))) (and (let ((.cse70 (exists ((v_DerPreprocessor_76 (Array Int Int)) (v_DerPreprocessor_77 (Array Int Int)) (v_DerPreprocessor_78 (Array Int Int))) (let ((.cse106 (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_76) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_77) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_78) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_76) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_77) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_78) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_76) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_77) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_78) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_76) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_77) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_78))) (let ((.cse107 (select .cse106 |c_ULTIMATE.start_main_~a~0#1.base|))) (and (= (select .cse106 |c_ULTIMATE.start_main_~b~0#1.base|) v_DerPreprocessor_77) (= .cse107 v_DerPreprocessor_76) (= .cse14 .cse107)))))) (.cse75 (exists ((v_DerPreprocessor_86 (Array Int Int)) (v_DerPreprocessor_87 (Array Int Int)) (v_DerPreprocessor_88 (Array Int Int))) (let ((.cse105 (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_86) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_87) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_88) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_86) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_87) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_88) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_86) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_87) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_88) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_86) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_87) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_88))) (and (= v_DerPreprocessor_86 (select .cse105 |c_ULTIMATE.start_main_~a~0#1.base|)) (= (select .cse105 |c_ULTIMATE.start_main_~b~0#1.base|) v_DerPreprocessor_87))))) (.cse84 (exists ((v_DerPreprocessor_70 (Array Int Int)) (v_DerPreprocessor_71 (Array Int Int)) (v_DerPreprocessor_72 (Array Int Int))) (let ((.cse103 (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_70) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_71) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_72) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_70) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_71) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_72) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_70) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_71) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_72) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_70) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_71) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_72))) (let ((.cse104 (select .cse103 |c_ULTIMATE.start_main_~a~0#1.base|))) (and (= v_DerPreprocessor_71 (select .cse103 |c_ULTIMATE.start_main_~b~0#1.base|)) (= v_DerPreprocessor_70 .cse104) (= .cse14 .cse104)))))) (.cse85 (exists ((v_DerPreprocessor_80 (Array Int Int)) (v_DerPreprocessor_81 (Array Int Int)) (v_DerPreprocessor_79 (Array Int Int))) (let ((.cse102 (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_79) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_80) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_81) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_79) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_80) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_81) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_79) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_80) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_81) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_79) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_80) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_81))) (and (= v_DerPreprocessor_79 (select .cse102 |c_ULTIMATE.start_main_~a~0#1.base|)) (= v_DerPreprocessor_80 (select .cse102 |c_ULTIMATE.start_main_~b~0#1.base|)))))) (.cse69 (exists ((v_DerPreprocessor_85 (Array Int Int))) (= .cse5 (select (select (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_85) |c_ULTIMATE.start_main_~b~0#1.base| .cse7) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_85) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_85) |c_ULTIMATE.start_main_~b~0#1.base| .cse7) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_85) |c_ULTIMATE.start_main_~a~0#1.base|) |c_ULTIMATE.start_main_~c~0#1.offset|))))) (or (and .cse2 .cse69 .cse0 .cse3) (and .cse70 .cse48 (exists ((v_DerPreprocessor_109 (Array Int Int)) (v_prenex_378 (Array Int Int)) (v_prenex_379 (Array Int Int)) (v_DerPreprocessor_107 (Array Int Int)) (v_DerPreprocessor_108 (Array Int Int))) (let ((.cse71 (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_107) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_108) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_109) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_107) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_108) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_109) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_107) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_108) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_109) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_107) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_108) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_109))) (let ((.cse72 (select .cse71 |c_ULTIMATE.start_main_~b~0#1.base|))) (let ((.cse74 (store (store (store (store (store (store .cse71 |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_378) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_379) |c_ULTIMATE.start_main_~c~0#1.base| .cse72) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_378) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_379) |c_ULTIMATE.start_main_~c~0#1.base| .cse72))) (let ((.cse73 (select .cse74 |c_ULTIMATE.start_main_~b~0#1.base|))) (and (= v_DerPreprocessor_107 (select .cse71 |c_ULTIMATE.start_main_~a~0#1.base|)) (= .cse72 v_DerPreprocessor_108) (<= (select v_DerPreprocessor_109 |c_ULTIMATE.start_main_~c~0#1.offset|) 0) (= v_prenex_379 .cse73) (= v_prenex_378 (select .cse74 |c_ULTIMATE.start_main_~a~0#1.base|)) (= .cse14 .cse73))))))) .cse75) (and (exists ((v_DerPreprocessor_112 (Array Int Int)) (v_DerPreprocessor_110 (Array Int Int)) (v_DerPreprocessor_111 (Array Int Int)) (v_DerPreprocessor_67 (Array Int Int)) (v_DerPreprocessor_68 (Array Int Int))) (let ((.cse79 (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_110) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_111) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_112) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_110) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_111) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_112) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_110) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_111) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_112) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_110) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_111) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_112) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_110) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_111) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_112) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_110) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_111) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_112) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_110) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_111) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_112) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_110) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_111) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_112))) (let ((.cse78 (select .cse79 |c_ULTIMATE.start_main_~b~0#1.base|))) (let ((.cse76 (select v_DerPreprocessor_112 |c_ULTIMATE.start_main_~c~0#1.offset|)) (.cse77 (store (store (store (store (store (store .cse79 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_67) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_68) |c_ULTIMATE.start_main_~c~0#1.base| .cse78) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_67) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_68) |c_ULTIMATE.start_main_~c~0#1.base| .cse78))) (and (= .cse76 .cse5) (= v_DerPreprocessor_67 (select .cse77 |c_ULTIMATE.start_main_~a~0#1.base|)) (<= .cse76 0) (= v_DerPreprocessor_68 (select .cse77 |c_ULTIMATE.start_main_~b~0#1.base|)) (= .cse78 v_DerPreprocessor_111) (= (select .cse79 |c_ULTIMATE.start_main_~a~0#1.base|) v_DerPreprocessor_110)))))) .cse48) (and .cse23 (or (and (exists ((v_DerPreprocessor_116 (Array Int Int)) (v_DerPreprocessor_117 (Array Int Int)) (v_prenex_378 (Array Int Int)) (v_prenex_379 (Array Int Int)) (v_DerPreprocessor_118 (Array Int Int))) (let ((.cse83 (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_116) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_117) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_118) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_116) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_117) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_118) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_116) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_117) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_118) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_116) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_117) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_118))) (let ((.cse82 (select .cse83 |c_ULTIMATE.start_main_~b~0#1.base|))) (let ((.cse81 (store (store (store (store (store (store .cse83 |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_378) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_379) |c_ULTIMATE.start_main_~c~0#1.base| .cse82) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_378) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_379) |c_ULTIMATE.start_main_~c~0#1.base| .cse82))) (let ((.cse80 (select .cse81 |c_ULTIMATE.start_main_~b~0#1.base|))) (and (= .cse80 v_prenex_379) (<= (select v_DerPreprocessor_118 |c_ULTIMATE.start_main_~c~0#1.offset|) 0) (= v_prenex_378 (select .cse81 |c_ULTIMATE.start_main_~a~0#1.base|)) (= v_DerPreprocessor_117 .cse82) (= v_DerPreprocessor_116 (select .cse83 |c_ULTIMATE.start_main_~a~0#1.base|)) (= .cse14 .cse80))))))) .cse84 .cse85) (exists ((v_DerPreprocessor_114 (Array Int Int)) (v_DerPreprocessor_115 (Array Int Int)) (v_DerPreprocessor_113 (Array Int Int)) (v_DerPreprocessor_67 (Array Int Int)) (v_DerPreprocessor_68 (Array Int Int))) (let ((.cse89 (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_113) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_114) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_115) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_113) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_114) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_115) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_113) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_114) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_115) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_113) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_114) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_115) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_113) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_114) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_115) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_113) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_114) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_115) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_113) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_114) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_115) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_113) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_114) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_115))) (let ((.cse87 (select .cse89 |c_ULTIMATE.start_main_~b~0#1.base|))) (let ((.cse86 (select v_DerPreprocessor_115 |c_ULTIMATE.start_main_~c~0#1.offset|)) (.cse88 (store (store (store (store (store (store .cse89 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_67) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_68) |c_ULTIMATE.start_main_~c~0#1.base| .cse87) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_67) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_68) |c_ULTIMATE.start_main_~c~0#1.base| .cse87))) (and (= .cse5 .cse86) (= v_DerPreprocessor_114 .cse87) (<= .cse86 0) (= (select .cse88 |c_ULTIMATE.start_main_~a~0#1.base|) v_DerPreprocessor_67) (= v_DerPreprocessor_113 (select .cse89 |c_ULTIMATE.start_main_~a~0#1.base|)) (= v_DerPreprocessor_68 (select .cse88 |c_ULTIMATE.start_main_~b~0#1.base|))))))))) (and .cse48 (or (and .cse70 .cse75 (exists ((v_DerPreprocessor_103 (Array Int Int)) (v_DerPreprocessor_101 (Array Int Int)) (v_DerPreprocessor_102 (Array Int Int)) (v_arrayElimCell_131 (Array Int Int)) (v_prenex_378 (Array Int Int)) (v_prenex_379 (Array Int Int))) (let ((.cse92 (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_101) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_102) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_103) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_101) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_102) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_103) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_101) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_102) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_103) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_101) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_102) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_103))) (let ((.cse93 (store (store (store (store (store (store .cse92 |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_378) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_379) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_131) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_378) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_379) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_131))) (let ((.cse90 (select v_DerPreprocessor_103 |c_ULTIMATE.start_main_~c~0#1.offset|)) (.cse91 (select .cse93 |c_ULTIMATE.start_main_~b~0#1.base|))) (and (= .cse5 .cse90) (= .cse91 .cse14) (= v_DerPreprocessor_101 (select .cse92 |c_ULTIMATE.start_main_~a~0#1.base|)) (= v_DerPreprocessor_102 (select .cse92 |c_ULTIMATE.start_main_~b~0#1.base|)) (<= .cse90 0) (= .cse91 v_prenex_379) (= (select .cse93 |c_ULTIMATE.start_main_~a~0#1.base|) v_prenex_378))))))) (exists ((v_DerPreprocessor_98 (Array Int Int)) (v_DerPreprocessor_100 (Array Int Int)) (v_arrayElimCell_131 (Array Int Int)) (v_DerPreprocessor_99 (Array Int Int)) (v_DerPreprocessor_67 (Array Int Int)) (v_DerPreprocessor_68 (Array Int Int))) (let ((.cse96 (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_98) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_99) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_100) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_98) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_99) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_100) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_98) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_99) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_100) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_98) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_99) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_100) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_98) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_99) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_100) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_98) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_99) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_100) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_98) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_99) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_100) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_98) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_99) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_100))) (let ((.cse95 (select v_DerPreprocessor_100 |c_ULTIMATE.start_main_~c~0#1.offset|)) (.cse94 (store (store (store (store (store (store .cse96 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_67) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_68) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_131) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_67) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_68) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_131))) (and (= v_DerPreprocessor_68 (select .cse94 |c_ULTIMATE.start_main_~b~0#1.base|)) (= .cse5 .cse95) (= v_DerPreprocessor_99 (select .cse96 |c_ULTIMATE.start_main_~b~0#1.base|)) (<= .cse95 0) (= (select v_arrayElimCell_131 |c_ULTIMATE.start_main_~c~0#1.offset|) .cse95) (= v_DerPreprocessor_98 (select .cse96 |c_ULTIMATE.start_main_~a~0#1.base|)) (= v_DerPreprocessor_67 (select .cse94 |c_ULTIMATE.start_main_~a~0#1.base|)))))) (and .cse84 (exists ((v_DerPreprocessor_105 (Array Int Int)) (v_DerPreprocessor_106 (Array Int Int)) (v_DerPreprocessor_104 (Array Int Int)) (v_arrayElimCell_131 (Array Int Int)) (v_prenex_378 (Array Int Int)) (v_prenex_379 (Array Int Int))) (let ((.cse99 (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_104) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_105) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_106) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_104) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_105) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_106) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_104) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_105) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_106) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_104) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_105) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_106))) (let ((.cse97 (store (store (store (store (store (store .cse99 |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_378) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_379) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_131) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_378) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_379) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_131))) (let ((.cse100 (select .cse97 |c_ULTIMATE.start_main_~b~0#1.base|)) (.cse98 (select v_DerPreprocessor_106 |c_ULTIMATE.start_main_~c~0#1.offset|))) (and (= v_prenex_378 (select .cse97 |c_ULTIMATE.start_main_~a~0#1.base|)) (= .cse5 .cse98) (= v_DerPreprocessor_104 (select .cse99 |c_ULTIMATE.start_main_~a~0#1.base|)) (= .cse14 .cse100) (= v_prenex_379 .cse100) (<= .cse98 0) (= v_DerPreprocessor_105 (select .cse99 |c_ULTIMATE.start_main_~b~0#1.base|))))))) .cse85))) (and (= .cse5 .cse101) .cse69 .cse1 .cse3))) .cse30))))) (= |c_ULTIMATE.start_main_~i~0#1| 1)))) is different from true [2022-10-16 10:46:45,803 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:46:45,804 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 32 [2022-10-16 10:46:46,048 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:46:46,050 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 30 [2022-10-16 10:46:46,308 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:46:46,308 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 32 [2022-10-16 10:46:46,540 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:46:46,541 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 32 [2022-10-16 10:46:46,750 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 13 [2022-10-16 10:46:46,783 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 2 not checked. [2022-10-16 10:46:46,783 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-16 10:46:49,130 WARN L833 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_112| Int)) (or (forall ((v_ArrVal_1643 Int)) (< (let ((.cse0 (store (select |c_#memory_int| |c_ULTIMATE.start_main_~b~0#1.base|) (+ (* 8 |v_ULTIMATE.start_main_~i~0#1_112|) |c_ULTIMATE.start_main_~b~0#1.offset|) v_ArrVal_1643))) (+ (select (select (store |c_#memory_int| |c_ULTIMATE.start_main_~b~0#1.base| .cse0) |c_ULTIMATE.start_main_~c~0#1.base|) |c_ULTIMATE.start_main_~c~0#1.offset|) (select .cse0 |c_ULTIMATE.start_main_~b~0#1.offset|))) 9223372036854775808)) (not (<= (+ |c_ULTIMATE.start_main_#t~post10#1| 1) |v_ULTIMATE.start_main_~i~0#1_112|)))) is different from false [2022-10-16 10:46:50,303 WARN L833 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_112| Int) (v_ArrVal_1643 Int)) (or (< (let ((.cse0 (store (select |c_#memory_int| |c_ULTIMATE.start_main_~b~0#1.base|) (+ (* 8 |v_ULTIMATE.start_main_~i~0#1_112|) |c_ULTIMATE.start_main_~b~0#1.offset|) v_ArrVal_1643))) (+ (select (select (store |c_#memory_int| |c_ULTIMATE.start_main_~b~0#1.base| .cse0) |c_ULTIMATE.start_main_~c~0#1.base|) |c_ULTIMATE.start_main_~c~0#1.offset|) (select .cse0 |c_ULTIMATE.start_main_~b~0#1.offset|))) 9223372036854775808) (< |v_ULTIMATE.start_main_~i~0#1_112| (+ |c_ULTIMATE.start_main_~i~0#1| 1)))) is different from false [2022-10-16 10:46:51,316 WARN L833 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_112| Int) (v_ArrVal_1641 Int) (v_ArrVal_1643 Int)) (or (< (let ((.cse0 (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~b~0#1.base|) (+ (* 8 |c_ULTIMATE.start_main_~i~0#1|) |c_ULTIMATE.start_main_~b~0#1.offset|) v_ArrVal_1641) (+ (* 8 |v_ULTIMATE.start_main_~i~0#1_112|) |c_ULTIMATE.start_main_~b~0#1.offset|) v_ArrVal_1643))) (+ (select (select (store |c_#memory_int| |c_ULTIMATE.start_main_~b~0#1.base| .cse0) |c_ULTIMATE.start_main_~c~0#1.base|) |c_ULTIMATE.start_main_~c~0#1.offset|) (select .cse0 |c_ULTIMATE.start_main_~b~0#1.offset|))) 9223372036854775808) (< |v_ULTIMATE.start_main_~i~0#1_112| (+ |c_ULTIMATE.start_main_~i~0#1| 1)))) is different from false [2022-10-16 10:46:52,336 WARN L833 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_112| Int) (v_ArrVal_1641 Int) (v_ArrVal_1643 Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_112| 2) (< (let ((.cse0 (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~b~0#1.base|) (+ 8 |c_ULTIMATE.start_main_~b~0#1.offset|) v_ArrVal_1641) (+ (* 8 |v_ULTIMATE.start_main_~i~0#1_112|) |c_ULTIMATE.start_main_~b~0#1.offset|) v_ArrVal_1643))) (+ (select (select (store |c_#memory_int| |c_ULTIMATE.start_main_~b~0#1.base| .cse0) |c_ULTIMATE.start_main_~c~0#1.base|) |c_ULTIMATE.start_main_~c~0#1.offset|) (select .cse0 |c_ULTIMATE.start_main_~b~0#1.offset|))) 9223372036854775808))) is different from false [2022-10-16 10:46:53,802 WARN L833 $PredicateComparison]: unable to prove that (forall ((v_ArrVal_1638 Int) (|v_ULTIMATE.start_main_~i~0#1_112| Int) (v_ArrVal_1641 Int) (v_ArrVal_1643 Int)) (or (< |v_ULTIMATE.start_main_~i~0#1_112| 2) (< (let ((.cse1 (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| (store (select |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base|) (+ (* 8 |c_ULTIMATE.start_main_~i~0#1|) |c_ULTIMATE.start_main_~a~0#1.offset|) v_ArrVal_1638)))) (let ((.cse0 (store (store (select .cse1 |c_ULTIMATE.start_main_~b~0#1.base|) (+ 8 |c_ULTIMATE.start_main_~b~0#1.offset|) v_ArrVal_1641) (+ (* 8 |v_ULTIMATE.start_main_~i~0#1_112|) |c_ULTIMATE.start_main_~b~0#1.offset|) v_ArrVal_1643))) (+ (select .cse0 |c_ULTIMATE.start_main_~b~0#1.offset|) (select (select (store .cse1 |c_ULTIMATE.start_main_~b~0#1.base| .cse0) |c_ULTIMATE.start_main_~c~0#1.base|) |c_ULTIMATE.start_main_~c~0#1.offset|)))) 9223372036854775808))) is different from false [2022-10-16 10:46:55,896 WARN L833 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_115| Int)) (or (forall ((v_ArrVal_1638 Int) (|v_ULTIMATE.start_main_~i~0#1_112| Int) (v_ArrVal_1641 Int) (v_ArrVal_1643 Int)) (or (< (let ((.cse1 (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| (store (select |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base|) (+ (* 8 |v_ULTIMATE.start_main_~i~0#1_115|) |c_ULTIMATE.start_main_~a~0#1.offset|) v_ArrVal_1638)))) (let ((.cse0 (store (store (select .cse1 |c_ULTIMATE.start_main_~b~0#1.base|) (+ 8 |c_ULTIMATE.start_main_~b~0#1.offset|) v_ArrVal_1641) (+ (* 8 |v_ULTIMATE.start_main_~i~0#1_112|) |c_ULTIMATE.start_main_~b~0#1.offset|) v_ArrVal_1643))) (+ (select .cse0 |c_ULTIMATE.start_main_~b~0#1.offset|) (select (select (store .cse1 |c_ULTIMATE.start_main_~b~0#1.base| .cse0) |c_ULTIMATE.start_main_~c~0#1.base|) |c_ULTIMATE.start_main_~c~0#1.offset|)))) 9223372036854775808) (< |v_ULTIMATE.start_main_~i~0#1_112| 2))) (not (<= (+ |c_ULTIMATE.start_main_#t~post8#1| 1) |v_ULTIMATE.start_main_~i~0#1_115|)))) is different from false [2022-10-16 10:47:25,265 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 21 not checked. [2022-10-16 10:47:25,266 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [136730432] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-16 10:47:25,266 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-16 10:47:25,266 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 11, 14] total 33 [2022-10-16 10:47:25,266 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [262406783] [2022-10-16 10:47:25,266 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-16 10:47:25,267 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 34 states [2022-10-16 10:47:25,267 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:47:25,267 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2022-10-16 10:47:25,268 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=141, Invalid=570, Unknown=19, NotChecked=392, Total=1122 [2022-10-16 10:47:25,268 INFO L87 Difference]: Start difference. First operand 243 states and 265 transitions. Second operand has 34 states, 33 states have (on average 4.151515151515151) internal successors, (137), 34 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:47:25,330 WARN L855 $PredicateComparison]: unable to prove that (let ((.cse9 (select |c_#memory_int| |c_ULTIMATE.start_main_~b~0#1.base|)) (.cse16 (select |c_#memory_int| |c_ULTIMATE.start_main_~c~0#1.base|))) (let ((.cse0 (select .cse16 |c_ULTIMATE.start_main_~c~0#1.offset|)) (.cse48 (= |c_ULTIMATE.start_main_~b~0#1.base| |c_ULTIMATE.start_main_~c~0#1.base|)) (.cse24 (= |c_ULTIMATE.start_main_~b~0#1.base| |c_ULTIMATE.start_main_~a~0#1.base|)) (.cse101 (select .cse9 |c_ULTIMATE.start_main_~c~0#1.offset|)) (.cse30 (= |c_ULTIMATE.start_main_~a~0#1.base| |c_ULTIMATE.start_main_~c~0#1.base|))) (let ((.cse3 (not .cse30)) (.cse1 (<= .cse101 1)) (.cse4 (not .cse24)) (.cse5 (not .cse48)) (.cse6 (<= .cse0 0)) (.cse2 (select .cse9 |c_ULTIMATE.start_main_~b~0#1.offset|))) (and (= .cse0 0) .cse1 (= 0 |c_ULTIMATE.start_main_~b~0#1.offset|) (= .cse2 1) .cse3 (= |c_ULTIMATE.start_main_~c~0#1.offset| 0) .cse4 (= |c_ULTIMATE.start_main_~a~0#1.offset| 0) .cse5 .cse6 (let ((.cse14 (select |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base|)) (.cse25 (<= .cse2 1)) (.cse54 (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| .cse16) |c_ULTIMATE.start_main_~b~0#1.base| .cse16) |c_ULTIMATE.start_main_~c~0#1.base| .cse16) |c_ULTIMATE.start_main_~a~0#1.base| .cse16) |c_ULTIMATE.start_main_~b~0#1.base| .cse16) |c_ULTIMATE.start_main_~c~0#1.base| .cse16))) (or (and (or (and (or (and .cse1 .cse4 .cse6) (and (or (exists ((v_DerPreprocessor_140 (Array Int Int))) (let ((.cse7 (select v_DerPreprocessor_140 |c_ULTIMATE.start_main_~c~0#1.offset|))) (and (= .cse7 .cse0) (<= .cse7 0) (exists ((v_DerPreprocessor_138 (Array Int Int)) (v_DerPreprocessor_139 (Array Int Int))) (let ((.cse8 (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_138) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_139) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_140) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_138) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_139) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_140))) (and (= (select .cse8 |c_ULTIMATE.start_main_~a~0#1.base|) v_DerPreprocessor_138) (= .cse9 (select .cse8 |c_ULTIMATE.start_main_~b~0#1.base|)) (exists ((v_prenex_61 (Array Int Int)) (v_prenex_60 (Array Int Int)) (v_prenex_120 (Array Int Int)) (v_prenex_62 (Array Int Int)) (v_prenex_121 (Array Int Int)) (v_prenex_122 (Array Int Int)) (v_DerPreprocessor_55 (Array Int Int)) (v_DerPreprocessor_56 (Array Int Int)) (v_prenex_59 (Array Int Int))) (let ((.cse13 (store (store (store (store (store (store .cse8 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_55) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_56) |c_ULTIMATE.start_main_~c~0#1.base| .cse16) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_55) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_56) |c_ULTIMATE.start_main_~c~0#1.base| .cse16))) (let ((.cse10 (select .cse13 |c_ULTIMATE.start_main_~a~0#1.base|)) (.cse11 (select (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_59) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_60) |c_ULTIMATE.start_main_~c~0#1.base| v_prenex_122) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_59) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_60) |c_ULTIMATE.start_main_~c~0#1.base| v_prenex_122) |c_ULTIMATE.start_main_~a~0#1.base|)) (.cse12 (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_120) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_121) |c_ULTIMATE.start_main_~c~0#1.base| v_prenex_122) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_120) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_121) |c_ULTIMATE.start_main_~c~0#1.base| v_prenex_122)) (.cse15 (select (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_61) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_62) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_140) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_61) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_62) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_140) |c_ULTIMATE.start_main_~a~0#1.base|))) (and (= .cse10 .cse11) (= (select .cse12 |c_ULTIMATE.start_main_~b~0#1.base|) (select .cse13 |c_ULTIMATE.start_main_~b~0#1.base|)) (= v_prenex_59 .cse11) (= .cse14 .cse11) (= .cse10 v_DerPreprocessor_55) (= .cse11 .cse15) (= v_prenex_120 (select .cse12 |c_ULTIMATE.start_main_~a~0#1.base|)) (= v_prenex_61 .cse15) (= .cse7 (select v_prenex_122 |c_ULTIMATE.start_main_~c~0#1.offset|)))))))))))) (exists ((v_DerPreprocessor_140 (Array Int Int))) (let ((.cse17 (select v_DerPreprocessor_140 |c_ULTIMATE.start_main_~c~0#1.offset|))) (and (= .cse17 .cse0) (<= .cse17 0) (exists ((v_DerPreprocessor_138 (Array Int Int)) (v_DerPreprocessor_139 (Array Int Int))) (let ((.cse23 (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_138) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_139) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_140) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_138) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_139) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_140))) (and (exists ((v_prenex_636 (Array Int Int)) (v_prenex_637 (Array Int Int)) (v_prenex_32 (Array Int Int)) (v_prenex_31 (Array Int Int)) (v_prenex_58 (Array Int Int)) (v_prenex_57 (Array Int Int)) (v_DerPreprocessor_34 (Array Int Int)) (v_DerPreprocessor_35 (Array Int Int)) (v_DerPreprocessor_36 (Array Int Int))) (let ((.cse18 (store (store (store (store (store (store .cse23 |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_636) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_637) |c_ULTIMATE.start_main_~c~0#1.base| .cse16) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_636) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_637) |c_ULTIMATE.start_main_~c~0#1.base| .cse16))) (let ((.cse20 (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_31) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_32) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_140) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_31) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_32) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_140)) (.cse19 (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_34) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_35) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_36) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_34) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_35) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_36)) (.cse22 (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_57) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_58) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_36) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_57) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_58) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_36)) (.cse21 (select .cse18 |c_ULTIMATE.start_main_~b~0#1.base|))) (and (= .cse17 (select v_DerPreprocessor_36 |c_ULTIMATE.start_main_~c~0#1.offset|)) (= v_prenex_636 (select .cse18 |c_ULTIMATE.start_main_~a~0#1.base|)) (= (select .cse19 |c_ULTIMATE.start_main_~a~0#1.base|) v_DerPreprocessor_34) (= (select .cse20 |c_ULTIMATE.start_main_~b~0#1.base|) .cse21) (= v_prenex_31 (select .cse20 |c_ULTIMATE.start_main_~a~0#1.base|)) (= .cse21 (select .cse19 |c_ULTIMATE.start_main_~b~0#1.base|)) (= (select .cse22 |c_ULTIMATE.start_main_~a~0#1.base|) v_prenex_57) (= .cse9 (select .cse22 |c_ULTIMATE.start_main_~b~0#1.base|)) (= (select .cse21 |c_ULTIMATE.start_main_~c~0#1.offset|) .cse2))))) (= (select .cse23 |c_ULTIMATE.start_main_~a~0#1.base|) v_DerPreprocessor_138) (= .cse9 (select .cse23 |c_ULTIMATE.start_main_~b~0#1.base|))))))))) .cse24 .cse25)) .cse3) (and (exists ((v_DerPreprocessor_52 (Array Int Int)) (v_DerPreprocessor_136 (Array Int Int)) (v_DerPreprocessor_53 (Array Int Int)) (v_DerPreprocessor_134 (Array Int Int)) (v_DerPreprocessor_135 (Array Int Int)) (v_arrayElimCell_123 (Array Int Int)) (v_DerPreprocessor_25 (Array Int Int))) (let ((.cse28 (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_25) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_134) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_25) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_25) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_134) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_25) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_135) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_136) |c_ULTIMATE.start_main_~c~0#1.base| .cse16) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_135) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_136) |c_ULTIMATE.start_main_~c~0#1.base| .cse16) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_135) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_136) |c_ULTIMATE.start_main_~c~0#1.base| .cse16) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_135) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_136) |c_ULTIMATE.start_main_~c~0#1.base| .cse16))) (let ((.cse29 (store (store (store (store (store (store .cse28 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_52) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_53) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_123) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_52) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_53) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_123))) (let ((.cse27 (select (select .cse28 |c_ULTIMATE.start_main_~b~0#1.base|) |c_ULTIMATE.start_main_~b~0#1.offset|)) (.cse26 (select .cse29 |c_ULTIMATE.start_main_~b~0#1.base|))) (and (= (select .cse26 |c_ULTIMATE.start_main_~c~0#1.offset|) .cse27) (= v_DerPreprocessor_134 .cse26) (= (select v_DerPreprocessor_25 |c_ULTIMATE.start_main_~c~0#1.offset|) .cse0) (= v_DerPreprocessor_135 (select .cse28 |c_ULTIMATE.start_main_~a~0#1.base|)) (= v_DerPreprocessor_52 (select .cse29 |c_ULTIMATE.start_main_~a~0#1.base|)) (<= .cse27 1) (= .cse9 .cse26) (= .cse0 (select v_arrayElimCell_123 |c_ULTIMATE.start_main_~c~0#1.offset|))))))) .cse30 .cse6)) .cse5) (and (or (and (or (exists ((v_DerPreprocessor_121 (Array Int Int))) (let ((.cse31 (select v_DerPreprocessor_121 |c_ULTIMATE.start_main_~c~0#1.offset|))) (and (<= .cse31 0) (exists ((v_DerPreprocessor_120 (Array Int Int)) (v_DerPreprocessor_119 (Array Int Int))) (let ((.cse32 (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_119) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_120) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_121) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_119) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_120) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_121))) (and (= (select .cse32 |c_ULTIMATE.start_main_~a~0#1.base|) v_DerPreprocessor_119) (exists ((v_prenex_61 (Array Int Int)) (v_prenex_60 (Array Int Int)) (v_prenex_591 (Array Int Int)) (v_prenex_592 (Array Int Int)) (v_prenex_120 (Array Int Int)) (v_prenex_62 (Array Int Int)) (v_prenex_121 (Array Int Int)) (v_prenex_122 (Array Int Int)) (v_prenex_593 Int) (v_prenex_59 (Array Int Int))) (let ((.cse38 (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_120) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_121) |c_ULTIMATE.start_main_~c~0#1.base| v_prenex_122) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_120) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_121) |c_ULTIMATE.start_main_~c~0#1.base| v_prenex_122)) (.cse39 (store (store (store (store (store (store .cse32 |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_592) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_591) |c_ULTIMATE.start_main_~c~0#1.base| .cse16) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_592) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_591) |c_ULTIMATE.start_main_~c~0#1.base| .cse16))) (let ((.cse33 (select (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_61) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_62) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_121) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_61) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_62) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_121) |c_ULTIMATE.start_main_~a~0#1.base|)) (.cse34 (select (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_59) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_60) |c_ULTIMATE.start_main_~c~0#1.base| v_prenex_122) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_59) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_60) |c_ULTIMATE.start_main_~c~0#1.base| v_prenex_122) |c_ULTIMATE.start_main_~a~0#1.base|)) (.cse37 (select .cse39 |c_ULTIMATE.start_main_~b~0#1.base|)) (.cse35 (select .cse38 |c_ULTIMATE.start_main_~a~0#1.base|))) (and (= .cse33 .cse34) (= v_prenex_61 .cse33) (= v_prenex_59 .cse34) (= .cse34 .cse35) (= .cse14 .cse34) (let ((.cse36 (store .cse37 |c_ULTIMATE.start_main_~b~0#1.offset| v_prenex_593))) (= .cse36 (store (store .cse16 |c_ULTIMATE.start_main_~c~0#1.offset| (select .cse36 |c_ULTIMATE.start_main_~c~0#1.offset|)) |c_ULTIMATE.start_main_~b~0#1.offset| v_prenex_593))) (= (select .cse38 |c_ULTIMATE.start_main_~b~0#1.base|) .cse37) (= v_prenex_592 (select .cse39 |c_ULTIMATE.start_main_~a~0#1.base|)) (= v_prenex_120 .cse35) (= .cse31 (select v_prenex_122 |c_ULTIMATE.start_main_~c~0#1.offset|)))))) (= .cse9 (select .cse32 |c_ULTIMATE.start_main_~b~0#1.base|))))) (= .cse31 .cse0)))) (exists ((v_DerPreprocessor_121 (Array Int Int))) (let ((.cse44 (select v_DerPreprocessor_121 |c_ULTIMATE.start_main_~c~0#1.offset|))) (and (exists ((v_DerPreprocessor_120 (Array Int Int)) (v_DerPreprocessor_119 (Array Int Int))) (let ((.cse40 (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_119) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_120) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_121) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_119) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_120) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_121))) (and (= (select .cse40 |c_ULTIMATE.start_main_~a~0#1.base|) v_DerPreprocessor_119) (= .cse9 (select .cse40 |c_ULTIMATE.start_main_~b~0#1.base|)) (exists ((v_DerPreprocessor_62 (Array Int Int)) (v_prenex_32 (Array Int Int)) (v_prenex_31 (Array Int Int)) (v_DerPreprocessor_61 (Array Int Int)) (v_prenex_58 (Array Int Int)) (v_prenex_57 (Array Int Int)) (v_DerPreprocessor_34 (Array Int Int)) (v_DerPreprocessor_51 Int) (v_DerPreprocessor_35 (Array Int Int)) (v_DerPreprocessor_36 (Array Int Int))) (let ((.cse46 (store (store (store (store (store (store .cse40 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_61) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_62) |c_ULTIMATE.start_main_~c~0#1.base| .cse16) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_61) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_62) |c_ULTIMATE.start_main_~c~0#1.base| .cse16))) (let ((.cse43 (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_34) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_35) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_36) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_34) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_35) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_36)) (.cse42 (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_31) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_32) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_121) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_31) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_32) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_121)) (.cse41 (select .cse46 |c_ULTIMATE.start_main_~b~0#1.base|)) (.cse45 (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_57) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_58) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_36) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_57) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_58) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_36))) (and (= (select .cse41 |c_ULTIMATE.start_main_~c~0#1.offset|) .cse2) (= (select .cse42 |c_ULTIMATE.start_main_~b~0#1.base|) .cse41) (= (select .cse43 |c_ULTIMATE.start_main_~a~0#1.base|) v_DerPreprocessor_34) (= .cse44 (select v_DerPreprocessor_36 |c_ULTIMATE.start_main_~c~0#1.offset|)) (= .cse41 (select .cse43 |c_ULTIMATE.start_main_~b~0#1.base|)) (= v_prenex_31 (select .cse42 |c_ULTIMATE.start_main_~a~0#1.base|)) (= (select .cse45 |c_ULTIMATE.start_main_~a~0#1.base|) v_prenex_57) (= v_DerPreprocessor_61 (select .cse46 |c_ULTIMATE.start_main_~a~0#1.base|)) (let ((.cse47 (store .cse41 |c_ULTIMATE.start_main_~b~0#1.offset| v_DerPreprocessor_51))) (= (store (store .cse16 |c_ULTIMATE.start_main_~c~0#1.offset| (select .cse47 |c_ULTIMATE.start_main_~c~0#1.offset|)) |c_ULTIMATE.start_main_~b~0#1.offset| v_DerPreprocessor_51) .cse47)) (= .cse9 (select .cse45 |c_ULTIMATE.start_main_~b~0#1.base|))))))))) (<= .cse44 0) (= .cse44 .cse0))))) .cse24 .cse25) (and .cse48 .cse6)) .cse3) (and .cse48 (let ((.cse49 (exists ((v_DerPreprocessor_43 Int)) (= (select (store .cse16 |c_ULTIMATE.start_main_~b~0#1.offset| v_DerPreprocessor_43) |c_ULTIMATE.start_main_~c~0#1.offset|) (select .cse16 |c_ULTIMATE.start_main_~b~0#1.offset|))))) (or (and .cse24 (or (and .cse49 (exists ((v_DerPreprocessor_128 (Array Int Int)) (v_DerPreprocessor_45 Int) (v_arrayElimCell_137 (Array Int Int)) (v_DerPreprocessor_39 Int) (v_DerPreprocessor_130 (Array Int Int)) (v_prenex_433 (Array Int Int)) (v_prenex_434 (Array Int Int)) (v_DerPreprocessor_129 (Array Int Int))) (let ((.cse52 (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_128) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_129) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_130) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_128) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_129) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_130) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_128) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_129) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_130) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_128) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_129) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_130) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_128) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_129) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_130) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_128) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_129) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_130) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_128) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_129) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_130) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_128) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_129) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_130))) (let ((.cse50 (select v_DerPreprocessor_130 |c_ULTIMATE.start_main_~c~0#1.offset|)) (.cse51 (store (store (store (store (store (store .cse52 |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_434) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_433) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_137) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_434) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_433) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_137))) (and (= (select (store .cse16 |c_ULTIMATE.start_main_~b~0#1.offset| v_DerPreprocessor_39) |c_ULTIMATE.start_main_~c~0#1.offset|) (select v_arrayElimCell_137 |c_ULTIMATE.start_main_~b~0#1.offset|)) (<= .cse50 0) (= (select v_arrayElimCell_137 |c_ULTIMATE.start_main_~c~0#1.offset|) .cse50) (= (select .cse51 |c_ULTIMATE.start_main_~b~0#1.base|) v_prenex_433) (= v_DerPreprocessor_128 (select .cse52 |c_ULTIMATE.start_main_~a~0#1.base|)) (let ((.cse53 (store .cse16 |c_ULTIMATE.start_main_~b~0#1.offset| v_DerPreprocessor_45))) (= (store (store v_arrayElimCell_137 |c_ULTIMATE.start_main_~c~0#1.offset| (select .cse53 |c_ULTIMATE.start_main_~c~0#1.offset|)) |c_ULTIMATE.start_main_~b~0#1.offset| v_DerPreprocessor_45) .cse53)) (= (select .cse52 |c_ULTIMATE.start_main_~b~0#1.base|) v_DerPreprocessor_129) (= .cse0 .cse50) (= (select .cse51 |c_ULTIMATE.start_main_~a~0#1.base|) v_prenex_434)))))) (and (exists ((v_DerPreprocessor_46 Int) (v_DerPreprocessor_47 Int) (v_arrayElimCell_137 (Array Int Int)) (v_DerPreprocessor_132 (Array Int Int)) (v_DerPreprocessor_133 (Array Int Int)) (v_DerPreprocessor_131 (Array Int Int)) (v_prenex_433 (Array Int Int)) (v_prenex_434 (Array Int Int))) (let ((.cse56 (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_131) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_132) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_133) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_131) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_132) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_133) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_131) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_132) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_133) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_131) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_132) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_133))) (let ((.cse55 (select v_DerPreprocessor_133 |c_ULTIMATE.start_main_~c~0#1.offset|)) (.cse57 (store (store (store (store (store (store .cse56 |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_434) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_433) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_137) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_434) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_433) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_137))) (and (<= .cse55 0) (= .cse0 .cse55) (= v_DerPreprocessor_132 (select .cse56 |c_ULTIMATE.start_main_~b~0#1.base|)) (= (select .cse56 |c_ULTIMATE.start_main_~a~0#1.base|) v_DerPreprocessor_131) (= (select v_arrayElimCell_137 |c_ULTIMATE.start_main_~c~0#1.offset|) .cse55) (= (select .cse57 |c_ULTIMATE.start_main_~b~0#1.base|) v_prenex_433) (= (select .cse57 |c_ULTIMATE.start_main_~a~0#1.base|) v_prenex_434) (= v_DerPreprocessor_46 (select (store (store v_arrayElimCell_137 |c_ULTIMATE.start_main_~c~0#1.offset| v_DerPreprocessor_46) |c_ULTIMATE.start_main_~b~0#1.offset| v_DerPreprocessor_47) |c_ULTIMATE.start_main_~c~0#1.offset|)))))) (exists ((v_DerPreprocessor_91 (Array Int Int)) (v_DerPreprocessor_90 (Array Int Int)) (v_DerPreprocessor_89 (Array Int Int))) (let ((.cse59 (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_89) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_90) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_91) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_89) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_90) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_91) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_89) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_90) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_91) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_89) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_90) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_91))) (let ((.cse58 (select .cse59 |c_ULTIMATE.start_main_~b~0#1.base|))) (and (= v_DerPreprocessor_90 .cse58) (= .cse16 .cse58) (= (select .cse59 |c_ULTIMATE.start_main_~a~0#1.base|) v_DerPreprocessor_89)))))))) (and .cse30 (or (and .cse49 (exists ((v_DerPreprocessor_127 (Array Int Int)) (v_DerPreprocessor_125 (Array Int Int)) (v_DerPreprocessor_126 (Array Int Int)) (v_DerPreprocessor_45 Int) (v_arrayElimCell_137 (Array Int Int)) (v_DerPreprocessor_39 Int) (v_prenex_433 (Array Int Int)) (v_prenex_434 (Array Int Int))) (let ((.cse62 (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_125) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_126) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_127) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_125) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_126) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_127) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_125) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_126) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_127) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_125) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_126) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_127) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_125) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_126) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_127) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_125) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_126) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_127) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_125) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_126) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_127) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_125) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_126) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_127))) (let ((.cse60 (store (store (store (store (store (store .cse62 |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_434) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_433) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_137) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_434) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_433) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_137)) (.cse61 (select v_DerPreprocessor_127 |c_ULTIMATE.start_main_~c~0#1.offset|))) (and (= (select (store .cse16 |c_ULTIMATE.start_main_~b~0#1.offset| v_DerPreprocessor_39) |c_ULTIMATE.start_main_~c~0#1.offset|) (select v_arrayElimCell_137 |c_ULTIMATE.start_main_~b~0#1.offset|)) (= (select .cse60 |c_ULTIMATE.start_main_~b~0#1.base|) v_prenex_433) (= v_prenex_434 (select .cse60 |c_ULTIMATE.start_main_~a~0#1.base|)) (<= .cse61 0) (= v_DerPreprocessor_125 (select .cse62 |c_ULTIMATE.start_main_~a~0#1.base|)) (= (select v_arrayElimCell_137 |c_ULTIMATE.start_main_~c~0#1.offset|) .cse61) (let ((.cse63 (store .cse16 |c_ULTIMATE.start_main_~b~0#1.offset| v_DerPreprocessor_45))) (= (store (store v_arrayElimCell_137 |c_ULTIMATE.start_main_~c~0#1.offset| (select .cse63 |c_ULTIMATE.start_main_~c~0#1.offset|)) |c_ULTIMATE.start_main_~b~0#1.offset| v_DerPreprocessor_45) .cse63)) (= .cse61 .cse0) (= (select .cse62 |c_ULTIMATE.start_main_~b~0#1.base|) v_DerPreprocessor_126)))))) (and (exists ((v_DerPreprocessor_46 Int) (v_DerPreprocessor_47 Int) (v_DerPreprocessor_123 (Array Int Int)) (v_arrayElimCell_137 (Array Int Int)) (v_DerPreprocessor_124 (Array Int Int)) (v_DerPreprocessor_122 (Array Int Int)) (v_prenex_433 (Array Int Int)) (v_prenex_434 (Array Int Int))) (let ((.cse66 (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_122) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_123) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_124) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_122) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_123) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_124) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_122) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_123) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_124) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_122) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_123) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_124))) (let ((.cse65 (store (store (store (store (store (store .cse66 |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_434) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_433) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_137) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_434) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_433) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_137)) (.cse64 (select v_DerPreprocessor_124 |c_ULTIMATE.start_main_~c~0#1.offset|))) (and (= .cse64 .cse0) (= (select v_arrayElimCell_137 |c_ULTIMATE.start_main_~c~0#1.offset|) .cse64) (= (select .cse65 |c_ULTIMATE.start_main_~b~0#1.base|) v_prenex_433) (= v_prenex_434 (select .cse65 |c_ULTIMATE.start_main_~a~0#1.base|)) (<= .cse64 0) (= (select .cse66 |c_ULTIMATE.start_main_~b~0#1.base|) v_DerPreprocessor_123) (= (select .cse66 |c_ULTIMATE.start_main_~a~0#1.base|) v_DerPreprocessor_122) (= v_DerPreprocessor_46 (select (store (store v_arrayElimCell_137 |c_ULTIMATE.start_main_~c~0#1.offset| v_DerPreprocessor_46) |c_ULTIMATE.start_main_~b~0#1.offset| v_DerPreprocessor_47) |c_ULTIMATE.start_main_~c~0#1.offset|)))))) (exists ((v_DerPreprocessor_92 (Array Int Int)) (v_DerPreprocessor_93 (Array Int Int)) (v_DerPreprocessor_94 (Array Int Int))) (let ((.cse67 (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_92) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_93) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_94) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_92) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_93) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_94) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_92) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_93) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_94) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_92) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_93) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_94))) (let ((.cse68 (select .cse67 |c_ULTIMATE.start_main_~b~0#1.base|))) (and (= v_DerPreprocessor_92 (select .cse67 |c_ULTIMATE.start_main_~a~0#1.base|)) (= .cse16 .cse68) (= v_DerPreprocessor_93 .cse68))))))))))) (and (let ((.cse70 (exists ((v_DerPreprocessor_76 (Array Int Int)) (v_DerPreprocessor_77 (Array Int Int)) (v_DerPreprocessor_78 (Array Int Int))) (let ((.cse106 (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_76) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_77) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_78) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_76) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_77) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_78) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_76) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_77) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_78) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_76) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_77) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_78))) (let ((.cse107 (select .cse106 |c_ULTIMATE.start_main_~a~0#1.base|))) (and (= (select .cse106 |c_ULTIMATE.start_main_~b~0#1.base|) v_DerPreprocessor_77) (= .cse107 v_DerPreprocessor_76) (= .cse16 .cse107)))))) (.cse75 (exists ((v_DerPreprocessor_86 (Array Int Int)) (v_DerPreprocessor_87 (Array Int Int)) (v_DerPreprocessor_88 (Array Int Int))) (let ((.cse105 (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_86) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_87) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_88) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_86) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_87) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_88) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_86) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_87) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_88) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_86) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_87) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_88))) (and (= v_DerPreprocessor_86 (select .cse105 |c_ULTIMATE.start_main_~a~0#1.base|)) (= (select .cse105 |c_ULTIMATE.start_main_~b~0#1.base|) v_DerPreprocessor_87))))) (.cse84 (exists ((v_DerPreprocessor_70 (Array Int Int)) (v_DerPreprocessor_71 (Array Int Int)) (v_DerPreprocessor_72 (Array Int Int))) (let ((.cse103 (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_70) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_71) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_72) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_70) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_71) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_72) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_70) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_71) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_72) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_70) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_71) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_72))) (let ((.cse104 (select .cse103 |c_ULTIMATE.start_main_~a~0#1.base|))) (and (= v_DerPreprocessor_71 (select .cse103 |c_ULTIMATE.start_main_~b~0#1.base|)) (= v_DerPreprocessor_70 .cse104) (= .cse16 .cse104)))))) (.cse85 (exists ((v_DerPreprocessor_80 (Array Int Int)) (v_DerPreprocessor_81 (Array Int Int)) (v_DerPreprocessor_79 (Array Int Int))) (let ((.cse102 (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_79) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_80) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_81) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_79) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_80) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_81) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_79) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_80) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_81) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_79) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_80) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_81))) (and (= v_DerPreprocessor_79 (select .cse102 |c_ULTIMATE.start_main_~a~0#1.base|)) (= v_DerPreprocessor_80 (select .cse102 |c_ULTIMATE.start_main_~b~0#1.base|)))))) (.cse69 (exists ((v_DerPreprocessor_85 (Array Int Int))) (= .cse0 (select (select (store (store (store (store (store (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_85) |c_ULTIMATE.start_main_~b~0#1.base| .cse9) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_85) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_85) |c_ULTIMATE.start_main_~b~0#1.base| .cse9) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_85) |c_ULTIMATE.start_main_~a~0#1.base|) |c_ULTIMATE.start_main_~c~0#1.offset|))))) (or (and .cse1 .cse69 .cse4 .cse6) (and .cse70 .cse48 (exists ((v_DerPreprocessor_109 (Array Int Int)) (v_prenex_378 (Array Int Int)) (v_prenex_379 (Array Int Int)) (v_DerPreprocessor_107 (Array Int Int)) (v_DerPreprocessor_108 (Array Int Int))) (let ((.cse71 (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_107) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_108) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_109) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_107) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_108) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_109) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_107) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_108) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_109) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_107) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_108) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_109))) (let ((.cse72 (select .cse71 |c_ULTIMATE.start_main_~b~0#1.base|))) (let ((.cse74 (store (store (store (store (store (store .cse71 |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_378) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_379) |c_ULTIMATE.start_main_~c~0#1.base| .cse72) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_378) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_379) |c_ULTIMATE.start_main_~c~0#1.base| .cse72))) (let ((.cse73 (select .cse74 |c_ULTIMATE.start_main_~b~0#1.base|))) (and (= v_DerPreprocessor_107 (select .cse71 |c_ULTIMATE.start_main_~a~0#1.base|)) (= .cse72 v_DerPreprocessor_108) (<= (select v_DerPreprocessor_109 |c_ULTIMATE.start_main_~c~0#1.offset|) 0) (= v_prenex_379 .cse73) (= v_prenex_378 (select .cse74 |c_ULTIMATE.start_main_~a~0#1.base|)) (= .cse16 .cse73))))))) .cse75) (and (exists ((v_DerPreprocessor_112 (Array Int Int)) (v_DerPreprocessor_110 (Array Int Int)) (v_DerPreprocessor_111 (Array Int Int)) (v_DerPreprocessor_67 (Array Int Int)) (v_DerPreprocessor_68 (Array Int Int))) (let ((.cse79 (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_110) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_111) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_112) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_110) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_111) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_112) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_110) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_111) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_112) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_110) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_111) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_112) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_110) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_111) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_112) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_110) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_111) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_112) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_110) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_111) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_112) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_110) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_111) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_112))) (let ((.cse78 (select .cse79 |c_ULTIMATE.start_main_~b~0#1.base|))) (let ((.cse76 (select v_DerPreprocessor_112 |c_ULTIMATE.start_main_~c~0#1.offset|)) (.cse77 (store (store (store (store (store (store .cse79 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_67) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_68) |c_ULTIMATE.start_main_~c~0#1.base| .cse78) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_67) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_68) |c_ULTIMATE.start_main_~c~0#1.base| .cse78))) (and (= .cse76 .cse0) (= v_DerPreprocessor_67 (select .cse77 |c_ULTIMATE.start_main_~a~0#1.base|)) (<= .cse76 0) (= v_DerPreprocessor_68 (select .cse77 |c_ULTIMATE.start_main_~b~0#1.base|)) (= .cse78 v_DerPreprocessor_111) (= (select .cse79 |c_ULTIMATE.start_main_~a~0#1.base|) v_DerPreprocessor_110)))))) .cse48) (and .cse24 (or (and (exists ((v_DerPreprocessor_116 (Array Int Int)) (v_DerPreprocessor_117 (Array Int Int)) (v_prenex_378 (Array Int Int)) (v_prenex_379 (Array Int Int)) (v_DerPreprocessor_118 (Array Int Int))) (let ((.cse83 (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_116) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_117) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_118) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_116) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_117) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_118) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_116) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_117) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_118) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_116) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_117) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_118))) (let ((.cse82 (select .cse83 |c_ULTIMATE.start_main_~b~0#1.base|))) (let ((.cse81 (store (store (store (store (store (store .cse83 |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_378) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_379) |c_ULTIMATE.start_main_~c~0#1.base| .cse82) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_378) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_379) |c_ULTIMATE.start_main_~c~0#1.base| .cse82))) (let ((.cse80 (select .cse81 |c_ULTIMATE.start_main_~b~0#1.base|))) (and (= .cse80 v_prenex_379) (<= (select v_DerPreprocessor_118 |c_ULTIMATE.start_main_~c~0#1.offset|) 0) (= v_prenex_378 (select .cse81 |c_ULTIMATE.start_main_~a~0#1.base|)) (= v_DerPreprocessor_117 .cse82) (= v_DerPreprocessor_116 (select .cse83 |c_ULTIMATE.start_main_~a~0#1.base|)) (= .cse16 .cse80))))))) .cse84 .cse85) (exists ((v_DerPreprocessor_114 (Array Int Int)) (v_DerPreprocessor_115 (Array Int Int)) (v_DerPreprocessor_113 (Array Int Int)) (v_DerPreprocessor_67 (Array Int Int)) (v_DerPreprocessor_68 (Array Int Int))) (let ((.cse89 (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_113) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_114) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_115) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_113) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_114) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_115) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_113) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_114) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_115) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_113) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_114) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_115) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_113) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_114) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_115) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_113) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_114) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_115) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_113) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_114) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_115) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_113) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_114) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_115))) (let ((.cse87 (select .cse89 |c_ULTIMATE.start_main_~b~0#1.base|))) (let ((.cse86 (select v_DerPreprocessor_115 |c_ULTIMATE.start_main_~c~0#1.offset|)) (.cse88 (store (store (store (store (store (store .cse89 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_67) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_68) |c_ULTIMATE.start_main_~c~0#1.base| .cse87) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_67) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_68) |c_ULTIMATE.start_main_~c~0#1.base| .cse87))) (and (= .cse0 .cse86) (= v_DerPreprocessor_114 .cse87) (<= .cse86 0) (= (select .cse88 |c_ULTIMATE.start_main_~a~0#1.base|) v_DerPreprocessor_67) (= v_DerPreprocessor_113 (select .cse89 |c_ULTIMATE.start_main_~a~0#1.base|)) (= v_DerPreprocessor_68 (select .cse88 |c_ULTIMATE.start_main_~b~0#1.base|))))))))) (and .cse48 (or (and .cse70 .cse75 (exists ((v_DerPreprocessor_103 (Array Int Int)) (v_DerPreprocessor_101 (Array Int Int)) (v_DerPreprocessor_102 (Array Int Int)) (v_arrayElimCell_131 (Array Int Int)) (v_prenex_378 (Array Int Int)) (v_prenex_379 (Array Int Int))) (let ((.cse92 (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_101) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_102) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_103) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_101) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_102) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_103) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_101) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_102) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_103) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_101) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_102) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_103))) (let ((.cse93 (store (store (store (store (store (store .cse92 |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_378) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_379) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_131) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_378) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_379) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_131))) (let ((.cse90 (select v_DerPreprocessor_103 |c_ULTIMATE.start_main_~c~0#1.offset|)) (.cse91 (select .cse93 |c_ULTIMATE.start_main_~b~0#1.base|))) (and (= .cse0 .cse90) (= .cse91 .cse16) (= v_DerPreprocessor_101 (select .cse92 |c_ULTIMATE.start_main_~a~0#1.base|)) (= v_DerPreprocessor_102 (select .cse92 |c_ULTIMATE.start_main_~b~0#1.base|)) (<= .cse90 0) (= .cse91 v_prenex_379) (= (select .cse93 |c_ULTIMATE.start_main_~a~0#1.base|) v_prenex_378))))))) (exists ((v_DerPreprocessor_98 (Array Int Int)) (v_DerPreprocessor_100 (Array Int Int)) (v_arrayElimCell_131 (Array Int Int)) (v_DerPreprocessor_99 (Array Int Int)) (v_DerPreprocessor_67 (Array Int Int)) (v_DerPreprocessor_68 (Array Int Int))) (let ((.cse96 (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_98) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_99) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_100) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_98) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_99) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_100) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_98) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_99) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_100) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_98) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_99) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_100) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_98) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_99) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_100) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_98) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_99) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_100) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_98) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_99) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_100) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_98) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_99) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_100))) (let ((.cse95 (select v_DerPreprocessor_100 |c_ULTIMATE.start_main_~c~0#1.offset|)) (.cse94 (store (store (store (store (store (store .cse96 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_67) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_68) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_131) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_67) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_68) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_131))) (and (= v_DerPreprocessor_68 (select .cse94 |c_ULTIMATE.start_main_~b~0#1.base|)) (= .cse0 .cse95) (= v_DerPreprocessor_99 (select .cse96 |c_ULTIMATE.start_main_~b~0#1.base|)) (<= .cse95 0) (= (select v_arrayElimCell_131 |c_ULTIMATE.start_main_~c~0#1.offset|) .cse95) (= v_DerPreprocessor_98 (select .cse96 |c_ULTIMATE.start_main_~a~0#1.base|)) (= v_DerPreprocessor_67 (select .cse94 |c_ULTIMATE.start_main_~a~0#1.base|)))))) (and .cse84 (exists ((v_DerPreprocessor_105 (Array Int Int)) (v_DerPreprocessor_106 (Array Int Int)) (v_DerPreprocessor_104 (Array Int Int)) (v_arrayElimCell_131 (Array Int Int)) (v_prenex_378 (Array Int Int)) (v_prenex_379 (Array Int Int))) (let ((.cse99 (store (store (store (store (store (store (store (store (store (store (store (store .cse54 |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_104) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_105) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_106) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_104) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_105) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_106) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_104) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_105) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_106) |c_ULTIMATE.start_main_~a~0#1.base| v_DerPreprocessor_104) |c_ULTIMATE.start_main_~b~0#1.base| v_DerPreprocessor_105) |c_ULTIMATE.start_main_~c~0#1.base| v_DerPreprocessor_106))) (let ((.cse97 (store (store (store (store (store (store .cse99 |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_378) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_379) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_131) |c_ULTIMATE.start_main_~a~0#1.base| v_prenex_378) |c_ULTIMATE.start_main_~b~0#1.base| v_prenex_379) |c_ULTIMATE.start_main_~c~0#1.base| v_arrayElimCell_131))) (let ((.cse100 (select .cse97 |c_ULTIMATE.start_main_~b~0#1.base|)) (.cse98 (select v_DerPreprocessor_106 |c_ULTIMATE.start_main_~c~0#1.offset|))) (and (= v_prenex_378 (select .cse97 |c_ULTIMATE.start_main_~a~0#1.base|)) (= .cse0 .cse98) (= v_DerPreprocessor_104 (select .cse99 |c_ULTIMATE.start_main_~a~0#1.base|)) (= .cse16 .cse100) (= v_prenex_379 .cse100) (<= .cse98 0) (= v_DerPreprocessor_105 (select .cse99 |c_ULTIMATE.start_main_~b~0#1.base|))))))) .cse85))) (and (= .cse0 .cse101) .cse69 .cse5 .cse6))) .cse30))) (= |c_ULTIMATE.start_main_~i~0#1| 1))))) is different from true [2022-10-16 10:47:27,032 WARN L833 $PredicateComparison]: unable to prove that (let ((.cse0 (select |c_#memory_int| |c_ULTIMATE.start_main_~b~0#1.base|))) (and (= (select (select |c_#memory_int| |c_ULTIMATE.start_main_~c~0#1.base|) |c_ULTIMATE.start_main_~c~0#1.offset|) 0) (= 0 |c_ULTIMATE.start_main_~b~0#1.offset|) (= (select .cse0 |c_ULTIMATE.start_main_~b~0#1.offset|) 1) (not (= |c_ULTIMATE.start_main_~a~0#1.base| |c_ULTIMATE.start_main_~c~0#1.base|)) (= |c_ULTIMATE.start_main_~c~0#1.offset| 0) (not (= |c_ULTIMATE.start_main_~b~0#1.base| |c_ULTIMATE.start_main_~a~0#1.base|)) (forall ((|v_ULTIMATE.start_main_~i~0#1_112| Int) (v_ArrVal_1643 Int)) (or (< (let ((.cse1 (store .cse0 (+ (* 8 |v_ULTIMATE.start_main_~i~0#1_112|) |c_ULTIMATE.start_main_~b~0#1.offset|) v_ArrVal_1643))) (+ (select (select (store |c_#memory_int| |c_ULTIMATE.start_main_~b~0#1.base| .cse1) |c_ULTIMATE.start_main_~c~0#1.base|) |c_ULTIMATE.start_main_~c~0#1.offset|) (select .cse1 |c_ULTIMATE.start_main_~b~0#1.offset|))) 9223372036854775808) (< |v_ULTIMATE.start_main_~i~0#1_112| (+ |c_ULTIMATE.start_main_~i~0#1| 1)))) (= |c_ULTIMATE.start_main_~i~0#1| 1))) is different from false [2022-10-16 10:47:29,042 WARN L833 $PredicateComparison]: unable to prove that (let ((.cse1 (select |c_#memory_int| |c_ULTIMATE.start_main_~b~0#1.base|))) (and (forall ((|v_ULTIMATE.start_main_~i~0#1_112| Int)) (or (forall ((v_ArrVal_1643 Int)) (< (let ((.cse0 (store .cse1 (+ (* 8 |v_ULTIMATE.start_main_~i~0#1_112|) |c_ULTIMATE.start_main_~b~0#1.offset|) v_ArrVal_1643))) (+ (select (select (store |c_#memory_int| |c_ULTIMATE.start_main_~b~0#1.base| .cse0) |c_ULTIMATE.start_main_~c~0#1.base|) |c_ULTIMATE.start_main_~c~0#1.offset|) (select .cse0 |c_ULTIMATE.start_main_~b~0#1.offset|))) 9223372036854775808)) (not (<= (+ |c_ULTIMATE.start_main_#t~post10#1| 1) |v_ULTIMATE.start_main_~i~0#1_112|)))) (= (select (select |c_#memory_int| |c_ULTIMATE.start_main_~c~0#1.base|) |c_ULTIMATE.start_main_~c~0#1.offset|) 0) (= 0 |c_ULTIMATE.start_main_~b~0#1.offset|) (= (select .cse1 |c_ULTIMATE.start_main_~b~0#1.offset|) 1) (not (= |c_ULTIMATE.start_main_~a~0#1.base| |c_ULTIMATE.start_main_~c~0#1.base|)) (= |c_ULTIMATE.start_main_~c~0#1.offset| 0) (not (= |c_ULTIMATE.start_main_~b~0#1.base| |c_ULTIMATE.start_main_~a~0#1.base|)) (= |c_ULTIMATE.start_main_#t~post10#1| 1))) is different from false [2022-10-16 10:47:29,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:47:29,686 INFO L93 Difference]: Finished difference Result 327 states and 347 transitions. [2022-10-16 10:47:29,686 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2022-10-16 10:47:29,687 INFO L78 Accepts]: Start accepts. Automaton has has 34 states, 33 states have (on average 4.151515151515151) internal successors, (137), 34 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 51 [2022-10-16 10:47:29,687 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:47:29,688 INFO L225 Difference]: With dead ends: 327 [2022-10-16 10:47:29,688 INFO L226 Difference]: Without dead ends: 325 [2022-10-16 10:47:29,691 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 147 GetRequests, 87 SyntacticMatches, 12 SemanticMatches, 48 ConstructedPredicates, 10 IntricatePredicates, 0 DeprecatedPredicates, 398 ImplicationChecksByTransitivity, 42.3s TimeCoverageRelationStatistics Valid=338, Invalid=1240, Unknown=22, NotChecked=850, Total=2450 [2022-10-16 10:47:29,691 INFO L413 NwaCegarLoop]: 31 mSDtfsCounter, 412 mSDsluCounter, 304 mSDsCounter, 0 mSdLazyCounter, 424 mSolverCounterSat, 60 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 412 SdHoareTripleChecker+Valid, 335 SdHoareTripleChecker+Invalid, 1328 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 60 IncrementalHoareTripleChecker+Valid, 424 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 844 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-10-16 10:47:29,691 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [412 Valid, 335 Invalid, 1328 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [60 Valid, 424 Invalid, 0 Unknown, 844 Unchecked, 0.5s Time] [2022-10-16 10:47:29,693 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 325 states. [2022-10-16 10:47:29,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 325 to 235. [2022-10-16 10:47:29,718 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 235 states, 226 states have (on average 1.1283185840707965) internal successors, (255), 234 states have internal predecessors, (255), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:47:29,719 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 235 states to 235 states and 255 transitions. [2022-10-16 10:47:29,720 INFO L78 Accepts]: Start accepts. Automaton has 235 states and 255 transitions. Word has length 51 [2022-10-16 10:47:29,720 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:47:29,720 INFO L495 AbstractCegarLoop]: Abstraction has 235 states and 255 transitions. [2022-10-16 10:47:29,720 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 34 states, 33 states have (on average 4.151515151515151) internal successors, (137), 34 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:47:29,720 INFO L276 IsEmpty]: Start isEmpty. Operand 235 states and 255 transitions. [2022-10-16 10:47:29,721 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2022-10-16 10:47:29,721 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:47:29,721 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:47:29,756 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Forceful destruction successful, exit code 0 [2022-10-16 10:47:29,935 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 26 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable31 [2022-10-16 10:47:29,935 INFO L420 AbstractCegarLoop]: === Iteration 33 === Targeting ULTIMATE.startErr18ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:47:29,936 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:47:29,937 INFO L85 PathProgramCache]: Analyzing trace with hash -1003588293, now seen corresponding path program 2 times [2022-10-16 10:47:29,937 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:47:29,937 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2000084235] [2022-10-16 10:47:29,938 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:47:29,938 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:47:29,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:47:30,107 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2022-10-16 10:47:30,107 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:47:30,107 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2000084235] [2022-10-16 10:47:30,107 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2000084235] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-16 10:47:30,107 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1303409852] [2022-10-16 10:47:30,108 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-10-16 10:47:30,108 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:47:30,108 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-10-16 10:47:30,113 INFO L229 MonitoredProcess]: Starting monitored process 27 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-16 10:47:30,119 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2022-10-16 10:47:30,238 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-10-16 10:47:30,239 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-16 10:47:30,240 INFO L263 TraceCheckSpWp]: Trace formula consists of 189 conjuncts, 8 conjunts are in the unsatisfiable core [2022-10-16 10:47:30,241 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-16 10:47:30,382 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 10 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2022-10-16 10:47:30,382 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-16 10:47:30,525 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 10 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2022-10-16 10:47:30,525 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1303409852] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-16 10:47:30,526 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-16 10:47:30,526 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9] total 16 [2022-10-16 10:47:30,526 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1411087159] [2022-10-16 10:47:30,526 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-16 10:47:30,526 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 16 states [2022-10-16 10:47:30,526 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-16 10:47:30,527 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2022-10-16 10:47:30,527 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=189, Unknown=0, NotChecked=0, Total=240 [2022-10-16 10:47:30,527 INFO L87 Difference]: Start difference. First operand 235 states and 255 transitions. Second operand has 16 states, 16 states have (on average 4.875) internal successors, (78), 16 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:47:31,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-16 10:47:31,174 INFO L93 Difference]: Finished difference Result 319 states and 338 transitions. [2022-10-16 10:47:31,175 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2022-10-16 10:47:31,175 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 4.875) internal successors, (78), 16 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 51 [2022-10-16 10:47:31,175 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-10-16 10:47:31,177 INFO L225 Difference]: With dead ends: 319 [2022-10-16 10:47:31,177 INFO L226 Difference]: Without dead ends: 267 [2022-10-16 10:47:31,178 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 117 GetRequests, 90 SyntacticMatches, 5 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 133 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=120, Invalid=432, Unknown=0, NotChecked=0, Total=552 [2022-10-16 10:47:31,178 INFO L413 NwaCegarLoop]: 46 mSDtfsCounter, 270 mSDsluCounter, 261 mSDsCounter, 0 mSdLazyCounter, 615 mSolverCounterSat, 29 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 270 SdHoareTripleChecker+Valid, 307 SdHoareTripleChecker+Invalid, 644 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 29 IncrementalHoareTripleChecker+Valid, 615 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-10-16 10:47:31,179 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [270 Valid, 307 Invalid, 644 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [29 Valid, 615 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2022-10-16 10:47:31,180 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 267 states. [2022-10-16 10:47:31,202 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 267 to 235. [2022-10-16 10:47:31,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 235 states, 226 states have (on average 1.1150442477876106) internal successors, (252), 234 states have internal predecessors, (252), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:47:31,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 235 states to 235 states and 252 transitions. [2022-10-16 10:47:31,204 INFO L78 Accepts]: Start accepts. Automaton has 235 states and 252 transitions. Word has length 51 [2022-10-16 10:47:31,204 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-10-16 10:47:31,204 INFO L495 AbstractCegarLoop]: Abstraction has 235 states and 252 transitions. [2022-10-16 10:47:31,205 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 16 states, 16 states have (on average 4.875) internal successors, (78), 16 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-16 10:47:31,205 INFO L276 IsEmpty]: Start isEmpty. Operand 235 states and 252 transitions. [2022-10-16 10:47:31,205 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2022-10-16 10:47:31,205 INFO L187 NwaCegarLoop]: Found error trace [2022-10-16 10:47:31,206 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-16 10:47:31,241 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Forceful destruction successful, exit code 0 [2022-10-16 10:47:31,419 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 27 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable32 [2022-10-16 10:47:31,420 INFO L420 AbstractCegarLoop]: === Iteration 34 === Targeting ULTIMATE.startErr10ASSERT_VIOLATIONINTEGER_OVERFLOW === [ULTIMATE.startErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, ULTIMATE.startErr2ASSERT_VIOLATIONINTEGER_OVERFLOW (and 23 more)] === [2022-10-16 10:47:31,420 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-16 10:47:31,421 INFO L85 PathProgramCache]: Analyzing trace with hash 935247593, now seen corresponding path program 4 times [2022-10-16 10:47:31,421 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-16 10:47:31,421 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1930134248] [2022-10-16 10:47:31,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-16 10:47:31,422 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-16 10:47:31,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-16 10:47:34,200 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 20 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:47:34,201 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-16 10:47:34,202 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1930134248] [2022-10-16 10:47:34,202 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1930134248] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-16 10:47:34,202 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [292977555] [2022-10-16 10:47:34,202 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-10-16 10:47:34,202 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-16 10:47:34,202 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-10-16 10:47:34,203 INFO L229 MonitoredProcess]: Starting monitored process 28 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-16 10:47:34,216 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2022-10-16 10:47:34,328 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-10-16 10:47:34,328 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-16 10:47:34,329 INFO L263 TraceCheckSpWp]: Trace formula consists of 199 conjuncts, 52 conjunts are in the unsatisfiable core [2022-10-16 10:47:34,332 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-16 10:47:34,353 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:47:34,358 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:47:34,359 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 26 [2022-10-16 10:47:34,369 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:47:34,370 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 26 [2022-10-16 10:47:34,383 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2022-10-16 10:47:34,392 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2022-10-16 10:47:34,407 INFO L356 Elim1Store]: treesize reduction 7, result has 12.5 percent of original size [2022-10-16 10:47:34,407 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 32 treesize of output 28 [2022-10-16 10:47:34,416 INFO L356 Elim1Store]: treesize reduction 7, result has 12.5 percent of original size [2022-10-16 10:47:34,417 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 21 treesize of output 26 [2022-10-16 10:47:34,631 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:47:34,632 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:47:34,633 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 2 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 42 [2022-10-16 10:47:34,976 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:47:34,977 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:47:34,978 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:47:34,980 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 46 [2022-10-16 10:47:35,281 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:47:35,282 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:47:35,283 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:47:35,284 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 46 [2022-10-16 10:47:35,596 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:47:35,597 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:47:35,598 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:47:35,599 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 46 [2022-10-16 10:47:36,194 INFO L173 IndexEqualityManager]: detected equality via solver [2022-10-16 10:47:36,195 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-10-16 10:47:36,197 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 4 select indices, 4 select index equivalence classes, 3 disjoint index pairs (out of 6 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 80 treesize of output 63 [2022-10-16 10:47:36,721 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 4 select indices, 4 select index equivalence classes, 2 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 0 case distinctions, treesize of input 59 treesize of output 23 [2022-10-16 10:47:36,778 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 7 proven. 51 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-16 10:47:36,778 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-16 10:47:40,369 WARN L833 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_127| Int)) (or (not (<= (+ |c_ULTIMATE.start_main_#t~post8#1| 1) |v_ULTIMATE.start_main_~i~0#1_127|)) (forall ((v_ArrVal_1790 Int) (v_ArrVal_1789 Int)) (let ((.cse2 (store (select |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base|) (+ (* 8 |v_ULTIMATE.start_main_~i~0#1_127|) |c_ULTIMATE.start_main_~a~0#1.offset|) v_ArrVal_1789))) (let ((.cse0 (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| .cse2))) (let ((.cse1 (select .cse0 |c_ULTIMATE.start_main_~b~0#1.base|))) (or (< (+ (select (select (store .cse0 |c_ULTIMATE.start_main_~b~0#1.base| (store .cse1 (+ 8 |c_ULTIMATE.start_main_~b~0#1.offset|) v_ArrVal_1790)) |c_ULTIMATE.start_main_~a~0#1.base|) (+ 8 |c_ULTIMATE.start_main_~a~0#1.offset|)) v_ArrVal_1790) 9223372036854775808) (< (+ (select .cse2 |c_ULTIMATE.start_main_~a~0#1.offset|) (select .cse1 |c_ULTIMATE.start_main_~b~0#1.offset|)) v_ArrVal_1790)))))))) is different from false [2022-10-16 10:47:42,431 WARN L833 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_127| Int) (v_ArrVal_1790 Int) (v_ArrVal_1789 Int)) (let ((.cse2 (store (select |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base|) (+ (* 8 |v_ULTIMATE.start_main_~i~0#1_127|) |c_ULTIMATE.start_main_~a~0#1.offset|) v_ArrVal_1789))) (let ((.cse0 (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| .cse2))) (let ((.cse1 (select .cse0 |c_ULTIMATE.start_main_~b~0#1.base|))) (or (< (+ (select (select (store .cse0 |c_ULTIMATE.start_main_~b~0#1.base| (store .cse1 (+ 8 |c_ULTIMATE.start_main_~b~0#1.offset|) v_ArrVal_1790)) |c_ULTIMATE.start_main_~a~0#1.base|) (+ 8 |c_ULTIMATE.start_main_~a~0#1.offset|)) v_ArrVal_1790) 9223372036854775808) (< |v_ULTIMATE.start_main_~i~0#1_127| (+ |c_ULTIMATE.start_main_~i~0#1| 1)) (< (+ (select .cse2 |c_ULTIMATE.start_main_~a~0#1.offset|) (select .cse1 |c_ULTIMATE.start_main_~b~0#1.offset|)) v_ArrVal_1790)))))) is different from false [2022-10-16 10:47:44,471 WARN L833 $PredicateComparison]: unable to prove that (forall ((|v_ULTIMATE.start_main_~i~0#1_127| Int) (v_ArrVal_1790 Int) (v_ArrVal_1787 Int) (v_ArrVal_1789 Int)) (let ((.cse0 (store (store (select |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base|) (+ (* 8 |c_ULTIMATE.start_main_~i~0#1|) |c_ULTIMATE.start_main_~a~0#1.offset|) v_ArrVal_1787) (+ (* 8 |v_ULTIMATE.start_main_~i~0#1_127|) |c_ULTIMATE.start_main_~a~0#1.offset|) v_ArrVal_1789))) (let ((.cse2 (store |c_#memory_int| |c_ULTIMATE.start_main_~a~0#1.base| .cse0))) (let ((.cse1 (select .cse2 |c_ULTIMATE.start_main_~b~0#1.base|))) (or (< (+ (select .cse0 |c_ULTIMATE.start_main_~a~0#1.offset|) (select .cse1 |c_ULTIMATE.start_main_~b~0#1.offset|)) v_ArrVal_1790) (< (+ (select (select (store .cse2 |c_ULTIMATE.start_main_~b~0#1.base| (store .cse1 (+ 8 |c_ULTIMATE.start_main_~b~0#1.offset|) v_ArrVal_1790)) |c_ULTIMATE.start_main_~a~0#1.base|) (+ 8 |c_ULTIMATE.start_main_~a~0#1.offset|)) v_ArrVal_1790) 9223372036854775808) (< |v_ULTIMATE.start_main_~i~0#1_127| (+ |c_ULTIMATE.start_main_~i~0#1| 1))))))) is different from false