./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.15.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbebbe10-9140-4cd8-b9a5-2c6ec8f1d51f/bin/ukojak-rkRKPMF4O4/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbebbe10-9140-4cd8-b9a5-2c6ec8f1d51f/bin/ukojak-rkRKPMF4O4/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbebbe10-9140-4cd8-b9a5-2c6ec8f1d51f/bin/ukojak-rkRKPMF4O4/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbebbe10-9140-4cd8-b9a5-2c6ec8f1d51f/bin/ukojak-rkRKPMF4O4/config/KojakReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.15.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbebbe10-9140-4cd8-b9a5-2c6ec8f1d51f/bin/ukojak-rkRKPMF4O4/config/svcomp-Reach-32bit-Kojak_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbebbe10-9140-4cd8-b9a5-2c6ec8f1d51f/bin/ukojak-rkRKPMF4O4 --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Kojak --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 05397c7941b2acd95b1b6d02c6c64b476ab8b290a5b56301ff8db7ca1986067b --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-14 18:44:42,516 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-14 18:44:42,518 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-14 18:44:42,536 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-14 18:44:42,537 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-14 18:44:42,538 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-14 18:44:42,539 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-14 18:44:42,541 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-14 18:44:42,542 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-14 18:44:42,543 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-14 18:44:42,544 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-14 18:44:42,545 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-14 18:44:42,545 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-14 18:44:42,546 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-14 18:44:42,547 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-14 18:44:42,549 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-14 18:44:42,549 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-14 18:44:42,550 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-14 18:44:42,552 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-14 18:44:42,553 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-14 18:44:42,555 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-14 18:44:42,556 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-14 18:44:42,557 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-14 18:44:42,558 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-14 18:44:42,565 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-14 18:44:42,566 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-14 18:44:42,566 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-14 18:44:42,567 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-14 18:44:42,568 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-14 18:44:42,569 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-14 18:44:42,569 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-14 18:44:42,570 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-14 18:44:42,570 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-14 18:44:42,571 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-14 18:44:42,572 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-14 18:44:42,572 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-14 18:44:42,573 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-14 18:44:42,573 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-14 18:44:42,573 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-14 18:44:42,574 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-14 18:44:42,575 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-14 18:44:42,576 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbebbe10-9140-4cd8-b9a5-2c6ec8f1d51f/bin/ukojak-rkRKPMF4O4/config/svcomp-Reach-32bit-Kojak_Default.epf [2022-12-14 18:44:42,595 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-14 18:44:42,596 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-14 18:44:42,596 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-12-14 18:44:42,597 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ALWAYS [2022-12-14 18:44:42,597 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-12-14 18:44:42,598 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-12-14 18:44:42,598 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-14 18:44:42,598 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-14 18:44:42,598 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-14 18:44:42,598 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-14 18:44:42,605 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-14 18:44:42,605 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-12-14 18:44:42,605 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-12-14 18:44:42,605 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-12-14 18:44:42,606 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-14 18:44:42,606 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-14 18:44:42,606 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-14 18:44:42,606 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-12-14 18:44:42,606 INFO L136 SettingsManager]: Preferences of CodeCheck differ from their defaults: [2022-12-14 18:44:42,607 INFO L138 SettingsManager]: * Timeout in seconds=1000000 [2022-12-14 18:44:42,607 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-14 18:44:42,607 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2022-12-14 18:44:42,607 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-14 18:44:42,607 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-12-14 18:44:42,607 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-12-14 18:44:42,608 INFO L138 SettingsManager]: * Trace refinement strategy=PENGUIN [2022-12-14 18:44:42,608 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-12-14 18:44:42,608 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-12-14 18:44:42,608 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbebbe10-9140-4cd8-b9a5-2c6ec8f1d51f/bin/ukojak-rkRKPMF4O4/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbebbe10-9140-4cd8-b9a5-2c6ec8f1d51f/bin/ukojak-rkRKPMF4O4 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Kojak Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 05397c7941b2acd95b1b6d02c6c64b476ab8b290a5b56301ff8db7ca1986067b [2022-12-14 18:44:42,799 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-14 18:44:42,819 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-14 18:44:42,821 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-14 18:44:42,823 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-14 18:44:42,823 INFO L275 PluginConnector]: CDTParser initialized [2022-12-14 18:44:42,824 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbebbe10-9140-4cd8-b9a5-2c6ec8f1d51f/bin/ukojak-rkRKPMF4O4/../../sv-benchmarks/c/systemc/transmitter.15.cil.c [2022-12-14 18:44:45,346 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-14 18:44:45,528 INFO L351 CDTParser]: Found 1 translation units. [2022-12-14 18:44:45,528 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbebbe10-9140-4cd8-b9a5-2c6ec8f1d51f/sv-benchmarks/c/systemc/transmitter.15.cil.c [2022-12-14 18:44:45,541 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbebbe10-9140-4cd8-b9a5-2c6ec8f1d51f/bin/ukojak-rkRKPMF4O4/data/0e4a07a0f/f95cbff10b2841a9b573ff5757416224/FLAG79da343b7 [2022-12-14 18:44:45,553 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbebbe10-9140-4cd8-b9a5-2c6ec8f1d51f/bin/ukojak-rkRKPMF4O4/data/0e4a07a0f/f95cbff10b2841a9b573ff5757416224 [2022-12-14 18:44:45,556 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-14 18:44:45,557 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-14 18:44:45,559 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-14 18:44:45,559 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-14 18:44:45,561 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-14 18:44:45,562 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.12 06:44:45" (1/1) ... [2022-12-14 18:44:45,563 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6f54c435 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 06:44:45, skipping insertion in model container [2022-12-14 18:44:45,563 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.12 06:44:45" (1/1) ... [2022-12-14 18:44:45,569 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-14 18:44:45,611 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-14 18:44:45,722 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbebbe10-9140-4cd8-b9a5-2c6ec8f1d51f/sv-benchmarks/c/systemc/transmitter.15.cil.c[706,719] [2022-12-14 18:44:45,842 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-14 18:44:45,854 INFO L203 MainTranslator]: Completed pre-run [2022-12-14 18:44:45,863 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbebbe10-9140-4cd8-b9a5-2c6ec8f1d51f/sv-benchmarks/c/systemc/transmitter.15.cil.c[706,719] [2022-12-14 18:44:45,905 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-14 18:44:45,918 INFO L208 MainTranslator]: Completed translation [2022-12-14 18:44:45,918 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 06:44:45 WrapperNode [2022-12-14 18:44:45,919 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-14 18:44:45,919 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-14 18:44:45,919 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-14 18:44:45,920 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-14 18:44:45,925 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 06:44:45" (1/1) ... [2022-12-14 18:44:45,933 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 06:44:45" (1/1) ... [2022-12-14 18:44:45,961 INFO L138 Inliner]: procedures = 54, calls = 69, calls flagged for inlining = 38, calls inlined = 38, statements flattened = 891 [2022-12-14 18:44:45,962 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-14 18:44:45,962 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-14 18:44:45,962 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-14 18:44:45,962 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-14 18:44:45,969 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 06:44:45" (1/1) ... [2022-12-14 18:44:45,969 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 06:44:45" (1/1) ... [2022-12-14 18:44:45,972 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 06:44:45" (1/1) ... [2022-12-14 18:44:45,972 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 06:44:45" (1/1) ... [2022-12-14 18:44:45,979 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 06:44:45" (1/1) ... [2022-12-14 18:44:45,987 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 06:44:45" (1/1) ... [2022-12-14 18:44:45,989 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 06:44:45" (1/1) ... [2022-12-14 18:44:45,991 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 06:44:45" (1/1) ... [2022-12-14 18:44:45,994 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-14 18:44:45,995 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-14 18:44:45,995 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-14 18:44:45,995 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-14 18:44:45,996 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 06:44:45" (1/1) ... [2022-12-14 18:44:46,000 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2022-12-14 18:44:46,009 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbebbe10-9140-4cd8-b9a5-2c6ec8f1d51f/bin/ukojak-rkRKPMF4O4/z3 [2022-12-14 18:44:46,018 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbebbe10-9140-4cd8-b9a5-2c6ec8f1d51f/bin/ukojak-rkRKPMF4O4/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (exit command is (exit), workingDir is null) [2022-12-14 18:44:46,020 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbebbe10-9140-4cd8-b9a5-2c6ec8f1d51f/bin/ukojak-rkRKPMF4O4/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (1)] Waiting until timeout for monitored process [2022-12-14 18:44:46,045 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-14 18:44:46,046 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2022-12-14 18:44:46,046 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2022-12-14 18:44:46,046 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2022-12-14 18:44:46,046 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2022-12-14 18:44:46,046 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2022-12-14 18:44:46,046 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2022-12-14 18:44:46,046 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2022-12-14 18:44:46,046 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2022-12-14 18:44:46,046 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2022-12-14 18:44:46,046 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2022-12-14 18:44:46,047 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2022-12-14 18:44:46,047 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2022-12-14 18:44:46,047 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-14 18:44:46,047 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-14 18:44:46,047 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-14 18:44:46,139 INFO L235 CfgBuilder]: Building ICFG [2022-12-14 18:44:46,141 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-14 18:44:46,766 INFO L276 CfgBuilder]: Performing block encoding [2022-12-14 18:44:47,063 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-14 18:44:47,063 INFO L300 CfgBuilder]: Removed 17 assume(true) statements. [2022-12-14 18:44:47,065 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.12 06:44:47 BoogieIcfgContainer [2022-12-14 18:44:47,066 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-14 18:44:47,066 INFO L113 PluginConnector]: ------------------------CodeCheck---------------------------- [2022-12-14 18:44:47,066 INFO L271 PluginConnector]: Initializing CodeCheck... [2022-12-14 18:44:47,073 INFO L275 PluginConnector]: CodeCheck initialized [2022-12-14 18:44:47,074 INFO L185 PluginConnector]: Executing the observer CodeCheckObserver from plugin CodeCheck for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.12 06:44:47" (1/1) ... [2022-12-14 18:44:47,080 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-14 18:44:47,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:47,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 299 states to 193 states and 299 transitions. [2022-12-14 18:44:47,122 INFO L276 IsEmpty]: Start isEmpty. Operand 193 states and 299 transitions. [2022-12-14 18:44:47,126 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:47,126 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:47,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:47,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:47,502 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:47,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:47,657 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 386 states to 234 states and 379 transitions. [2022-12-14 18:44:47,657 INFO L276 IsEmpty]: Start isEmpty. Operand 234 states and 379 transitions. [2022-12-14 18:44:47,658 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:47,658 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:47,658 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:47,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:47,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:47,791 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:47,794 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 386 states to 235 states and 379 transitions. [2022-12-14 18:44:47,794 INFO L276 IsEmpty]: Start isEmpty. Operand 235 states and 379 transitions. [2022-12-14 18:44:47,795 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:47,795 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:47,796 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:47,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:47,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:47,901 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:47,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 386 states to 236 states and 379 transitions. [2022-12-14 18:44:47,904 INFO L276 IsEmpty]: Start isEmpty. Operand 236 states and 379 transitions. [2022-12-14 18:44:47,906 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:47,906 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:47,906 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:47,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:48,014 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:48,025 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:48,027 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 386 states to 237 states and 379 transitions. [2022-12-14 18:44:48,028 INFO L276 IsEmpty]: Start isEmpty. Operand 237 states and 379 transitions. [2022-12-14 18:44:48,029 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:48,030 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:48,030 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:48,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:48,125 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:48,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:48,138 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 386 states to 238 states and 379 transitions. [2022-12-14 18:44:48,138 INFO L276 IsEmpty]: Start isEmpty. Operand 238 states and 379 transitions. [2022-12-14 18:44:48,140 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:48,140 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:48,140 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:48,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:48,238 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:48,249 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:48,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 386 states to 239 states and 379 transitions. [2022-12-14 18:44:48,251 INFO L276 IsEmpty]: Start isEmpty. Operand 239 states and 379 transitions. [2022-12-14 18:44:48,252 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:48,252 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:48,253 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:48,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:48,336 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:48,347 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:48,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 386 states to 240 states and 379 transitions. [2022-12-14 18:44:48,349 INFO L276 IsEmpty]: Start isEmpty. Operand 240 states and 379 transitions. [2022-12-14 18:44:48,350 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:48,350 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:48,350 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:48,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:48,433 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:48,443 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:48,445 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 386 states to 241 states and 379 transitions. [2022-12-14 18:44:48,445 INFO L276 IsEmpty]: Start isEmpty. Operand 241 states and 379 transitions. [2022-12-14 18:44:48,446 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:48,446 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:48,446 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:48,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:48,558 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:48,569 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:48,570 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 386 states to 242 states and 379 transitions. [2022-12-14 18:44:48,570 INFO L276 IsEmpty]: Start isEmpty. Operand 242 states and 379 transitions. [2022-12-14 18:44:48,571 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:48,571 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:48,571 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:48,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:48,624 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:48,633 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:48,634 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 386 states to 243 states and 379 transitions. [2022-12-14 18:44:48,634 INFO L276 IsEmpty]: Start isEmpty. Operand 243 states and 379 transitions. [2022-12-14 18:44:48,635 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:48,635 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:48,635 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:48,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:48,689 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:48,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:48,700 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 386 states to 244 states and 379 transitions. [2022-12-14 18:44:48,701 INFO L276 IsEmpty]: Start isEmpty. Operand 244 states and 379 transitions. [2022-12-14 18:44:48,701 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:48,701 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:48,701 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:48,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:48,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:48,790 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:48,791 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 386 states to 245 states and 379 transitions. [2022-12-14 18:44:48,792 INFO L276 IsEmpty]: Start isEmpty. Operand 245 states and 379 transitions. [2022-12-14 18:44:48,792 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:48,792 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:48,793 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:48,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:48,876 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:48,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:48,888 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 386 states to 246 states and 379 transitions. [2022-12-14 18:44:48,888 INFO L276 IsEmpty]: Start isEmpty. Operand 246 states and 379 transitions. [2022-12-14 18:44:48,889 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:48,889 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:48,889 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:48,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:48,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:48,952 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:48,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 386 states to 247 states and 379 transitions. [2022-12-14 18:44:48,954 INFO L276 IsEmpty]: Start isEmpty. Operand 247 states and 379 transitions. [2022-12-14 18:44:48,955 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:48,955 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:48,955 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:48,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:49,066 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:49,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:49,222 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 283 states and 450 transitions. [2022-12-14 18:44:49,222 INFO L276 IsEmpty]: Start isEmpty. Operand 283 states and 450 transitions. [2022-12-14 18:44:49,223 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:49,223 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:49,223 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:49,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:49,284 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:49,294 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:49,295 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 284 states and 450 transitions. [2022-12-14 18:44:49,295 INFO L276 IsEmpty]: Start isEmpty. Operand 284 states and 450 transitions. [2022-12-14 18:44:49,295 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:49,296 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:49,296 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:49,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:49,354 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:49,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:49,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 285 states and 450 transitions. [2022-12-14 18:44:49,373 INFO L276 IsEmpty]: Start isEmpty. Operand 285 states and 450 transitions. [2022-12-14 18:44:49,374 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:49,374 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:49,374 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:49,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:49,463 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:49,474 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:49,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 286 states and 450 transitions. [2022-12-14 18:44:49,476 INFO L276 IsEmpty]: Start isEmpty. Operand 286 states and 450 transitions. [2022-12-14 18:44:49,476 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:49,476 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:49,476 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:49,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:49,532 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:49,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:49,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 287 states and 450 transitions. [2022-12-14 18:44:49,544 INFO L276 IsEmpty]: Start isEmpty. Operand 287 states and 450 transitions. [2022-12-14 18:44:49,545 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:49,545 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:49,545 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:49,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:49,612 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:49,626 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:49,628 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 288 states and 450 transitions. [2022-12-14 18:44:49,628 INFO L276 IsEmpty]: Start isEmpty. Operand 288 states and 450 transitions. [2022-12-14 18:44:49,629 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:49,629 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:49,629 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:49,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:49,703 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:49,714 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:49,715 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 289 states and 450 transitions. [2022-12-14 18:44:49,715 INFO L276 IsEmpty]: Start isEmpty. Operand 289 states and 450 transitions. [2022-12-14 18:44:49,716 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:49,716 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:49,716 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:49,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:49,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:49,780 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:49,781 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 290 states and 450 transitions. [2022-12-14 18:44:49,782 INFO L276 IsEmpty]: Start isEmpty. Operand 290 states and 450 transitions. [2022-12-14 18:44:49,782 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:49,782 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:49,782 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:49,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:49,838 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:49,847 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:49,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 291 states and 450 transitions. [2022-12-14 18:44:49,848 INFO L276 IsEmpty]: Start isEmpty. Operand 291 states and 450 transitions. [2022-12-14 18:44:49,849 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:49,849 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:49,849 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:49,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:49,909 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:49,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:49,920 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 292 states and 450 transitions. [2022-12-14 18:44:49,920 INFO L276 IsEmpty]: Start isEmpty. Operand 292 states and 450 transitions. [2022-12-14 18:44:49,921 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:49,921 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:49,921 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:49,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:49,977 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:49,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:49,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 293 states and 450 transitions. [2022-12-14 18:44:49,989 INFO L276 IsEmpty]: Start isEmpty. Operand 293 states and 450 transitions. [2022-12-14 18:44:49,989 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:49,989 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:49,989 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:50,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:50,044 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:50,055 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:50,056 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 294 states and 450 transitions. [2022-12-14 18:44:50,056 INFO L276 IsEmpty]: Start isEmpty. Operand 294 states and 450 transitions. [2022-12-14 18:44:50,056 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:50,057 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:50,057 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:50,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:50,137 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:50,313 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:50,315 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 536 states to 326 states and 515 transitions. [2022-12-14 18:44:50,315 INFO L276 IsEmpty]: Start isEmpty. Operand 326 states and 515 transitions. [2022-12-14 18:44:50,315 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:50,315 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:50,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:50,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:50,372 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:50,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:50,383 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 536 states to 327 states and 515 transitions. [2022-12-14 18:44:50,384 INFO L276 IsEmpty]: Start isEmpty. Operand 327 states and 515 transitions. [2022-12-14 18:44:50,384 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:50,384 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:50,384 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:50,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:50,442 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:50,451 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:50,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 536 states to 328 states and 515 transitions. [2022-12-14 18:44:50,452 INFO L276 IsEmpty]: Start isEmpty. Operand 328 states and 515 transitions. [2022-12-14 18:44:50,453 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:50,453 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:50,453 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:50,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:50,512 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:50,524 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:50,525 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 536 states to 329 states and 515 transitions. [2022-12-14 18:44:50,525 INFO L276 IsEmpty]: Start isEmpty. Operand 329 states and 515 transitions. [2022-12-14 18:44:50,526 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:50,526 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:50,526 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:50,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:50,578 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:50,588 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:50,589 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 536 states to 330 states and 515 transitions. [2022-12-14 18:44:50,589 INFO L276 IsEmpty]: Start isEmpty. Operand 330 states and 515 transitions. [2022-12-14 18:44:50,590 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:50,590 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:50,590 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:50,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:50,643 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:50,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:50,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 536 states to 331 states and 515 transitions. [2022-12-14 18:44:50,655 INFO L276 IsEmpty]: Start isEmpty. Operand 331 states and 515 transitions. [2022-12-14 18:44:50,655 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:50,655 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:50,655 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:50,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:50,716 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:50,732 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:50,733 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 536 states to 332 states and 515 transitions. [2022-12-14 18:44:50,733 INFO L276 IsEmpty]: Start isEmpty. Operand 332 states and 515 transitions. [2022-12-14 18:44:50,734 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:50,734 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:50,734 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:50,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:50,807 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:50,817 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:50,818 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 536 states to 333 states and 515 transitions. [2022-12-14 18:44:50,818 INFO L276 IsEmpty]: Start isEmpty. Operand 333 states and 515 transitions. [2022-12-14 18:44:50,819 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:50,819 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:50,819 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:50,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:50,871 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:50,881 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:50,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 536 states to 334 states and 515 transitions. [2022-12-14 18:44:50,882 INFO L276 IsEmpty]: Start isEmpty. Operand 334 states and 515 transitions. [2022-12-14 18:44:50,883 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:50,883 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:50,883 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:50,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:50,935 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:50,945 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:50,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 536 states to 335 states and 515 transitions. [2022-12-14 18:44:50,947 INFO L276 IsEmpty]: Start isEmpty. Operand 335 states and 515 transitions. [2022-12-14 18:44:50,947 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:50,947 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:50,947 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:50,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:51,006 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:51,017 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:51,018 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 536 states to 336 states and 515 transitions. [2022-12-14 18:44:51,018 INFO L276 IsEmpty]: Start isEmpty. Operand 336 states and 515 transitions. [2022-12-14 18:44:51,018 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:51,018 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:51,019 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:51,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:51,090 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:51,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:51,273 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 596 states to 362 states and 568 transitions. [2022-12-14 18:44:51,273 INFO L276 IsEmpty]: Start isEmpty. Operand 362 states and 568 transitions. [2022-12-14 18:44:51,274 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:51,274 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:51,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:51,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:51,328 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:51,337 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:51,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 596 states to 363 states and 568 transitions. [2022-12-14 18:44:51,338 INFO L276 IsEmpty]: Start isEmpty. Operand 363 states and 568 transitions. [2022-12-14 18:44:51,339 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:51,339 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:51,339 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:51,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:51,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:51,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:51,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 596 states to 364 states and 568 transitions. [2022-12-14 18:44:51,406 INFO L276 IsEmpty]: Start isEmpty. Operand 364 states and 568 transitions. [2022-12-14 18:44:51,407 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:51,407 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:51,407 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:51,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:51,457 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:51,467 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:51,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 596 states to 365 states and 568 transitions. [2022-12-14 18:44:51,468 INFO L276 IsEmpty]: Start isEmpty. Operand 365 states and 568 transitions. [2022-12-14 18:44:51,468 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:51,468 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:51,469 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:51,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:51,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:51,535 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:51,536 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 596 states to 366 states and 568 transitions. [2022-12-14 18:44:51,536 INFO L276 IsEmpty]: Start isEmpty. Operand 366 states and 568 transitions. [2022-12-14 18:44:51,536 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:51,536 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:51,536 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:51,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:51,591 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:51,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:51,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 596 states to 367 states and 568 transitions. [2022-12-14 18:44:51,610 INFO L276 IsEmpty]: Start isEmpty. Operand 367 states and 568 transitions. [2022-12-14 18:44:51,611 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:51,611 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:51,611 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:51,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:51,698 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:51,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:51,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 596 states to 368 states and 568 transitions. [2022-12-14 18:44:51,717 INFO L276 IsEmpty]: Start isEmpty. Operand 368 states and 568 transitions. [2022-12-14 18:44:51,717 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:51,718 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:51,718 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:51,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:51,786 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:51,795 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:51,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 596 states to 369 states and 568 transitions. [2022-12-14 18:44:51,796 INFO L276 IsEmpty]: Start isEmpty. Operand 369 states and 568 transitions. [2022-12-14 18:44:51,797 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:51,797 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:51,797 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:51,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:51,849 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:51,858 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:51,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 596 states to 370 states and 568 transitions. [2022-12-14 18:44:51,859 INFO L276 IsEmpty]: Start isEmpty. Operand 370 states and 568 transitions. [2022-12-14 18:44:51,860 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:51,860 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:51,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:51,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:51,925 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:52,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:52,394 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 644 states to 390 states and 609 transitions. [2022-12-14 18:44:52,394 INFO L276 IsEmpty]: Start isEmpty. Operand 390 states and 609 transitions. [2022-12-14 18:44:52,396 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:52,396 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:52,396 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:52,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:52,454 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:52,746 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:52,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 644 states to 391 states and 609 transitions. [2022-12-14 18:44:52,748 INFO L276 IsEmpty]: Start isEmpty. Operand 391 states and 609 transitions. [2022-12-14 18:44:52,748 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:52,748 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:52,748 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:52,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:52,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:53,045 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:53,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 644 states to 392 states and 609 transitions. [2022-12-14 18:44:53,046 INFO L276 IsEmpty]: Start isEmpty. Operand 392 states and 609 transitions. [2022-12-14 18:44:53,046 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:53,046 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:53,047 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:53,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:53,085 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:53,329 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:53,331 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 644 states to 393 states and 609 transitions. [2022-12-14 18:44:53,331 INFO L276 IsEmpty]: Start isEmpty. Operand 393 states and 609 transitions. [2022-12-14 18:44:53,331 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:53,331 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:53,331 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:53,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:53,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:53,682 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:53,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 644 states to 394 states and 609 transitions. [2022-12-14 18:44:53,684 INFO L276 IsEmpty]: Start isEmpty. Operand 394 states and 609 transitions. [2022-12-14 18:44:53,685 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:53,685 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:53,685 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:53,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:53,733 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:54,013 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:54,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 644 states to 395 states and 609 transitions. [2022-12-14 18:44:54,015 INFO L276 IsEmpty]: Start isEmpty. Operand 395 states and 609 transitions. [2022-12-14 18:44:54,015 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:54,015 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:54,016 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:54,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:54,073 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:54,329 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:54,330 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 644 states to 396 states and 609 transitions. [2022-12-14 18:44:54,330 INFO L276 IsEmpty]: Start isEmpty. Operand 396 states and 609 transitions. [2022-12-14 18:44:54,331 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:54,331 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:54,331 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:54,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:54,422 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:54,633 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:54,635 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 680 states to 410 states and 638 transitions. [2022-12-14 18:44:54,635 INFO L276 IsEmpty]: Start isEmpty. Operand 410 states and 638 transitions. [2022-12-14 18:44:54,636 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:54,636 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:54,636 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:54,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:54,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:54,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:54,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 680 states to 411 states and 638 transitions. [2022-12-14 18:44:54,701 INFO L276 IsEmpty]: Start isEmpty. Operand 411 states and 638 transitions. [2022-12-14 18:44:54,701 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:54,701 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:54,702 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:54,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:54,751 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:54,768 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:54,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 680 states to 412 states and 638 transitions. [2022-12-14 18:44:54,769 INFO L276 IsEmpty]: Start isEmpty. Operand 412 states and 638 transitions. [2022-12-14 18:44:54,770 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:54,770 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:54,770 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:54,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:54,844 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:54,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:54,862 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 680 states to 413 states and 638 transitions. [2022-12-14 18:44:54,862 INFO L276 IsEmpty]: Start isEmpty. Operand 413 states and 638 transitions. [2022-12-14 18:44:54,863 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:54,863 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:54,863 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:54,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:54,922 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:54,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:54,941 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 680 states to 414 states and 638 transitions. [2022-12-14 18:44:54,941 INFO L276 IsEmpty]: Start isEmpty. Operand 414 states and 638 transitions. [2022-12-14 18:44:54,942 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:54,942 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:54,942 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:54,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:55,036 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:55,284 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:55,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 704 states to 422 states and 655 transitions. [2022-12-14 18:44:55,285 INFO L276 IsEmpty]: Start isEmpty. Operand 422 states and 655 transitions. [2022-12-14 18:44:55,286 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:55,286 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:55,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:55,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:55,336 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:55,357 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:55,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 704 states to 423 states and 655 transitions. [2022-12-14 18:44:55,359 INFO L276 IsEmpty]: Start isEmpty. Operand 423 states and 655 transitions. [2022-12-14 18:44:55,359 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:55,359 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:55,360 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:55,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:55,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:55,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:55,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 704 states to 424 states and 655 transitions. [2022-12-14 18:44:55,431 INFO L276 IsEmpty]: Start isEmpty. Operand 424 states and 655 transitions. [2022-12-14 18:44:55,431 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:55,432 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:55,432 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:55,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:55,530 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:56,001 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:56,002 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 722 states to 429 states and 666 transitions. [2022-12-14 18:44:56,002 INFO L276 IsEmpty]: Start isEmpty. Operand 429 states and 666 transitions. [2022-12-14 18:44:56,003 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:56,003 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:56,003 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:56,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:56,039 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:56,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:56,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 722 states to 430 states and 666 transitions. [2022-12-14 18:44:56,216 INFO L276 IsEmpty]: Start isEmpty. Operand 430 states and 666 transitions. [2022-12-14 18:44:56,217 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:56,217 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:56,217 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:56,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:56,457 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:57,909 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:57,911 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 839 states to 476 states and 757 transitions. [2022-12-14 18:44:57,912 INFO L276 IsEmpty]: Start isEmpty. Operand 476 states and 757 transitions. [2022-12-14 18:44:57,913 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:57,913 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:57,913 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:57,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:58,046 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:44:58,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:44:58,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 855 states to 478 states and 762 transitions. [2022-12-14 18:44:58,748 INFO L276 IsEmpty]: Start isEmpty. Operand 478 states and 762 transitions. [2022-12-14 18:44:58,749 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:44:58,749 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:44:58,749 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:44:58,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:44:58,880 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:45:00,776 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:45:00,777 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 889 states to 489 states and 785 transitions. [2022-12-14 18:45:00,777 INFO L276 IsEmpty]: Start isEmpty. Operand 489 states and 785 transitions. [2022-12-14 18:45:00,777 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:45:00,777 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:45:00,777 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:45:00,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:45:00,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:45:02,909 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:45:02,910 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 935 states to 506 states and 820 transitions. [2022-12-14 18:45:02,910 INFO L276 IsEmpty]: Start isEmpty. Operand 506 states and 820 transitions. [2022-12-14 18:45:02,911 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:45:02,911 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:45:02,911 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:45:02,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:45:03,064 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:45:06,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:45:06,353 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 993 states to 529 states and 867 transitions. [2022-12-14 18:45:06,353 INFO L276 IsEmpty]: Start isEmpty. Operand 529 states and 867 transitions. [2022-12-14 18:45:06,354 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:45:06,354 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:45:06,354 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:45:06,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:45:06,597 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:45:11,851 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:45:11,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1063 states to 558 states and 926 transitions. [2022-12-14 18:45:11,852 INFO L276 IsEmpty]: Start isEmpty. Operand 558 states and 926 transitions. [2022-12-14 18:45:11,853 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-12-14 18:45:11,853 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:45:11,853 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:45:11,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:45:12,092 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:45:22,986 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:45:22,987 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1151 states to 596 states and 1003 transitions. [2022-12-14 18:45:22,987 INFO L276 IsEmpty]: Start isEmpty. Operand 596 states and 1003 transitions. [2022-12-14 18:45:22,988 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2022-12-14 18:45:22,988 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:45:22,988 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:45:22,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:45:23,031 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:45:23,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:45:23,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1152 states to 597 states and 1004 transitions. [2022-12-14 18:45:23,162 INFO L276 IsEmpty]: Start isEmpty. Operand 597 states and 1004 transitions. [2022-12-14 18:45:23,162 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2022-12-14 18:45:23,162 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:45:23,163 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:45:23,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:45:23,207 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:45:23,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:45:23,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1153 states to 598 states and 1005 transitions. [2022-12-14 18:45:23,350 INFO L276 IsEmpty]: Start isEmpty. Operand 598 states and 1005 transitions. [2022-12-14 18:45:23,351 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2022-12-14 18:45:23,351 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:45:23,351 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:45:23,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:45:23,419 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:45:23,588 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:45:23,589 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1154 states to 599 states and 1006 transitions. [2022-12-14 18:45:23,589 INFO L276 IsEmpty]: Start isEmpty. Operand 599 states and 1006 transitions. [2022-12-14 18:45:23,590 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2022-12-14 18:45:23,590 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:45:23,590 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:45:23,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:45:23,625 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:45:24,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:45:24,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1155 states to 600 states and 1007 transitions. [2022-12-14 18:45:24,055 INFO L276 IsEmpty]: Start isEmpty. Operand 600 states and 1007 transitions. [2022-12-14 18:45:24,056 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2022-12-14 18:45:24,056 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:45:24,056 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:45:24,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:45:24,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:45:24,247 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:45:24,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1156 states to 601 states and 1008 transitions. [2022-12-14 18:45:24,249 INFO L276 IsEmpty]: Start isEmpty. Operand 601 states and 1008 transitions. [2022-12-14 18:45:24,249 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2022-12-14 18:45:24,249 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:45:24,249 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:45:24,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:45:24,293 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:45:24,470 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:45:24,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1157 states to 602 states and 1009 transitions. [2022-12-14 18:45:24,471 INFO L276 IsEmpty]: Start isEmpty. Operand 602 states and 1009 transitions. [2022-12-14 18:45:24,472 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2022-12-14 18:45:24,472 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:45:24,472 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:45:24,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 18:45:24,505 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 18:45:24,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2022-12-14 18:45:24,832 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1158 states to 603 states and 1010 transitions. [2022-12-14 18:45:24,832 INFO L276 IsEmpty]: Start isEmpty. Operand 603 states and 1010 transitions. [2022-12-14 18:45:24,833 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2022-12-14 18:45:24,833 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2022-12-14 18:45:24,833 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 18:45:24,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-14 18:45:24,848 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-14 18:45:24,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-14 18:45:25,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-14 18:45:25,029 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-14 18:45:25,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-14 18:45:25,162 WARN L475 CodeCheckObserver]: This program is UNSAFE, Check terminated with 78 iterations. [2022-12-14 18:45:25,310 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck CFG 14.12 06:45:25 ImpRootNode [2022-12-14 18:45:25,310 INFO L132 PluginConnector]: ------------------------ END CodeCheck---------------------------- [2022-12-14 18:45:25,311 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-12-14 18:45:25,311 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-12-14 18:45:25,311 INFO L275 PluginConnector]: Witness Printer initialized [2022-12-14 18:45:25,311 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.12 06:44:47" (3/4) ... [2022-12-14 18:45:25,313 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2022-12-14 18:45:25,422 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbebbe10-9140-4cd8-b9a5-2c6ec8f1d51f/bin/ukojak-rkRKPMF4O4/witness.graphml [2022-12-14 18:45:25,422 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-12-14 18:45:25,423 INFO L158 Benchmark]: Toolchain (without parser) took 39865.72ms. Allocated memory was 127.9MB in the beginning and 415.2MB in the end (delta: 287.3MB). Free memory was 92.2MB in the beginning and 339.0MB in the end (delta: -246.8MB). Peak memory consumption was 264.1MB. Max. memory is 16.1GB. [2022-12-14 18:45:25,423 INFO L158 Benchmark]: CDTParser took 0.20ms. Allocated memory is still 127.9MB. Free memory is still 94.1MB. There was no memory consumed. Max. memory is 16.1GB. [2022-12-14 18:45:25,423 INFO L158 Benchmark]: CACSL2BoogieTranslator took 360.08ms. Allocated memory is still 127.9MB. Free memory was 91.8MB in the beginning and 68.5MB in the end (delta: 23.3MB). Peak memory consumption was 23.1MB. Max. memory is 16.1GB. [2022-12-14 18:45:25,423 INFO L158 Benchmark]: Boogie Procedure Inliner took 42.41ms. Allocated memory is still 127.9MB. Free memory was 68.5MB in the beginning and 64.6MB in the end (delta: 3.9MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-12-14 18:45:25,424 INFO L158 Benchmark]: Boogie Preprocessor took 32.36ms. Allocated memory is still 127.9MB. Free memory was 64.6MB in the beginning and 60.4MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-12-14 18:45:25,424 INFO L158 Benchmark]: RCFGBuilder took 1070.77ms. Allocated memory was 127.9MB in the beginning and 165.7MB in the end (delta: 37.7MB). Free memory was 60.4MB in the beginning and 109.8MB in the end (delta: -49.4MB). Peak memory consumption was 54.2MB. Max. memory is 16.1GB. [2022-12-14 18:45:25,424 INFO L158 Benchmark]: CodeCheck took 38244.06ms. Allocated memory was 165.7MB in the beginning and 415.2MB in the end (delta: 249.6MB). Free memory was 109.8MB in the beginning and 133.6MB in the end (delta: -23.9MB). Peak memory consumption was 224.6MB. Max. memory is 16.1GB. [2022-12-14 18:45:25,424 INFO L158 Benchmark]: Witness Printer took 111.75ms. Allocated memory is still 415.2MB. Free memory was 133.6MB in the beginning and 339.0MB in the end (delta: -205.4MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2022-12-14 18:45:25,426 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck: - StatisticsResult: Ultimate CodeCheck benchmark data CFG has 7 procedures, 193 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 38.1s, OverallIterations: 78, TraceHistogramMax: 0, PathProgramHistogramMax: 0, EmptinessCheckTime: 0.0s, AutomataDifference: 0.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 50442 SdHoareTripleChecker+Valid, 30.2s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 38592 mSDsluCounter, 75702 SdHoareTripleChecker+Invalid, 26.1s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 60174 mSDsCounter, 3359 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 25547 IncrementalHoareTripleChecker+Invalid, 28906 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 3359 mSolverCounterUnsat, 15528 mSDtfsCounter, 25547 mSolverCounterSat, 1.3s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 48740 GetRequests, 47869 SyntacticMatches, 479 SemanticMatches, 392 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 106696 ImplicationChecksByTransitivity, 29.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=-1occurred in iteration=-1, InterpolantAutomatonStates: 0, traceCheckStatistics: 0.3s SsaConstructionTime, 0.5s SatisfiabilityAnalysisTime, 4.9s InterpolantComputationTime, 5234 NumberOfCodeBlocks, 5234 NumberOfCodeBlocksAsserted, 78 NumberOfCheckSat, 5089 ConstructedInterpolants, 0 QuantifiedInterpolants, 13654 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 77 InterpolantComputations, 77 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: No data available, ReuseStatistics: No data available - CounterExampleResult [Line: 21]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int t6_pc = 0; [L32] int t7_pc = 0; [L33] int t8_pc = 0; [L34] int t9_pc = 0; [L35] int t10_pc = 0; [L36] int t11_pc = 0; [L37] int t12_pc = 0; [L38] int t13_pc = 0; [L39] int m_st ; [L40] int t1_st ; [L41] int t2_st ; [L42] int t3_st ; [L43] int t4_st ; [L44] int t5_st ; [L45] int t6_st ; [L46] int t7_st ; [L47] int t8_st ; [L48] int t9_st ; [L49] int t10_st ; [L50] int t11_st ; [L51] int t12_st ; [L52] int t13_st ; [L53] int m_i ; [L54] int t1_i ; [L55] int t2_i ; [L56] int t3_i ; [L57] int t4_i ; [L58] int t5_i ; [L59] int t6_i ; [L60] int t7_i ; [L61] int t8_i ; [L62] int t9_i ; [L63] int t10_i ; [L64] int t11_i ; [L65] int t12_i ; [L66] int t13_i ; [L67] int M_E = 2; [L68] int T1_E = 2; [L69] int T2_E = 2; [L70] int T3_E = 2; [L71] int T4_E = 2; [L72] int T5_E = 2; [L73] int T6_E = 2; [L74] int T7_E = 2; [L75] int T8_E = 2; [L76] int T9_E = 2; [L77] int T10_E = 2; [L78] int T11_E = 2; [L79] int T12_E = 2; [L80] int T13_E = 2; [L81] int E_1 = 2; [L82] int E_2 = 2; [L83] int E_3 = 2; [L84] int E_4 = 2; [L85] int E_5 = 2; [L86] int E_6 = 2; [L87] int E_7 = 2; [L88] int E_8 = 2; [L89] int E_9 = 2; [L90] int E_10 = 2; [L91] int E_11 = 2; [L92] int E_12 = 2; [L93] int E_13 = 2; [L1937] int __retres1 ; [L1941] CALL init_model() [L1840] m_i = 1 [L1841] t1_i = 1 [L1842] t2_i = 1 [L1843] t3_i = 1 [L1844] t4_i = 1 [L1845] t5_i = 1 [L1846] t6_i = 1 [L1847] t7_i = 1 [L1848] t8_i = 1 [L1849] t9_i = 1 [L1850] t10_i = 1 [L1851] t11_i = 1 [L1852] t12_i = 1 [L1853] t13_i = 1 [L1941] RET init_model() [L1942] CALL start_simulation() [L1878] int kernel_st ; [L1879] int tmp ; [L1880] int tmp___0 ; [L1884] kernel_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1885] FCALL update_channels() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1886] CALL init_threads() [L881] COND TRUE m_i == 1 [L882] m_st = 0 [L886] COND TRUE t1_i == 1 [L887] t1_st = 0 [L891] COND TRUE t2_i == 1 [L892] t2_st = 0 [L896] COND TRUE t3_i == 1 [L897] t3_st = 0 [L901] COND TRUE t4_i == 1 [L902] t4_st = 0 [L906] COND TRUE t5_i == 1 [L907] t5_st = 0 [L911] COND TRUE t6_i == 1 [L912] t6_st = 0 [L916] COND TRUE t7_i == 1 [L917] t7_st = 0 [L921] COND TRUE t8_i == 1 [L922] t8_st = 0 [L926] COND TRUE t9_i == 1 [L927] t9_st = 0 [L931] COND TRUE t10_i == 1 [L932] t10_st = 0 [L936] COND TRUE t11_i == 1 [L937] t11_st = 0 [L941] COND TRUE t12_i == 1 [L942] t12_st = 0 [L946] COND TRUE t13_i == 1 [L947] t13_st = 0 [L1886] RET init_threads() [L1887] CALL fire_delta_events() VAL [\old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1258] COND FALSE !(M_E == 0) [L1263] COND FALSE !(T1_E == 0) [L1268] COND FALSE !(T2_E == 0) [L1273] COND FALSE !(T3_E == 0) [L1278] COND FALSE !(T4_E == 0) [L1283] COND FALSE !(T5_E == 0) [L1288] COND FALSE !(T6_E == 0) [L1293] COND FALSE !(T7_E == 0) [L1298] COND FALSE !(T8_E == 0) [L1303] COND FALSE !(T9_E == 0) [L1308] COND FALSE !(T10_E == 0) [L1313] COND FALSE !(T11_E == 0) [L1318] COND FALSE !(T12_E == 0) [L1323] COND FALSE !(T13_E == 0) [L1328] COND FALSE !(E_1 == 0) [L1333] COND FALSE !(E_2 == 0) [L1338] COND FALSE !(E_3 == 0) [L1343] COND FALSE !(E_4 == 0) [L1348] COND FALSE !(E_5 == 0) [L1353] COND FALSE !(E_6 == 0) [L1358] COND FALSE !(E_7 == 0) [L1363] COND FALSE !(E_8 == 0) [L1368] COND FALSE !(E_9 == 0) [L1373] COND FALSE !(E_10 == 0) [L1378] COND FALSE !(E_11 == 0) [L1383] COND FALSE !(E_12 == 0) [L1388] COND FALSE !(E_13 == 0) [L1887] RET fire_delta_events() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1888] CALL activate_threads() VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1541] int tmp ; [L1542] int tmp___0 ; [L1543] int tmp___1 ; [L1544] int tmp___2 ; [L1545] int tmp___3 ; [L1546] int tmp___4 ; [L1547] int tmp___5 ; [L1548] int tmp___6 ; [L1549] int tmp___7 ; [L1550] int tmp___8 ; [L1551] int tmp___9 ; [L1552] int tmp___10 ; [L1553] int tmp___11 ; [L1554] int tmp___12 ; [L1558] CALL, EXPR is_master_triggered() [L604] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L607] COND FALSE !(m_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L617] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L619] return (__retres1); [L1558] RET, EXPR is_master_triggered() [L1558] tmp = is_master_triggered() [L1560] COND FALSE !(\read(tmp)) [L1566] CALL, EXPR is_transmit1_triggered() [L623] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L626] COND FALSE !(t1_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L636] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L638] return (__retres1); [L1566] RET, EXPR is_transmit1_triggered() [L1566] tmp___0 = is_transmit1_triggered() [L1568] COND FALSE !(\read(tmp___0)) [L1574] CALL, EXPR is_transmit2_triggered() [L642] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L645] COND FALSE !(t2_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L655] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L657] return (__retres1); [L1574] RET, EXPR is_transmit2_triggered() [L1574] tmp___1 = is_transmit2_triggered() [L1576] COND FALSE !(\read(tmp___1)) [L1582] CALL, EXPR is_transmit3_triggered() [L661] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L664] COND FALSE !(t3_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L674] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L676] return (__retres1); [L1582] RET, EXPR is_transmit3_triggered() [L1582] tmp___2 = is_transmit3_triggered() [L1584] COND FALSE !(\read(tmp___2)) [L1590] CALL, EXPR is_transmit4_triggered() [L680] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L683] COND FALSE !(t4_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L693] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L695] return (__retres1); [L1590] RET, EXPR is_transmit4_triggered() [L1590] tmp___3 = is_transmit4_triggered() [L1592] COND FALSE !(\read(tmp___3)) [L1598] CALL, EXPR is_transmit5_triggered() [L699] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L702] COND FALSE !(t5_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L712] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L714] return (__retres1); [L1598] RET, EXPR is_transmit5_triggered() [L1598] tmp___4 = is_transmit5_triggered() [L1600] COND FALSE !(\read(tmp___4)) [L1606] CALL, EXPR is_transmit6_triggered() [L718] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L721] COND FALSE !(t6_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L731] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L733] return (__retres1); [L1606] RET, EXPR is_transmit6_triggered() [L1606] tmp___5 = is_transmit6_triggered() [L1608] COND FALSE !(\read(tmp___5)) [L1614] CALL, EXPR is_transmit7_triggered() [L737] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L740] COND FALSE !(t7_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L750] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L752] return (__retres1); [L1614] RET, EXPR is_transmit7_triggered() [L1614] tmp___6 = is_transmit7_triggered() [L1616] COND FALSE !(\read(tmp___6)) [L1622] CALL, EXPR is_transmit8_triggered() [L756] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L759] COND FALSE !(t8_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L769] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L771] return (__retres1); [L1622] RET, EXPR is_transmit8_triggered() [L1622] tmp___7 = is_transmit8_triggered() [L1624] COND FALSE !(\read(tmp___7)) [L1630] CALL, EXPR is_transmit9_triggered() [L775] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L778] COND FALSE !(t9_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L788] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L790] return (__retres1); [L1630] RET, EXPR is_transmit9_triggered() [L1630] tmp___8 = is_transmit9_triggered() [L1632] COND FALSE !(\read(tmp___8)) [L1638] CALL, EXPR is_transmit10_triggered() [L794] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L797] COND FALSE !(t10_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L807] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L809] return (__retres1); [L1638] RET, EXPR is_transmit10_triggered() [L1638] tmp___9 = is_transmit10_triggered() [L1640] COND FALSE !(\read(tmp___9)) [L1646] CALL, EXPR is_transmit11_triggered() [L813] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L816] COND FALSE !(t11_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L826] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L828] return (__retres1); [L1646] RET, EXPR is_transmit11_triggered() [L1646] tmp___10 = is_transmit11_triggered() [L1648] COND FALSE !(\read(tmp___10)) [L1654] CALL, EXPR is_transmit12_triggered() [L832] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L835] COND FALSE !(t12_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L845] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L847] return (__retres1); [L1654] RET, EXPR is_transmit12_triggered() [L1654] tmp___11 = is_transmit12_triggered() [L1656] COND FALSE !(\read(tmp___11)) [L1662] CALL, EXPR is_transmit13_triggered() [L851] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L854] COND FALSE !(t13_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L864] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L866] return (__retres1); [L1662] RET, EXPR is_transmit13_triggered() [L1662] tmp___12 = is_transmit13_triggered() [L1664] COND FALSE !(\read(tmp___12)) [L1888] RET activate_threads() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1889] CALL reset_delta_events() VAL [\old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1401] COND FALSE !(M_E == 1) [L1406] COND FALSE !(T1_E == 1) [L1411] COND FALSE !(T2_E == 1) [L1416] COND FALSE !(T3_E == 1) [L1421] COND FALSE !(T4_E == 1) [L1426] COND FALSE !(T5_E == 1) [L1431] COND FALSE !(T6_E == 1) [L1436] COND FALSE !(T7_E == 1) [L1441] COND FALSE !(T8_E == 1) [L1446] COND FALSE !(T9_E == 1) [L1451] COND FALSE !(T10_E == 1) [L1456] COND FALSE !(T11_E == 1) [L1461] COND FALSE !(T12_E == 1) [L1466] COND FALSE !(T13_E == 1) [L1471] COND FALSE !(E_1 == 1) [L1476] COND FALSE !(E_2 == 1) [L1481] COND FALSE !(E_3 == 1) [L1486] COND FALSE !(E_4 == 1) [L1491] COND FALSE !(E_5 == 1) [L1496] COND FALSE !(E_6 == 1) [L1501] COND FALSE !(E_7 == 1) [L1506] COND FALSE !(E_8 == 1) [L1511] COND FALSE !(E_9 == 1) [L1516] COND FALSE !(E_10 == 1) [L1521] COND FALSE !(E_11 == 1) [L1526] COND FALSE !(E_12 == 1) [L1531] COND FALSE !(E_13 == 1) [L1889] RET reset_delta_events() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1892] COND TRUE 1 [L1895] kernel_st = 1 [L1896] CALL eval() [L1037] int tmp ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1041] COND TRUE 1 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1044] CALL, EXPR exists_runnable_thread() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L956] int __retres1 ; [L959] COND TRUE m_st == 0 [L960] __retres1 = 1 [L1032] return (__retres1); [L1044] RET, EXPR exists_runnable_thread() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1044] tmp = exists_runnable_thread() [L1046] COND TRUE \read(tmp) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0, tmp=1] [L1051] COND TRUE m_st == 0 [L1052] int tmp_ndt_1; [L1053] tmp_ndt_1 = __VERIFIER_nondet_int() [L1054] COND FALSE !(\read(tmp_ndt_1)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0, tmp=1, tmp_ndt_1=0] [L1065] COND TRUE t1_st == 0 [L1066] int tmp_ndt_2; [L1067] tmp_ndt_2 = __VERIFIER_nondet_int() [L1068] COND FALSE !(\read(tmp_ndt_2)) [L1074] CALL error() [L21] reach_error() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20ms. Allocated memory is still 127.9MB. Free memory is still 94.1MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 360.08ms. Allocated memory is still 127.9MB. Free memory was 91.8MB in the beginning and 68.5MB in the end (delta: 23.3MB). Peak memory consumption was 23.1MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 42.41ms. Allocated memory is still 127.9MB. Free memory was 68.5MB in the beginning and 64.6MB in the end (delta: 3.9MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 32.36ms. Allocated memory is still 127.9MB. Free memory was 64.6MB in the beginning and 60.4MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 1070.77ms. Allocated memory was 127.9MB in the beginning and 165.7MB in the end (delta: 37.7MB). Free memory was 60.4MB in the beginning and 109.8MB in the end (delta: -49.4MB). Peak memory consumption was 54.2MB. Max. memory is 16.1GB. * CodeCheck took 38244.06ms. Allocated memory was 165.7MB in the beginning and 415.2MB in the end (delta: 249.6MB). Free memory was 109.8MB in the beginning and 133.6MB in the end (delta: -23.9MB). Peak memory consumption was 224.6MB. Max. memory is 16.1GB. * Witness Printer took 111.75ms. Allocated memory is still 415.2MB. Free memory was 133.6MB in the beginning and 339.0MB in the end (delta: -205.4MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. RESULT: Ultimate proved your program to be incorrect! [2022-12-14 18:45:25,444 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_cbebbe10-9140-4cd8-b9a5-2c6ec8f1d51f/bin/ukojak-rkRKPMF4O4/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE