./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.cav14_example_v.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 5e519f3a Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/config/TaipanReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.cav14_example_v.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 5be708e4386faa2194d0a9a7729d1e392e6e7cc3ee8507b4184729819136d34a --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-5e519f3 [2022-11-03 02:43:02,690 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-03 02:43:02,694 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-03 02:43:02,734 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-03 02:43:02,735 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-03 02:43:02,736 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-03 02:43:02,738 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-03 02:43:02,740 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-03 02:43:02,742 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-03 02:43:02,743 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-03 02:43:02,744 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-03 02:43:02,745 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-03 02:43:02,746 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-03 02:43:02,747 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-03 02:43:02,748 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-03 02:43:02,749 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-03 02:43:02,750 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-03 02:43:02,751 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-03 02:43:02,753 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-03 02:43:02,755 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-03 02:43:02,757 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-03 02:43:02,758 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-03 02:43:02,759 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-03 02:43:02,760 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-03 02:43:02,764 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-03 02:43:02,764 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-03 02:43:02,765 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-03 02:43:02,766 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-03 02:43:02,766 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-03 02:43:02,767 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-03 02:43:02,768 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-03 02:43:02,768 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-03 02:43:02,769 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-03 02:43:02,770 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-03 02:43:02,771 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-03 02:43:02,772 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-03 02:43:02,772 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-03 02:43:02,773 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-03 02:43:02,773 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-03 02:43:02,774 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-03 02:43:02,775 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-03 02:43:02,776 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Default.epf [2022-11-03 02:43:02,797 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-03 02:43:02,797 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-03 02:43:02,798 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-03 02:43:02,798 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-03 02:43:02,799 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-11-03 02:43:02,799 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-11-03 02:43:02,799 INFO L138 SettingsManager]: * User list type=DISABLED [2022-11-03 02:43:02,800 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2022-11-03 02:43:02,800 INFO L138 SettingsManager]: * Explicit value domain=true [2022-11-03 02:43:02,800 INFO L138 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2022-11-03 02:43:02,800 INFO L138 SettingsManager]: * Octagon Domain=false [2022-11-03 02:43:02,801 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2022-11-03 02:43:02,801 INFO L138 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2022-11-03 02:43:02,801 INFO L138 SettingsManager]: * Use the RCFG-of-the-future interface=true [2022-11-03 02:43:02,801 INFO L138 SettingsManager]: * Interval Domain=false [2022-11-03 02:43:02,802 INFO L136 SettingsManager]: Preferences of Sifa differ from their defaults: [2022-11-03 02:43:02,802 INFO L138 SettingsManager]: * Call Summarizer=TopInputCallSummarizer [2022-11-03 02:43:02,802 INFO L138 SettingsManager]: * Simplification Technique=POLY_PAC [2022-11-03 02:43:02,803 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-03 02:43:02,803 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-03 02:43:02,804 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-03 02:43:02,804 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-11-03 02:43:02,804 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-11-03 02:43:02,804 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-11-03 02:43:02,805 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-03 02:43:02,805 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-03 02:43:02,805 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-11-03 02:43:02,805 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-03 02:43:02,806 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-11-03 02:43:02,806 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 02:43:02,806 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-03 02:43:02,807 INFO L138 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2022-11-03 02:43:02,807 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-11-03 02:43:02,807 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-11-03 02:43:02,808 INFO L138 SettingsManager]: * Trace refinement strategy=SIFA_TAIPAN [2022-11-03 02:43:02,808 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-11-03 02:43:02,808 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-11-03 02:43:02,808 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-11-03 02:43:02,809 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 5be708e4386faa2194d0a9a7729d1e392e6e7cc3ee8507b4184729819136d34a [2022-11-03 02:43:03,130 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-03 02:43:03,162 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-03 02:43:03,164 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-03 02:43:03,166 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-03 02:43:03,167 INFO L275 PluginConnector]: CDTParser initialized [2022-11-03 02:43:03,169 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.cav14_example_v.c [2022-11-03 02:43:03,269 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/data/37fe35982/eae697a6a71641e3be0ef25427b86501/FLAGfeb9d0769 [2022-11-03 02:43:03,742 INFO L306 CDTParser]: Found 1 translation units. [2022-11-03 02:43:03,743 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.cav14_example_v.c [2022-11-03 02:43:03,751 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/data/37fe35982/eae697a6a71641e3be0ef25427b86501/FLAGfeb9d0769 [2022-11-03 02:43:04,111 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/data/37fe35982/eae697a6a71641e3be0ef25427b86501 [2022-11-03 02:43:04,119 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-03 02:43:04,121 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-03 02:43:04,123 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-03 02:43:04,123 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-03 02:43:04,127 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-03 02:43:04,128 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 02:43:04" (1/1) ... [2022-11-03 02:43:04,131 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@68d7f4d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:43:04, skipping insertion in model container [2022-11-03 02:43:04,131 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 02:43:04" (1/1) ... [2022-11-03 02:43:04,140 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-03 02:43:04,173 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-03 02:43:04,320 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.cav14_example_v.c[1107,1120] [2022-11-03 02:43:04,393 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 02:43:04,397 INFO L203 MainTranslator]: Completed pre-run [2022-11-03 02:43:04,422 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.cav14_example_v.c[1107,1120] [2022-11-03 02:43:04,445 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 02:43:04,460 INFO L208 MainTranslator]: Completed translation [2022-11-03 02:43:04,460 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:43:04 WrapperNode [2022-11-03 02:43:04,460 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-03 02:43:04,462 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-03 02:43:04,462 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-03 02:43:04,462 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-03 02:43:04,470 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:43:04" (1/1) ... [2022-11-03 02:43:04,478 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:43:04" (1/1) ... [2022-11-03 02:43:04,514 INFO L138 Inliner]: procedures = 11, calls = 3, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 115 [2022-11-03 02:43:04,522 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-03 02:43:04,523 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-03 02:43:04,523 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-03 02:43:04,524 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-03 02:43:04,536 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:43:04" (1/1) ... [2022-11-03 02:43:04,537 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:43:04" (1/1) ... [2022-11-03 02:43:04,541 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:43:04" (1/1) ... [2022-11-03 02:43:04,541 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:43:04" (1/1) ... [2022-11-03 02:43:04,548 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:43:04" (1/1) ... [2022-11-03 02:43:04,553 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:43:04" (1/1) ... [2022-11-03 02:43:04,555 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:43:04" (1/1) ... [2022-11-03 02:43:04,557 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:43:04" (1/1) ... [2022-11-03 02:43:04,560 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-03 02:43:04,561 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-03 02:43:04,561 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-03 02:43:04,561 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-03 02:43:04,562 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:43:04" (1/1) ... [2022-11-03 02:43:04,580 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 02:43:04,596 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:43:04,609 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-11-03 02:43:04,615 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-11-03 02:43:04,657 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-03 02:43:04,658 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-03 02:43:04,761 INFO L235 CfgBuilder]: Building ICFG [2022-11-03 02:43:04,764 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-03 02:43:05,133 INFO L276 CfgBuilder]: Performing block encoding [2022-11-03 02:43:05,424 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-03 02:43:05,424 INFO L300 CfgBuilder]: Removed 1 assume(true) statements. [2022-11-03 02:43:05,427 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:43:05 BoogieIcfgContainer [2022-11-03 02:43:05,427 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-03 02:43:05,429 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-11-03 02:43:05,429 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-11-03 02:43:05,433 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-11-03 02:43:05,433 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 03.11 02:43:04" (1/3) ... [2022-11-03 02:43:05,434 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@693d1ac7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 02:43:05, skipping insertion in model container [2022-11-03 02:43:05,434 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:43:04" (2/3) ... [2022-11-03 02:43:05,435 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@693d1ac7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 02:43:05, skipping insertion in model container [2022-11-03 02:43:05,435 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:43:05" (3/3) ... [2022-11-03 02:43:05,436 INFO L112 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.cav14_example_v.c [2022-11-03 02:43:05,482 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-11-03 02:43:05,482 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-11-03 02:43:05,585 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-11-03 02:43:05,593 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@7f802, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-11-03 02:43:05,593 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-11-03 02:43:05,598 INFO L276 IsEmpty]: Start isEmpty. Operand has 7 states, 5 states have (on average 1.6) internal successors, (8), 6 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:43:05,605 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2022-11-03 02:43:05,605 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:43:05,606 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1] [2022-11-03 02:43:05,606 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:43:05,612 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:43:05,613 INFO L85 PathProgramCache]: Analyzing trace with hash 2661427, now seen corresponding path program 1 times [2022-11-03 02:43:05,624 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-03 02:43:05,624 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [703692736] [2022-11-03 02:43:05,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:43:05,625 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-03 02:43:05,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-03 02:43:05,889 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-03 02:43:05,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-03 02:43:06,026 INFO L130 FreeRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2022-11-03 02:43:06,030 INFO L359 BasicCegarLoop]: Counterexample is feasible [2022-11-03 02:43:06,032 INFO L805 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2022-11-03 02:43:06,035 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-11-03 02:43:06,041 INFO L444 BasicCegarLoop]: Path program histogram: [1] [2022-11-03 02:43:06,047 INFO L178 ceAbstractionStarter]: Computing trace abstraction results [2022-11-03 02:43:06,069 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:43:06,080 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 03.11 02:43:06 BoogieIcfgContainer [2022-11-03 02:43:06,080 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2022-11-03 02:43:06,083 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-03 02:43:06,084 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-03 02:43:06,084 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-03 02:43:06,085 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:43:05" (3/4) ... [2022-11-03 02:43:06,091 INFO L140 WitnessPrinter]: No result that supports witness generation found [2022-11-03 02:43:06,091 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-03 02:43:06,094 INFO L158 Benchmark]: Toolchain (without parser) took 1972.67ms. Allocated memory is still 109.1MB. Free memory was 69.7MB in the beginning and 67.5MB in the end (delta: 2.1MB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 02:43:06,095 INFO L158 Benchmark]: CDTParser took 0.30ms. Allocated memory is still 109.1MB. Free memory is still 86.1MB. There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 02:43:06,096 INFO L158 Benchmark]: CACSL2BoogieTranslator took 338.04ms. Allocated memory is still 109.1MB. Free memory was 69.5MB in the beginning and 83.9MB in the end (delta: -14.4MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-11-03 02:43:06,097 INFO L158 Benchmark]: Boogie Procedure Inliner took 60.37ms. Allocated memory is still 109.1MB. Free memory was 83.9MB in the beginning and 81.2MB in the end (delta: 2.7MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-11-03 02:43:06,099 INFO L158 Benchmark]: Boogie Preprocessor took 37.32ms. Allocated memory is still 109.1MB. Free memory was 81.2MB in the beginning and 79.7MB in the end (delta: 1.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-11-03 02:43:06,105 INFO L158 Benchmark]: RCFGBuilder took 866.23ms. Allocated memory is still 109.1MB. Free memory was 79.7MB in the beginning and 45.0MB in the end (delta: 34.7MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. [2022-11-03 02:43:06,105 INFO L158 Benchmark]: TraceAbstraction took 651.38ms. Allocated memory is still 109.1MB. Free memory was 44.4MB in the beginning and 68.0MB in the end (delta: -23.7MB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 02:43:06,108 INFO L158 Benchmark]: Witness Printer took 9.14ms. Allocated memory is still 109.1MB. Free memory was 68.0MB in the beginning and 67.5MB in the end (delta: 486.2kB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 02:43:06,117 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.30ms. Allocated memory is still 109.1MB. Free memory is still 86.1MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 338.04ms. Allocated memory is still 109.1MB. Free memory was 69.5MB in the beginning and 83.9MB in the end (delta: -14.4MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 60.37ms. Allocated memory is still 109.1MB. Free memory was 83.9MB in the beginning and 81.2MB in the end (delta: 2.7MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 37.32ms. Allocated memory is still 109.1MB. Free memory was 81.2MB in the beginning and 79.7MB in the end (delta: 1.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 866.23ms. Allocated memory is still 109.1MB. Free memory was 79.7MB in the beginning and 45.0MB in the end (delta: 34.7MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. * TraceAbstraction took 651.38ms. Allocated memory is still 109.1MB. Free memory was 44.4MB in the beginning and 68.0MB in the end (delta: -23.7MB). There was no memory consumed. Max. memory is 16.1GB. * Witness Printer took 9.14ms. Allocated memory is still 109.1MB. Free memory was 68.0MB in the beginning and 67.5MB in the end (delta: 486.2kB). There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - UnprovableResult [Line: 20]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: overapproximation of bitwiseComplement at line 54, overapproximation of bitwiseAnd at line 59. Possible FailurePath: [L25] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 1); [L26] const SORT_1 msb_SORT_1 = (SORT_1)1 << (1 - 1); [L28] const SORT_3 mask_SORT_3 = (SORT_3)-1 >> (sizeof(SORT_3) * 8 - 4); [L29] const SORT_3 msb_SORT_3 = (SORT_3)1 << (4 - 1); [L31] const SORT_3 var_4 = 0; [L32] const SORT_3 var_7 = 1; [L33] const SORT_1 var_14 = 1; [L34] const SORT_3 var_20 = 15; [L36] SORT_1 input_2; [L38] SORT_3 state_5 = __VERIFIER_nondet_uchar() & mask_SORT_3; [L39] SORT_3 state_8 = __VERIFIER_nondet_uchar() & mask_SORT_3; [L41] SORT_3 init_6_arg_1 = var_4; [L42] state_5 = init_6_arg_1 [L43] SORT_3 init_9_arg_1 = var_7; [L44] state_8 = init_9_arg_1 VAL [init_6_arg_1=0, init_9_arg_1=1, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, state_5=0, state_8=1, var_14=1, var_20=15, var_4=0, var_7=1] [L47] input_2 = __VERIFIER_nondet_uchar() [L50] SORT_3 var_10_arg_0 = state_5; [L51] SORT_3 var_10_arg_1 = state_8; [L52] SORT_1 var_10 = var_10_arg_0 > var_10_arg_1; [L53] SORT_1 var_11_arg_0 = var_10; [L54] SORT_1 var_11 = ~var_11_arg_0; [L55] SORT_1 var_15_arg_0 = var_11; [L56] SORT_1 var_15 = ~var_15_arg_0; [L57] SORT_1 var_16_arg_0 = var_14; [L58] SORT_1 var_16_arg_1 = var_15; [L59] SORT_1 var_16 = var_16_arg_0 & var_16_arg_1; [L60] var_16 = var_16 & mask_SORT_1 [L61] SORT_1 bad_17_arg_0 = var_16; [L62] CALL __VERIFIER_assert(!(bad_17_arg_0)) [L20] COND TRUE !(cond) VAL [\old(cond)=0, cond=0] [L20] reach_error() VAL [\old(cond)=0, cond=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 7 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 0.5s, OverallIterations: 1, TraceHistogramMax: 1, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.0s, AutomataDifference: 0.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: , PredicateUnifierStatistics: No data available, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=7occurred in iteration=0, InterpolantAutomatonStates: 0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 0.0s InterpolantComputationTime, 4 NumberOfCodeBlocks, 4 NumberOfCodeBlocksAsserted, 1 NumberOfCheckSat, 0 ConstructedInterpolants, 0 QuantifiedInterpolants, 0 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 0 InterpolantComputations, 0 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces [2022-11-03 02:43:06,169 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis ### Bit-precise run ### Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/config/TaipanReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.cav14_example_v.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 5be708e4386faa2194d0a9a7729d1e392e6e7cc3ee8507b4184729819136d34a --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-5e519f3 [2022-11-03 02:43:08,677 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-03 02:43:08,681 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-03 02:43:08,718 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-03 02:43:08,719 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-03 02:43:08,723 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-03 02:43:08,724 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-03 02:43:08,726 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-03 02:43:08,728 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-03 02:43:08,735 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-03 02:43:08,737 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-03 02:43:08,740 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-03 02:43:08,740 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-03 02:43:08,743 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-03 02:43:08,745 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-03 02:43:08,747 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-03 02:43:08,749 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-03 02:43:08,750 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-03 02:43:08,752 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-03 02:43:08,760 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-03 02:43:08,765 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-03 02:43:08,766 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-03 02:43:08,768 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-03 02:43:08,770 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-03 02:43:08,778 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-03 02:43:08,782 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-03 02:43:08,783 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-03 02:43:08,784 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-03 02:43:08,785 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-03 02:43:08,786 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-03 02:43:08,787 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-03 02:43:08,788 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-03 02:43:08,789 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-03 02:43:08,790 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-03 02:43:08,791 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-03 02:43:08,792 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-03 02:43:08,793 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-03 02:43:08,793 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-03 02:43:08,793 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-03 02:43:08,795 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-03 02:43:08,796 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-03 02:43:08,797 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Bitvector.epf [2022-11-03 02:43:08,838 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-03 02:43:08,839 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-03 02:43:08,840 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-03 02:43:08,840 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-03 02:43:08,841 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-11-03 02:43:08,842 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-11-03 02:43:08,842 INFO L138 SettingsManager]: * User list type=DISABLED [2022-11-03 02:43:08,842 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2022-11-03 02:43:08,842 INFO L138 SettingsManager]: * Explicit value domain=true [2022-11-03 02:43:08,843 INFO L138 SettingsManager]: * Octagon Domain=false [2022-11-03 02:43:08,844 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2022-11-03 02:43:08,844 INFO L138 SettingsManager]: * Interval Domain=false [2022-11-03 02:43:08,845 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-03 02:43:08,846 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-03 02:43:08,846 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-11-03 02:43:08,846 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-11-03 02:43:08,846 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-11-03 02:43:08,846 INFO L138 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2022-11-03 02:43:08,847 INFO L138 SettingsManager]: * Use bitvectors instead of ints=true [2022-11-03 02:43:08,847 INFO L138 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2022-11-03 02:43:08,847 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-03 02:43:08,847 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-03 02:43:08,848 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-11-03 02:43:08,848 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-03 02:43:08,848 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-03 02:43:08,848 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-11-03 02:43:08,848 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 02:43:08,849 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-03 02:43:08,849 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-11-03 02:43:08,849 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-11-03 02:43:08,849 INFO L138 SettingsManager]: * Trace refinement strategy=WALRUS [2022-11-03 02:43:08,850 INFO L138 SettingsManager]: * Command for external solver=cvc4 --incremental --print-success --lang smt [2022-11-03 02:43:08,850 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-11-03 02:43:08,851 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-11-03 02:43:08,851 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2022-11-03 02:43:08,851 INFO L138 SettingsManager]: * Logic for external solver=AUFBV WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 5be708e4386faa2194d0a9a7729d1e392e6e7cc3ee8507b4184729819136d34a [2022-11-03 02:43:09,269 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-03 02:43:09,305 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-03 02:43:09,308 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-03 02:43:09,309 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-03 02:43:09,310 INFO L275 PluginConnector]: CDTParser initialized [2022-11-03 02:43:09,312 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.cav14_example_v.c [2022-11-03 02:43:09,384 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/data/0d53c27aa/5cf583fcde944044b3922e26f61215f4/FLAGaac2d1c09 [2022-11-03 02:43:09,999 INFO L306 CDTParser]: Found 1 translation units. [2022-11-03 02:43:10,000 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.cav14_example_v.c [2022-11-03 02:43:10,009 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/data/0d53c27aa/5cf583fcde944044b3922e26f61215f4/FLAGaac2d1c09 [2022-11-03 02:43:10,338 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/data/0d53c27aa/5cf583fcde944044b3922e26f61215f4 [2022-11-03 02:43:10,346 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-03 02:43:10,348 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-03 02:43:10,354 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-03 02:43:10,354 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-03 02:43:10,358 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-03 02:43:10,359 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 02:43:10" (1/1) ... [2022-11-03 02:43:10,360 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@72562891 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:43:10, skipping insertion in model container [2022-11-03 02:43:10,360 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 02:43:10" (1/1) ... [2022-11-03 02:43:10,368 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-03 02:43:10,387 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-03 02:43:10,520 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.cav14_example_v.c[1107,1120] [2022-11-03 02:43:10,589 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 02:43:10,592 INFO L203 MainTranslator]: Completed pre-run [2022-11-03 02:43:10,618 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.cav14_example_v.c[1107,1120] [2022-11-03 02:43:10,667 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 02:43:10,684 INFO L208 MainTranslator]: Completed translation [2022-11-03 02:43:10,685 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:43:10 WrapperNode [2022-11-03 02:43:10,685 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-03 02:43:10,686 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-03 02:43:10,686 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-03 02:43:10,686 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-03 02:43:10,693 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:43:10" (1/1) ... [2022-11-03 02:43:10,700 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:43:10" (1/1) ... [2022-11-03 02:43:10,736 INFO L138 Inliner]: procedures = 11, calls = 3, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 115 [2022-11-03 02:43:10,736 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-03 02:43:10,737 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-03 02:43:10,737 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-03 02:43:10,737 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-03 02:43:10,746 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:43:10" (1/1) ... [2022-11-03 02:43:10,747 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:43:10" (1/1) ... [2022-11-03 02:43:10,750 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:43:10" (1/1) ... [2022-11-03 02:43:10,750 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:43:10" (1/1) ... [2022-11-03 02:43:10,756 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:43:10" (1/1) ... [2022-11-03 02:43:10,760 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:43:10" (1/1) ... [2022-11-03 02:43:10,761 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:43:10" (1/1) ... [2022-11-03 02:43:10,763 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:43:10" (1/1) ... [2022-11-03 02:43:10,765 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-03 02:43:10,766 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-03 02:43:10,766 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-03 02:43:10,767 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-03 02:43:10,767 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:43:10" (1/1) ... [2022-11-03 02:43:10,784 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 02:43:10,796 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:43:10,808 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-11-03 02:43:10,822 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-11-03 02:43:10,859 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-03 02:43:10,860 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-03 02:43:10,945 INFO L235 CfgBuilder]: Building ICFG [2022-11-03 02:43:10,947 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-03 02:43:11,269 INFO L276 CfgBuilder]: Performing block encoding [2022-11-03 02:43:11,277 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-03 02:43:11,290 INFO L300 CfgBuilder]: Removed 1 assume(true) statements. [2022-11-03 02:43:11,292 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:43:11 BoogieIcfgContainer [2022-11-03 02:43:11,293 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-03 02:43:11,295 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-11-03 02:43:11,295 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-11-03 02:43:11,298 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-11-03 02:43:11,298 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 03.11 02:43:10" (1/3) ... [2022-11-03 02:43:11,299 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7e5508dd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 02:43:11, skipping insertion in model container [2022-11-03 02:43:11,300 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:43:10" (2/3) ... [2022-11-03 02:43:11,300 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7e5508dd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 02:43:11, skipping insertion in model container [2022-11-03 02:43:11,300 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:43:11" (3/3) ... [2022-11-03 02:43:11,302 INFO L112 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.cav14_example_v.c [2022-11-03 02:43:11,366 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-11-03 02:43:11,366 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-11-03 02:43:11,464 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-11-03 02:43:11,471 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@76a97e45, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-11-03 02:43:11,471 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-11-03 02:43:11,477 INFO L276 IsEmpty]: Start isEmpty. Operand has 19 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 18 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:43:11,484 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2022-11-03 02:43:11,491 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:43:11,492 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2022-11-03 02:43:11,493 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:43:11,504 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:43:11,506 INFO L85 PathProgramCache]: Analyzing trace with hash 28698761, now seen corresponding path program 1 times [2022-11-03 02:43:11,519 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:43:11,520 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1175185496] [2022-11-03 02:43:11,521 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:43:11,521 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:43:11,522 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:43:11,529 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:43:11,535 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (2)] Waiting until timeout for monitored process [2022-11-03 02:43:11,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:43:11,658 WARN L261 TraceCheckSpWp]: Trace formula consists of 31 conjuncts, 16 conjunts are in the unsatisfiable core [2022-11-03 02:43:11,664 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:43:11,952 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:43:11,952 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:43:11,953 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:43:11,954 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1175185496] [2022-11-03 02:43:11,955 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1175185496] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:43:11,955 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:43:11,955 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-03 02:43:11,957 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1170451823] [2022-11-03 02:43:11,958 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:43:11,963 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 02:43:11,963 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:43:12,005 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 02:43:12,007 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 02:43:12,010 INFO L87 Difference]: Start difference. First operand has 19 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 18 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:43:12,091 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:43:12,093 INFO L93 Difference]: Finished difference Result 44 states and 66 transitions. [2022-11-03 02:43:12,095 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 02:43:12,097 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 5 [2022-11-03 02:43:12,098 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:43:12,108 INFO L225 Difference]: With dead ends: 44 [2022-11-03 02:43:12,109 INFO L226 Difference]: Without dead ends: 27 [2022-11-03 02:43:12,117 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:43:12,122 INFO L413 NwaCegarLoop]: 16 mSDtfsCounter, 28 mSDsluCounter, 30 mSDsCounter, 0 mSdLazyCounter, 11 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 28 SdHoareTripleChecker+Valid, 46 SdHoareTripleChecker+Invalid, 11 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 11 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 02:43:12,124 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [28 Valid, 46 Invalid, 11 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 11 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-03 02:43:12,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states. [2022-11-03 02:43:12,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 17. [2022-11-03 02:43:12,164 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 16 states have (on average 1.3125) internal successors, (21), 16 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:43:12,166 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 21 transitions. [2022-11-03 02:43:12,168 INFO L78 Accepts]: Start accepts. Automaton has 17 states and 21 transitions. Word has length 5 [2022-11-03 02:43:12,169 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:43:12,169 INFO L495 AbstractCegarLoop]: Abstraction has 17 states and 21 transitions. [2022-11-03 02:43:12,169 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:43:12,170 INFO L276 IsEmpty]: Start isEmpty. Operand 17 states and 21 transitions. [2022-11-03 02:43:12,171 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-11-03 02:43:12,171 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:43:12,172 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:43:12,186 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (2)] Forceful destruction successful, exit code 0 [2022-11-03 02:43:12,384 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:43:12,384 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:43:12,385 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:43:12,385 INFO L85 PathProgramCache]: Analyzing trace with hash -1667101803, now seen corresponding path program 1 times [2022-11-03 02:43:12,389 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:43:12,390 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1563374783] [2022-11-03 02:43:12,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:43:12,391 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:43:12,391 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:43:12,395 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:43:12,438 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (3)] Waiting until timeout for monitored process [2022-11-03 02:43:12,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:43:12,521 INFO L263 TraceCheckSpWp]: Trace formula consists of 104 conjuncts, 7 conjunts are in the unsatisfiable core [2022-11-03 02:43:12,526 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:43:12,627 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:43:12,628 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:43:12,628 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:43:12,628 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1563374783] [2022-11-03 02:43:12,629 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1563374783] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:43:12,629 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:43:12,630 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 02:43:12,630 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1741501165] [2022-11-03 02:43:12,631 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:43:12,633 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:43:12,634 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:43:12,635 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:43:12,636 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:43:12,638 INFO L87 Difference]: Start difference. First operand 17 states and 21 transitions. Second operand has 5 states, 5 states have (on average 3.2) internal successors, (16), 5 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:43:12,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:43:12,741 INFO L93 Difference]: Finished difference Result 60 states and 77 transitions. [2022-11-03 02:43:12,742 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 02:43:12,742 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 3.2) internal successors, (16), 5 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 16 [2022-11-03 02:43:12,743 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:43:12,743 INFO L225 Difference]: With dead ends: 60 [2022-11-03 02:43:12,744 INFO L226 Difference]: Without dead ends: 47 [2022-11-03 02:43:12,744 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 12 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:43:12,746 INFO L413 NwaCegarLoop]: 26 mSDtfsCounter, 48 mSDsluCounter, 51 mSDsCounter, 0 mSdLazyCounter, 20 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 48 SdHoareTripleChecker+Valid, 77 SdHoareTripleChecker+Invalid, 21 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 20 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 02:43:12,746 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [48 Valid, 77 Invalid, 21 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 20 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-03 02:43:12,747 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2022-11-03 02:43:12,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 25. [2022-11-03 02:43:12,751 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 24 states have (on average 1.3333333333333333) internal successors, (32), 24 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:43:12,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 32 transitions. [2022-11-03 02:43:12,753 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 32 transitions. Word has length 16 [2022-11-03 02:43:12,754 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:43:12,754 INFO L495 AbstractCegarLoop]: Abstraction has 25 states and 32 transitions. [2022-11-03 02:43:12,755 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 3.2) internal successors, (16), 5 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:43:12,759 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 32 transitions. [2022-11-03 02:43:12,761 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-11-03 02:43:12,761 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:43:12,761 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:43:12,786 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (3)] Forceful destruction successful, exit code 0 [2022-11-03 02:43:12,973 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:43:12,974 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:43:12,974 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:43:12,974 INFO L85 PathProgramCache]: Analyzing trace with hash -1665254761, now seen corresponding path program 1 times [2022-11-03 02:43:12,975 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:43:12,975 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [192380942] [2022-11-03 02:43:12,975 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:43:12,976 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:43:12,976 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:43:12,977 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:43:12,981 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (4)] Waiting until timeout for monitored process [2022-11-03 02:43:13,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:43:13,076 INFO L263 TraceCheckSpWp]: Trace formula consists of 104 conjuncts, 25 conjunts are in the unsatisfiable core [2022-11-03 02:43:13,082 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:43:13,408 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:43:13,408 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:43:13,876 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:43:13,876 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:43:13,876 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [192380942] [2022-11-03 02:43:13,877 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [192380942] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:43:13,877 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [461942876] [2022-11-03 02:43:13,877 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:43:13,877 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:43:13,878 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:43:13,880 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:43:13,922 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (5)] Waiting until timeout for monitored process [2022-11-03 02:43:14,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:43:14,040 INFO L263 TraceCheckSpWp]: Trace formula consists of 104 conjuncts, 40 conjunts are in the unsatisfiable core [2022-11-03 02:43:14,043 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:43:14,633 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:43:14,633 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:43:15,569 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:43:15,569 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [461942876] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:43:15,569 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1931943560] [2022-11-03 02:43:15,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:43:15,570 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:43:15,570 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:43:15,576 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:43:15,598 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-11-03 02:43:15,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:43:15,666 INFO L263 TraceCheckSpWp]: Trace formula consists of 104 conjuncts, 28 conjunts are in the unsatisfiable core [2022-11-03 02:43:15,672 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:43:15,879 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:43:15,879 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:43:16,173 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:43:16,173 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1931943560] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:43:16,174 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:43:16,174 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 13, 13, 11, 11] total 40 [2022-11-03 02:43:16,174 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2027009704] [2022-11-03 02:43:16,174 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:43:16,177 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 40 states [2022-11-03 02:43:16,177 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:43:16,177 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2022-11-03 02:43:16,179 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=172, Invalid=1388, Unknown=0, NotChecked=0, Total=1560 [2022-11-03 02:43:16,179 INFO L87 Difference]: Start difference. First operand 25 states and 32 transitions. Second operand has 40 states, 40 states have (on average 1.5) internal successors, (60), 40 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:43:18,453 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:43:18,454 INFO L93 Difference]: Finished difference Result 105 states and 139 transitions. [2022-11-03 02:43:18,454 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2022-11-03 02:43:18,454 INFO L78 Accepts]: Start accepts. Automaton has has 40 states, 40 states have (on average 1.5) internal successors, (60), 40 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 16 [2022-11-03 02:43:18,454 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:43:18,456 INFO L225 Difference]: With dead ends: 105 [2022-11-03 02:43:18,457 INFO L226 Difference]: Without dead ends: 103 [2022-11-03 02:43:18,462 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 125 GetRequests, 58 SyntacticMatches, 1 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1148 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=669, Invalid=3887, Unknown=0, NotChecked=0, Total=4556 [2022-11-03 02:43:18,466 INFO L413 NwaCegarLoop]: 19 mSDtfsCounter, 377 mSDsluCounter, 404 mSDsCounter, 0 mSdLazyCounter, 122 mSolverCounterSat, 29 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 377 SdHoareTripleChecker+Valid, 423 SdHoareTripleChecker+Invalid, 581 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 29 IncrementalHoareTripleChecker+Valid, 122 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 430 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 02:43:18,470 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [377 Valid, 423 Invalid, 581 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [29 Valid, 122 Invalid, 0 Unknown, 430 Unchecked, 0.2s Time] [2022-11-03 02:43:18,470 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 103 states. [2022-11-03 02:43:18,487 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 103 to 42. [2022-11-03 02:43:18,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 41 states have (on average 1.3414634146341464) internal successors, (55), 41 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:43:18,493 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 55 transitions. [2022-11-03 02:43:18,494 INFO L78 Accepts]: Start accepts. Automaton has 42 states and 55 transitions. Word has length 16 [2022-11-03 02:43:18,494 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:43:18,495 INFO L495 AbstractCegarLoop]: Abstraction has 42 states and 55 transitions. [2022-11-03 02:43:18,496 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 40 states, 40 states have (on average 1.5) internal successors, (60), 40 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:43:18,497 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 55 transitions. [2022-11-03 02:43:18,498 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-11-03 02:43:18,498 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:43:18,498 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:43:18,542 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2022-11-03 02:43:18,712 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (5)] Forceful destruction successful, exit code 0 [2022-11-03 02:43:18,924 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (4)] Forceful destruction successful, exit code 0 [2022-11-03 02:43:19,110 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:43:19,111 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:43:19,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:43:19,111 INFO L85 PathProgramCache]: Analyzing trace with hash 1949654165, now seen corresponding path program 1 times [2022-11-03 02:43:19,112 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:43:19,112 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [667993696] [2022-11-03 02:43:19,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:43:19,112 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:43:19,113 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:43:19,114 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:43:19,127 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (7)] Waiting until timeout for monitored process [2022-11-03 02:43:19,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:43:19,185 INFO L263 TraceCheckSpWp]: Trace formula consists of 104 conjuncts, 11 conjunts are in the unsatisfiable core [2022-11-03 02:43:19,187 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:43:19,228 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:43:19,229 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:43:19,229 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:43:19,229 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [667993696] [2022-11-03 02:43:19,229 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [667993696] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:43:19,230 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:43:19,230 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 02:43:19,230 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1005368741] [2022-11-03 02:43:19,230 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:43:19,231 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:43:19,231 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:43:19,231 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:43:19,232 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:43:19,232 INFO L87 Difference]: Start difference. First operand 42 states and 55 transitions. Second operand has 5 states, 5 states have (on average 3.2) internal successors, (16), 5 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:43:19,300 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:43:19,300 INFO L93 Difference]: Finished difference Result 81 states and 102 transitions. [2022-11-03 02:43:19,301 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 02:43:19,301 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 3.2) internal successors, (16), 5 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 16 [2022-11-03 02:43:19,301 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:43:19,302 INFO L225 Difference]: With dead ends: 81 [2022-11-03 02:43:19,302 INFO L226 Difference]: Without dead ends: 64 [2022-11-03 02:43:19,302 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 12 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:43:19,303 INFO L413 NwaCegarLoop]: 19 mSDtfsCounter, 49 mSDsluCounter, 45 mSDsCounter, 0 mSdLazyCounter, 20 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 49 SdHoareTripleChecker+Valid, 64 SdHoareTripleChecker+Invalid, 21 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 20 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 02:43:19,304 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [49 Valid, 64 Invalid, 21 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 20 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-03 02:43:19,305 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2022-11-03 02:43:19,310 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 42. [2022-11-03 02:43:19,311 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 41 states have (on average 1.2926829268292683) internal successors, (53), 41 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:43:19,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 53 transitions. [2022-11-03 02:43:19,312 INFO L78 Accepts]: Start accepts. Automaton has 42 states and 53 transitions. Word has length 16 [2022-11-03 02:43:19,312 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:43:19,312 INFO L495 AbstractCegarLoop]: Abstraction has 42 states and 53 transitions. [2022-11-03 02:43:19,312 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 3.2) internal successors, (16), 5 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:43:19,312 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 53 transitions. [2022-11-03 02:43:19,313 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-11-03 02:43:19,313 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:43:19,313 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:43:19,326 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (7)] Forceful destruction successful, exit code 0 [2022-11-03 02:43:19,524 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:43:19,525 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:43:19,525 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:43:19,525 INFO L85 PathProgramCache]: Analyzing trace with hash -964190183, now seen corresponding path program 1 times [2022-11-03 02:43:19,525 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:43:19,525 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [258899681] [2022-11-03 02:43:19,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:43:19,526 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:43:19,526 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:43:19,527 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:43:19,561 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (8)] Waiting until timeout for monitored process [2022-11-03 02:43:19,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:43:19,597 INFO L263 TraceCheckSpWp]: Trace formula consists of 104 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-03 02:43:19,599 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:43:19,644 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:43:19,645 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:43:19,645 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:43:19,645 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [258899681] [2022-11-03 02:43:19,645 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [258899681] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:43:19,645 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:43:19,646 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-03 02:43:19,646 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [59368930] [2022-11-03 02:43:19,646 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:43:19,646 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 02:43:19,647 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:43:19,647 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 02:43:19,647 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 02:43:19,647 INFO L87 Difference]: Start difference. First operand 42 states and 53 transitions. Second operand has 4 states, 4 states have (on average 4.0) internal successors, (16), 4 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:43:19,679 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:43:19,679 INFO L93 Difference]: Finished difference Result 55 states and 70 transitions. [2022-11-03 02:43:19,680 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-03 02:43:19,680 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 4.0) internal successors, (16), 4 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 16 [2022-11-03 02:43:19,680 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:43:19,681 INFO L225 Difference]: With dead ends: 55 [2022-11-03 02:43:19,681 INFO L226 Difference]: Without dead ends: 36 [2022-11-03 02:43:19,681 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 13 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:43:19,682 INFO L413 NwaCegarLoop]: 16 mSDtfsCounter, 1 mSDsluCounter, 26 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 42 SdHoareTripleChecker+Invalid, 12 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 5 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 02:43:19,683 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 42 Invalid, 12 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 7 Invalid, 0 Unknown, 5 Unchecked, 0.0s Time] [2022-11-03 02:43:19,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2022-11-03 02:43:19,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2022-11-03 02:43:19,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36 states, 35 states have (on average 1.2857142857142858) internal successors, (45), 35 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:43:19,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 45 transitions. [2022-11-03 02:43:19,689 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 45 transitions. Word has length 16 [2022-11-03 02:43:19,689 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:43:19,690 INFO L495 AbstractCegarLoop]: Abstraction has 36 states and 45 transitions. [2022-11-03 02:43:19,690 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 4.0) internal successors, (16), 4 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:43:19,690 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 45 transitions. [2022-11-03 02:43:19,691 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2022-11-03 02:43:19,691 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:43:19,691 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:43:19,707 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (8)] Forceful destruction successful, exit code 0 [2022-11-03 02:43:19,902 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:43:19,903 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:43:19,903 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:43:19,903 INFO L85 PathProgramCache]: Analyzing trace with hash 1992337093, now seen corresponding path program 1 times [2022-11-03 02:43:19,904 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:43:19,904 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1782839992] [2022-11-03 02:43:19,904 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:43:19,904 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:43:19,904 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:43:19,905 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:43:19,909 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (9)] Waiting until timeout for monitored process [2022-11-03 02:43:19,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:43:19,992 INFO L263 TraceCheckSpWp]: Trace formula consists of 177 conjuncts, 31 conjunts are in the unsatisfiable core [2022-11-03 02:43:19,995 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:43:20,312 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 9 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:43:20,312 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:43:20,737 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 9 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:43:20,737 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:43:20,737 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1782839992] [2022-11-03 02:43:20,737 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1782839992] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:43:20,737 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [209734339] [2022-11-03 02:43:20,737 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:43:20,738 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:43:20,738 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:43:20,739 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:43:20,744 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (10)] Waiting until timeout for monitored process [2022-11-03 02:43:20,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:43:20,894 INFO L263 TraceCheckSpWp]: Trace formula consists of 177 conjuncts, 32 conjunts are in the unsatisfiable core [2022-11-03 02:43:20,897 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:43:21,035 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 9 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:43:21,035 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:43:21,103 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 9 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:43:21,104 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [209734339] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:43:21,104 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [101107460] [2022-11-03 02:43:21,104 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:43:21,104 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:43:21,104 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:43:21,105 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:43:21,130 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2022-11-03 02:43:21,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:43:21,194 INFO L263 TraceCheckSpWp]: Trace formula consists of 177 conjuncts, 31 conjunts are in the unsatisfiable core [2022-11-03 02:43:21,196 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:43:21,314 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 9 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:43:21,315 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:43:21,373 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 9 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:43:21,374 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [101107460] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:43:21,374 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:43:21,374 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14, 14] total 24 [2022-11-03 02:43:21,374 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [709916157] [2022-11-03 02:43:21,375 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:43:21,375 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 24 states [2022-11-03 02:43:21,375 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:43:21,376 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2022-11-03 02:43:21,376 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=56, Invalid=496, Unknown=0, NotChecked=0, Total=552 [2022-11-03 02:43:21,376 INFO L87 Difference]: Start difference. First operand 36 states and 45 transitions. Second operand has 24 states, 24 states have (on average 1.75) internal successors, (42), 24 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:43:23,033 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:43:23,033 INFO L93 Difference]: Finished difference Result 146 states and 186 transitions. [2022-11-03 02:43:23,034 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2022-11-03 02:43:23,034 INFO L78 Accepts]: Start accepts. Automaton has has 24 states, 24 states have (on average 1.75) internal successors, (42), 24 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 27 [2022-11-03 02:43:23,034 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:43:23,035 INFO L225 Difference]: With dead ends: 146 [2022-11-03 02:43:23,035 INFO L226 Difference]: Without dead ends: 133 [2022-11-03 02:43:23,041 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 183 GetRequests, 134 SyntacticMatches, 0 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 444 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=477, Invalid=2073, Unknown=0, NotChecked=0, Total=2550 [2022-11-03 02:43:23,041 INFO L413 NwaCegarLoop]: 12 mSDtfsCounter, 281 mSDsluCounter, 277 mSDsCounter, 0 mSdLazyCounter, 346 mSolverCounterSat, 94 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 281 SdHoareTripleChecker+Valid, 289 SdHoareTripleChecker+Invalid, 440 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 94 IncrementalHoareTripleChecker+Valid, 346 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-11-03 02:43:23,042 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [281 Valid, 289 Invalid, 440 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [94 Valid, 346 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2022-11-03 02:43:23,043 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133 states. [2022-11-03 02:43:23,051 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133 to 58. [2022-11-03 02:43:23,052 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 58 states, 57 states have (on average 1.2456140350877194) internal successors, (71), 57 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:43:23,053 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 71 transitions. [2022-11-03 02:43:23,053 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 71 transitions. Word has length 27 [2022-11-03 02:43:23,053 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:43:23,053 INFO L495 AbstractCegarLoop]: Abstraction has 58 states and 71 transitions. [2022-11-03 02:43:23,053 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 24 states, 24 states have (on average 1.75) internal successors, (42), 24 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:43:23,054 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 71 transitions. [2022-11-03 02:43:23,054 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2022-11-03 02:43:23,054 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:43:23,055 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:43:23,081 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Forceful destruction successful, exit code 0 [2022-11-03 02:43:23,278 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (9)] Forceful destruction successful, exit code 0 [2022-11-03 02:43:23,472 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (10)] Forceful destruction successful, exit code 0 [2022-11-03 02:43:23,670 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt [2022-11-03 02:43:23,671 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:43:23,671 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:43:23,671 INFO L85 PathProgramCache]: Analyzing trace with hash -921507255, now seen corresponding path program 1 times [2022-11-03 02:43:23,671 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:43:23,672 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1249629832] [2022-11-03 02:43:23,672 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:43:23,672 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:43:23,672 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:43:23,673 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:43:23,679 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (12)] Waiting until timeout for monitored process [2022-11-03 02:43:23,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:43:23,767 INFO L263 TraceCheckSpWp]: Trace formula consists of 177 conjuncts, 23 conjunts are in the unsatisfiable core [2022-11-03 02:43:23,768 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:43:23,993 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 11 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:43:23,993 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:43:24,448 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 11 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:43:24,449 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:43:24,449 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1249629832] [2022-11-03 02:43:24,449 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1249629832] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:43:24,449 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1243457239] [2022-11-03 02:43:24,449 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:43:24,450 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:43:24,450 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:43:24,451 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:43:24,459 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (13)] Waiting until timeout for monitored process [2022-11-03 02:43:24,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:43:24,613 INFO L263 TraceCheckSpWp]: Trace formula consists of 177 conjuncts, 23 conjunts are in the unsatisfiable core [2022-11-03 02:43:24,616 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:43:24,766 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 11 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:43:24,766 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:43:24,928 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 11 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:43:24,928 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1243457239] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:43:24,928 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [420208458] [2022-11-03 02:43:24,929 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:43:24,929 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:43:24,929 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:43:24,931 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:43:24,939 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2022-11-03 02:43:25,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:43:25,017 INFO L263 TraceCheckSpWp]: Trace formula consists of 177 conjuncts, 16 conjunts are in the unsatisfiable core [2022-11-03 02:43:25,019 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:43:25,321 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 5 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:43:25,321 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:43:25,605 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 8 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:43:25,605 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [420208458] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:43:25,605 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:43:25,605 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 11, 11] total 30 [2022-11-03 02:43:25,606 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [942987202] [2022-11-03 02:43:25,606 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:43:25,607 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 30 states [2022-11-03 02:43:25,607 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:43:25,607 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2022-11-03 02:43:25,608 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=72, Invalid=798, Unknown=0, NotChecked=0, Total=870 [2022-11-03 02:43:25,608 INFO L87 Difference]: Start difference. First operand 58 states and 71 transitions. Second operand has 30 states, 30 states have (on average 2.433333333333333) internal successors, (73), 30 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:43:26,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:43:26,768 INFO L93 Difference]: Finished difference Result 116 states and 146 transitions. [2022-11-03 02:43:26,769 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2022-11-03 02:43:26,769 INFO L78 Accepts]: Start accepts. Automaton has has 30 states, 30 states have (on average 2.433333333333333) internal successors, (73), 30 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 27 [2022-11-03 02:43:26,769 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:43:26,770 INFO L225 Difference]: With dead ends: 116 [2022-11-03 02:43:26,770 INFO L226 Difference]: Without dead ends: 90 [2022-11-03 02:43:26,772 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 186 GetRequests, 127 SyntacticMatches, 2 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 559 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=480, Invalid=2942, Unknown=0, NotChecked=0, Total=3422 [2022-11-03 02:43:26,773 INFO L413 NwaCegarLoop]: 23 mSDtfsCounter, 189 mSDsluCounter, 410 mSDsCounter, 0 mSdLazyCounter, 158 mSolverCounterSat, 54 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 189 SdHoareTripleChecker+Valid, 433 SdHoareTripleChecker+Invalid, 399 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 54 IncrementalHoareTripleChecker+Valid, 158 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 187 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 02:43:26,773 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [189 Valid, 433 Invalid, 399 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [54 Valid, 158 Invalid, 0 Unknown, 187 Unchecked, 0.2s Time] [2022-11-03 02:43:26,774 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states. [2022-11-03 02:43:26,782 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 64. [2022-11-03 02:43:26,783 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64 states, 63 states have (on average 1.2380952380952381) internal successors, (78), 63 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:43:26,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 78 transitions. [2022-11-03 02:43:26,783 INFO L78 Accepts]: Start accepts. Automaton has 64 states and 78 transitions. Word has length 27 [2022-11-03 02:43:26,784 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:43:26,784 INFO L495 AbstractCegarLoop]: Abstraction has 64 states and 78 transitions. [2022-11-03 02:43:26,784 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 30 states, 30 states have (on average 2.433333333333333) internal successors, (73), 30 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:43:26,784 INFO L276 IsEmpty]: Start isEmpty. Operand 64 states and 78 transitions. [2022-11-03 02:43:26,785 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2022-11-03 02:43:26,785 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:43:26,785 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:43:26,796 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (12)] Ended with exit code 0 [2022-11-03 02:43:26,998 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (13)] Forceful destruction successful, exit code 0 [2022-11-03 02:43:27,224 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Forceful destruction successful, exit code 0 [2022-11-03 02:43:27,396 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,13 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,14 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:43:27,396 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:43:27,397 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:43:27,397 INFO L85 PathProgramCache]: Analyzing trace with hash 39429, now seen corresponding path program 1 times [2022-11-03 02:43:27,397 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:43:27,397 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1479481246] [2022-11-03 02:43:27,397 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:43:27,398 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:43:27,398 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:43:27,399 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:43:27,400 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (15)] Waiting until timeout for monitored process [2022-11-03 02:43:27,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:43:27,471 INFO L263 TraceCheckSpWp]: Trace formula consists of 177 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-03 02:43:27,472 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:43:27,540 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2022-11-03 02:43:27,541 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:43:27,541 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:43:27,541 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1479481246] [2022-11-03 02:43:27,541 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1479481246] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:43:27,541 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:43:27,541 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-03 02:43:27,542 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [9451953] [2022-11-03 02:43:27,542 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:43:27,542 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 02:43:27,542 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:43:27,543 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 02:43:27,543 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 02:43:27,543 INFO L87 Difference]: Start difference. First operand 64 states and 78 transitions. Second operand has 4 states, 4 states have (on average 5.75) internal successors, (23), 4 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:43:27,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:43:27,582 INFO L93 Difference]: Finished difference Result 94 states and 117 transitions. [2022-11-03 02:43:27,582 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-03 02:43:27,583 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 5.75) internal successors, (23), 4 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 27 [2022-11-03 02:43:27,583 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:43:27,584 INFO L225 Difference]: With dead ends: 94 [2022-11-03 02:43:27,584 INFO L226 Difference]: Without dead ends: 64 [2022-11-03 02:43:27,584 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 24 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:43:27,585 INFO L413 NwaCegarLoop]: 15 mSDtfsCounter, 1 mSDsluCounter, 25 mSDsCounter, 0 mSdLazyCounter, 8 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 40 SdHoareTripleChecker+Invalid, 14 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 8 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 6 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 02:43:27,585 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 40 Invalid, 14 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 8 Invalid, 0 Unknown, 6 Unchecked, 0.0s Time] [2022-11-03 02:43:27,586 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2022-11-03 02:43:27,594 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 64. [2022-11-03 02:43:27,594 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64 states, 63 states have (on average 1.2222222222222223) internal successors, (77), 63 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:43:27,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 77 transitions. [2022-11-03 02:43:27,595 INFO L78 Accepts]: Start accepts. Automaton has 64 states and 77 transitions. Word has length 27 [2022-11-03 02:43:27,595 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:43:27,595 INFO L495 AbstractCegarLoop]: Abstraction has 64 states and 77 transitions. [2022-11-03 02:43:27,596 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 5.75) internal successors, (23), 4 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:43:27,596 INFO L276 IsEmpty]: Start isEmpty. Operand 64 states and 77 transitions. [2022-11-03 02:43:27,597 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2022-11-03 02:43:27,597 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:43:27,597 INFO L195 NwaCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1] [2022-11-03 02:43:27,615 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (15)] Forceful destruction successful, exit code 0 [2022-11-03 02:43:27,809 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:43:27,809 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:43:27,809 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:43:27,810 INFO L85 PathProgramCache]: Analyzing trace with hash -896643689, now seen corresponding path program 2 times [2022-11-03 02:43:27,810 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:43:27,810 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [2090452031] [2022-11-03 02:43:27,810 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-03 02:43:27,811 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:43:27,811 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:43:27,812 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:43:27,816 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (16)] Waiting until timeout for monitored process [2022-11-03 02:43:27,918 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-03 02:43:27,918 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:43:27,924 INFO L263 TraceCheckSpWp]: Trace formula consists of 250 conjuncts, 16 conjunts are in the unsatisfiable core [2022-11-03 02:43:27,926 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:43:28,054 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 26 proven. 10 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-11-03 02:43:28,055 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:43:28,206 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 29 proven. 7 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-11-03 02:43:28,207 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:43:28,207 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [2090452031] [2022-11-03 02:43:28,207 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [2090452031] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:43:28,207 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [984112239] [2022-11-03 02:43:28,207 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-03 02:43:28,208 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:43:28,208 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:43:28,209 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:43:28,212 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (17)] Waiting until timeout for monitored process [2022-11-03 02:43:28,385 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-03 02:43:28,385 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:43:28,389 INFO L263 TraceCheckSpWp]: Trace formula consists of 250 conjuncts, 72 conjunts are in the unsatisfiable core [2022-11-03 02:43:28,392 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:43:29,960 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 35 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-11-03 02:43:29,960 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:43:34,062 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 39 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:43:34,062 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [984112239] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:43:34,062 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1385576067] [2022-11-03 02:43:34,063 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-03 02:43:34,063 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:43:34,063 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:43:34,064 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:43:34,065 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2022-11-03 02:43:34,159 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-03 02:43:34,159 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:43:34,162 INFO L263 TraceCheckSpWp]: Trace formula consists of 250 conjuncts, 16 conjunts are in the unsatisfiable core [2022-11-03 02:43:34,164 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:43:34,230 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 26 proven. 10 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-11-03 02:43:34,231 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:43:34,286 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 29 proven. 7 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-11-03 02:43:34,286 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1385576067] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:43:34,287 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:43:34,287 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 27, 29, 11, 11] total 68 [2022-11-03 02:43:34,287 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1012221819] [2022-11-03 02:43:34,287 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:43:34,288 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 68 states [2022-11-03 02:43:34,288 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:43:34,290 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2022-11-03 02:43:34,291 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=244, Invalid=4312, Unknown=0, NotChecked=0, Total=4556 [2022-11-03 02:43:34,292 INFO L87 Difference]: Start difference. First operand 64 states and 77 transitions. Second operand has 68 states, 68 states have (on average 1.661764705882353) internal successors, (113), 68 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:43:40,936 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:43:40,936 INFO L93 Difference]: Finished difference Result 172 states and 210 transitions. [2022-11-03 02:43:40,937 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2022-11-03 02:43:40,937 INFO L78 Accepts]: Start accepts. Automaton has has 68 states, 68 states have (on average 1.661764705882353) internal successors, (113), 68 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 38 [2022-11-03 02:43:40,937 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:43:40,938 INFO L225 Difference]: With dead ends: 172 [2022-11-03 02:43:40,938 INFO L226 Difference]: Without dead ends: 142 [2022-11-03 02:43:40,942 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 290 GetRequests, 168 SyntacticMatches, 3 SemanticMatches, 119 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3569 ImplicationChecksByTransitivity, 11.1s TimeCoverageRelationStatistics Valid=1437, Invalid=13083, Unknown=0, NotChecked=0, Total=14520 [2022-11-03 02:43:40,943 INFO L413 NwaCegarLoop]: 13 mSDtfsCounter, 489 mSDsluCounter, 658 mSDsCounter, 0 mSdLazyCounter, 367 mSolverCounterSat, 120 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 489 SdHoareTripleChecker+Valid, 671 SdHoareTripleChecker+Invalid, 1402 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 120 IncrementalHoareTripleChecker+Valid, 367 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 915 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-11-03 02:43:40,943 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [489 Valid, 671 Invalid, 1402 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [120 Valid, 367 Invalid, 0 Unknown, 915 Unchecked, 0.4s Time] [2022-11-03 02:43:40,944 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142 states. [2022-11-03 02:43:40,953 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142 to 62. [2022-11-03 02:43:40,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62 states, 61 states have (on average 1.1967213114754098) internal successors, (73), 61 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:43:40,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 73 transitions. [2022-11-03 02:43:40,954 INFO L78 Accepts]: Start accepts. Automaton has 62 states and 73 transitions. Word has length 38 [2022-11-03 02:43:40,955 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:43:40,955 INFO L495 AbstractCegarLoop]: Abstraction has 62 states and 73 transitions. [2022-11-03 02:43:40,955 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 68 states, 68 states have (on average 1.661764705882353) internal successors, (113), 68 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:43:40,955 INFO L276 IsEmpty]: Start isEmpty. Operand 62 states and 73 transitions. [2022-11-03 02:43:40,956 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2022-11-03 02:43:40,956 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:43:40,956 INFO L195 NwaCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1] [2022-11-03 02:43:40,980 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (16)] Forceful destruction successful, exit code 0 [2022-11-03 02:43:41,194 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Forceful destruction successful, exit code 0 [2022-11-03 02:43:41,375 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (17)] Forceful destruction successful, exit code 0 [2022-11-03 02:43:41,569 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 16 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,18 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,17 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt [2022-11-03 02:43:41,569 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:43:41,569 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:43:41,569 INFO L85 PathProgramCache]: Analyzing trace with hash -536589095, now seen corresponding path program 1 times [2022-11-03 02:43:41,570 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:43:41,570 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [86571729] [2022-11-03 02:43:41,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:43:41,570 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:43:41,570 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:43:41,571 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:43:41,584 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (19)] Waiting until timeout for monitored process [2022-11-03 02:43:41,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:43:41,694 INFO L263 TraceCheckSpWp]: Trace formula consists of 250 conjuncts, 34 conjunts are in the unsatisfiable core [2022-11-03 02:43:41,696 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:43:42,215 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 20 proven. 19 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:43:42,215 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:43:43,439 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 20 proven. 19 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:43:43,439 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:43:43,439 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [86571729] [2022-11-03 02:43:43,440 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [86571729] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:43:43,440 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [204786764] [2022-11-03 02:43:43,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:43:43,440 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:43:43,440 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:43:43,441 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:43:43,466 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (20)] Waiting until timeout for monitored process [2022-11-03 02:43:43,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:43:43,661 INFO L263 TraceCheckSpWp]: Trace formula consists of 250 conjuncts, 34 conjunts are in the unsatisfiable core [2022-11-03 02:43:43,663 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:43:43,944 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 20 proven. 19 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:43:43,945 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:43:44,216 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 20 proven. 19 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:43:44,217 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [204786764] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:43:44,217 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [698791859] [2022-11-03 02:43:44,217 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:43:44,217 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:43:44,218 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:43:44,219 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:43:44,234 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2022-11-03 02:43:44,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:43:44,338 INFO L263 TraceCheckSpWp]: Trace formula consists of 250 conjuncts, 62 conjunts are in the unsatisfiable core [2022-11-03 02:43:44,341 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:43:46,457 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 39 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:43:46,458 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:43:50,762 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 39 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:43:50,762 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [698791859] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:43:50,762 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:43:50,762 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 24, 24] total 70 [2022-11-03 02:43:50,763 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [611262640] [2022-11-03 02:43:50,763 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:43:50,763 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 70 states [2022-11-03 02:43:50,764 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:43:50,764 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2022-11-03 02:43:50,765 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=231, Invalid=4599, Unknown=0, NotChecked=0, Total=4830 [2022-11-03 02:43:50,766 INFO L87 Difference]: Start difference. First operand 62 states and 73 transitions. Second operand has 70 states, 70 states have (on average 1.957142857142857) internal successors, (137), 70 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:44:01,576 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:44:01,576 INFO L93 Difference]: Finished difference Result 141 states and 171 transitions. [2022-11-03 02:44:01,576 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2022-11-03 02:44:01,577 INFO L78 Accepts]: Start accepts. Automaton has has 70 states, 70 states have (on average 1.957142857142857) internal successors, (137), 70 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 38 [2022-11-03 02:44:01,577 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:44:01,577 INFO L225 Difference]: With dead ends: 141 [2022-11-03 02:44:01,577 INFO L226 Difference]: Without dead ends: 120 [2022-11-03 02:44:01,579 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 263 GetRequests, 158 SyntacticMatches, 2 SemanticMatches, 103 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1862 ImplicationChecksByTransitivity, 17.3s TimeCoverageRelationStatistics Valid=869, Invalid=10051, Unknown=0, NotChecked=0, Total=10920 [2022-11-03 02:44:01,580 INFO L413 NwaCegarLoop]: 27 mSDtfsCounter, 212 mSDsluCounter, 1002 mSDsCounter, 0 mSdLazyCounter, 353 mSolverCounterSat, 11 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 212 SdHoareTripleChecker+Valid, 1029 SdHoareTripleChecker+Invalid, 1209 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 11 IncrementalHoareTripleChecker+Valid, 353 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 845 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-11-03 02:44:01,580 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [212 Valid, 1029 Invalid, 1209 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [11 Valid, 353 Invalid, 0 Unknown, 845 Unchecked, 0.4s Time] [2022-11-03 02:44:01,580 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120 states. [2022-11-03 02:44:01,593 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120 to 89. [2022-11-03 02:44:01,593 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 89 states, 88 states have (on average 1.1818181818181819) internal successors, (104), 88 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:44:01,594 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 104 transitions. [2022-11-03 02:44:01,594 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 104 transitions. Word has length 38 [2022-11-03 02:44:01,594 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:44:01,595 INFO L495 AbstractCegarLoop]: Abstraction has 89 states and 104 transitions. [2022-11-03 02:44:01,595 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 70 states, 70 states have (on average 1.957142857142857) internal successors, (137), 70 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:44:01,595 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 104 transitions. [2022-11-03 02:44:01,596 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2022-11-03 02:44:01,596 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:44:01,596 INFO L195 NwaCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1] [2022-11-03 02:44:01,605 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (19)] Forceful destruction successful, exit code 0 [2022-11-03 02:44:01,804 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (20)] Forceful destruction successful, exit code 0 [2022-11-03 02:44:02,023 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Forceful destruction successful, exit code 0 [2022-11-03 02:44:02,202 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 19 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,20 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,21 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:44:02,203 INFO L420 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:44:02,203 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:44:02,203 INFO L85 PathProgramCache]: Analyzing trace with hash 383110547, now seen corresponding path program 2 times [2022-11-03 02:44:02,204 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:44:02,204 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [413070699] [2022-11-03 02:44:02,204 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-03 02:44:02,204 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:44:02,204 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:44:02,205 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:44:02,210 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (22)] Waiting until timeout for monitored process [2022-11-03 02:44:02,295 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-03 02:44:02,295 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:44:02,300 INFO L263 TraceCheckSpWp]: Trace formula consists of 250 conjuncts, 23 conjunts are in the unsatisfiable core [2022-11-03 02:44:02,301 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:44:02,527 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 26 proven. 8 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2022-11-03 02:44:02,528 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:44:02,949 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 26 proven. 8 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2022-11-03 02:44:02,950 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:44:02,950 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [413070699] [2022-11-03 02:44:02,950 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [413070699] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:44:02,950 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [499236237] [2022-11-03 02:44:02,950 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-03 02:44:02,951 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:44:02,951 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:44:02,952 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:44:02,959 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (23)] Waiting until timeout for monitored process [2022-11-03 02:44:03,134 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-03 02:44:03,134 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:44:03,137 INFO L263 TraceCheckSpWp]: Trace formula consists of 250 conjuncts, 62 conjunts are in the unsatisfiable core [2022-11-03 02:44:03,139 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:44:04,383 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 14 proven. 22 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-11-03 02:44:04,383 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:44:06,762 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 26 proven. 10 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-11-03 02:44:06,762 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [499236237] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:44:06,762 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [982980684] [2022-11-03 02:44:06,762 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-03 02:44:06,763 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:44:06,763 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:44:06,764 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:44:06,780 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2022-11-03 02:44:06,856 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-03 02:44:06,856 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:44:06,859 INFO L263 TraceCheckSpWp]: Trace formula consists of 250 conjuncts, 62 conjunts are in the unsatisfiable core [2022-11-03 02:44:06,862 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:44:08,087 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 37 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-03 02:44:08,088 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:44:08,626 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 22 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2022-11-03 02:44:08,627 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [982980684] provided 1 perfect and 1 imperfect interpolant sequences [2022-11-03 02:44:08,627 INFO L184 FreeRefinementEngine]: Found 1 perfect and 5 imperfect interpolant sequences. [2022-11-03 02:44:08,627 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [9, 9, 26, 20, 23] total 68 [2022-11-03 02:44:08,627 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1877819229] [2022-11-03 02:44:08,628 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:44:08,628 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 11 states [2022-11-03 02:44:08,628 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:44:08,628 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2022-11-03 02:44:08,630 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=222, Invalid=4334, Unknown=0, NotChecked=0, Total=4556 [2022-11-03 02:44:08,630 INFO L87 Difference]: Start difference. First operand 89 states and 104 transitions. Second operand has 11 states, 11 states have (on average 2.3636363636363638) internal successors, (26), 11 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:44:08,788 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:44:08,789 INFO L93 Difference]: Finished difference Result 108 states and 127 transitions. [2022-11-03 02:44:08,789 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-03 02:44:08,789 INFO L78 Accepts]: Start accepts. Automaton has has 11 states, 11 states have (on average 2.3636363636363638) internal successors, (26), 11 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 38 [2022-11-03 02:44:08,789 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:44:08,790 INFO L225 Difference]: With dead ends: 108 [2022-11-03 02:44:08,790 INFO L226 Difference]: Without dead ends: 106 [2022-11-03 02:44:08,792 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 224 GetRequests, 155 SyntacticMatches, 2 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1235 ImplicationChecksByTransitivity, 4.9s TimeCoverageRelationStatistics Valid=226, Invalid=4466, Unknown=0, NotChecked=0, Total=4692 [2022-11-03 02:44:08,793 INFO L413 NwaCegarLoop]: 21 mSDtfsCounter, 9 mSDsluCounter, 113 mSDsCounter, 0 mSdLazyCounter, 3 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 9 SdHoareTripleChecker+Valid, 134 SdHoareTripleChecker+Invalid, 91 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 3 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 87 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 02:44:08,793 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [9 Valid, 134 Invalid, 91 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 3 Invalid, 0 Unknown, 87 Unchecked, 0.0s Time] [2022-11-03 02:44:08,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states. [2022-11-03 02:44:08,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 100. [2022-11-03 02:44:08,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100 states, 99 states have (on average 1.1818181818181819) internal successors, (117), 99 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:44:08,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 117 transitions. [2022-11-03 02:44:08,807 INFO L78 Accepts]: Start accepts. Automaton has 100 states and 117 transitions. Word has length 38 [2022-11-03 02:44:08,807 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:44:08,808 INFO L495 AbstractCegarLoop]: Abstraction has 100 states and 117 transitions. [2022-11-03 02:44:08,808 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 11 states, 11 states have (on average 2.3636363636363638) internal successors, (26), 11 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:44:08,808 INFO L276 IsEmpty]: Start isEmpty. Operand 100 states and 117 transitions. [2022-11-03 02:44:08,809 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2022-11-03 02:44:08,809 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:44:08,809 INFO L195 NwaCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1] [2022-11-03 02:44:08,821 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (22)] Forceful destruction successful, exit code 0 [2022-11-03 02:44:09,020 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (23)] Forceful destruction successful, exit code 0 [2022-11-03 02:44:09,242 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Ended with exit code 0 [2022-11-03 02:44:09,418 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 22 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,23 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,24 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:44:09,419 INFO L420 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:44:09,419 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:44:09,419 INFO L85 PathProgramCache]: Analyzing trace with hash -2136849387, now seen corresponding path program 3 times [2022-11-03 02:44:09,419 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:44:09,419 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1384671268] [2022-11-03 02:44:09,420 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-03 02:44:09,420 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:44:09,420 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:44:09,421 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:44:09,422 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (25)] Waiting until timeout for monitored process [2022-11-03 02:44:09,478 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2022-11-03 02:44:09,478 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:44:09,480 INFO L263 TraceCheckSpWp]: Trace formula consists of 104 conjuncts, 14 conjunts are in the unsatisfiable core [2022-11-03 02:44:09,482 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:44:09,629 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 20 proven. 2 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2022-11-03 02:44:09,629 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:44:09,887 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 14 proven. 8 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2022-11-03 02:44:09,887 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:44:09,888 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1384671268] [2022-11-03 02:44:09,888 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1384671268] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:44:09,888 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [923747193] [2022-11-03 02:44:09,888 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-03 02:44:09,889 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:44:09,889 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:44:09,890 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:44:09,926 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (26)] Waiting until timeout for monitored process [2022-11-03 02:44:10,039 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2022-11-03 02:44:10,040 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:44:10,043 INFO L263 TraceCheckSpWp]: Trace formula consists of 104 conjuncts, 26 conjunts are in the unsatisfiable core [2022-11-03 02:44:10,045 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:44:10,456 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 16 proven. 6 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2022-11-03 02:44:10,456 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:44:10,725 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 22 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2022-11-03 02:44:10,725 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [923747193] provided 1 perfect and 1 imperfect interpolant sequences [2022-11-03 02:44:10,725 INFO L184 FreeRefinementEngine]: Found 1 perfect and 3 imperfect interpolant sequences. [2022-11-03 02:44:10,726 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [7, 7, 8] total 23 [2022-11-03 02:44:10,726 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1357043360] [2022-11-03 02:44:10,726 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:44:10,726 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 02:44:10,727 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:44:10,727 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 02:44:10,727 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=428, Unknown=0, NotChecked=0, Total=506 [2022-11-03 02:44:10,727 INFO L87 Difference]: Start difference. First operand 100 states and 117 transitions. Second operand has 7 states, 7 states have (on average 3.7142857142857144) internal successors, (26), 7 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:44:10,997 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:44:10,997 INFO L93 Difference]: Finished difference Result 187 states and 226 transitions. [2022-11-03 02:44:10,997 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-03 02:44:10,997 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 3.7142857142857144) internal successors, (26), 7 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 38 [2022-11-03 02:44:10,998 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:44:10,998 INFO L225 Difference]: With dead ends: 187 [2022-11-03 02:44:10,999 INFO L226 Difference]: Without dead ends: 142 [2022-11-03 02:44:11,000 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 156 GetRequests, 129 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 186 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=115, Invalid=697, Unknown=0, NotChecked=0, Total=812 [2022-11-03 02:44:11,002 INFO L413 NwaCegarLoop]: 26 mSDtfsCounter, 36 mSDsluCounter, 75 mSDsCounter, 0 mSdLazyCounter, 15 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 36 SdHoareTripleChecker+Valid, 101 SdHoareTripleChecker+Invalid, 40 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 15 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 22 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 02:44:11,003 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [36 Valid, 101 Invalid, 40 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 15 Invalid, 0 Unknown, 22 Unchecked, 0.0s Time] [2022-11-03 02:44:11,003 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142 states. [2022-11-03 02:44:11,021 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142 to 110. [2022-11-03 02:44:11,021 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 110 states, 109 states have (on average 1.146788990825688) internal successors, (125), 109 states have internal predecessors, (125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:44:11,022 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 125 transitions. [2022-11-03 02:44:11,022 INFO L78 Accepts]: Start accepts. Automaton has 110 states and 125 transitions. Word has length 38 [2022-11-03 02:44:11,022 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:44:11,022 INFO L495 AbstractCegarLoop]: Abstraction has 110 states and 125 transitions. [2022-11-03 02:44:11,023 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 3.7142857142857144) internal successors, (26), 7 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:44:11,023 INFO L276 IsEmpty]: Start isEmpty. Operand 110 states and 125 transitions. [2022-11-03 02:44:11,024 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:44:11,024 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:44:11,024 INFO L195 NwaCegarLoop]: trace histogram [6, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1] [2022-11-03 02:44:11,039 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (26)] Forceful destruction successful, exit code 0 [2022-11-03 02:44:11,233 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (25)] Ended with exit code 0 [2022-11-03 02:44:11,426 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 26 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,25 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:44:11,427 INFO L420 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:44:11,427 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:44:11,427 INFO L85 PathProgramCache]: Analyzing trace with hash 1937877079, now seen corresponding path program 3 times [2022-11-03 02:44:11,428 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:44:11,428 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [607640039] [2022-11-03 02:44:11,428 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-03 02:44:11,428 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:44:11,428 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:44:11,429 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:44:11,430 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (27)] Waiting until timeout for monitored process [2022-11-03 02:44:11,514 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2022-11-03 02:44:11,515 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:44:11,518 INFO L263 TraceCheckSpWp]: Trace formula consists of 177 conjuncts, 25 conjunts are in the unsatisfiable core [2022-11-03 02:44:11,520 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:44:11,934 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 14 proven. 52 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2022-11-03 02:44:11,934 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:44:12,360 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 14 proven. 52 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2022-11-03 02:44:12,360 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:44:12,361 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [607640039] [2022-11-03 02:44:12,361 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [607640039] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:44:12,361 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1467360515] [2022-11-03 02:44:12,361 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-03 02:44:12,361 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:44:12,361 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:44:12,362 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:44:12,363 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (28)] Waiting until timeout for monitored process [2022-11-03 02:44:12,527 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2022-11-03 02:44:12,527 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:44:12,530 INFO L263 TraceCheckSpWp]: Trace formula consists of 177 conjuncts, 60 conjunts are in the unsatisfiable core [2022-11-03 02:44:12,532 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:44:13,729 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 26 proven. 55 refuted. 0 times theorem prover too weak. 39 trivial. 0 not checked. [2022-11-03 02:44:13,730 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:44:14,306 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 70 proven. 8 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2022-11-03 02:44:14,306 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1467360515] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:44:14,306 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1850934521] [2022-11-03 02:44:14,306 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-03 02:44:14,307 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:44:14,307 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:44:14,308 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:44:14,328 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2022-11-03 02:44:14,407 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2022-11-03 02:44:14,407 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:44:14,410 INFO L263 TraceCheckSpWp]: Trace formula consists of 177 conjuncts, 28 conjunts are in the unsatisfiable core [2022-11-03 02:44:14,412 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:44:15,107 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 26 proven. 40 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2022-11-03 02:44:15,107 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:44:15,400 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 14 proven. 52 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2022-11-03 02:44:15,401 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1850934521] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:44:15,401 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:44:15,401 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 16, 15, 9, 9] total 39 [2022-11-03 02:44:15,401 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1876469400] [2022-11-03 02:44:15,401 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:44:15,402 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 39 states [2022-11-03 02:44:15,402 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:44:15,402 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2022-11-03 02:44:15,403 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=311, Invalid=1171, Unknown=0, NotChecked=0, Total=1482 [2022-11-03 02:44:15,403 INFO L87 Difference]: Start difference. First operand 110 states and 125 transitions. Second operand has 39 states, 39 states have (on average 3.1794871794871793) internal successors, (124), 39 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:44:16,545 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:44:16,545 INFO L93 Difference]: Finished difference Result 154 states and 182 transitions. [2022-11-03 02:44:16,545 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2022-11-03 02:44:16,545 INFO L78 Accepts]: Start accepts. Automaton has has 39 states, 39 states have (on average 3.1794871794871793) internal successors, (124), 39 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:44:16,546 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:44:16,546 INFO L225 Difference]: With dead ends: 154 [2022-11-03 02:44:16,547 INFO L226 Difference]: Without dead ends: 124 [2022-11-03 02:44:16,548 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 382 GetRequests, 325 SyntacticMatches, 1 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 878 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=765, Invalid=2541, Unknown=0, NotChecked=0, Total=3306 [2022-11-03 02:44:16,552 INFO L413 NwaCegarLoop]: 14 mSDtfsCounter, 80 mSDsluCounter, 153 mSDsCounter, 0 mSdLazyCounter, 11 mSolverCounterSat, 12 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 80 SdHoareTripleChecker+Valid, 167 SdHoareTripleChecker+Invalid, 178 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 12 IncrementalHoareTripleChecker+Valid, 11 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 155 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 02:44:16,552 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [80 Valid, 167 Invalid, 178 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [12 Valid, 11 Invalid, 0 Unknown, 155 Unchecked, 0.0s Time] [2022-11-03 02:44:16,553 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124 states. [2022-11-03 02:44:16,566 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124 to 108. [2022-11-03 02:44:16,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108 states, 107 states have (on average 1.1308411214953271) internal successors, (121), 107 states have internal predecessors, (121), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:44:16,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 121 transitions. [2022-11-03 02:44:16,568 INFO L78 Accepts]: Start accepts. Automaton has 108 states and 121 transitions. Word has length 60 [2022-11-03 02:44:16,568 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:44:16,568 INFO L495 AbstractCegarLoop]: Abstraction has 108 states and 121 transitions. [2022-11-03 02:44:16,569 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 39 states, 39 states have (on average 3.1794871794871793) internal successors, (124), 39 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:44:16,569 INFO L276 IsEmpty]: Start isEmpty. Operand 108 states and 121 transitions. [2022-11-03 02:44:16,570 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:44:16,570 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:44:16,570 INFO L195 NwaCegarLoop]: trace histogram [6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 1, 1, 1, 1, 1] [2022-11-03 02:44:16,583 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (27)] Forceful destruction successful, exit code 0 [2022-11-03 02:44:16,784 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (28)] Forceful destruction successful, exit code 0 [2022-11-03 02:44:17,005 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Forceful destruction successful, exit code 0 [2022-11-03 02:44:17,182 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 27 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,28 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,29 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:44:17,182 INFO L420 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:44:17,183 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:44:17,183 INFO L85 PathProgramCache]: Analyzing trace with hash 1939724121, now seen corresponding path program 1 times [2022-11-03 02:44:17,183 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:44:17,183 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [956890953] [2022-11-03 02:44:17,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:44:17,183 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:44:17,183 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:44:17,184 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:44:17,186 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (30)] Waiting until timeout for monitored process [2022-11-03 02:44:17,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:44:17,312 INFO L263 TraceCheckSpWp]: Trace formula consists of 396 conjuncts, 69 conjunts are in the unsatisfiable core [2022-11-03 02:44:17,315 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:44:18,853 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 62 proven. 51 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2022-11-03 02:44:18,853 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:44:22,498 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 62 proven. 51 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2022-11-03 02:44:22,498 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:44:22,498 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [956890953] [2022-11-03 02:44:22,498 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [956890953] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:44:22,498 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1188961525] [2022-11-03 02:44:22,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:44:22,499 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:44:22,499 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:44:22,500 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:44:22,503 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (31)] Waiting until timeout for monitored process [2022-11-03 02:44:22,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:44:22,767 INFO L263 TraceCheckSpWp]: Trace formula consists of 396 conjuncts, 70 conjunts are in the unsatisfiable core [2022-11-03 02:44:22,770 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:44:23,109 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 62 proven. 51 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2022-11-03 02:44:23,109 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:44:23,298 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 62 proven. 51 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2022-11-03 02:44:23,298 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1188961525] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:44:23,298 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2077581400] [2022-11-03 02:44:23,298 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:44:23,298 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:44:23,298 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:44:23,299 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:44:23,300 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2022-11-03 02:44:23,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:44:23,441 INFO L263 TraceCheckSpWp]: Trace formula consists of 396 conjuncts, 69 conjunts are in the unsatisfiable core [2022-11-03 02:44:23,444 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:44:23,760 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 62 proven. 51 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2022-11-03 02:44:23,760 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:44:23,956 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 62 proven. 51 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2022-11-03 02:44:23,956 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2077581400] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:44:23,956 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:44:23,956 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32, 32, 32, 32, 32] total 60 [2022-11-03 02:44:23,957 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1143292451] [2022-11-03 02:44:23,957 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:44:23,957 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 60 states [2022-11-03 02:44:23,957 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:44:23,958 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 60 interpolants. [2022-11-03 02:44:23,958 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=194, Invalid=3346, Unknown=0, NotChecked=0, Total=3540 [2022-11-03 02:44:23,958 INFO L87 Difference]: Start difference. First operand 108 states and 121 transitions. Second operand has 60 states, 60 states have (on average 1.5166666666666666) internal successors, (91), 60 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:44:35,827 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:44:35,827 INFO L93 Difference]: Finished difference Result 206 states and 238 transitions. [2022-11-03 02:44:35,831 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2022-11-03 02:44:35,831 INFO L78 Accepts]: Start accepts. Automaton has has 60 states, 60 states have (on average 1.5166666666666666) internal successors, (91), 60 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:44:35,831 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:44:35,832 INFO L225 Difference]: With dead ends: 206 [2022-11-03 02:44:35,833 INFO L226 Difference]: Without dead ends: 161 [2022-11-03 02:44:35,834 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 405 GetRequests, 296 SyntacticMatches, 0 SemanticMatches, 109 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1845 ImplicationChecksByTransitivity, 14.7s TimeCoverageRelationStatistics Valid=1685, Invalid=10525, Unknown=0, NotChecked=0, Total=12210 [2022-11-03 02:44:35,835 INFO L413 NwaCegarLoop]: 12 mSDtfsCounter, 494 mSDsluCounter, 417 mSDsCounter, 0 mSdLazyCounter, 1248 mSolverCounterSat, 328 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 494 SdHoareTripleChecker+Valid, 429 SdHoareTripleChecker+Invalid, 1576 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 328 IncrementalHoareTripleChecker+Valid, 1248 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.8s IncrementalHoareTripleChecker+Time [2022-11-03 02:44:35,836 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [494 Valid, 429 Invalid, 1576 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [328 Valid, 1248 Invalid, 0 Unknown, 0 Unchecked, 1.8s Time] [2022-11-03 02:44:35,836 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 161 states. [2022-11-03 02:44:35,850 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 161 to 125. [2022-11-03 02:44:35,850 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 125 states, 124 states have (on average 1.1209677419354838) internal successors, (139), 124 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:44:35,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 139 transitions. [2022-11-03 02:44:35,851 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 139 transitions. Word has length 60 [2022-11-03 02:44:35,851 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:44:35,851 INFO L495 AbstractCegarLoop]: Abstraction has 125 states and 139 transitions. [2022-11-03 02:44:35,851 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 60 states, 60 states have (on average 1.5166666666666666) internal successors, (91), 60 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:44:35,851 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 139 transitions. [2022-11-03 02:44:35,852 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2022-11-03 02:44:35,853 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:44:35,853 INFO L195 NwaCegarLoop]: trace histogram [7, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 1, 1, 1, 1, 1] [2022-11-03 02:44:35,878 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Forceful destruction successful, exit code 0 [2022-11-03 02:44:36,059 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (31)] Forceful destruction successful, exit code 0 [2022-11-03 02:44:36,264 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (30)] Forceful destruction successful, exit code 0 [2022-11-03 02:44:36,456 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 32 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,31 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,30 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:44:36,456 INFO L420 AbstractCegarLoop]: === Iteration 15 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:44:36,456 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:44:36,457 INFO L85 PathProgramCache]: Analyzing trace with hash -2144935989, now seen corresponding path program 2 times [2022-11-03 02:44:36,457 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:44:36,457 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1378345887] [2022-11-03 02:44:36,457 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-03 02:44:36,457 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:44:36,457 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:44:36,458 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:44:36,461 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (33)] Waiting until timeout for monitored process [2022-11-03 02:44:36,650 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-03 02:44:36,650 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:44:36,663 INFO L263 TraceCheckSpWp]: Trace formula consists of 469 conjuncts, 68 conjunts are in the unsatisfiable core [2022-11-03 02:44:36,667 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:44:38,882 INFO L134 CoverageAnalysis]: Checked inductivity of 177 backedges. 47 proven. 130 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:44:38,882 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:44:45,101 INFO L134 CoverageAnalysis]: Checked inductivity of 177 backedges. 47 proven. 130 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:44:45,101 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:44:45,101 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1378345887] [2022-11-03 02:44:45,102 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1378345887] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:44:45,102 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [945959079] [2022-11-03 02:44:45,102 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-03 02:44:45,102 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:44:45,102 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:44:45,104 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:44:45,105 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (34)] Waiting until timeout for monitored process [2022-11-03 02:44:45,410 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-03 02:44:45,411 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:44:45,434 INFO L263 TraceCheckSpWp]: Trace formula consists of 469 conjuncts, 92 conjunts are in the unsatisfiable core [2022-11-03 02:44:45,436 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:44:52,796 INFO L134 CoverageAnalysis]: Checked inductivity of 177 backedges. 0 proven. 177 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:44:52,797 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:45:08,147 INFO L134 CoverageAnalysis]: Checked inductivity of 177 backedges. 0 proven. 177 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:45:08,147 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [945959079] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:45:08,147 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [284343398] [2022-11-03 02:45:08,147 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-03 02:45:08,147 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:45:08,147 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:45:08,148 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:45:08,149 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2022-11-03 02:45:08,279 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-03 02:45:08,279 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:45:08,284 INFO L263 TraceCheckSpWp]: Trace formula consists of 469 conjuncts, 95 conjunts are in the unsatisfiable core [2022-11-03 02:45:08,288 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:45:09,254 INFO L134 CoverageAnalysis]: Checked inductivity of 177 backedges. 0 proven. 177 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:45:09,254 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:45:10,782 INFO L134 CoverageAnalysis]: Checked inductivity of 177 backedges. 0 proven. 177 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:45:10,782 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [284343398] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:45:10,782 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:45:10,782 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 38, 38, 39, 39] total 130 [2022-11-03 02:45:10,782 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2130185489] [2022-11-03 02:45:10,782 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:45:10,783 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 130 states [2022-11-03 02:45:10,783 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:45:10,784 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 130 interpolants. [2022-11-03 02:45:10,785 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=712, Invalid=16058, Unknown=0, NotChecked=0, Total=16770 [2022-11-03 02:45:10,785 INFO L87 Difference]: Start difference. First operand 125 states and 139 transitions. Second operand has 130 states, 130 states have (on average 2.1) internal successors, (273), 130 states have internal predecessors, (273), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:46:26,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:46:26,035 INFO L93 Difference]: Finished difference Result 385 states and 441 transitions. [2022-11-03 02:46:26,038 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 126 states. [2022-11-03 02:46:26,038 INFO L78 Accepts]: Start accepts. Automaton has has 130 states, 130 states have (on average 2.1) internal successors, (273), 130 states have internal predecessors, (273), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 71 [2022-11-03 02:46:26,039 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:46:26,040 INFO L225 Difference]: With dead ends: 385 [2022-11-03 02:46:26,040 INFO L226 Difference]: Without dead ends: 347 [2022-11-03 02:46:26,047 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 548 GetRequests, 299 SyntacticMatches, 2 SemanticMatches, 247 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12746 ImplicationChecksByTransitivity, 103.2s TimeCoverageRelationStatistics Valid=4404, Invalid=57348, Unknown=0, NotChecked=0, Total=61752 [2022-11-03 02:46:26,048 INFO L413 NwaCegarLoop]: 45 mSDtfsCounter, 695 mSDsluCounter, 3235 mSDsCounter, 0 mSdLazyCounter, 1102 mSolverCounterSat, 71 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 695 SdHoareTripleChecker+Valid, 3280 SdHoareTripleChecker+Invalid, 4530 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 71 IncrementalHoareTripleChecker+Valid, 1102 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 3357 IncrementalHoareTripleChecker+Unchecked, 1.2s IncrementalHoareTripleChecker+Time [2022-11-03 02:46:26,048 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [695 Valid, 3280 Invalid, 4530 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [71 Valid, 1102 Invalid, 0 Unknown, 3357 Unchecked, 1.2s Time] [2022-11-03 02:46:26,049 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 347 states. [2022-11-03 02:46:26,075 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 347 to 218. [2022-11-03 02:46:26,075 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 218 states, 217 states have (on average 1.1105990783410138) internal successors, (241), 217 states have internal predecessors, (241), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:46:26,076 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 218 states to 218 states and 241 transitions. [2022-11-03 02:46:26,076 INFO L78 Accepts]: Start accepts. Automaton has 218 states and 241 transitions. Word has length 71 [2022-11-03 02:46:26,077 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:46:26,077 INFO L495 AbstractCegarLoop]: Abstraction has 218 states and 241 transitions. [2022-11-03 02:46:26,077 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 130 states, 130 states have (on average 2.1) internal successors, (273), 130 states have internal predecessors, (273), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:46:26,077 INFO L276 IsEmpty]: Start isEmpty. Operand 218 states and 241 transitions. [2022-11-03 02:46:26,079 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2022-11-03 02:46:26,079 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:46:26,079 INFO L195 NwaCegarLoop]: trace histogram [10, 9, 9, 9, 9, 9, 9, 9, 9, 9, 8, 1, 1, 1, 1, 1] [2022-11-03 02:46:26,087 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (34)] Forceful destruction successful, exit code 0 [2022-11-03 02:46:26,304 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Forceful destruction successful, exit code 0 [2022-11-03 02:46:26,492 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (33)] Forceful destruction successful, exit code 0 [2022-11-03 02:46:26,683 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 34 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,35 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,33 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:46:26,683 INFO L420 AbstractCegarLoop]: === Iteration 16 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:46:26,684 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:46:26,684 INFO L85 PathProgramCache]: Analyzing trace with hash -652680999, now seen corresponding path program 2 times [2022-11-03 02:46:26,684 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:46:26,684 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [2046960362] [2022-11-03 02:46:26,684 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-03 02:46:26,685 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:46:26,685 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:46:26,685 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:46:26,686 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (36)] Waiting until timeout for monitored process [2022-11-03 02:46:26,875 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-03 02:46:26,875 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:46:26,887 INFO L263 TraceCheckSpWp]: Trace formula consists of 688 conjuncts, 145 conjunts are in the unsatisfiable core [2022-11-03 02:46:26,891 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:46:35,824 INFO L134 CoverageAnalysis]: Checked inductivity of 414 backedges. 134 proven. 273 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2022-11-03 02:46:35,824 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:47:05,775 INFO L134 CoverageAnalysis]: Checked inductivity of 414 backedges. 134 proven. 273 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2022-11-03 02:47:05,776 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:47:05,776 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [2046960362] [2022-11-03 02:47:05,776 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [2046960362] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:47:05,776 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [640850238] [2022-11-03 02:47:05,776 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-03 02:47:05,776 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:47:05,776 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:47:05,777 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:47:05,779 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (37)] Waiting until timeout for monitored process [2022-11-03 02:47:06,232 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-03 02:47:06,232 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:47:06,264 INFO L263 TraceCheckSpWp]: Trace formula consists of 688 conjuncts, 192 conjunts are in the unsatisfiable core [2022-11-03 02:47:06,272 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:47:44,978 INFO L134 CoverageAnalysis]: Checked inductivity of 414 backedges. 0 proven. 414 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:47:44,978 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:49:20,190 INFO L134 CoverageAnalysis]: Checked inductivity of 414 backedges. 0 proven. 414 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:49:20,191 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [640850238] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:49:20,191 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [701516039] [2022-11-03 02:49:20,191 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-03 02:49:20,191 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:49:20,191 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:49:20,192 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:49:20,193 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2022-11-03 02:49:20,360 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-03 02:49:20,360 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:49:20,366 INFO L263 TraceCheckSpWp]: Trace formula consists of 688 conjuncts, 94 conjunts are in the unsatisfiable core [2022-11-03 02:49:20,368 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:49:30,300 INFO L134 CoverageAnalysis]: Checked inductivity of 414 backedges. 58 proven. 125 refuted. 0 times theorem prover too weak. 231 trivial. 0 not checked. [2022-11-03 02:49:30,300 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:49:37,835 INFO L134 CoverageAnalysis]: Checked inductivity of 414 backedges. 159 proven. 3 refuted. 0 times theorem prover too weak. 252 trivial. 0 not checked. [2022-11-03 02:49:37,835 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [701516039] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:49:37,835 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:49:37,835 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 68, 84, 84, 19, 12] total 322 [2022-11-03 02:49:37,835 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [204404897] [2022-11-03 02:49:37,836 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:49:37,836 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 322 states [2022-11-03 02:49:37,836 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:49:37,837 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 322 interpolants. [2022-11-03 02:49:37,845 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3455, Invalid=99907, Unknown=0, NotChecked=0, Total=103362 [2022-11-03 02:49:37,846 INFO L87 Difference]: Start difference. First operand 218 states and 241 transitions. Second operand has 322 states, 322 states have (on average 1.3571428571428572) internal successors, (437), 322 states have internal predecessors, (437), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:54:12,746 WARN L234 SmtUtils]: Spent 5.63s on a formula simplification. DAG size of input: 491 DAG size of output: 479 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-11-03 02:54:34,363 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:54:34,364 INFO L93 Difference]: Finished difference Result 449 states and 524 transitions. [2022-11-03 02:54:34,364 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 221 states. [2022-11-03 02:54:34,364 INFO L78 Accepts]: Start accepts. Automaton has has 322 states, 322 states have (on average 1.3571428571428572) internal successors, (437), 322 states have internal predecessors, (437), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 104 [2022-11-03 02:54:34,365 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:54:34,367 INFO L225 Difference]: With dead ends: 449 [2022-11-03 02:54:34,367 INFO L226 Difference]: Without dead ends: 360 [2022-11-03 02:54:34,395 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 906 GetRequests, 353 SyntacticMatches, 17 SemanticMatches, 536 ConstructedPredicates, 0 IntricatePredicates, 1 DeprecatedPredicates, 78958 ImplicationChecksByTransitivity, 467.1s TimeCoverageRelationStatistics Valid=15482, Invalid=273424, Unknown=0, NotChecked=0, Total=288906 [2022-11-03 02:54:34,396 INFO L413 NwaCegarLoop]: 39 mSDtfsCounter, 2083 mSDsluCounter, 5421 mSDsCounter, 0 mSdLazyCounter, 8313 mSolverCounterSat, 841 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 11.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2083 SdHoareTripleChecker+Valid, 5460 SdHoareTripleChecker+Invalid, 21412 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 841 IncrementalHoareTripleChecker+Valid, 8313 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 12258 IncrementalHoareTripleChecker+Unchecked, 13.2s IncrementalHoareTripleChecker+Time [2022-11-03 02:54:34,396 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [2083 Valid, 5460 Invalid, 21412 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [841 Valid, 8313 Invalid, 0 Unknown, 12258 Unchecked, 13.2s Time] [2022-11-03 02:54:34,397 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 360 states. [2022-11-03 02:54:34,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 360 to 219. [2022-11-03 02:54:34,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 219 states, 218 states have (on average 1.0825688073394495) internal successors, (236), 218 states have internal predecessors, (236), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:54:34,435 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 219 states to 219 states and 236 transitions. [2022-11-03 02:54:34,436 INFO L78 Accepts]: Start accepts. Automaton has 219 states and 236 transitions. Word has length 104 [2022-11-03 02:54:34,436 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:54:34,436 INFO L495 AbstractCegarLoop]: Abstraction has 219 states and 236 transitions. [2022-11-03 02:54:34,437 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 322 states, 322 states have (on average 1.3571428571428572) internal successors, (437), 322 states have internal predecessors, (437), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:54:34,437 INFO L276 IsEmpty]: Start isEmpty. Operand 219 states and 236 transitions. [2022-11-03 02:54:34,439 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2022-11-03 02:54:34,439 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:54:34,439 INFO L195 NwaCegarLoop]: trace histogram [13, 12, 12, 12, 12, 12, 12, 12, 12, 12, 11, 1, 1, 1, 1, 1] [2022-11-03 02:54:34,470 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Forceful destruction successful, exit code 0 [2022-11-03 02:54:34,665 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (36)] Ended with exit code 0 [2022-11-03 02:54:34,858 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (37)] Forceful destruction successful, exit code 0 [2022-11-03 02:54:35,054 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 38 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,36 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,37 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt [2022-11-03 02:54:35,055 INFO L420 AbstractCegarLoop]: === Iteration 17 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:54:35,055 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:54:35,055 INFO L85 PathProgramCache]: Analyzing trace with hash -146603637, now seen corresponding path program 3 times [2022-11-03 02:54:35,056 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:54:35,056 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [900232795] [2022-11-03 02:54:35,056 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-03 02:54:35,056 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:54:35,057 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:54:35,057 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:54:35,059 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (39)] Waiting until timeout for monitored process [2022-11-03 02:54:35,193 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2022-11-03 02:54:35,193 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:54:35,197 INFO L263 TraceCheckSpWp]: Trace formula consists of 104 conjuncts, 25 conjunts are in the unsatisfiable core [2022-11-03 02:54:35,201 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:54:36,040 INFO L134 CoverageAnalysis]: Checked inductivity of 750 backedges. 101 proven. 11 refuted. 0 times theorem prover too weak. 638 trivial. 0 not checked. [2022-11-03 02:54:36,041 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:54:36,281 INFO L134 CoverageAnalysis]: Checked inductivity of 750 backedges. 112 proven. 0 refuted. 0 times theorem prover too weak. 638 trivial. 0 not checked. [2022-11-03 02:54:36,281 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:54:36,281 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [900232795] [2022-11-03 02:54:36,282 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [900232795] provided 1 perfect and 1 imperfect interpolant sequences [2022-11-03 02:54:36,282 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-11-03 02:54:36,282 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [8] total 12 [2022-11-03 02:54:36,282 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [88126145] [2022-11-03 02:54:36,282 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:54:36,282 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 02:54:36,283 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:54:36,283 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 02:54:36,283 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2022-11-03 02:54:36,284 INFO L87 Difference]: Start difference. First operand 219 states and 236 transitions. Second operand has 7 states, 7 states have (on average 3.5714285714285716) internal successors, (25), 7 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:54:36,694 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:54:36,694 INFO L93 Difference]: Finished difference Result 283 states and 313 transitions. [2022-11-03 02:54:36,695 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-03 02:54:36,695 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 3.5714285714285716) internal successors, (25), 7 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 137 [2022-11-03 02:54:36,696 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:54:36,697 INFO L225 Difference]: With dead ends: 283 [2022-11-03 02:54:36,697 INFO L226 Difference]: Without dead ends: 247 [2022-11-03 02:54:36,698 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 284 GetRequests, 267 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 67 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=92, Invalid=250, Unknown=0, NotChecked=0, Total=342 [2022-11-03 02:54:36,699 INFO L413 NwaCegarLoop]: 24 mSDtfsCounter, 55 mSDsluCounter, 49 mSDsCounter, 0 mSdLazyCounter, 84 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 55 SdHoareTripleChecker+Valid, 73 SdHoareTripleChecker+Invalid, 89 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 84 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:54:36,699 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [55 Valid, 73 Invalid, 89 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 84 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:54:36,700 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 247 states. [2022-11-03 02:54:36,738 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 247 to 219. [2022-11-03 02:54:36,739 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 219 states, 218 states have (on average 1.0779816513761469) internal successors, (235), 218 states have internal predecessors, (235), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:54:36,739 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 219 states to 219 states and 235 transitions. [2022-11-03 02:54:36,739 INFO L78 Accepts]: Start accepts. Automaton has 219 states and 235 transitions. Word has length 137 [2022-11-03 02:54:36,740 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:54:36,740 INFO L495 AbstractCegarLoop]: Abstraction has 219 states and 235 transitions. [2022-11-03 02:54:36,740 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 3.5714285714285716) internal successors, (25), 7 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:54:36,740 INFO L276 IsEmpty]: Start isEmpty. Operand 219 states and 235 transitions. [2022-11-03 02:54:36,741 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2022-11-03 02:54:36,741 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:54:36,741 INFO L195 NwaCegarLoop]: trace histogram [13, 12, 12, 12, 12, 12, 12, 12, 12, 11, 11, 1, 1, 1, 1, 1, 1] [2022-11-03 02:54:36,751 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (39)] Forceful destruction successful, exit code 0 [2022-11-03 02:54:36,942 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 39 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:54:36,942 INFO L420 AbstractCegarLoop]: === Iteration 18 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:54:36,942 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:54:36,942 INFO L85 PathProgramCache]: Analyzing trace with hash 1628403725, now seen corresponding path program 1 times [2022-11-03 02:54:36,943 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:54:36,943 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1762536648] [2022-11-03 02:54:36,943 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:54:36,943 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:54:36,943 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:54:36,944 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:54:36,946 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (40)] Waiting until timeout for monitored process [2022-11-03 02:54:37,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:54:37,250 INFO L263 TraceCheckSpWp]: Trace formula consists of 907 conjuncts, 134 conjunts are in the unsatisfiable core [2022-11-03 02:54:37,256 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:54:49,794 INFO L134 CoverageAnalysis]: Checked inductivity of 750 backedges. 101 proven. 649 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:54:49,794 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:55:30,867 INFO L134 CoverageAnalysis]: Checked inductivity of 750 backedges. 101 proven. 649 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:55:30,867 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:55:30,867 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1762536648] [2022-11-03 02:55:30,867 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1762536648] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:55:30,867 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [2138524474] [2022-11-03 02:55:30,868 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:55:30,868 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:55:30,868 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:55:30,868 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:55:30,871 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (41)] Waiting until timeout for monitored process [2022-11-03 02:55:31,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:55:31,452 INFO L263 TraceCheckSpWp]: Trace formula consists of 907 conjuncts, 134 conjunts are in the unsatisfiable core [2022-11-03 02:55:31,455 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:55:33,777 INFO L134 CoverageAnalysis]: Checked inductivity of 750 backedges. 101 proven. 649 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:55:33,777 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:55:35,843 INFO L134 CoverageAnalysis]: Checked inductivity of 750 backedges. 101 proven. 649 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:55:35,843 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [2138524474] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:55:35,844 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1515909635] [2022-11-03 02:55:35,844 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:55:35,844 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:55:35,844 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:55:35,846 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:55:35,849 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2022-11-03 02:55:36,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:55:36,075 INFO L263 TraceCheckSpWp]: Trace formula consists of 907 conjuncts, 134 conjunts are in the unsatisfiable core [2022-11-03 02:55:36,080 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:55:38,926 INFO L134 CoverageAnalysis]: Checked inductivity of 750 backedges. 57 proven. 693 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:55:38,927 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:55:41,430 INFO L134 CoverageAnalysis]: Checked inductivity of 750 backedges. 57 proven. 693 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:55:41,430 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1515909635] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:55:41,430 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:55:41,430 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59, 59, 59, 59, 59] total 118 [2022-11-03 02:55:41,430 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [363473684] [2022-11-03 02:55:41,430 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:55:41,431 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 118 states [2022-11-03 02:55:41,431 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:55:41,431 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 118 interpolants. [2022-11-03 02:55:41,432 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=801, Invalid=13005, Unknown=0, NotChecked=0, Total=13806 [2022-11-03 02:55:41,432 INFO L87 Difference]: Start difference. First operand 219 states and 235 transitions. Second operand has 118 states, 118 states have (on average 2.330508474576271) internal successors, (275), 118 states have internal predecessors, (275), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:56:47,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:56:47,527 INFO L93 Difference]: Finished difference Result 443 states and 500 transitions. [2022-11-03 02:56:47,527 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 122 states. [2022-11-03 02:56:47,527 INFO L78 Accepts]: Start accepts. Automaton has has 118 states, 118 states have (on average 2.330508474576271) internal successors, (275), 118 states have internal predecessors, (275), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 137 [2022-11-03 02:56:47,527 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:56:47,529 INFO L225 Difference]: With dead ends: 443 [2022-11-03 02:56:47,529 INFO L226 Difference]: Without dead ends: 399 [2022-11-03 02:56:47,532 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 942 GetRequests, 708 SyntacticMatches, 2 SemanticMatches, 232 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8867 ImplicationChecksByTransitivity, 114.9s TimeCoverageRelationStatistics Valid=3818, Invalid=50704, Unknown=0, NotChecked=0, Total=54522 [2022-11-03 02:56:47,532 INFO L413 NwaCegarLoop]: 44 mSDtfsCounter, 537 mSDsluCounter, 2464 mSDsCounter, 0 mSdLazyCounter, 1312 mSolverCounterSat, 76 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 537 SdHoareTripleChecker+Valid, 2508 SdHoareTripleChecker+Invalid, 4015 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 76 IncrementalHoareTripleChecker+Valid, 1312 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 2627 IncrementalHoareTripleChecker+Unchecked, 1.9s IncrementalHoareTripleChecker+Time [2022-11-03 02:56:47,533 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [537 Valid, 2508 Invalid, 4015 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [76 Valid, 1312 Invalid, 0 Unknown, 2627 Unchecked, 1.9s Time] [2022-11-03 02:56:47,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 399 states. [2022-11-03 02:56:47,587 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 399 to 382. [2022-11-03 02:56:47,588 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 382 states, 381 states have (on average 1.0656167979002624) internal successors, (406), 381 states have internal predecessors, (406), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:56:47,589 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 382 states to 382 states and 406 transitions. [2022-11-03 02:56:47,589 INFO L78 Accepts]: Start accepts. Automaton has 382 states and 406 transitions. Word has length 137 [2022-11-03 02:56:47,589 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:56:47,589 INFO L495 AbstractCegarLoop]: Abstraction has 382 states and 406 transitions. [2022-11-03 02:56:47,590 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 118 states, 118 states have (on average 2.330508474576271) internal successors, (275), 118 states have internal predecessors, (275), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:56:47,590 INFO L276 IsEmpty]: Start isEmpty. Operand 382 states and 406 transitions. [2022-11-03 02:56:47,592 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 171 [2022-11-03 02:56:47,592 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:56:47,592 INFO L195 NwaCegarLoop]: trace histogram [16, 15, 15, 15, 15, 15, 15, 15, 15, 14, 14, 1, 1, 1, 1, 1, 1] [2022-11-03 02:56:47,599 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (41)] Forceful destruction successful, exit code 0 [2022-11-03 02:56:47,819 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Forceful destruction successful, exit code 0 [2022-11-03 02:56:48,009 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (40)] Forceful destruction successful, exit code 0 [2022-11-03 02:56:48,198 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 41 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,42 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,40 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:56:48,198 INFO L420 AbstractCegarLoop]: === Iteration 19 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:56:48,198 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:56:48,198 INFO L85 PathProgramCache]: Analyzing trace with hash 141656027, now seen corresponding path program 2 times [2022-11-03 02:56:48,199 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:56:48,199 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [114159180] [2022-11-03 02:56:48,199 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-03 02:56:48,199 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:56:48,200 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:56:48,201 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:56:48,202 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (43)] Waiting until timeout for monitored process [2022-11-03 02:56:48,531 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-03 02:56:48,531 INFO L229 tOrderPrioritization]: Conjunction of SSA is sat [2022-11-03 02:56:48,532 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-03 02:56:48,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-03 02:56:49,089 INFO L130 FreeRefinementEngine]: Strategy WALRUS found a feasible trace [2022-11-03 02:56:49,089 INFO L359 BasicCegarLoop]: Counterexample is feasible [2022-11-03 02:56:49,090 INFO L805 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2022-11-03 02:56:49,112 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (43)] Forceful destruction successful, exit code 0 [2022-11-03 02:56:49,311 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 43 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:56:49,314 INFO L444 BasicCegarLoop]: Path program histogram: [3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1] [2022-11-03 02:56:49,318 INFO L178 ceAbstractionStarter]: Computing trace abstraction results [2022-11-03 02:56:49,494 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,495 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,495 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,495 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,495 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,495 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,496 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,496 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,496 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,496 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,496 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,496 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,496 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,497 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,497 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,497 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,537 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 03.11 02:56:49 BoogieIcfgContainer [2022-11-03 02:56:49,537 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2022-11-03 02:56:49,538 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-03 02:56:49,538 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-03 02:56:49,538 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-03 02:56:49,539 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:43:11" (3/4) ... [2022-11-03 02:56:49,542 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2022-11-03 02:56:49,617 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,617 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,617 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,617 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,617 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,618 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,618 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,618 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,618 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,618 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,618 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,618 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,619 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,619 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,619 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,619 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:56:49,845 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/witness.graphml [2022-11-03 02:56:49,845 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-03 02:56:49,846 INFO L158 Benchmark]: Toolchain (without parser) took 819497.79ms. Allocated memory was 69.2MB in the beginning and 851.4MB in the end (delta: 782.2MB). Free memory was 44.2MB in the beginning and 585.7MB in the end (delta: -541.5MB). Peak memory consumption was 237.8MB. Max. memory is 16.1GB. [2022-11-03 02:56:49,846 INFO L158 Benchmark]: CDTParser took 0.32ms. Allocated memory is still 50.3MB. Free memory was 29.7MB in the beginning and 29.6MB in the end (delta: 36.2kB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 02:56:49,847 INFO L158 Benchmark]: CACSL2BoogieTranslator took 331.51ms. Allocated memory is still 69.2MB. Free memory was 44.0MB in the beginning and 51.0MB in the end (delta: -7.0MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-11-03 02:56:49,847 INFO L158 Benchmark]: Boogie Procedure Inliner took 50.59ms. Allocated memory is still 69.2MB. Free memory was 50.8MB in the beginning and 49.0MB in the end (delta: 1.7MB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 02:56:49,847 INFO L158 Benchmark]: Boogie Preprocessor took 28.57ms. Allocated memory is still 69.2MB. Free memory was 49.0MB in the beginning and 47.6MB in the end (delta: 1.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-11-03 02:56:49,848 INFO L158 Benchmark]: RCFGBuilder took 526.63ms. Allocated memory is still 69.2MB. Free memory was 47.4MB in the beginning and 34.0MB in the end (delta: 13.3MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2022-11-03 02:56:49,852 INFO L158 Benchmark]: TraceAbstraction took 818242.94ms. Allocated memory was 69.2MB in the beginning and 851.4MB in the end (delta: 782.2MB). Free memory was 33.2MB in the beginning and 631.2MB in the end (delta: -598.0MB). Peak memory consumption was 185.7MB. Max. memory is 16.1GB. [2022-11-03 02:56:49,855 INFO L158 Benchmark]: Witness Printer took 307.04ms. Allocated memory is still 851.4MB. Free memory was 631.2MB in the beginning and 585.7MB in the end (delta: 45.5MB). Peak memory consumption was 44.0MB. Max. memory is 16.1GB. [2022-11-03 02:56:49,858 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.32ms. Allocated memory is still 50.3MB. Free memory was 29.7MB in the beginning and 29.6MB in the end (delta: 36.2kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 331.51ms. Allocated memory is still 69.2MB. Free memory was 44.0MB in the beginning and 51.0MB in the end (delta: -7.0MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 50.59ms. Allocated memory is still 69.2MB. Free memory was 50.8MB in the beginning and 49.0MB in the end (delta: 1.7MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 28.57ms. Allocated memory is still 69.2MB. Free memory was 49.0MB in the beginning and 47.6MB in the end (delta: 1.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 526.63ms. Allocated memory is still 69.2MB. Free memory was 47.4MB in the beginning and 34.0MB in the end (delta: 13.3MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * TraceAbstraction took 818242.94ms. Allocated memory was 69.2MB in the beginning and 851.4MB in the end (delta: 782.2MB). Free memory was 33.2MB in the beginning and 631.2MB in the end (delta: -598.0MB). Peak memory consumption was 185.7MB. Max. memory is 16.1GB. * Witness Printer took 307.04ms. Allocated memory is still 851.4MB. Free memory was 631.2MB in the beginning and 585.7MB in the end (delta: 45.5MB). Peak memory consumption was 44.0MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - CounterExampleResult [Line: 20]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L25] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 1); [L26] const SORT_1 msb_SORT_1 = (SORT_1)1 << (1 - 1); [L28] const SORT_3 mask_SORT_3 = (SORT_3)-1 >> (sizeof(SORT_3) * 8 - 4); [L29] const SORT_3 msb_SORT_3 = (SORT_3)1 << (4 - 1); [L31] const SORT_3 var_4 = 0; [L32] const SORT_3 var_7 = 1; [L33] const SORT_1 var_14 = 1; [L34] const SORT_3 var_20 = 15; [L36] SORT_1 input_2; [L38] SORT_3 state_5 = __VERIFIER_nondet_uchar() & mask_SORT_3; [L39] SORT_3 state_8 = __VERIFIER_nondet_uchar() & mask_SORT_3; [L41] SORT_3 init_6_arg_1 = var_4; [L42] state_5 = init_6_arg_1 [L43] SORT_3 init_9_arg_1 = var_7; [L44] state_8 = init_9_arg_1 VAL [init_6_arg_1=0, init_9_arg_1=1, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, state_5=0, state_8=1, var_14=1, var_20=15, var_4=0, var_7=1] [L47] input_2 = __VERIFIER_nondet_uchar() [L50] SORT_3 var_10_arg_0 = state_5; [L51] SORT_3 var_10_arg_1 = state_8; [L52] SORT_1 var_10 = var_10_arg_0 > var_10_arg_1; [L53] SORT_1 var_11_arg_0 = var_10; [L54] SORT_1 var_11 = ~var_11_arg_0; [L55] SORT_1 var_15_arg_0 = var_11; [L56] SORT_1 var_15 = ~var_15_arg_0; [L57] SORT_1 var_16_arg_0 = var_14; [L58] SORT_1 var_16_arg_1 = var_15; [L59] SORT_1 var_16 = var_16_arg_0 & var_16_arg_1; [L60] var_16 = var_16 & mask_SORT_1 [L61] SORT_1 bad_17_arg_0 = var_16; [L62] CALL __VERIFIER_assert(!(bad_17_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L62] RET __VERIFIER_assert(!(bad_17_arg_0)) [L64] SORT_3 var_25_arg_0 = state_5; [L65] SORT_3 var_25_arg_1 = state_8; [L66] SORT_1 var_25 = var_25_arg_0 == var_25_arg_1; [L67] SORT_3 var_24_arg_0 = state_5; [L68] SORT_3 var_24_arg_1 = var_7; [L69] SORT_3 var_24 = var_24_arg_0 + var_24_arg_1; [L70] SORT_3 var_19_arg_0 = state_5; [L71] SORT_3 var_19_arg_1 = state_8; [L72] SORT_1 var_19 = var_19_arg_0 > var_19_arg_1; [L73] SORT_3 var_21_arg_0 = state_8; [L74] SORT_3 var_21_arg_1 = var_20; [L75] SORT_1 var_21 = var_21_arg_0 != var_21_arg_1; [L76] SORT_1 var_22_arg_0 = var_19; [L77] SORT_1 var_22_arg_1 = var_21; [L78] SORT_1 var_22 = var_22_arg_0 | var_22_arg_1; [L79] var_22 = var_22 & mask_SORT_1 [L80] SORT_1 var_23_arg_0 = var_22; [L81] SORT_3 var_23_arg_1 = state_5; [L82] SORT_3 var_23_arg_2 = state_8; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=17, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, state_5=0, state_8=1, var_10=0, var_10_arg_0=0, var_10_arg_1=1, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=1, var_20=15, var_21=1, var_21_arg_0=1, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=1, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=1, var_4=0, var_7=1] [L83] EXPR var_23_arg_0 ? var_23_arg_1 : var_23_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=17, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, state_5=0, state_8=1, var_10=0, var_10_arg_0=0, var_10_arg_1=1, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=1, var_20=15, var_21=1, var_21_arg_0=1, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23_arg_0=1, var_23_arg_0 ? var_23_arg_1 : var_23_arg_2=0, var_23_arg_1=0, var_23_arg_2=1, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=1, var_4=0, var_7=1] [L83] SORT_3 var_23 = var_23_arg_0 ? var_23_arg_1 : var_23_arg_2; [L84] SORT_1 var_26_arg_0 = var_25; [L85] SORT_3 var_26_arg_1 = var_24; [L86] SORT_3 var_26_arg_2 = var_23; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=17, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, state_5=0, state_8=1, var_10=0, var_10_arg_0=0, var_10_arg_1=1, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=1, var_20=15, var_21=1, var_21_arg_0=1, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=1, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=1, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_4=0, var_7=1] [L87] EXPR var_26_arg_0 ? var_26_arg_1 : var_26_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=17, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, state_5=0, state_8=1, var_10=0, var_10_arg_0=0, var_10_arg_1=1, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=1, var_20=15, var_21=1, var_21_arg_0=1, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=1, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=1, var_26_arg_0=0, var_26_arg_0 ? var_26_arg_1 : var_26_arg_2=0, var_26_arg_1=1, var_26_arg_2=0, var_4=0, var_7=1] [L87] SORT_3 var_26 = var_26_arg_0 ? var_26_arg_1 : var_26_arg_2; [L88] var_26 = var_26 & mask_SORT_3 [L89] SORT_3 next_27_arg_1 = var_26; [L90] SORT_3 var_33_arg_0 = state_5; [L91] SORT_3 var_33_arg_1 = state_8; [L92] SORT_1 var_33 = var_33_arg_0 > var_33_arg_1; [L93] SORT_3 var_29_arg_0 = state_5; [L94] SORT_3 var_29_arg_1 = state_8; [L95] SORT_1 var_29 = var_29_arg_0 == var_29_arg_1; [L96] SORT_3 var_30_arg_0 = state_8; [L97] SORT_3 var_30_arg_1 = var_20; [L98] SORT_1 var_30 = var_30_arg_0 != var_30_arg_1; [L99] SORT_1 var_31_arg_0 = var_29; [L100] SORT_1 var_31_arg_1 = var_30; [L101] SORT_1 var_31 = var_31_arg_0 | var_31_arg_1; [L102] var_31 = var_31 & mask_SORT_1 [L103] SORT_3 var_28_arg_0 = state_8; [L104] SORT_3 var_28_arg_1 = var_7; [L105] SORT_3 var_28 = var_28_arg_0 + var_28_arg_1; [L106] SORT_1 var_32_arg_0 = var_31; [L107] SORT_3 var_32_arg_1 = var_28; [L108] SORT_3 var_32_arg_2 = state_5; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=17, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, state_5=0, state_8=1, var_10=0, var_10_arg_0=0, var_10_arg_1=1, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=1, var_20=15, var_21=1, var_21_arg_0=1, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=1, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=1, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=2, var_28_arg_0=1, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=1, var_30=1, var_30_arg_0=1, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32_arg_0=1, var_32_arg_1=2, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=1, var_4=0, var_7=1] [L109] EXPR var_32_arg_0 ? var_32_arg_1 : var_32_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=17, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, state_5=0, state_8=1, var_10=0, var_10_arg_0=0, var_10_arg_1=1, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=1, var_20=15, var_21=1, var_21_arg_0=1, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=1, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=1, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=2, var_28_arg_0=1, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=1, var_30=1, var_30_arg_0=1, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32_arg_0=1, var_32_arg_0 ? var_32_arg_1 : var_32_arg_2=2, var_32_arg_1=2, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=1, var_4=0, var_7=1] [L109] SORT_3 var_32 = var_32_arg_0 ? var_32_arg_1 : var_32_arg_2; [L110] SORT_1 var_34_arg_0 = var_33; [L111] SORT_3 var_34_arg_1 = state_8; [L112] SORT_3 var_34_arg_2 = var_32; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=17, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, state_5=0, state_8=1, var_10=0, var_10_arg_0=0, var_10_arg_1=1, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=1, var_20=15, var_21=1, var_21_arg_0=1, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=1, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=1, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=2, var_28_arg_0=1, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=1, var_30=1, var_30_arg_0=1, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=2, var_32_arg_0=1, var_32_arg_1=2, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=1, var_34_arg_0=0, var_34_arg_1=1, var_34_arg_2=2, var_4=0, var_7=1] [L113] EXPR var_34_arg_0 ? var_34_arg_1 : var_34_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=17, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, state_5=0, state_8=1, var_10=0, var_10_arg_0=0, var_10_arg_1=1, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=1, var_20=15, var_21=1, var_21_arg_0=1, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=1, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=1, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=2, var_28_arg_0=1, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=1, var_30=1, var_30_arg_0=1, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=2, var_32_arg_0=1, var_32_arg_1=2, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=1, var_34_arg_0=0, var_34_arg_0 ? var_34_arg_1 : var_34_arg_2=2, var_34_arg_1=1, var_34_arg_2=2, var_4=0, var_7=1] [L113] SORT_3 var_34 = var_34_arg_0 ? var_34_arg_1 : var_34_arg_2; [L114] var_34 = var_34 & mask_SORT_3 [L115] SORT_3 next_35_arg_1 = var_34; [L117] state_5 = next_27_arg_1 [L118] state_8 = next_35_arg_1 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=17, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=2, state_5=0, state_8=2, var_10=0, var_10_arg_0=0, var_10_arg_1=1, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=1, var_20=15, var_21=1, var_21_arg_0=1, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=1, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=1, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=2, var_28_arg_0=1, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=1, var_30=1, var_30_arg_0=1, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=2, var_32_arg_0=1, var_32_arg_1=2, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=1, var_34=2, var_34_arg_0=0, var_34_arg_1=1, var_34_arg_2=2, var_4=0, var_7=1] [L47] input_2 = __VERIFIER_nondet_uchar() [L50] SORT_3 var_10_arg_0 = state_5; [L51] SORT_3 var_10_arg_1 = state_8; [L52] SORT_1 var_10 = var_10_arg_0 > var_10_arg_1; [L53] SORT_1 var_11_arg_0 = var_10; [L54] SORT_1 var_11 = ~var_11_arg_0; [L55] SORT_1 var_15_arg_0 = var_11; [L56] SORT_1 var_15 = ~var_15_arg_0; [L57] SORT_1 var_16_arg_0 = var_14; [L58] SORT_1 var_16_arg_1 = var_15; [L59] SORT_1 var_16 = var_16_arg_0 & var_16_arg_1; [L60] var_16 = var_16 & mask_SORT_1 [L61] SORT_1 bad_17_arg_0 = var_16; [L62] CALL __VERIFIER_assert(!(bad_17_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L62] RET __VERIFIER_assert(!(bad_17_arg_0)) [L64] SORT_3 var_25_arg_0 = state_5; [L65] SORT_3 var_25_arg_1 = state_8; [L66] SORT_1 var_25 = var_25_arg_0 == var_25_arg_1; [L67] SORT_3 var_24_arg_0 = state_5; [L68] SORT_3 var_24_arg_1 = var_7; [L69] SORT_3 var_24 = var_24_arg_0 + var_24_arg_1; [L70] SORT_3 var_19_arg_0 = state_5; [L71] SORT_3 var_19_arg_1 = state_8; [L72] SORT_1 var_19 = var_19_arg_0 > var_19_arg_1; [L73] SORT_3 var_21_arg_0 = state_8; [L74] SORT_3 var_21_arg_1 = var_20; [L75] SORT_1 var_21 = var_21_arg_0 != var_21_arg_1; [L76] SORT_1 var_22_arg_0 = var_19; [L77] SORT_1 var_22_arg_1 = var_21; [L78] SORT_1 var_22 = var_22_arg_0 | var_22_arg_1; [L79] var_22 = var_22 & mask_SORT_1 [L80] SORT_1 var_23_arg_0 = var_22; [L81] SORT_3 var_23_arg_1 = state_5; [L82] SORT_3 var_23_arg_2 = state_8; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=18, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=2, state_5=0, state_8=2, var_10=0, var_10_arg_0=0, var_10_arg_1=2, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=2, var_20=15, var_21=1, var_21_arg_0=2, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=2, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=2, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=2, var_28_arg_0=1, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=1, var_30=1, var_30_arg_0=1, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=2, var_32_arg_0=1, var_32_arg_1=2, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=1, var_34=2, var_34_arg_0=0, var_34_arg_1=1, var_34_arg_2=2, var_4=0, var_7=1] [L83] EXPR var_23_arg_0 ? var_23_arg_1 : var_23_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=18, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=2, state_5=0, state_8=2, var_10=0, var_10_arg_0=0, var_10_arg_1=2, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=2, var_20=15, var_21=1, var_21_arg_0=2, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_0 ? var_23_arg_1 : var_23_arg_2=0, var_23_arg_1=0, var_23_arg_2=2, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=2, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=2, var_28_arg_0=1, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=1, var_30=1, var_30_arg_0=1, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=2, var_32_arg_0=1, var_32_arg_1=2, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=1, var_34=2, var_34_arg_0=0, var_34_arg_1=1, var_34_arg_2=2, var_4=0, var_7=1] [L83] SORT_3 var_23 = var_23_arg_0 ? var_23_arg_1 : var_23_arg_2; [L84] SORT_1 var_26_arg_0 = var_25; [L85] SORT_3 var_26_arg_1 = var_24; [L86] SORT_3 var_26_arg_2 = var_23; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=18, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=2, state_5=0, state_8=2, var_10=0, var_10_arg_0=0, var_10_arg_1=2, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=2, var_20=15, var_21=1, var_21_arg_0=2, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=2, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=2, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=2, var_28_arg_0=1, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=1, var_30=1, var_30_arg_0=1, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=2, var_32_arg_0=1, var_32_arg_1=2, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=1, var_34=2, var_34_arg_0=0, var_34_arg_1=1, var_34_arg_2=2, var_4=0, var_7=1] [L87] EXPR var_26_arg_0 ? var_26_arg_1 : var_26_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=18, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=2, state_5=0, state_8=2, var_10=0, var_10_arg_0=0, var_10_arg_1=2, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=2, var_20=15, var_21=1, var_21_arg_0=2, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=2, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=2, var_26=0, var_26_arg_0=0, var_26_arg_0 ? var_26_arg_1 : var_26_arg_2=0, var_26_arg_1=1, var_26_arg_2=0, var_28=2, var_28_arg_0=1, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=1, var_30=1, var_30_arg_0=1, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=2, var_32_arg_0=1, var_32_arg_1=2, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=1, var_34=2, var_34_arg_0=0, var_34_arg_1=1, var_34_arg_2=2, var_4=0, var_7=1] [L87] SORT_3 var_26 = var_26_arg_0 ? var_26_arg_1 : var_26_arg_2; [L88] var_26 = var_26 & mask_SORT_3 [L89] SORT_3 next_27_arg_1 = var_26; [L90] SORT_3 var_33_arg_0 = state_5; [L91] SORT_3 var_33_arg_1 = state_8; [L92] SORT_1 var_33 = var_33_arg_0 > var_33_arg_1; [L93] SORT_3 var_29_arg_0 = state_5; [L94] SORT_3 var_29_arg_1 = state_8; [L95] SORT_1 var_29 = var_29_arg_0 == var_29_arg_1; [L96] SORT_3 var_30_arg_0 = state_8; [L97] SORT_3 var_30_arg_1 = var_20; [L98] SORT_1 var_30 = var_30_arg_0 != var_30_arg_1; [L99] SORT_1 var_31_arg_0 = var_29; [L100] SORT_1 var_31_arg_1 = var_30; [L101] SORT_1 var_31 = var_31_arg_0 | var_31_arg_1; [L102] var_31 = var_31 & mask_SORT_1 [L103] SORT_3 var_28_arg_0 = state_8; [L104] SORT_3 var_28_arg_1 = var_7; [L105] SORT_3 var_28 = var_28_arg_0 + var_28_arg_1; [L106] SORT_1 var_32_arg_0 = var_31; [L107] SORT_3 var_32_arg_1 = var_28; [L108] SORT_3 var_32_arg_2 = state_5; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=18, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=2, state_5=0, state_8=2, var_10=0, var_10_arg_0=0, var_10_arg_1=2, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=2, var_20=15, var_21=1, var_21_arg_0=2, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=2, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=2, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=3, var_28_arg_0=2, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=2, var_30=1, var_30_arg_0=2, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=2, var_32_arg_0=1, var_32_arg_1=3, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=2, var_34=2, var_34_arg_0=0, var_34_arg_1=1, var_34_arg_2=2, var_4=0, var_7=1] [L109] EXPR var_32_arg_0 ? var_32_arg_1 : var_32_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=18, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=2, state_5=0, state_8=2, var_10=0, var_10_arg_0=0, var_10_arg_1=2, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=2, var_20=15, var_21=1, var_21_arg_0=2, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=2, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=2, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=3, var_28_arg_0=2, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=2, var_30=1, var_30_arg_0=2, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=2, var_32_arg_0=1, var_32_arg_0 ? var_32_arg_1 : var_32_arg_2=3, var_32_arg_1=3, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=2, var_34=2, var_34_arg_0=0, var_34_arg_1=1, var_34_arg_2=2, var_4=0, var_7=1] [L109] SORT_3 var_32 = var_32_arg_0 ? var_32_arg_1 : var_32_arg_2; [L110] SORT_1 var_34_arg_0 = var_33; [L111] SORT_3 var_34_arg_1 = state_8; [L112] SORT_3 var_34_arg_2 = var_32; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=18, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=2, state_5=0, state_8=2, var_10=0, var_10_arg_0=0, var_10_arg_1=2, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=2, var_20=15, var_21=1, var_21_arg_0=2, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=2, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=2, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=3, var_28_arg_0=2, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=2, var_30=1, var_30_arg_0=2, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=3, var_32_arg_0=1, var_32_arg_1=3, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=2, var_34=2, var_34_arg_0=0, var_34_arg_1=2, var_34_arg_2=3, var_4=0, var_7=1] [L113] EXPR var_34_arg_0 ? var_34_arg_1 : var_34_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=18, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=2, state_5=0, state_8=2, var_10=0, var_10_arg_0=0, var_10_arg_1=2, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=2, var_20=15, var_21=1, var_21_arg_0=2, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=2, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=2, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=3, var_28_arg_0=2, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=2, var_30=1, var_30_arg_0=2, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=3, var_32_arg_0=1, var_32_arg_1=3, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=2, var_34=2, var_34_arg_0=0, var_34_arg_0 ? var_34_arg_1 : var_34_arg_2=3, var_34_arg_1=2, var_34_arg_2=3, var_4=0, var_7=1] [L113] SORT_3 var_34 = var_34_arg_0 ? var_34_arg_1 : var_34_arg_2; [L114] var_34 = var_34 & mask_SORT_3 [L115] SORT_3 next_35_arg_1 = var_34; [L117] state_5 = next_27_arg_1 [L118] state_8 = next_35_arg_1 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=18, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=3, state_5=0, state_8=3, var_10=0, var_10_arg_0=0, var_10_arg_1=2, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=2, var_20=15, var_21=1, var_21_arg_0=2, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=2, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=2, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=3, var_28_arg_0=2, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=2, var_30=1, var_30_arg_0=2, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=3, var_32_arg_0=1, var_32_arg_1=3, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=2, var_34=3, var_34_arg_0=0, var_34_arg_1=2, var_34_arg_2=3, var_4=0, var_7=1] [L47] input_2 = __VERIFIER_nondet_uchar() [L50] SORT_3 var_10_arg_0 = state_5; [L51] SORT_3 var_10_arg_1 = state_8; [L52] SORT_1 var_10 = var_10_arg_0 > var_10_arg_1; [L53] SORT_1 var_11_arg_0 = var_10; [L54] SORT_1 var_11 = ~var_11_arg_0; [L55] SORT_1 var_15_arg_0 = var_11; [L56] SORT_1 var_15 = ~var_15_arg_0; [L57] SORT_1 var_16_arg_0 = var_14; [L58] SORT_1 var_16_arg_1 = var_15; [L59] SORT_1 var_16 = var_16_arg_0 & var_16_arg_1; [L60] var_16 = var_16 & mask_SORT_1 [L61] SORT_1 bad_17_arg_0 = var_16; [L62] CALL __VERIFIER_assert(!(bad_17_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L62] RET __VERIFIER_assert(!(bad_17_arg_0)) [L64] SORT_3 var_25_arg_0 = state_5; [L65] SORT_3 var_25_arg_1 = state_8; [L66] SORT_1 var_25 = var_25_arg_0 == var_25_arg_1; [L67] SORT_3 var_24_arg_0 = state_5; [L68] SORT_3 var_24_arg_1 = var_7; [L69] SORT_3 var_24 = var_24_arg_0 + var_24_arg_1; [L70] SORT_3 var_19_arg_0 = state_5; [L71] SORT_3 var_19_arg_1 = state_8; [L72] SORT_1 var_19 = var_19_arg_0 > var_19_arg_1; [L73] SORT_3 var_21_arg_0 = state_8; [L74] SORT_3 var_21_arg_1 = var_20; [L75] SORT_1 var_21 = var_21_arg_0 != var_21_arg_1; [L76] SORT_1 var_22_arg_0 = var_19; [L77] SORT_1 var_22_arg_1 = var_21; [L78] SORT_1 var_22 = var_22_arg_0 | var_22_arg_1; [L79] var_22 = var_22 & mask_SORT_1 [L80] SORT_1 var_23_arg_0 = var_22; [L81] SORT_3 var_23_arg_1 = state_5; [L82] SORT_3 var_23_arg_2 = state_8; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=19, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=3, state_5=0, state_8=3, var_10=0, var_10_arg_0=0, var_10_arg_1=3, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=3, var_20=15, var_21=1, var_21_arg_0=3, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=3, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=3, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=3, var_28_arg_0=2, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=2, var_30=1, var_30_arg_0=2, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=3, var_32_arg_0=1, var_32_arg_1=3, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=2, var_34=3, var_34_arg_0=0, var_34_arg_1=2, var_34_arg_2=3, var_4=0, var_7=1] [L83] EXPR var_23_arg_0 ? var_23_arg_1 : var_23_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=19, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=3, state_5=0, state_8=3, var_10=0, var_10_arg_0=0, var_10_arg_1=3, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=3, var_20=15, var_21=1, var_21_arg_0=3, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_0 ? var_23_arg_1 : var_23_arg_2=0, var_23_arg_1=0, var_23_arg_2=3, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=3, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=3, var_28_arg_0=2, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=2, var_30=1, var_30_arg_0=2, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=3, var_32_arg_0=1, var_32_arg_1=3, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=2, var_34=3, var_34_arg_0=0, var_34_arg_1=2, var_34_arg_2=3, var_4=0, var_7=1] [L83] SORT_3 var_23 = var_23_arg_0 ? var_23_arg_1 : var_23_arg_2; [L84] SORT_1 var_26_arg_0 = var_25; [L85] SORT_3 var_26_arg_1 = var_24; [L86] SORT_3 var_26_arg_2 = var_23; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=19, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=3, state_5=0, state_8=3, var_10=0, var_10_arg_0=0, var_10_arg_1=3, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=3, var_20=15, var_21=1, var_21_arg_0=3, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=3, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=3, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=3, var_28_arg_0=2, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=2, var_30=1, var_30_arg_0=2, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=3, var_32_arg_0=1, var_32_arg_1=3, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=2, var_34=3, var_34_arg_0=0, var_34_arg_1=2, var_34_arg_2=3, var_4=0, var_7=1] [L87] EXPR var_26_arg_0 ? var_26_arg_1 : var_26_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=19, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=3, state_5=0, state_8=3, var_10=0, var_10_arg_0=0, var_10_arg_1=3, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=3, var_20=15, var_21=1, var_21_arg_0=3, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=3, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=3, var_26=0, var_26_arg_0=0, var_26_arg_0 ? var_26_arg_1 : var_26_arg_2=0, var_26_arg_1=1, var_26_arg_2=0, var_28=3, var_28_arg_0=2, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=2, var_30=1, var_30_arg_0=2, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=3, var_32_arg_0=1, var_32_arg_1=3, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=2, var_34=3, var_34_arg_0=0, var_34_arg_1=2, var_34_arg_2=3, var_4=0, var_7=1] [L87] SORT_3 var_26 = var_26_arg_0 ? var_26_arg_1 : var_26_arg_2; [L88] var_26 = var_26 & mask_SORT_3 [L89] SORT_3 next_27_arg_1 = var_26; [L90] SORT_3 var_33_arg_0 = state_5; [L91] SORT_3 var_33_arg_1 = state_8; [L92] SORT_1 var_33 = var_33_arg_0 > var_33_arg_1; [L93] SORT_3 var_29_arg_0 = state_5; [L94] SORT_3 var_29_arg_1 = state_8; [L95] SORT_1 var_29 = var_29_arg_0 == var_29_arg_1; [L96] SORT_3 var_30_arg_0 = state_8; [L97] SORT_3 var_30_arg_1 = var_20; [L98] SORT_1 var_30 = var_30_arg_0 != var_30_arg_1; [L99] SORT_1 var_31_arg_0 = var_29; [L100] SORT_1 var_31_arg_1 = var_30; [L101] SORT_1 var_31 = var_31_arg_0 | var_31_arg_1; [L102] var_31 = var_31 & mask_SORT_1 [L103] SORT_3 var_28_arg_0 = state_8; [L104] SORT_3 var_28_arg_1 = var_7; [L105] SORT_3 var_28 = var_28_arg_0 + var_28_arg_1; [L106] SORT_1 var_32_arg_0 = var_31; [L107] SORT_3 var_32_arg_1 = var_28; [L108] SORT_3 var_32_arg_2 = state_5; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=19, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=3, state_5=0, state_8=3, var_10=0, var_10_arg_0=0, var_10_arg_1=3, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=3, var_20=15, var_21=1, var_21_arg_0=3, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=3, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=3, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=4, var_28_arg_0=3, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=3, var_30=1, var_30_arg_0=3, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=3, var_32_arg_0=1, var_32_arg_1=4, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=3, var_34=3, var_34_arg_0=0, var_34_arg_1=2, var_34_arg_2=3, var_4=0, var_7=1] [L109] EXPR var_32_arg_0 ? var_32_arg_1 : var_32_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=19, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=3, state_5=0, state_8=3, var_10=0, var_10_arg_0=0, var_10_arg_1=3, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=3, var_20=15, var_21=1, var_21_arg_0=3, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=3, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=3, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=4, var_28_arg_0=3, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=3, var_30=1, var_30_arg_0=3, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=3, var_32_arg_0=1, var_32_arg_0 ? var_32_arg_1 : var_32_arg_2=4, var_32_arg_1=4, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=3, var_34=3, var_34_arg_0=0, var_34_arg_1=2, var_34_arg_2=3, var_4=0, var_7=1] [L109] SORT_3 var_32 = var_32_arg_0 ? var_32_arg_1 : var_32_arg_2; [L110] SORT_1 var_34_arg_0 = var_33; [L111] SORT_3 var_34_arg_1 = state_8; [L112] SORT_3 var_34_arg_2 = var_32; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=19, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=3, state_5=0, state_8=3, var_10=0, var_10_arg_0=0, var_10_arg_1=3, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=3, var_20=15, var_21=1, var_21_arg_0=3, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=3, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=3, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=4, var_28_arg_0=3, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=3, var_30=1, var_30_arg_0=3, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=4, var_32_arg_0=1, var_32_arg_1=4, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=3, var_34=3, var_34_arg_0=0, var_34_arg_1=3, var_34_arg_2=4, var_4=0, var_7=1] [L113] EXPR var_34_arg_0 ? var_34_arg_1 : var_34_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=19, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=3, state_5=0, state_8=3, var_10=0, var_10_arg_0=0, var_10_arg_1=3, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=3, var_20=15, var_21=1, var_21_arg_0=3, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=3, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=3, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=4, var_28_arg_0=3, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=3, var_30=1, var_30_arg_0=3, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=4, var_32_arg_0=1, var_32_arg_1=4, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=3, var_34=3, var_34_arg_0=0, var_34_arg_0 ? var_34_arg_1 : var_34_arg_2=4, var_34_arg_1=3, var_34_arg_2=4, var_4=0, var_7=1] [L113] SORT_3 var_34 = var_34_arg_0 ? var_34_arg_1 : var_34_arg_2; [L114] var_34 = var_34 & mask_SORT_3 [L115] SORT_3 next_35_arg_1 = var_34; [L117] state_5 = next_27_arg_1 [L118] state_8 = next_35_arg_1 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=19, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=4, state_5=0, state_8=4, var_10=0, var_10_arg_0=0, var_10_arg_1=3, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=3, var_20=15, var_21=1, var_21_arg_0=3, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=3, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=3, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=4, var_28_arg_0=3, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=3, var_30=1, var_30_arg_0=3, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=4, var_32_arg_0=1, var_32_arg_1=4, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=3, var_34=4, var_34_arg_0=0, var_34_arg_1=3, var_34_arg_2=4, var_4=0, var_7=1] [L47] input_2 = __VERIFIER_nondet_uchar() [L50] SORT_3 var_10_arg_0 = state_5; [L51] SORT_3 var_10_arg_1 = state_8; [L52] SORT_1 var_10 = var_10_arg_0 > var_10_arg_1; [L53] SORT_1 var_11_arg_0 = var_10; [L54] SORT_1 var_11 = ~var_11_arg_0; [L55] SORT_1 var_15_arg_0 = var_11; [L56] SORT_1 var_15 = ~var_15_arg_0; [L57] SORT_1 var_16_arg_0 = var_14; [L58] SORT_1 var_16_arg_1 = var_15; [L59] SORT_1 var_16 = var_16_arg_0 & var_16_arg_1; [L60] var_16 = var_16 & mask_SORT_1 [L61] SORT_1 bad_17_arg_0 = var_16; [L62] CALL __VERIFIER_assert(!(bad_17_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L62] RET __VERIFIER_assert(!(bad_17_arg_0)) [L64] SORT_3 var_25_arg_0 = state_5; [L65] SORT_3 var_25_arg_1 = state_8; [L66] SORT_1 var_25 = var_25_arg_0 == var_25_arg_1; [L67] SORT_3 var_24_arg_0 = state_5; [L68] SORT_3 var_24_arg_1 = var_7; [L69] SORT_3 var_24 = var_24_arg_0 + var_24_arg_1; [L70] SORT_3 var_19_arg_0 = state_5; [L71] SORT_3 var_19_arg_1 = state_8; [L72] SORT_1 var_19 = var_19_arg_0 > var_19_arg_1; [L73] SORT_3 var_21_arg_0 = state_8; [L74] SORT_3 var_21_arg_1 = var_20; [L75] SORT_1 var_21 = var_21_arg_0 != var_21_arg_1; [L76] SORT_1 var_22_arg_0 = var_19; [L77] SORT_1 var_22_arg_1 = var_21; [L78] SORT_1 var_22 = var_22_arg_0 | var_22_arg_1; [L79] var_22 = var_22 & mask_SORT_1 [L80] SORT_1 var_23_arg_0 = var_22; [L81] SORT_3 var_23_arg_1 = state_5; [L82] SORT_3 var_23_arg_2 = state_8; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=20, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=4, state_5=0, state_8=4, var_10=0, var_10_arg_0=0, var_10_arg_1=4, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=4, var_20=15, var_21=1, var_21_arg_0=4, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=4, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=4, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=4, var_28_arg_0=3, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=3, var_30=1, var_30_arg_0=3, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=4, var_32_arg_0=1, var_32_arg_1=4, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=3, var_34=4, var_34_arg_0=0, var_34_arg_1=3, var_34_arg_2=4, var_4=0, var_7=1] [L83] EXPR var_23_arg_0 ? var_23_arg_1 : var_23_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=20, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=4, state_5=0, state_8=4, var_10=0, var_10_arg_0=0, var_10_arg_1=4, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=4, var_20=15, var_21=1, var_21_arg_0=4, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_0 ? var_23_arg_1 : var_23_arg_2=0, var_23_arg_1=0, var_23_arg_2=4, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=4, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=4, var_28_arg_0=3, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=3, var_30=1, var_30_arg_0=3, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=4, var_32_arg_0=1, var_32_arg_1=4, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=3, var_34=4, var_34_arg_0=0, var_34_arg_1=3, var_34_arg_2=4, var_4=0, var_7=1] [L83] SORT_3 var_23 = var_23_arg_0 ? var_23_arg_1 : var_23_arg_2; [L84] SORT_1 var_26_arg_0 = var_25; [L85] SORT_3 var_26_arg_1 = var_24; [L86] SORT_3 var_26_arg_2 = var_23; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=20, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=4, state_5=0, state_8=4, var_10=0, var_10_arg_0=0, var_10_arg_1=4, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=4, var_20=15, var_21=1, var_21_arg_0=4, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=4, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=4, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=4, var_28_arg_0=3, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=3, var_30=1, var_30_arg_0=3, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=4, var_32_arg_0=1, var_32_arg_1=4, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=3, var_34=4, var_34_arg_0=0, var_34_arg_1=3, var_34_arg_2=4, var_4=0, var_7=1] [L87] EXPR var_26_arg_0 ? var_26_arg_1 : var_26_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=20, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=4, state_5=0, state_8=4, var_10=0, var_10_arg_0=0, var_10_arg_1=4, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=4, var_20=15, var_21=1, var_21_arg_0=4, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=4, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=4, var_26=0, var_26_arg_0=0, var_26_arg_0 ? var_26_arg_1 : var_26_arg_2=0, var_26_arg_1=1, var_26_arg_2=0, var_28=4, var_28_arg_0=3, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=3, var_30=1, var_30_arg_0=3, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=4, var_32_arg_0=1, var_32_arg_1=4, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=3, var_34=4, var_34_arg_0=0, var_34_arg_1=3, var_34_arg_2=4, var_4=0, var_7=1] [L87] SORT_3 var_26 = var_26_arg_0 ? var_26_arg_1 : var_26_arg_2; [L88] var_26 = var_26 & mask_SORT_3 [L89] SORT_3 next_27_arg_1 = var_26; [L90] SORT_3 var_33_arg_0 = state_5; [L91] SORT_3 var_33_arg_1 = state_8; [L92] SORT_1 var_33 = var_33_arg_0 > var_33_arg_1; [L93] SORT_3 var_29_arg_0 = state_5; [L94] SORT_3 var_29_arg_1 = state_8; [L95] SORT_1 var_29 = var_29_arg_0 == var_29_arg_1; [L96] SORT_3 var_30_arg_0 = state_8; [L97] SORT_3 var_30_arg_1 = var_20; [L98] SORT_1 var_30 = var_30_arg_0 != var_30_arg_1; [L99] SORT_1 var_31_arg_0 = var_29; [L100] SORT_1 var_31_arg_1 = var_30; [L101] SORT_1 var_31 = var_31_arg_0 | var_31_arg_1; [L102] var_31 = var_31 & mask_SORT_1 [L103] SORT_3 var_28_arg_0 = state_8; [L104] SORT_3 var_28_arg_1 = var_7; [L105] SORT_3 var_28 = var_28_arg_0 + var_28_arg_1; [L106] SORT_1 var_32_arg_0 = var_31; [L107] SORT_3 var_32_arg_1 = var_28; [L108] SORT_3 var_32_arg_2 = state_5; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=20, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=4, state_5=0, state_8=4, var_10=0, var_10_arg_0=0, var_10_arg_1=4, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=4, var_20=15, var_21=1, var_21_arg_0=4, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=4, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=4, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=5, var_28_arg_0=4, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=4, var_30=1, var_30_arg_0=4, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=4, var_32_arg_0=1, var_32_arg_1=5, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=4, var_34=4, var_34_arg_0=0, var_34_arg_1=3, var_34_arg_2=4, var_4=0, var_7=1] [L109] EXPR var_32_arg_0 ? var_32_arg_1 : var_32_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=20, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=4, state_5=0, state_8=4, var_10=0, var_10_arg_0=0, var_10_arg_1=4, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=4, var_20=15, var_21=1, var_21_arg_0=4, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=4, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=4, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=5, var_28_arg_0=4, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=4, var_30=1, var_30_arg_0=4, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=4, var_32_arg_0=1, var_32_arg_0 ? var_32_arg_1 : var_32_arg_2=5, var_32_arg_1=5, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=4, var_34=4, var_34_arg_0=0, var_34_arg_1=3, var_34_arg_2=4, var_4=0, var_7=1] [L109] SORT_3 var_32 = var_32_arg_0 ? var_32_arg_1 : var_32_arg_2; [L110] SORT_1 var_34_arg_0 = var_33; [L111] SORT_3 var_34_arg_1 = state_8; [L112] SORT_3 var_34_arg_2 = var_32; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=20, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=4, state_5=0, state_8=4, var_10=0, var_10_arg_0=0, var_10_arg_1=4, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=4, var_20=15, var_21=1, var_21_arg_0=4, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=4, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=4, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=5, var_28_arg_0=4, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=4, var_30=1, var_30_arg_0=4, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=5, var_32_arg_0=1, var_32_arg_1=5, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=4, var_34=4, var_34_arg_0=0, var_34_arg_1=4, var_34_arg_2=5, var_4=0, var_7=1] [L113] EXPR var_34_arg_0 ? var_34_arg_1 : var_34_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=20, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=4, state_5=0, state_8=4, var_10=0, var_10_arg_0=0, var_10_arg_1=4, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=4, var_20=15, var_21=1, var_21_arg_0=4, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=4, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=4, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=5, var_28_arg_0=4, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=4, var_30=1, var_30_arg_0=4, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=5, var_32_arg_0=1, var_32_arg_1=5, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=4, var_34=4, var_34_arg_0=0, var_34_arg_0 ? var_34_arg_1 : var_34_arg_2=5, var_34_arg_1=4, var_34_arg_2=5, var_4=0, var_7=1] [L113] SORT_3 var_34 = var_34_arg_0 ? var_34_arg_1 : var_34_arg_2; [L114] var_34 = var_34 & mask_SORT_3 [L115] SORT_3 next_35_arg_1 = var_34; [L117] state_5 = next_27_arg_1 [L118] state_8 = next_35_arg_1 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=20, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=5, state_5=0, state_8=5, var_10=0, var_10_arg_0=0, var_10_arg_1=4, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=4, var_20=15, var_21=1, var_21_arg_0=4, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=4, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=4, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=5, var_28_arg_0=4, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=4, var_30=1, var_30_arg_0=4, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=5, var_32_arg_0=1, var_32_arg_1=5, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=4, var_34=5, var_34_arg_0=0, var_34_arg_1=4, var_34_arg_2=5, var_4=0, var_7=1] [L47] input_2 = __VERIFIER_nondet_uchar() [L50] SORT_3 var_10_arg_0 = state_5; [L51] SORT_3 var_10_arg_1 = state_8; [L52] SORT_1 var_10 = var_10_arg_0 > var_10_arg_1; [L53] SORT_1 var_11_arg_0 = var_10; [L54] SORT_1 var_11 = ~var_11_arg_0; [L55] SORT_1 var_15_arg_0 = var_11; [L56] SORT_1 var_15 = ~var_15_arg_0; [L57] SORT_1 var_16_arg_0 = var_14; [L58] SORT_1 var_16_arg_1 = var_15; [L59] SORT_1 var_16 = var_16_arg_0 & var_16_arg_1; [L60] var_16 = var_16 & mask_SORT_1 [L61] SORT_1 bad_17_arg_0 = var_16; [L62] CALL __VERIFIER_assert(!(bad_17_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L62] RET __VERIFIER_assert(!(bad_17_arg_0)) [L64] SORT_3 var_25_arg_0 = state_5; [L65] SORT_3 var_25_arg_1 = state_8; [L66] SORT_1 var_25 = var_25_arg_0 == var_25_arg_1; [L67] SORT_3 var_24_arg_0 = state_5; [L68] SORT_3 var_24_arg_1 = var_7; [L69] SORT_3 var_24 = var_24_arg_0 + var_24_arg_1; [L70] SORT_3 var_19_arg_0 = state_5; [L71] SORT_3 var_19_arg_1 = state_8; [L72] SORT_1 var_19 = var_19_arg_0 > var_19_arg_1; [L73] SORT_3 var_21_arg_0 = state_8; [L74] SORT_3 var_21_arg_1 = var_20; [L75] SORT_1 var_21 = var_21_arg_0 != var_21_arg_1; [L76] SORT_1 var_22_arg_0 = var_19; [L77] SORT_1 var_22_arg_1 = var_21; [L78] SORT_1 var_22 = var_22_arg_0 | var_22_arg_1; [L79] var_22 = var_22 & mask_SORT_1 [L80] SORT_1 var_23_arg_0 = var_22; [L81] SORT_3 var_23_arg_1 = state_5; [L82] SORT_3 var_23_arg_2 = state_8; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=21, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=5, state_5=0, state_8=5, var_10=0, var_10_arg_0=0, var_10_arg_1=5, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=5, var_20=15, var_21=1, var_21_arg_0=5, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=5, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=5, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=5, var_28_arg_0=4, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=4, var_30=1, var_30_arg_0=4, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=5, var_32_arg_0=1, var_32_arg_1=5, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=4, var_34=5, var_34_arg_0=0, var_34_arg_1=4, var_34_arg_2=5, var_4=0, var_7=1] [L83] EXPR var_23_arg_0 ? var_23_arg_1 : var_23_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=21, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=5, state_5=0, state_8=5, var_10=0, var_10_arg_0=0, var_10_arg_1=5, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=5, var_20=15, var_21=1, var_21_arg_0=5, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_0 ? var_23_arg_1 : var_23_arg_2=0, var_23_arg_1=0, var_23_arg_2=5, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=5, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=5, var_28_arg_0=4, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=4, var_30=1, var_30_arg_0=4, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=5, var_32_arg_0=1, var_32_arg_1=5, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=4, var_34=5, var_34_arg_0=0, var_34_arg_1=4, var_34_arg_2=5, var_4=0, var_7=1] [L83] SORT_3 var_23 = var_23_arg_0 ? var_23_arg_1 : var_23_arg_2; [L84] SORT_1 var_26_arg_0 = var_25; [L85] SORT_3 var_26_arg_1 = var_24; [L86] SORT_3 var_26_arg_2 = var_23; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=21, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=5, state_5=0, state_8=5, var_10=0, var_10_arg_0=0, var_10_arg_1=5, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=5, var_20=15, var_21=1, var_21_arg_0=5, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=5, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=5, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=5, var_28_arg_0=4, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=4, var_30=1, var_30_arg_0=4, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=5, var_32_arg_0=1, var_32_arg_1=5, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=4, var_34=5, var_34_arg_0=0, var_34_arg_1=4, var_34_arg_2=5, var_4=0, var_7=1] [L87] EXPR var_26_arg_0 ? var_26_arg_1 : var_26_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=21, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=5, state_5=0, state_8=5, var_10=0, var_10_arg_0=0, var_10_arg_1=5, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=5, var_20=15, var_21=1, var_21_arg_0=5, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=5, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=5, var_26=0, var_26_arg_0=0, var_26_arg_0 ? var_26_arg_1 : var_26_arg_2=0, var_26_arg_1=1, var_26_arg_2=0, var_28=5, var_28_arg_0=4, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=4, var_30=1, var_30_arg_0=4, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=5, var_32_arg_0=1, var_32_arg_1=5, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=4, var_34=5, var_34_arg_0=0, var_34_arg_1=4, var_34_arg_2=5, var_4=0, var_7=1] [L87] SORT_3 var_26 = var_26_arg_0 ? var_26_arg_1 : var_26_arg_2; [L88] var_26 = var_26 & mask_SORT_3 [L89] SORT_3 next_27_arg_1 = var_26; [L90] SORT_3 var_33_arg_0 = state_5; [L91] SORT_3 var_33_arg_1 = state_8; [L92] SORT_1 var_33 = var_33_arg_0 > var_33_arg_1; [L93] SORT_3 var_29_arg_0 = state_5; [L94] SORT_3 var_29_arg_1 = state_8; [L95] SORT_1 var_29 = var_29_arg_0 == var_29_arg_1; [L96] SORT_3 var_30_arg_0 = state_8; [L97] SORT_3 var_30_arg_1 = var_20; [L98] SORT_1 var_30 = var_30_arg_0 != var_30_arg_1; [L99] SORT_1 var_31_arg_0 = var_29; [L100] SORT_1 var_31_arg_1 = var_30; [L101] SORT_1 var_31 = var_31_arg_0 | var_31_arg_1; [L102] var_31 = var_31 & mask_SORT_1 [L103] SORT_3 var_28_arg_0 = state_8; [L104] SORT_3 var_28_arg_1 = var_7; [L105] SORT_3 var_28 = var_28_arg_0 + var_28_arg_1; [L106] SORT_1 var_32_arg_0 = var_31; [L107] SORT_3 var_32_arg_1 = var_28; [L108] SORT_3 var_32_arg_2 = state_5; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=21, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=5, state_5=0, state_8=5, var_10=0, var_10_arg_0=0, var_10_arg_1=5, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=5, var_20=15, var_21=1, var_21_arg_0=5, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=5, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=5, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=6, var_28_arg_0=5, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=5, var_30=1, var_30_arg_0=5, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=5, var_32_arg_0=1, var_32_arg_1=6, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=5, var_34=5, var_34_arg_0=0, var_34_arg_1=4, var_34_arg_2=5, var_4=0, var_7=1] [L109] EXPR var_32_arg_0 ? var_32_arg_1 : var_32_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=21, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=5, state_5=0, state_8=5, var_10=0, var_10_arg_0=0, var_10_arg_1=5, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=5, var_20=15, var_21=1, var_21_arg_0=5, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=5, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=5, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=6, var_28_arg_0=5, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=5, var_30=1, var_30_arg_0=5, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=5, var_32_arg_0=1, var_32_arg_0 ? var_32_arg_1 : var_32_arg_2=6, var_32_arg_1=6, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=5, var_34=5, var_34_arg_0=0, var_34_arg_1=4, var_34_arg_2=5, var_4=0, var_7=1] [L109] SORT_3 var_32 = var_32_arg_0 ? var_32_arg_1 : var_32_arg_2; [L110] SORT_1 var_34_arg_0 = var_33; [L111] SORT_3 var_34_arg_1 = state_8; [L112] SORT_3 var_34_arg_2 = var_32; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=21, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=5, state_5=0, state_8=5, var_10=0, var_10_arg_0=0, var_10_arg_1=5, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=5, var_20=15, var_21=1, var_21_arg_0=5, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=5, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=5, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=6, var_28_arg_0=5, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=5, var_30=1, var_30_arg_0=5, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=6, var_32_arg_0=1, var_32_arg_1=6, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=5, var_34=5, var_34_arg_0=0, var_34_arg_1=5, var_34_arg_2=6, var_4=0, var_7=1] [L113] EXPR var_34_arg_0 ? var_34_arg_1 : var_34_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=21, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=5, state_5=0, state_8=5, var_10=0, var_10_arg_0=0, var_10_arg_1=5, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=5, var_20=15, var_21=1, var_21_arg_0=5, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=5, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=5, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=6, var_28_arg_0=5, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=5, var_30=1, var_30_arg_0=5, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=6, var_32_arg_0=1, var_32_arg_1=6, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=5, var_34=5, var_34_arg_0=0, var_34_arg_0 ? var_34_arg_1 : var_34_arg_2=6, var_34_arg_1=5, var_34_arg_2=6, var_4=0, var_7=1] [L113] SORT_3 var_34 = var_34_arg_0 ? var_34_arg_1 : var_34_arg_2; [L114] var_34 = var_34 & mask_SORT_3 [L115] SORT_3 next_35_arg_1 = var_34; [L117] state_5 = next_27_arg_1 [L118] state_8 = next_35_arg_1 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=21, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=6, state_5=0, state_8=6, var_10=0, var_10_arg_0=0, var_10_arg_1=5, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=5, var_20=15, var_21=1, var_21_arg_0=5, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=5, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=5, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=6, var_28_arg_0=5, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=5, var_30=1, var_30_arg_0=5, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=6, var_32_arg_0=1, var_32_arg_1=6, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=5, var_34=6, var_34_arg_0=0, var_34_arg_1=5, var_34_arg_2=6, var_4=0, var_7=1] [L47] input_2 = __VERIFIER_nondet_uchar() [L50] SORT_3 var_10_arg_0 = state_5; [L51] SORT_3 var_10_arg_1 = state_8; [L52] SORT_1 var_10 = var_10_arg_0 > var_10_arg_1; [L53] SORT_1 var_11_arg_0 = var_10; [L54] SORT_1 var_11 = ~var_11_arg_0; [L55] SORT_1 var_15_arg_0 = var_11; [L56] SORT_1 var_15 = ~var_15_arg_0; [L57] SORT_1 var_16_arg_0 = var_14; [L58] SORT_1 var_16_arg_1 = var_15; [L59] SORT_1 var_16 = var_16_arg_0 & var_16_arg_1; [L60] var_16 = var_16 & mask_SORT_1 [L61] SORT_1 bad_17_arg_0 = var_16; [L62] CALL __VERIFIER_assert(!(bad_17_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L62] RET __VERIFIER_assert(!(bad_17_arg_0)) [L64] SORT_3 var_25_arg_0 = state_5; [L65] SORT_3 var_25_arg_1 = state_8; [L66] SORT_1 var_25 = var_25_arg_0 == var_25_arg_1; [L67] SORT_3 var_24_arg_0 = state_5; [L68] SORT_3 var_24_arg_1 = var_7; [L69] SORT_3 var_24 = var_24_arg_0 + var_24_arg_1; [L70] SORT_3 var_19_arg_0 = state_5; [L71] SORT_3 var_19_arg_1 = state_8; [L72] SORT_1 var_19 = var_19_arg_0 > var_19_arg_1; [L73] SORT_3 var_21_arg_0 = state_8; [L74] SORT_3 var_21_arg_1 = var_20; [L75] SORT_1 var_21 = var_21_arg_0 != var_21_arg_1; [L76] SORT_1 var_22_arg_0 = var_19; [L77] SORT_1 var_22_arg_1 = var_21; [L78] SORT_1 var_22 = var_22_arg_0 | var_22_arg_1; [L79] var_22 = var_22 & mask_SORT_1 [L80] SORT_1 var_23_arg_0 = var_22; [L81] SORT_3 var_23_arg_1 = state_5; [L82] SORT_3 var_23_arg_2 = state_8; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=22, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=6, state_5=0, state_8=6, var_10=0, var_10_arg_0=0, var_10_arg_1=6, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=6, var_20=15, var_21=1, var_21_arg_0=6, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=6, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=6, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=6, var_28_arg_0=5, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=5, var_30=1, var_30_arg_0=5, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=6, var_32_arg_0=1, var_32_arg_1=6, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=5, var_34=6, var_34_arg_0=0, var_34_arg_1=5, var_34_arg_2=6, var_4=0, var_7=1] [L83] EXPR var_23_arg_0 ? var_23_arg_1 : var_23_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=22, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=6, state_5=0, state_8=6, var_10=0, var_10_arg_0=0, var_10_arg_1=6, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=6, var_20=15, var_21=1, var_21_arg_0=6, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_0 ? var_23_arg_1 : var_23_arg_2=0, var_23_arg_1=0, var_23_arg_2=6, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=6, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=6, var_28_arg_0=5, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=5, var_30=1, var_30_arg_0=5, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=6, var_32_arg_0=1, var_32_arg_1=6, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=5, var_34=6, var_34_arg_0=0, var_34_arg_1=5, var_34_arg_2=6, var_4=0, var_7=1] [L83] SORT_3 var_23 = var_23_arg_0 ? var_23_arg_1 : var_23_arg_2; [L84] SORT_1 var_26_arg_0 = var_25; [L85] SORT_3 var_26_arg_1 = var_24; [L86] SORT_3 var_26_arg_2 = var_23; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=22, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=6, state_5=0, state_8=6, var_10=0, var_10_arg_0=0, var_10_arg_1=6, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=6, var_20=15, var_21=1, var_21_arg_0=6, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=6, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=6, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=6, var_28_arg_0=5, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=5, var_30=1, var_30_arg_0=5, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=6, var_32_arg_0=1, var_32_arg_1=6, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=5, var_34=6, var_34_arg_0=0, var_34_arg_1=5, var_34_arg_2=6, var_4=0, var_7=1] [L87] EXPR var_26_arg_0 ? var_26_arg_1 : var_26_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=22, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=6, state_5=0, state_8=6, var_10=0, var_10_arg_0=0, var_10_arg_1=6, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=6, var_20=15, var_21=1, var_21_arg_0=6, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=6, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=6, var_26=0, var_26_arg_0=0, var_26_arg_0 ? var_26_arg_1 : var_26_arg_2=0, var_26_arg_1=1, var_26_arg_2=0, var_28=6, var_28_arg_0=5, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=5, var_30=1, var_30_arg_0=5, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=6, var_32_arg_0=1, var_32_arg_1=6, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=5, var_34=6, var_34_arg_0=0, var_34_arg_1=5, var_34_arg_2=6, var_4=0, var_7=1] [L87] SORT_3 var_26 = var_26_arg_0 ? var_26_arg_1 : var_26_arg_2; [L88] var_26 = var_26 & mask_SORT_3 [L89] SORT_3 next_27_arg_1 = var_26; [L90] SORT_3 var_33_arg_0 = state_5; [L91] SORT_3 var_33_arg_1 = state_8; [L92] SORT_1 var_33 = var_33_arg_0 > var_33_arg_1; [L93] SORT_3 var_29_arg_0 = state_5; [L94] SORT_3 var_29_arg_1 = state_8; [L95] SORT_1 var_29 = var_29_arg_0 == var_29_arg_1; [L96] SORT_3 var_30_arg_0 = state_8; [L97] SORT_3 var_30_arg_1 = var_20; [L98] SORT_1 var_30 = var_30_arg_0 != var_30_arg_1; [L99] SORT_1 var_31_arg_0 = var_29; [L100] SORT_1 var_31_arg_1 = var_30; [L101] SORT_1 var_31 = var_31_arg_0 | var_31_arg_1; [L102] var_31 = var_31 & mask_SORT_1 [L103] SORT_3 var_28_arg_0 = state_8; [L104] SORT_3 var_28_arg_1 = var_7; [L105] SORT_3 var_28 = var_28_arg_0 + var_28_arg_1; [L106] SORT_1 var_32_arg_0 = var_31; [L107] SORT_3 var_32_arg_1 = var_28; [L108] SORT_3 var_32_arg_2 = state_5; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=22, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=6, state_5=0, state_8=6, var_10=0, var_10_arg_0=0, var_10_arg_1=6, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=6, var_20=15, var_21=1, var_21_arg_0=6, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=6, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=6, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=7, var_28_arg_0=6, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=6, var_30=1, var_30_arg_0=6, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=6, var_32_arg_0=1, var_32_arg_1=7, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=6, var_34=6, var_34_arg_0=0, var_34_arg_1=5, var_34_arg_2=6, var_4=0, var_7=1] [L109] EXPR var_32_arg_0 ? var_32_arg_1 : var_32_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=22, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=6, state_5=0, state_8=6, var_10=0, var_10_arg_0=0, var_10_arg_1=6, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=6, var_20=15, var_21=1, var_21_arg_0=6, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=6, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=6, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=7, var_28_arg_0=6, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=6, var_30=1, var_30_arg_0=6, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=6, var_32_arg_0=1, var_32_arg_0 ? var_32_arg_1 : var_32_arg_2=7, var_32_arg_1=7, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=6, var_34=6, var_34_arg_0=0, var_34_arg_1=5, var_34_arg_2=6, var_4=0, var_7=1] [L109] SORT_3 var_32 = var_32_arg_0 ? var_32_arg_1 : var_32_arg_2; [L110] SORT_1 var_34_arg_0 = var_33; [L111] SORT_3 var_34_arg_1 = state_8; [L112] SORT_3 var_34_arg_2 = var_32; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=22, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=6, state_5=0, state_8=6, var_10=0, var_10_arg_0=0, var_10_arg_1=6, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=6, var_20=15, var_21=1, var_21_arg_0=6, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=6, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=6, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=7, var_28_arg_0=6, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=6, var_30=1, var_30_arg_0=6, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=7, var_32_arg_0=1, var_32_arg_1=7, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=6, var_34=6, var_34_arg_0=0, var_34_arg_1=6, var_34_arg_2=7, var_4=0, var_7=1] [L113] EXPR var_34_arg_0 ? var_34_arg_1 : var_34_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=22, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=6, state_5=0, state_8=6, var_10=0, var_10_arg_0=0, var_10_arg_1=6, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=6, var_20=15, var_21=1, var_21_arg_0=6, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=6, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=6, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=7, var_28_arg_0=6, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=6, var_30=1, var_30_arg_0=6, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=7, var_32_arg_0=1, var_32_arg_1=7, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=6, var_34=6, var_34_arg_0=0, var_34_arg_0 ? var_34_arg_1 : var_34_arg_2=7, var_34_arg_1=6, var_34_arg_2=7, var_4=0, var_7=1] [L113] SORT_3 var_34 = var_34_arg_0 ? var_34_arg_1 : var_34_arg_2; [L114] var_34 = var_34 & mask_SORT_3 [L115] SORT_3 next_35_arg_1 = var_34; [L117] state_5 = next_27_arg_1 [L118] state_8 = next_35_arg_1 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=22, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=7, state_5=0, state_8=7, var_10=0, var_10_arg_0=0, var_10_arg_1=6, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=6, var_20=15, var_21=1, var_21_arg_0=6, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=6, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=6, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=7, var_28_arg_0=6, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=6, var_30=1, var_30_arg_0=6, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=7, var_32_arg_0=1, var_32_arg_1=7, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=6, var_34=7, var_34_arg_0=0, var_34_arg_1=6, var_34_arg_2=7, var_4=0, var_7=1] [L47] input_2 = __VERIFIER_nondet_uchar() [L50] SORT_3 var_10_arg_0 = state_5; [L51] SORT_3 var_10_arg_1 = state_8; [L52] SORT_1 var_10 = var_10_arg_0 > var_10_arg_1; [L53] SORT_1 var_11_arg_0 = var_10; [L54] SORT_1 var_11 = ~var_11_arg_0; [L55] SORT_1 var_15_arg_0 = var_11; [L56] SORT_1 var_15 = ~var_15_arg_0; [L57] SORT_1 var_16_arg_0 = var_14; [L58] SORT_1 var_16_arg_1 = var_15; [L59] SORT_1 var_16 = var_16_arg_0 & var_16_arg_1; [L60] var_16 = var_16 & mask_SORT_1 [L61] SORT_1 bad_17_arg_0 = var_16; [L62] CALL __VERIFIER_assert(!(bad_17_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L62] RET __VERIFIER_assert(!(bad_17_arg_0)) [L64] SORT_3 var_25_arg_0 = state_5; [L65] SORT_3 var_25_arg_1 = state_8; [L66] SORT_1 var_25 = var_25_arg_0 == var_25_arg_1; [L67] SORT_3 var_24_arg_0 = state_5; [L68] SORT_3 var_24_arg_1 = var_7; [L69] SORT_3 var_24 = var_24_arg_0 + var_24_arg_1; [L70] SORT_3 var_19_arg_0 = state_5; [L71] SORT_3 var_19_arg_1 = state_8; [L72] SORT_1 var_19 = var_19_arg_0 > var_19_arg_1; [L73] SORT_3 var_21_arg_0 = state_8; [L74] SORT_3 var_21_arg_1 = var_20; [L75] SORT_1 var_21 = var_21_arg_0 != var_21_arg_1; [L76] SORT_1 var_22_arg_0 = var_19; [L77] SORT_1 var_22_arg_1 = var_21; [L78] SORT_1 var_22 = var_22_arg_0 | var_22_arg_1; [L79] var_22 = var_22 & mask_SORT_1 [L80] SORT_1 var_23_arg_0 = var_22; [L81] SORT_3 var_23_arg_1 = state_5; [L82] SORT_3 var_23_arg_2 = state_8; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=23, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=7, state_5=0, state_8=7, var_10=0, var_10_arg_0=0, var_10_arg_1=7, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=7, var_20=15, var_21=1, var_21_arg_0=7, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=7, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=7, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=7, var_28_arg_0=6, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=6, var_30=1, var_30_arg_0=6, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=7, var_32_arg_0=1, var_32_arg_1=7, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=6, var_34=7, var_34_arg_0=0, var_34_arg_1=6, var_34_arg_2=7, var_4=0, var_7=1] [L83] EXPR var_23_arg_0 ? var_23_arg_1 : var_23_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=23, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=7, state_5=0, state_8=7, var_10=0, var_10_arg_0=0, var_10_arg_1=7, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=7, var_20=15, var_21=1, var_21_arg_0=7, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_0 ? var_23_arg_1 : var_23_arg_2=0, var_23_arg_1=0, var_23_arg_2=7, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=7, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=7, var_28_arg_0=6, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=6, var_30=1, var_30_arg_0=6, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=7, var_32_arg_0=1, var_32_arg_1=7, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=6, var_34=7, var_34_arg_0=0, var_34_arg_1=6, var_34_arg_2=7, var_4=0, var_7=1] [L83] SORT_3 var_23 = var_23_arg_0 ? var_23_arg_1 : var_23_arg_2; [L84] SORT_1 var_26_arg_0 = var_25; [L85] SORT_3 var_26_arg_1 = var_24; [L86] SORT_3 var_26_arg_2 = var_23; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=23, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=7, state_5=0, state_8=7, var_10=0, var_10_arg_0=0, var_10_arg_1=7, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=7, var_20=15, var_21=1, var_21_arg_0=7, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=7, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=7, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=7, var_28_arg_0=6, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=6, var_30=1, var_30_arg_0=6, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=7, var_32_arg_0=1, var_32_arg_1=7, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=6, var_34=7, var_34_arg_0=0, var_34_arg_1=6, var_34_arg_2=7, var_4=0, var_7=1] [L87] EXPR var_26_arg_0 ? var_26_arg_1 : var_26_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=23, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=7, state_5=0, state_8=7, var_10=0, var_10_arg_0=0, var_10_arg_1=7, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=7, var_20=15, var_21=1, var_21_arg_0=7, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=7, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=7, var_26=0, var_26_arg_0=0, var_26_arg_0 ? var_26_arg_1 : var_26_arg_2=0, var_26_arg_1=1, var_26_arg_2=0, var_28=7, var_28_arg_0=6, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=6, var_30=1, var_30_arg_0=6, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=7, var_32_arg_0=1, var_32_arg_1=7, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=6, var_34=7, var_34_arg_0=0, var_34_arg_1=6, var_34_arg_2=7, var_4=0, var_7=1] [L87] SORT_3 var_26 = var_26_arg_0 ? var_26_arg_1 : var_26_arg_2; [L88] var_26 = var_26 & mask_SORT_3 [L89] SORT_3 next_27_arg_1 = var_26; [L90] SORT_3 var_33_arg_0 = state_5; [L91] SORT_3 var_33_arg_1 = state_8; [L92] SORT_1 var_33 = var_33_arg_0 > var_33_arg_1; [L93] SORT_3 var_29_arg_0 = state_5; [L94] SORT_3 var_29_arg_1 = state_8; [L95] SORT_1 var_29 = var_29_arg_0 == var_29_arg_1; [L96] SORT_3 var_30_arg_0 = state_8; [L97] SORT_3 var_30_arg_1 = var_20; [L98] SORT_1 var_30 = var_30_arg_0 != var_30_arg_1; [L99] SORT_1 var_31_arg_0 = var_29; [L100] SORT_1 var_31_arg_1 = var_30; [L101] SORT_1 var_31 = var_31_arg_0 | var_31_arg_1; [L102] var_31 = var_31 & mask_SORT_1 [L103] SORT_3 var_28_arg_0 = state_8; [L104] SORT_3 var_28_arg_1 = var_7; [L105] SORT_3 var_28 = var_28_arg_0 + var_28_arg_1; [L106] SORT_1 var_32_arg_0 = var_31; [L107] SORT_3 var_32_arg_1 = var_28; [L108] SORT_3 var_32_arg_2 = state_5; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=23, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=7, state_5=0, state_8=7, var_10=0, var_10_arg_0=0, var_10_arg_1=7, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=7, var_20=15, var_21=1, var_21_arg_0=7, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=7, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=7, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=8, var_28_arg_0=7, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=7, var_30=1, var_30_arg_0=7, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=7, var_32_arg_0=1, var_32_arg_1=8, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=7, var_34=7, var_34_arg_0=0, var_34_arg_1=6, var_34_arg_2=7, var_4=0, var_7=1] [L109] EXPR var_32_arg_0 ? var_32_arg_1 : var_32_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=23, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=7, state_5=0, state_8=7, var_10=0, var_10_arg_0=0, var_10_arg_1=7, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=7, var_20=15, var_21=1, var_21_arg_0=7, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=7, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=7, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=8, var_28_arg_0=7, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=7, var_30=1, var_30_arg_0=7, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=7, var_32_arg_0=1, var_32_arg_0 ? var_32_arg_1 : var_32_arg_2=8, var_32_arg_1=8, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=7, var_34=7, var_34_arg_0=0, var_34_arg_1=6, var_34_arg_2=7, var_4=0, var_7=1] [L109] SORT_3 var_32 = var_32_arg_0 ? var_32_arg_1 : var_32_arg_2; [L110] SORT_1 var_34_arg_0 = var_33; [L111] SORT_3 var_34_arg_1 = state_8; [L112] SORT_3 var_34_arg_2 = var_32; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=23, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=7, state_5=0, state_8=7, var_10=0, var_10_arg_0=0, var_10_arg_1=7, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=7, var_20=15, var_21=1, var_21_arg_0=7, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=7, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=7, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=8, var_28_arg_0=7, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=7, var_30=1, var_30_arg_0=7, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=8, var_32_arg_0=1, var_32_arg_1=8, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=7, var_34=7, var_34_arg_0=0, var_34_arg_1=7, var_34_arg_2=8, var_4=0, var_7=1] [L113] EXPR var_34_arg_0 ? var_34_arg_1 : var_34_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=23, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=7, state_5=0, state_8=7, var_10=0, var_10_arg_0=0, var_10_arg_1=7, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=7, var_20=15, var_21=1, var_21_arg_0=7, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=7, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=7, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=8, var_28_arg_0=7, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=7, var_30=1, var_30_arg_0=7, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=8, var_32_arg_0=1, var_32_arg_1=8, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=7, var_34=7, var_34_arg_0=0, var_34_arg_0 ? var_34_arg_1 : var_34_arg_2=8, var_34_arg_1=7, var_34_arg_2=8, var_4=0, var_7=1] [L113] SORT_3 var_34 = var_34_arg_0 ? var_34_arg_1 : var_34_arg_2; [L114] var_34 = var_34 & mask_SORT_3 [L115] SORT_3 next_35_arg_1 = var_34; [L117] state_5 = next_27_arg_1 [L118] state_8 = next_35_arg_1 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=23, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=8, state_5=0, state_8=8, var_10=0, var_10_arg_0=0, var_10_arg_1=7, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=7, var_20=15, var_21=1, var_21_arg_0=7, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=7, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=7, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=8, var_28_arg_0=7, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=7, var_30=1, var_30_arg_0=7, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=8, var_32_arg_0=1, var_32_arg_1=8, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=7, var_34=8, var_34_arg_0=0, var_34_arg_1=7, var_34_arg_2=8, var_4=0, var_7=1] [L47] input_2 = __VERIFIER_nondet_uchar() [L50] SORT_3 var_10_arg_0 = state_5; [L51] SORT_3 var_10_arg_1 = state_8; [L52] SORT_1 var_10 = var_10_arg_0 > var_10_arg_1; [L53] SORT_1 var_11_arg_0 = var_10; [L54] SORT_1 var_11 = ~var_11_arg_0; [L55] SORT_1 var_15_arg_0 = var_11; [L56] SORT_1 var_15 = ~var_15_arg_0; [L57] SORT_1 var_16_arg_0 = var_14; [L58] SORT_1 var_16_arg_1 = var_15; [L59] SORT_1 var_16 = var_16_arg_0 & var_16_arg_1; [L60] var_16 = var_16 & mask_SORT_1 [L61] SORT_1 bad_17_arg_0 = var_16; [L62] CALL __VERIFIER_assert(!(bad_17_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L62] RET __VERIFIER_assert(!(bad_17_arg_0)) [L64] SORT_3 var_25_arg_0 = state_5; [L65] SORT_3 var_25_arg_1 = state_8; [L66] SORT_1 var_25 = var_25_arg_0 == var_25_arg_1; [L67] SORT_3 var_24_arg_0 = state_5; [L68] SORT_3 var_24_arg_1 = var_7; [L69] SORT_3 var_24 = var_24_arg_0 + var_24_arg_1; [L70] SORT_3 var_19_arg_0 = state_5; [L71] SORT_3 var_19_arg_1 = state_8; [L72] SORT_1 var_19 = var_19_arg_0 > var_19_arg_1; [L73] SORT_3 var_21_arg_0 = state_8; [L74] SORT_3 var_21_arg_1 = var_20; [L75] SORT_1 var_21 = var_21_arg_0 != var_21_arg_1; [L76] SORT_1 var_22_arg_0 = var_19; [L77] SORT_1 var_22_arg_1 = var_21; [L78] SORT_1 var_22 = var_22_arg_0 | var_22_arg_1; [L79] var_22 = var_22 & mask_SORT_1 [L80] SORT_1 var_23_arg_0 = var_22; [L81] SORT_3 var_23_arg_1 = state_5; [L82] SORT_3 var_23_arg_2 = state_8; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=24, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=8, state_5=0, state_8=8, var_10=0, var_10_arg_0=0, var_10_arg_1=8, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=8, var_20=15, var_21=1, var_21_arg_0=8, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=8, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=8, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=8, var_28_arg_0=7, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=7, var_30=1, var_30_arg_0=7, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=8, var_32_arg_0=1, var_32_arg_1=8, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=7, var_34=8, var_34_arg_0=0, var_34_arg_1=7, var_34_arg_2=8, var_4=0, var_7=1] [L83] EXPR var_23_arg_0 ? var_23_arg_1 : var_23_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=24, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=8, state_5=0, state_8=8, var_10=0, var_10_arg_0=0, var_10_arg_1=8, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=8, var_20=15, var_21=1, var_21_arg_0=8, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_0 ? var_23_arg_1 : var_23_arg_2=0, var_23_arg_1=0, var_23_arg_2=8, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=8, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=8, var_28_arg_0=7, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=7, var_30=1, var_30_arg_0=7, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=8, var_32_arg_0=1, var_32_arg_1=8, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=7, var_34=8, var_34_arg_0=0, var_34_arg_1=7, var_34_arg_2=8, var_4=0, var_7=1] [L83] SORT_3 var_23 = var_23_arg_0 ? var_23_arg_1 : var_23_arg_2; [L84] SORT_1 var_26_arg_0 = var_25; [L85] SORT_3 var_26_arg_1 = var_24; [L86] SORT_3 var_26_arg_2 = var_23; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=24, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=8, state_5=0, state_8=8, var_10=0, var_10_arg_0=0, var_10_arg_1=8, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=8, var_20=15, var_21=1, var_21_arg_0=8, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=8, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=8, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=8, var_28_arg_0=7, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=7, var_30=1, var_30_arg_0=7, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=8, var_32_arg_0=1, var_32_arg_1=8, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=7, var_34=8, var_34_arg_0=0, var_34_arg_1=7, var_34_arg_2=8, var_4=0, var_7=1] [L87] EXPR var_26_arg_0 ? var_26_arg_1 : var_26_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=24, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=8, state_5=0, state_8=8, var_10=0, var_10_arg_0=0, var_10_arg_1=8, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=8, var_20=15, var_21=1, var_21_arg_0=8, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=8, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=8, var_26=0, var_26_arg_0=0, var_26_arg_0 ? var_26_arg_1 : var_26_arg_2=0, var_26_arg_1=1, var_26_arg_2=0, var_28=8, var_28_arg_0=7, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=7, var_30=1, var_30_arg_0=7, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=8, var_32_arg_0=1, var_32_arg_1=8, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=7, var_34=8, var_34_arg_0=0, var_34_arg_1=7, var_34_arg_2=8, var_4=0, var_7=1] [L87] SORT_3 var_26 = var_26_arg_0 ? var_26_arg_1 : var_26_arg_2; [L88] var_26 = var_26 & mask_SORT_3 [L89] SORT_3 next_27_arg_1 = var_26; [L90] SORT_3 var_33_arg_0 = state_5; [L91] SORT_3 var_33_arg_1 = state_8; [L92] SORT_1 var_33 = var_33_arg_0 > var_33_arg_1; [L93] SORT_3 var_29_arg_0 = state_5; [L94] SORT_3 var_29_arg_1 = state_8; [L95] SORT_1 var_29 = var_29_arg_0 == var_29_arg_1; [L96] SORT_3 var_30_arg_0 = state_8; [L97] SORT_3 var_30_arg_1 = var_20; [L98] SORT_1 var_30 = var_30_arg_0 != var_30_arg_1; [L99] SORT_1 var_31_arg_0 = var_29; [L100] SORT_1 var_31_arg_1 = var_30; [L101] SORT_1 var_31 = var_31_arg_0 | var_31_arg_1; [L102] var_31 = var_31 & mask_SORT_1 [L103] SORT_3 var_28_arg_0 = state_8; [L104] SORT_3 var_28_arg_1 = var_7; [L105] SORT_3 var_28 = var_28_arg_0 + var_28_arg_1; [L106] SORT_1 var_32_arg_0 = var_31; [L107] SORT_3 var_32_arg_1 = var_28; [L108] SORT_3 var_32_arg_2 = state_5; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=24, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=8, state_5=0, state_8=8, var_10=0, var_10_arg_0=0, var_10_arg_1=8, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=8, var_20=15, var_21=1, var_21_arg_0=8, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=8, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=8, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=9, var_28_arg_0=8, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=8, var_30=1, var_30_arg_0=8, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=8, var_32_arg_0=1, var_32_arg_1=9, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=8, var_34=8, var_34_arg_0=0, var_34_arg_1=7, var_34_arg_2=8, var_4=0, var_7=1] [L109] EXPR var_32_arg_0 ? var_32_arg_1 : var_32_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=24, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=8, state_5=0, state_8=8, var_10=0, var_10_arg_0=0, var_10_arg_1=8, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=8, var_20=15, var_21=1, var_21_arg_0=8, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=8, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=8, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=9, var_28_arg_0=8, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=8, var_30=1, var_30_arg_0=8, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=8, var_32_arg_0=1, var_32_arg_0 ? var_32_arg_1 : var_32_arg_2=9, var_32_arg_1=9, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=8, var_34=8, var_34_arg_0=0, var_34_arg_1=7, var_34_arg_2=8, var_4=0, var_7=1] [L109] SORT_3 var_32 = var_32_arg_0 ? var_32_arg_1 : var_32_arg_2; [L110] SORT_1 var_34_arg_0 = var_33; [L111] SORT_3 var_34_arg_1 = state_8; [L112] SORT_3 var_34_arg_2 = var_32; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=24, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=8, state_5=0, state_8=8, var_10=0, var_10_arg_0=0, var_10_arg_1=8, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=8, var_20=15, var_21=1, var_21_arg_0=8, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=8, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=8, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=9, var_28_arg_0=8, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=8, var_30=1, var_30_arg_0=8, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=9, var_32_arg_0=1, var_32_arg_1=9, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=8, var_34=8, var_34_arg_0=0, var_34_arg_1=8, var_34_arg_2=9, var_4=0, var_7=1] [L113] EXPR var_34_arg_0 ? var_34_arg_1 : var_34_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=24, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=8, state_5=0, state_8=8, var_10=0, var_10_arg_0=0, var_10_arg_1=8, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=8, var_20=15, var_21=1, var_21_arg_0=8, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=8, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=8, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=9, var_28_arg_0=8, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=8, var_30=1, var_30_arg_0=8, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=9, var_32_arg_0=1, var_32_arg_1=9, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=8, var_34=8, var_34_arg_0=0, var_34_arg_0 ? var_34_arg_1 : var_34_arg_2=9, var_34_arg_1=8, var_34_arg_2=9, var_4=0, var_7=1] [L113] SORT_3 var_34 = var_34_arg_0 ? var_34_arg_1 : var_34_arg_2; [L114] var_34 = var_34 & mask_SORT_3 [L115] SORT_3 next_35_arg_1 = var_34; [L117] state_5 = next_27_arg_1 [L118] state_8 = next_35_arg_1 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=24, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=9, state_5=0, state_8=9, var_10=0, var_10_arg_0=0, var_10_arg_1=8, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=8, var_20=15, var_21=1, var_21_arg_0=8, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=8, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=8, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=9, var_28_arg_0=8, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=8, var_30=1, var_30_arg_0=8, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=9, var_32_arg_0=1, var_32_arg_1=9, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=8, var_34=9, var_34_arg_0=0, var_34_arg_1=8, var_34_arg_2=9, var_4=0, var_7=1] [L47] input_2 = __VERIFIER_nondet_uchar() [L50] SORT_3 var_10_arg_0 = state_5; [L51] SORT_3 var_10_arg_1 = state_8; [L52] SORT_1 var_10 = var_10_arg_0 > var_10_arg_1; [L53] SORT_1 var_11_arg_0 = var_10; [L54] SORT_1 var_11 = ~var_11_arg_0; [L55] SORT_1 var_15_arg_0 = var_11; [L56] SORT_1 var_15 = ~var_15_arg_0; [L57] SORT_1 var_16_arg_0 = var_14; [L58] SORT_1 var_16_arg_1 = var_15; [L59] SORT_1 var_16 = var_16_arg_0 & var_16_arg_1; [L60] var_16 = var_16 & mask_SORT_1 [L61] SORT_1 bad_17_arg_0 = var_16; [L62] CALL __VERIFIER_assert(!(bad_17_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L62] RET __VERIFIER_assert(!(bad_17_arg_0)) [L64] SORT_3 var_25_arg_0 = state_5; [L65] SORT_3 var_25_arg_1 = state_8; [L66] SORT_1 var_25 = var_25_arg_0 == var_25_arg_1; [L67] SORT_3 var_24_arg_0 = state_5; [L68] SORT_3 var_24_arg_1 = var_7; [L69] SORT_3 var_24 = var_24_arg_0 + var_24_arg_1; [L70] SORT_3 var_19_arg_0 = state_5; [L71] SORT_3 var_19_arg_1 = state_8; [L72] SORT_1 var_19 = var_19_arg_0 > var_19_arg_1; [L73] SORT_3 var_21_arg_0 = state_8; [L74] SORT_3 var_21_arg_1 = var_20; [L75] SORT_1 var_21 = var_21_arg_0 != var_21_arg_1; [L76] SORT_1 var_22_arg_0 = var_19; [L77] SORT_1 var_22_arg_1 = var_21; [L78] SORT_1 var_22 = var_22_arg_0 | var_22_arg_1; [L79] var_22 = var_22 & mask_SORT_1 [L80] SORT_1 var_23_arg_0 = var_22; [L81] SORT_3 var_23_arg_1 = state_5; [L82] SORT_3 var_23_arg_2 = state_8; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=25, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=9, state_5=0, state_8=9, var_10=0, var_10_arg_0=0, var_10_arg_1=9, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=9, var_20=15, var_21=1, var_21_arg_0=9, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=9, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=9, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=9, var_28_arg_0=8, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=8, var_30=1, var_30_arg_0=8, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=9, var_32_arg_0=1, var_32_arg_1=9, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=8, var_34=9, var_34_arg_0=0, var_34_arg_1=8, var_34_arg_2=9, var_4=0, var_7=1] [L83] EXPR var_23_arg_0 ? var_23_arg_1 : var_23_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=25, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=9, state_5=0, state_8=9, var_10=0, var_10_arg_0=0, var_10_arg_1=9, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=9, var_20=15, var_21=1, var_21_arg_0=9, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_0 ? var_23_arg_1 : var_23_arg_2=0, var_23_arg_1=0, var_23_arg_2=9, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=9, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=9, var_28_arg_0=8, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=8, var_30=1, var_30_arg_0=8, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=9, var_32_arg_0=1, var_32_arg_1=9, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=8, var_34=9, var_34_arg_0=0, var_34_arg_1=8, var_34_arg_2=9, var_4=0, var_7=1] [L83] SORT_3 var_23 = var_23_arg_0 ? var_23_arg_1 : var_23_arg_2; [L84] SORT_1 var_26_arg_0 = var_25; [L85] SORT_3 var_26_arg_1 = var_24; [L86] SORT_3 var_26_arg_2 = var_23; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=25, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=9, state_5=0, state_8=9, var_10=0, var_10_arg_0=0, var_10_arg_1=9, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=9, var_20=15, var_21=1, var_21_arg_0=9, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=9, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=9, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=9, var_28_arg_0=8, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=8, var_30=1, var_30_arg_0=8, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=9, var_32_arg_0=1, var_32_arg_1=9, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=8, var_34=9, var_34_arg_0=0, var_34_arg_1=8, var_34_arg_2=9, var_4=0, var_7=1] [L87] EXPR var_26_arg_0 ? var_26_arg_1 : var_26_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=25, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=9, state_5=0, state_8=9, var_10=0, var_10_arg_0=0, var_10_arg_1=9, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=9, var_20=15, var_21=1, var_21_arg_0=9, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=9, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=9, var_26=0, var_26_arg_0=0, var_26_arg_0 ? var_26_arg_1 : var_26_arg_2=0, var_26_arg_1=1, var_26_arg_2=0, var_28=9, var_28_arg_0=8, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=8, var_30=1, var_30_arg_0=8, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=9, var_32_arg_0=1, var_32_arg_1=9, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=8, var_34=9, var_34_arg_0=0, var_34_arg_1=8, var_34_arg_2=9, var_4=0, var_7=1] [L87] SORT_3 var_26 = var_26_arg_0 ? var_26_arg_1 : var_26_arg_2; [L88] var_26 = var_26 & mask_SORT_3 [L89] SORT_3 next_27_arg_1 = var_26; [L90] SORT_3 var_33_arg_0 = state_5; [L91] SORT_3 var_33_arg_1 = state_8; [L92] SORT_1 var_33 = var_33_arg_0 > var_33_arg_1; [L93] SORT_3 var_29_arg_0 = state_5; [L94] SORT_3 var_29_arg_1 = state_8; [L95] SORT_1 var_29 = var_29_arg_0 == var_29_arg_1; [L96] SORT_3 var_30_arg_0 = state_8; [L97] SORT_3 var_30_arg_1 = var_20; [L98] SORT_1 var_30 = var_30_arg_0 != var_30_arg_1; [L99] SORT_1 var_31_arg_0 = var_29; [L100] SORT_1 var_31_arg_1 = var_30; [L101] SORT_1 var_31 = var_31_arg_0 | var_31_arg_1; [L102] var_31 = var_31 & mask_SORT_1 [L103] SORT_3 var_28_arg_0 = state_8; [L104] SORT_3 var_28_arg_1 = var_7; [L105] SORT_3 var_28 = var_28_arg_0 + var_28_arg_1; [L106] SORT_1 var_32_arg_0 = var_31; [L107] SORT_3 var_32_arg_1 = var_28; [L108] SORT_3 var_32_arg_2 = state_5; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=25, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=9, state_5=0, state_8=9, var_10=0, var_10_arg_0=0, var_10_arg_1=9, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=9, var_20=15, var_21=1, var_21_arg_0=9, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=9, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=9, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=10, var_28_arg_0=9, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=9, var_30=1, var_30_arg_0=9, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=9, var_32_arg_0=1, var_32_arg_1=10, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=9, var_34=9, var_34_arg_0=0, var_34_arg_1=8, var_34_arg_2=9, var_4=0, var_7=1] [L109] EXPR var_32_arg_0 ? var_32_arg_1 : var_32_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=25, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=9, state_5=0, state_8=9, var_10=0, var_10_arg_0=0, var_10_arg_1=9, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=9, var_20=15, var_21=1, var_21_arg_0=9, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=9, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=9, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=10, var_28_arg_0=9, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=9, var_30=1, var_30_arg_0=9, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=9, var_32_arg_0=1, var_32_arg_0 ? var_32_arg_1 : var_32_arg_2=10, var_32_arg_1=10, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=9, var_34=9, var_34_arg_0=0, var_34_arg_1=8, var_34_arg_2=9, var_4=0, var_7=1] [L109] SORT_3 var_32 = var_32_arg_0 ? var_32_arg_1 : var_32_arg_2; [L110] SORT_1 var_34_arg_0 = var_33; [L111] SORT_3 var_34_arg_1 = state_8; [L112] SORT_3 var_34_arg_2 = var_32; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=25, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=9, state_5=0, state_8=9, var_10=0, var_10_arg_0=0, var_10_arg_1=9, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=9, var_20=15, var_21=1, var_21_arg_0=9, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=9, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=9, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=10, var_28_arg_0=9, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=9, var_30=1, var_30_arg_0=9, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=10, var_32_arg_0=1, var_32_arg_1=10, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=9, var_34=9, var_34_arg_0=0, var_34_arg_1=9, var_34_arg_2=10, var_4=0, var_7=1] [L113] EXPR var_34_arg_0 ? var_34_arg_1 : var_34_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=25, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=9, state_5=0, state_8=9, var_10=0, var_10_arg_0=0, var_10_arg_1=9, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=9, var_20=15, var_21=1, var_21_arg_0=9, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=9, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=9, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=10, var_28_arg_0=9, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=9, var_30=1, var_30_arg_0=9, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=10, var_32_arg_0=1, var_32_arg_1=10, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=9, var_34=9, var_34_arg_0=0, var_34_arg_0 ? var_34_arg_1 : var_34_arg_2=10, var_34_arg_1=9, var_34_arg_2=10, var_4=0, var_7=1] [L113] SORT_3 var_34 = var_34_arg_0 ? var_34_arg_1 : var_34_arg_2; [L114] var_34 = var_34 & mask_SORT_3 [L115] SORT_3 next_35_arg_1 = var_34; [L117] state_5 = next_27_arg_1 [L118] state_8 = next_35_arg_1 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=25, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=10, state_5=0, state_8=10, var_10=0, var_10_arg_0=0, var_10_arg_1=9, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=9, var_20=15, var_21=1, var_21_arg_0=9, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=9, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=9, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=10, var_28_arg_0=9, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=9, var_30=1, var_30_arg_0=9, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=10, var_32_arg_0=1, var_32_arg_1=10, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=9, var_34=10, var_34_arg_0=0, var_34_arg_1=9, var_34_arg_2=10, var_4=0, var_7=1] [L47] input_2 = __VERIFIER_nondet_uchar() [L50] SORT_3 var_10_arg_0 = state_5; [L51] SORT_3 var_10_arg_1 = state_8; [L52] SORT_1 var_10 = var_10_arg_0 > var_10_arg_1; [L53] SORT_1 var_11_arg_0 = var_10; [L54] SORT_1 var_11 = ~var_11_arg_0; [L55] SORT_1 var_15_arg_0 = var_11; [L56] SORT_1 var_15 = ~var_15_arg_0; [L57] SORT_1 var_16_arg_0 = var_14; [L58] SORT_1 var_16_arg_1 = var_15; [L59] SORT_1 var_16 = var_16_arg_0 & var_16_arg_1; [L60] var_16 = var_16 & mask_SORT_1 [L61] SORT_1 bad_17_arg_0 = var_16; [L62] CALL __VERIFIER_assert(!(bad_17_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L62] RET __VERIFIER_assert(!(bad_17_arg_0)) [L64] SORT_3 var_25_arg_0 = state_5; [L65] SORT_3 var_25_arg_1 = state_8; [L66] SORT_1 var_25 = var_25_arg_0 == var_25_arg_1; [L67] SORT_3 var_24_arg_0 = state_5; [L68] SORT_3 var_24_arg_1 = var_7; [L69] SORT_3 var_24 = var_24_arg_0 + var_24_arg_1; [L70] SORT_3 var_19_arg_0 = state_5; [L71] SORT_3 var_19_arg_1 = state_8; [L72] SORT_1 var_19 = var_19_arg_0 > var_19_arg_1; [L73] SORT_3 var_21_arg_0 = state_8; [L74] SORT_3 var_21_arg_1 = var_20; [L75] SORT_1 var_21 = var_21_arg_0 != var_21_arg_1; [L76] SORT_1 var_22_arg_0 = var_19; [L77] SORT_1 var_22_arg_1 = var_21; [L78] SORT_1 var_22 = var_22_arg_0 | var_22_arg_1; [L79] var_22 = var_22 & mask_SORT_1 [L80] SORT_1 var_23_arg_0 = var_22; [L81] SORT_3 var_23_arg_1 = state_5; [L82] SORT_3 var_23_arg_2 = state_8; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=26, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=10, state_5=0, state_8=10, var_10=0, var_10_arg_0=0, var_10_arg_1=10, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=10, var_20=15, var_21=1, var_21_arg_0=10, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=10, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=10, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=10, var_28_arg_0=9, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=9, var_30=1, var_30_arg_0=9, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=10, var_32_arg_0=1, var_32_arg_1=10, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=9, var_34=10, var_34_arg_0=0, var_34_arg_1=9, var_34_arg_2=10, var_4=0, var_7=1] [L83] EXPR var_23_arg_0 ? var_23_arg_1 : var_23_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=26, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=10, state_5=0, state_8=10, var_10=0, var_10_arg_0=0, var_10_arg_1=10, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=10, var_20=15, var_21=1, var_21_arg_0=10, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_0 ? var_23_arg_1 : var_23_arg_2=0, var_23_arg_1=0, var_23_arg_2=10, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=10, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=10, var_28_arg_0=9, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=9, var_30=1, var_30_arg_0=9, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=10, var_32_arg_0=1, var_32_arg_1=10, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=9, var_34=10, var_34_arg_0=0, var_34_arg_1=9, var_34_arg_2=10, var_4=0, var_7=1] [L83] SORT_3 var_23 = var_23_arg_0 ? var_23_arg_1 : var_23_arg_2; [L84] SORT_1 var_26_arg_0 = var_25; [L85] SORT_3 var_26_arg_1 = var_24; [L86] SORT_3 var_26_arg_2 = var_23; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=26, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=10, state_5=0, state_8=10, var_10=0, var_10_arg_0=0, var_10_arg_1=10, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=10, var_20=15, var_21=1, var_21_arg_0=10, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=10, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=10, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=10, var_28_arg_0=9, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=9, var_30=1, var_30_arg_0=9, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=10, var_32_arg_0=1, var_32_arg_1=10, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=9, var_34=10, var_34_arg_0=0, var_34_arg_1=9, var_34_arg_2=10, var_4=0, var_7=1] [L87] EXPR var_26_arg_0 ? var_26_arg_1 : var_26_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=26, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=10, state_5=0, state_8=10, var_10=0, var_10_arg_0=0, var_10_arg_1=10, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=10, var_20=15, var_21=1, var_21_arg_0=10, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=10, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=10, var_26=0, var_26_arg_0=0, var_26_arg_0 ? var_26_arg_1 : var_26_arg_2=0, var_26_arg_1=1, var_26_arg_2=0, var_28=10, var_28_arg_0=9, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=9, var_30=1, var_30_arg_0=9, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=10, var_32_arg_0=1, var_32_arg_1=10, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=9, var_34=10, var_34_arg_0=0, var_34_arg_1=9, var_34_arg_2=10, var_4=0, var_7=1] [L87] SORT_3 var_26 = var_26_arg_0 ? var_26_arg_1 : var_26_arg_2; [L88] var_26 = var_26 & mask_SORT_3 [L89] SORT_3 next_27_arg_1 = var_26; [L90] SORT_3 var_33_arg_0 = state_5; [L91] SORT_3 var_33_arg_1 = state_8; [L92] SORT_1 var_33 = var_33_arg_0 > var_33_arg_1; [L93] SORT_3 var_29_arg_0 = state_5; [L94] SORT_3 var_29_arg_1 = state_8; [L95] SORT_1 var_29 = var_29_arg_0 == var_29_arg_1; [L96] SORT_3 var_30_arg_0 = state_8; [L97] SORT_3 var_30_arg_1 = var_20; [L98] SORT_1 var_30 = var_30_arg_0 != var_30_arg_1; [L99] SORT_1 var_31_arg_0 = var_29; [L100] SORT_1 var_31_arg_1 = var_30; [L101] SORT_1 var_31 = var_31_arg_0 | var_31_arg_1; [L102] var_31 = var_31 & mask_SORT_1 [L103] SORT_3 var_28_arg_0 = state_8; [L104] SORT_3 var_28_arg_1 = var_7; [L105] SORT_3 var_28 = var_28_arg_0 + var_28_arg_1; [L106] SORT_1 var_32_arg_0 = var_31; [L107] SORT_3 var_32_arg_1 = var_28; [L108] SORT_3 var_32_arg_2 = state_5; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=26, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=10, state_5=0, state_8=10, var_10=0, var_10_arg_0=0, var_10_arg_1=10, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=10, var_20=15, var_21=1, var_21_arg_0=10, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=10, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=10, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=11, var_28_arg_0=10, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=10, var_30=1, var_30_arg_0=10, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=10, var_32_arg_0=1, var_32_arg_1=11, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=10, var_34=10, var_34_arg_0=0, var_34_arg_1=9, var_34_arg_2=10, var_4=0, var_7=1] [L109] EXPR var_32_arg_0 ? var_32_arg_1 : var_32_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=26, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=10, state_5=0, state_8=10, var_10=0, var_10_arg_0=0, var_10_arg_1=10, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=10, var_20=15, var_21=1, var_21_arg_0=10, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=10, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=10, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=11, var_28_arg_0=10, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=10, var_30=1, var_30_arg_0=10, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=10, var_32_arg_0=1, var_32_arg_0 ? var_32_arg_1 : var_32_arg_2=11, var_32_arg_1=11, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=10, var_34=10, var_34_arg_0=0, var_34_arg_1=9, var_34_arg_2=10, var_4=0, var_7=1] [L109] SORT_3 var_32 = var_32_arg_0 ? var_32_arg_1 : var_32_arg_2; [L110] SORT_1 var_34_arg_0 = var_33; [L111] SORT_3 var_34_arg_1 = state_8; [L112] SORT_3 var_34_arg_2 = var_32; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=26, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=10, state_5=0, state_8=10, var_10=0, var_10_arg_0=0, var_10_arg_1=10, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=10, var_20=15, var_21=1, var_21_arg_0=10, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=10, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=10, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=11, var_28_arg_0=10, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=10, var_30=1, var_30_arg_0=10, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=11, var_32_arg_0=1, var_32_arg_1=11, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=10, var_34=10, var_34_arg_0=0, var_34_arg_1=10, var_34_arg_2=11, var_4=0, var_7=1] [L113] EXPR var_34_arg_0 ? var_34_arg_1 : var_34_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=26, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=10, state_5=0, state_8=10, var_10=0, var_10_arg_0=0, var_10_arg_1=10, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=10, var_20=15, var_21=1, var_21_arg_0=10, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=10, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=10, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=11, var_28_arg_0=10, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=10, var_30=1, var_30_arg_0=10, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=11, var_32_arg_0=1, var_32_arg_1=11, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=10, var_34=10, var_34_arg_0=0, var_34_arg_0 ? var_34_arg_1 : var_34_arg_2=11, var_34_arg_1=10, var_34_arg_2=11, var_4=0, var_7=1] [L113] SORT_3 var_34 = var_34_arg_0 ? var_34_arg_1 : var_34_arg_2; [L114] var_34 = var_34 & mask_SORT_3 [L115] SORT_3 next_35_arg_1 = var_34; [L117] state_5 = next_27_arg_1 [L118] state_8 = next_35_arg_1 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=26, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=11, state_5=0, state_8=11, var_10=0, var_10_arg_0=0, var_10_arg_1=10, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=10, var_20=15, var_21=1, var_21_arg_0=10, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=10, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=10, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=11, var_28_arg_0=10, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=10, var_30=1, var_30_arg_0=10, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=11, var_32_arg_0=1, var_32_arg_1=11, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=10, var_34=11, var_34_arg_0=0, var_34_arg_1=10, var_34_arg_2=11, var_4=0, var_7=1] [L47] input_2 = __VERIFIER_nondet_uchar() [L50] SORT_3 var_10_arg_0 = state_5; [L51] SORT_3 var_10_arg_1 = state_8; [L52] SORT_1 var_10 = var_10_arg_0 > var_10_arg_1; [L53] SORT_1 var_11_arg_0 = var_10; [L54] SORT_1 var_11 = ~var_11_arg_0; [L55] SORT_1 var_15_arg_0 = var_11; [L56] SORT_1 var_15 = ~var_15_arg_0; [L57] SORT_1 var_16_arg_0 = var_14; [L58] SORT_1 var_16_arg_1 = var_15; [L59] SORT_1 var_16 = var_16_arg_0 & var_16_arg_1; [L60] var_16 = var_16 & mask_SORT_1 [L61] SORT_1 bad_17_arg_0 = var_16; [L62] CALL __VERIFIER_assert(!(bad_17_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L62] RET __VERIFIER_assert(!(bad_17_arg_0)) [L64] SORT_3 var_25_arg_0 = state_5; [L65] SORT_3 var_25_arg_1 = state_8; [L66] SORT_1 var_25 = var_25_arg_0 == var_25_arg_1; [L67] SORT_3 var_24_arg_0 = state_5; [L68] SORT_3 var_24_arg_1 = var_7; [L69] SORT_3 var_24 = var_24_arg_0 + var_24_arg_1; [L70] SORT_3 var_19_arg_0 = state_5; [L71] SORT_3 var_19_arg_1 = state_8; [L72] SORT_1 var_19 = var_19_arg_0 > var_19_arg_1; [L73] SORT_3 var_21_arg_0 = state_8; [L74] SORT_3 var_21_arg_1 = var_20; [L75] SORT_1 var_21 = var_21_arg_0 != var_21_arg_1; [L76] SORT_1 var_22_arg_0 = var_19; [L77] SORT_1 var_22_arg_1 = var_21; [L78] SORT_1 var_22 = var_22_arg_0 | var_22_arg_1; [L79] var_22 = var_22 & mask_SORT_1 [L80] SORT_1 var_23_arg_0 = var_22; [L81] SORT_3 var_23_arg_1 = state_5; [L82] SORT_3 var_23_arg_2 = state_8; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=27, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=11, state_5=0, state_8=11, var_10=0, var_10_arg_0=0, var_10_arg_1=11, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=11, var_20=15, var_21=1, var_21_arg_0=11, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=11, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=11, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=11, var_28_arg_0=10, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=10, var_30=1, var_30_arg_0=10, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=11, var_32_arg_0=1, var_32_arg_1=11, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=10, var_34=11, var_34_arg_0=0, var_34_arg_1=10, var_34_arg_2=11, var_4=0, var_7=1] [L83] EXPR var_23_arg_0 ? var_23_arg_1 : var_23_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=27, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=11, state_5=0, state_8=11, var_10=0, var_10_arg_0=0, var_10_arg_1=11, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=11, var_20=15, var_21=1, var_21_arg_0=11, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_0 ? var_23_arg_1 : var_23_arg_2=0, var_23_arg_1=0, var_23_arg_2=11, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=11, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=11, var_28_arg_0=10, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=10, var_30=1, var_30_arg_0=10, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=11, var_32_arg_0=1, var_32_arg_1=11, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=10, var_34=11, var_34_arg_0=0, var_34_arg_1=10, var_34_arg_2=11, var_4=0, var_7=1] [L83] SORT_3 var_23 = var_23_arg_0 ? var_23_arg_1 : var_23_arg_2; [L84] SORT_1 var_26_arg_0 = var_25; [L85] SORT_3 var_26_arg_1 = var_24; [L86] SORT_3 var_26_arg_2 = var_23; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=27, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=11, state_5=0, state_8=11, var_10=0, var_10_arg_0=0, var_10_arg_1=11, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=11, var_20=15, var_21=1, var_21_arg_0=11, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=11, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=11, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=11, var_28_arg_0=10, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=10, var_30=1, var_30_arg_0=10, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=11, var_32_arg_0=1, var_32_arg_1=11, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=10, var_34=11, var_34_arg_0=0, var_34_arg_1=10, var_34_arg_2=11, var_4=0, var_7=1] [L87] EXPR var_26_arg_0 ? var_26_arg_1 : var_26_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=27, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=11, state_5=0, state_8=11, var_10=0, var_10_arg_0=0, var_10_arg_1=11, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=11, var_20=15, var_21=1, var_21_arg_0=11, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=11, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=11, var_26=0, var_26_arg_0=0, var_26_arg_0 ? var_26_arg_1 : var_26_arg_2=0, var_26_arg_1=1, var_26_arg_2=0, var_28=11, var_28_arg_0=10, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=10, var_30=1, var_30_arg_0=10, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=11, var_32_arg_0=1, var_32_arg_1=11, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=10, var_34=11, var_34_arg_0=0, var_34_arg_1=10, var_34_arg_2=11, var_4=0, var_7=1] [L87] SORT_3 var_26 = var_26_arg_0 ? var_26_arg_1 : var_26_arg_2; [L88] var_26 = var_26 & mask_SORT_3 [L89] SORT_3 next_27_arg_1 = var_26; [L90] SORT_3 var_33_arg_0 = state_5; [L91] SORT_3 var_33_arg_1 = state_8; [L92] SORT_1 var_33 = var_33_arg_0 > var_33_arg_1; [L93] SORT_3 var_29_arg_0 = state_5; [L94] SORT_3 var_29_arg_1 = state_8; [L95] SORT_1 var_29 = var_29_arg_0 == var_29_arg_1; [L96] SORT_3 var_30_arg_0 = state_8; [L97] SORT_3 var_30_arg_1 = var_20; [L98] SORT_1 var_30 = var_30_arg_0 != var_30_arg_1; [L99] SORT_1 var_31_arg_0 = var_29; [L100] SORT_1 var_31_arg_1 = var_30; [L101] SORT_1 var_31 = var_31_arg_0 | var_31_arg_1; [L102] var_31 = var_31 & mask_SORT_1 [L103] SORT_3 var_28_arg_0 = state_8; [L104] SORT_3 var_28_arg_1 = var_7; [L105] SORT_3 var_28 = var_28_arg_0 + var_28_arg_1; [L106] SORT_1 var_32_arg_0 = var_31; [L107] SORT_3 var_32_arg_1 = var_28; [L108] SORT_3 var_32_arg_2 = state_5; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=27, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=11, state_5=0, state_8=11, var_10=0, var_10_arg_0=0, var_10_arg_1=11, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=11, var_20=15, var_21=1, var_21_arg_0=11, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=11, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=11, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=12, var_28_arg_0=11, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=11, var_30=1, var_30_arg_0=11, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=11, var_32_arg_0=1, var_32_arg_1=12, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=11, var_34=11, var_34_arg_0=0, var_34_arg_1=10, var_34_arg_2=11, var_4=0, var_7=1] [L109] EXPR var_32_arg_0 ? var_32_arg_1 : var_32_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=27, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=11, state_5=0, state_8=11, var_10=0, var_10_arg_0=0, var_10_arg_1=11, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=11, var_20=15, var_21=1, var_21_arg_0=11, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=11, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=11, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=12, var_28_arg_0=11, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=11, var_30=1, var_30_arg_0=11, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=11, var_32_arg_0=1, var_32_arg_0 ? var_32_arg_1 : var_32_arg_2=12, var_32_arg_1=12, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=11, var_34=11, var_34_arg_0=0, var_34_arg_1=10, var_34_arg_2=11, var_4=0, var_7=1] [L109] SORT_3 var_32 = var_32_arg_0 ? var_32_arg_1 : var_32_arg_2; [L110] SORT_1 var_34_arg_0 = var_33; [L111] SORT_3 var_34_arg_1 = state_8; [L112] SORT_3 var_34_arg_2 = var_32; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=27, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=11, state_5=0, state_8=11, var_10=0, var_10_arg_0=0, var_10_arg_1=11, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=11, var_20=15, var_21=1, var_21_arg_0=11, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=11, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=11, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=12, var_28_arg_0=11, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=11, var_30=1, var_30_arg_0=11, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=12, var_32_arg_0=1, var_32_arg_1=12, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=11, var_34=11, var_34_arg_0=0, var_34_arg_1=11, var_34_arg_2=12, var_4=0, var_7=1] [L113] EXPR var_34_arg_0 ? var_34_arg_1 : var_34_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=27, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=11, state_5=0, state_8=11, var_10=0, var_10_arg_0=0, var_10_arg_1=11, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=11, var_20=15, var_21=1, var_21_arg_0=11, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=11, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=11, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=12, var_28_arg_0=11, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=11, var_30=1, var_30_arg_0=11, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=12, var_32_arg_0=1, var_32_arg_1=12, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=11, var_34=11, var_34_arg_0=0, var_34_arg_0 ? var_34_arg_1 : var_34_arg_2=12, var_34_arg_1=11, var_34_arg_2=12, var_4=0, var_7=1] [L113] SORT_3 var_34 = var_34_arg_0 ? var_34_arg_1 : var_34_arg_2; [L114] var_34 = var_34 & mask_SORT_3 [L115] SORT_3 next_35_arg_1 = var_34; [L117] state_5 = next_27_arg_1 [L118] state_8 = next_35_arg_1 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=27, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=12, state_5=0, state_8=12, var_10=0, var_10_arg_0=0, var_10_arg_1=11, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=11, var_20=15, var_21=1, var_21_arg_0=11, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=11, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=11, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=12, var_28_arg_0=11, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=11, var_30=1, var_30_arg_0=11, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=12, var_32_arg_0=1, var_32_arg_1=12, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=11, var_34=12, var_34_arg_0=0, var_34_arg_1=11, var_34_arg_2=12, var_4=0, var_7=1] [L47] input_2 = __VERIFIER_nondet_uchar() [L50] SORT_3 var_10_arg_0 = state_5; [L51] SORT_3 var_10_arg_1 = state_8; [L52] SORT_1 var_10 = var_10_arg_0 > var_10_arg_1; [L53] SORT_1 var_11_arg_0 = var_10; [L54] SORT_1 var_11 = ~var_11_arg_0; [L55] SORT_1 var_15_arg_0 = var_11; [L56] SORT_1 var_15 = ~var_15_arg_0; [L57] SORT_1 var_16_arg_0 = var_14; [L58] SORT_1 var_16_arg_1 = var_15; [L59] SORT_1 var_16 = var_16_arg_0 & var_16_arg_1; [L60] var_16 = var_16 & mask_SORT_1 [L61] SORT_1 bad_17_arg_0 = var_16; [L62] CALL __VERIFIER_assert(!(bad_17_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L62] RET __VERIFIER_assert(!(bad_17_arg_0)) [L64] SORT_3 var_25_arg_0 = state_5; [L65] SORT_3 var_25_arg_1 = state_8; [L66] SORT_1 var_25 = var_25_arg_0 == var_25_arg_1; [L67] SORT_3 var_24_arg_0 = state_5; [L68] SORT_3 var_24_arg_1 = var_7; [L69] SORT_3 var_24 = var_24_arg_0 + var_24_arg_1; [L70] SORT_3 var_19_arg_0 = state_5; [L71] SORT_3 var_19_arg_1 = state_8; [L72] SORT_1 var_19 = var_19_arg_0 > var_19_arg_1; [L73] SORT_3 var_21_arg_0 = state_8; [L74] SORT_3 var_21_arg_1 = var_20; [L75] SORT_1 var_21 = var_21_arg_0 != var_21_arg_1; [L76] SORT_1 var_22_arg_0 = var_19; [L77] SORT_1 var_22_arg_1 = var_21; [L78] SORT_1 var_22 = var_22_arg_0 | var_22_arg_1; [L79] var_22 = var_22 & mask_SORT_1 [L80] SORT_1 var_23_arg_0 = var_22; [L81] SORT_3 var_23_arg_1 = state_5; [L82] SORT_3 var_23_arg_2 = state_8; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=28, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=12, state_5=0, state_8=12, var_10=0, var_10_arg_0=0, var_10_arg_1=12, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=12, var_20=15, var_21=1, var_21_arg_0=12, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=12, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=12, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=12, var_28_arg_0=11, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=11, var_30=1, var_30_arg_0=11, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=12, var_32_arg_0=1, var_32_arg_1=12, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=11, var_34=12, var_34_arg_0=0, var_34_arg_1=11, var_34_arg_2=12, var_4=0, var_7=1] [L83] EXPR var_23_arg_0 ? var_23_arg_1 : var_23_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=28, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=12, state_5=0, state_8=12, var_10=0, var_10_arg_0=0, var_10_arg_1=12, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=12, var_20=15, var_21=1, var_21_arg_0=12, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_0 ? var_23_arg_1 : var_23_arg_2=0, var_23_arg_1=0, var_23_arg_2=12, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=12, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=12, var_28_arg_0=11, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=11, var_30=1, var_30_arg_0=11, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=12, var_32_arg_0=1, var_32_arg_1=12, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=11, var_34=12, var_34_arg_0=0, var_34_arg_1=11, var_34_arg_2=12, var_4=0, var_7=1] [L83] SORT_3 var_23 = var_23_arg_0 ? var_23_arg_1 : var_23_arg_2; [L84] SORT_1 var_26_arg_0 = var_25; [L85] SORT_3 var_26_arg_1 = var_24; [L86] SORT_3 var_26_arg_2 = var_23; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=28, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=12, state_5=0, state_8=12, var_10=0, var_10_arg_0=0, var_10_arg_1=12, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=12, var_20=15, var_21=1, var_21_arg_0=12, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=12, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=12, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=12, var_28_arg_0=11, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=11, var_30=1, var_30_arg_0=11, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=12, var_32_arg_0=1, var_32_arg_1=12, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=11, var_34=12, var_34_arg_0=0, var_34_arg_1=11, var_34_arg_2=12, var_4=0, var_7=1] [L87] EXPR var_26_arg_0 ? var_26_arg_1 : var_26_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=28, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=12, state_5=0, state_8=12, var_10=0, var_10_arg_0=0, var_10_arg_1=12, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=12, var_20=15, var_21=1, var_21_arg_0=12, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=12, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=12, var_26=0, var_26_arg_0=0, var_26_arg_0 ? var_26_arg_1 : var_26_arg_2=0, var_26_arg_1=1, var_26_arg_2=0, var_28=12, var_28_arg_0=11, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=11, var_30=1, var_30_arg_0=11, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=12, var_32_arg_0=1, var_32_arg_1=12, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=11, var_34=12, var_34_arg_0=0, var_34_arg_1=11, var_34_arg_2=12, var_4=0, var_7=1] [L87] SORT_3 var_26 = var_26_arg_0 ? var_26_arg_1 : var_26_arg_2; [L88] var_26 = var_26 & mask_SORT_3 [L89] SORT_3 next_27_arg_1 = var_26; [L90] SORT_3 var_33_arg_0 = state_5; [L91] SORT_3 var_33_arg_1 = state_8; [L92] SORT_1 var_33 = var_33_arg_0 > var_33_arg_1; [L93] SORT_3 var_29_arg_0 = state_5; [L94] SORT_3 var_29_arg_1 = state_8; [L95] SORT_1 var_29 = var_29_arg_0 == var_29_arg_1; [L96] SORT_3 var_30_arg_0 = state_8; [L97] SORT_3 var_30_arg_1 = var_20; [L98] SORT_1 var_30 = var_30_arg_0 != var_30_arg_1; [L99] SORT_1 var_31_arg_0 = var_29; [L100] SORT_1 var_31_arg_1 = var_30; [L101] SORT_1 var_31 = var_31_arg_0 | var_31_arg_1; [L102] var_31 = var_31 & mask_SORT_1 [L103] SORT_3 var_28_arg_0 = state_8; [L104] SORT_3 var_28_arg_1 = var_7; [L105] SORT_3 var_28 = var_28_arg_0 + var_28_arg_1; [L106] SORT_1 var_32_arg_0 = var_31; [L107] SORT_3 var_32_arg_1 = var_28; [L108] SORT_3 var_32_arg_2 = state_5; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=28, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=12, state_5=0, state_8=12, var_10=0, var_10_arg_0=0, var_10_arg_1=12, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=12, var_20=15, var_21=1, var_21_arg_0=12, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=12, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=12, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=13, var_28_arg_0=12, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=12, var_30=1, var_30_arg_0=12, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=12, var_32_arg_0=1, var_32_arg_1=13, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=12, var_34=12, var_34_arg_0=0, var_34_arg_1=11, var_34_arg_2=12, var_4=0, var_7=1] [L109] EXPR var_32_arg_0 ? var_32_arg_1 : var_32_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=28, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=12, state_5=0, state_8=12, var_10=0, var_10_arg_0=0, var_10_arg_1=12, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=12, var_20=15, var_21=1, var_21_arg_0=12, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=12, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=12, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=13, var_28_arg_0=12, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=12, var_30=1, var_30_arg_0=12, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=12, var_32_arg_0=1, var_32_arg_0 ? var_32_arg_1 : var_32_arg_2=13, var_32_arg_1=13, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=12, var_34=12, var_34_arg_0=0, var_34_arg_1=11, var_34_arg_2=12, var_4=0, var_7=1] [L109] SORT_3 var_32 = var_32_arg_0 ? var_32_arg_1 : var_32_arg_2; [L110] SORT_1 var_34_arg_0 = var_33; [L111] SORT_3 var_34_arg_1 = state_8; [L112] SORT_3 var_34_arg_2 = var_32; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=28, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=12, state_5=0, state_8=12, var_10=0, var_10_arg_0=0, var_10_arg_1=12, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=12, var_20=15, var_21=1, var_21_arg_0=12, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=12, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=12, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=13, var_28_arg_0=12, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=12, var_30=1, var_30_arg_0=12, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=13, var_32_arg_0=1, var_32_arg_1=13, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=12, var_34=12, var_34_arg_0=0, var_34_arg_1=12, var_34_arg_2=13, var_4=0, var_7=1] [L113] EXPR var_34_arg_0 ? var_34_arg_1 : var_34_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=28, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=12, state_5=0, state_8=12, var_10=0, var_10_arg_0=0, var_10_arg_1=12, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=12, var_20=15, var_21=1, var_21_arg_0=12, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=12, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=12, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=13, var_28_arg_0=12, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=12, var_30=1, var_30_arg_0=12, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=13, var_32_arg_0=1, var_32_arg_1=13, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=12, var_34=12, var_34_arg_0=0, var_34_arg_0 ? var_34_arg_1 : var_34_arg_2=13, var_34_arg_1=12, var_34_arg_2=13, var_4=0, var_7=1] [L113] SORT_3 var_34 = var_34_arg_0 ? var_34_arg_1 : var_34_arg_2; [L114] var_34 = var_34 & mask_SORT_3 [L115] SORT_3 next_35_arg_1 = var_34; [L117] state_5 = next_27_arg_1 [L118] state_8 = next_35_arg_1 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=28, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=13, state_5=0, state_8=13, var_10=0, var_10_arg_0=0, var_10_arg_1=12, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=12, var_20=15, var_21=1, var_21_arg_0=12, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=12, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=12, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=13, var_28_arg_0=12, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=12, var_30=1, var_30_arg_0=12, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=13, var_32_arg_0=1, var_32_arg_1=13, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=12, var_34=13, var_34_arg_0=0, var_34_arg_1=12, var_34_arg_2=13, var_4=0, var_7=1] [L47] input_2 = __VERIFIER_nondet_uchar() [L50] SORT_3 var_10_arg_0 = state_5; [L51] SORT_3 var_10_arg_1 = state_8; [L52] SORT_1 var_10 = var_10_arg_0 > var_10_arg_1; [L53] SORT_1 var_11_arg_0 = var_10; [L54] SORT_1 var_11 = ~var_11_arg_0; [L55] SORT_1 var_15_arg_0 = var_11; [L56] SORT_1 var_15 = ~var_15_arg_0; [L57] SORT_1 var_16_arg_0 = var_14; [L58] SORT_1 var_16_arg_1 = var_15; [L59] SORT_1 var_16 = var_16_arg_0 & var_16_arg_1; [L60] var_16 = var_16 & mask_SORT_1 [L61] SORT_1 bad_17_arg_0 = var_16; [L62] CALL __VERIFIER_assert(!(bad_17_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L62] RET __VERIFIER_assert(!(bad_17_arg_0)) [L64] SORT_3 var_25_arg_0 = state_5; [L65] SORT_3 var_25_arg_1 = state_8; [L66] SORT_1 var_25 = var_25_arg_0 == var_25_arg_1; [L67] SORT_3 var_24_arg_0 = state_5; [L68] SORT_3 var_24_arg_1 = var_7; [L69] SORT_3 var_24 = var_24_arg_0 + var_24_arg_1; [L70] SORT_3 var_19_arg_0 = state_5; [L71] SORT_3 var_19_arg_1 = state_8; [L72] SORT_1 var_19 = var_19_arg_0 > var_19_arg_1; [L73] SORT_3 var_21_arg_0 = state_8; [L74] SORT_3 var_21_arg_1 = var_20; [L75] SORT_1 var_21 = var_21_arg_0 != var_21_arg_1; [L76] SORT_1 var_22_arg_0 = var_19; [L77] SORT_1 var_22_arg_1 = var_21; [L78] SORT_1 var_22 = var_22_arg_0 | var_22_arg_1; [L79] var_22 = var_22 & mask_SORT_1 [L80] SORT_1 var_23_arg_0 = var_22; [L81] SORT_3 var_23_arg_1 = state_5; [L82] SORT_3 var_23_arg_2 = state_8; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=29, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=13, state_5=0, state_8=13, var_10=0, var_10_arg_0=0, var_10_arg_1=13, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=13, var_20=15, var_21=1, var_21_arg_0=13, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=13, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=13, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=13, var_28_arg_0=12, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=12, var_30=1, var_30_arg_0=12, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=13, var_32_arg_0=1, var_32_arg_1=13, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=12, var_34=13, var_34_arg_0=0, var_34_arg_1=12, var_34_arg_2=13, var_4=0, var_7=1] [L83] EXPR var_23_arg_0 ? var_23_arg_1 : var_23_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=29, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=13, state_5=0, state_8=13, var_10=0, var_10_arg_0=0, var_10_arg_1=13, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=13, var_20=15, var_21=1, var_21_arg_0=13, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_0 ? var_23_arg_1 : var_23_arg_2=0, var_23_arg_1=0, var_23_arg_2=13, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=13, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=13, var_28_arg_0=12, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=12, var_30=1, var_30_arg_0=12, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=13, var_32_arg_0=1, var_32_arg_1=13, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=12, var_34=13, var_34_arg_0=0, var_34_arg_1=12, var_34_arg_2=13, var_4=0, var_7=1] [L83] SORT_3 var_23 = var_23_arg_0 ? var_23_arg_1 : var_23_arg_2; [L84] SORT_1 var_26_arg_0 = var_25; [L85] SORT_3 var_26_arg_1 = var_24; [L86] SORT_3 var_26_arg_2 = var_23; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=29, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=13, state_5=0, state_8=13, var_10=0, var_10_arg_0=0, var_10_arg_1=13, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=13, var_20=15, var_21=1, var_21_arg_0=13, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=13, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=13, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=13, var_28_arg_0=12, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=12, var_30=1, var_30_arg_0=12, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=13, var_32_arg_0=1, var_32_arg_1=13, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=12, var_34=13, var_34_arg_0=0, var_34_arg_1=12, var_34_arg_2=13, var_4=0, var_7=1] [L87] EXPR var_26_arg_0 ? var_26_arg_1 : var_26_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=29, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=13, state_5=0, state_8=13, var_10=0, var_10_arg_0=0, var_10_arg_1=13, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=13, var_20=15, var_21=1, var_21_arg_0=13, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=13, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=13, var_26=0, var_26_arg_0=0, var_26_arg_0 ? var_26_arg_1 : var_26_arg_2=0, var_26_arg_1=1, var_26_arg_2=0, var_28=13, var_28_arg_0=12, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=12, var_30=1, var_30_arg_0=12, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=13, var_32_arg_0=1, var_32_arg_1=13, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=12, var_34=13, var_34_arg_0=0, var_34_arg_1=12, var_34_arg_2=13, var_4=0, var_7=1] [L87] SORT_3 var_26 = var_26_arg_0 ? var_26_arg_1 : var_26_arg_2; [L88] var_26 = var_26 & mask_SORT_3 [L89] SORT_3 next_27_arg_1 = var_26; [L90] SORT_3 var_33_arg_0 = state_5; [L91] SORT_3 var_33_arg_1 = state_8; [L92] SORT_1 var_33 = var_33_arg_0 > var_33_arg_1; [L93] SORT_3 var_29_arg_0 = state_5; [L94] SORT_3 var_29_arg_1 = state_8; [L95] SORT_1 var_29 = var_29_arg_0 == var_29_arg_1; [L96] SORT_3 var_30_arg_0 = state_8; [L97] SORT_3 var_30_arg_1 = var_20; [L98] SORT_1 var_30 = var_30_arg_0 != var_30_arg_1; [L99] SORT_1 var_31_arg_0 = var_29; [L100] SORT_1 var_31_arg_1 = var_30; [L101] SORT_1 var_31 = var_31_arg_0 | var_31_arg_1; [L102] var_31 = var_31 & mask_SORT_1 [L103] SORT_3 var_28_arg_0 = state_8; [L104] SORT_3 var_28_arg_1 = var_7; [L105] SORT_3 var_28 = var_28_arg_0 + var_28_arg_1; [L106] SORT_1 var_32_arg_0 = var_31; [L107] SORT_3 var_32_arg_1 = var_28; [L108] SORT_3 var_32_arg_2 = state_5; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=29, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=13, state_5=0, state_8=13, var_10=0, var_10_arg_0=0, var_10_arg_1=13, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=13, var_20=15, var_21=1, var_21_arg_0=13, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=13, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=13, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=14, var_28_arg_0=13, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=13, var_30=1, var_30_arg_0=13, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=13, var_32_arg_0=1, var_32_arg_1=14, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=13, var_34=13, var_34_arg_0=0, var_34_arg_1=12, var_34_arg_2=13, var_4=0, var_7=1] [L109] EXPR var_32_arg_0 ? var_32_arg_1 : var_32_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=29, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=13, state_5=0, state_8=13, var_10=0, var_10_arg_0=0, var_10_arg_1=13, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=13, var_20=15, var_21=1, var_21_arg_0=13, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=13, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=13, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=14, var_28_arg_0=13, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=13, var_30=1, var_30_arg_0=13, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=13, var_32_arg_0=1, var_32_arg_0 ? var_32_arg_1 : var_32_arg_2=14, var_32_arg_1=14, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=13, var_34=13, var_34_arg_0=0, var_34_arg_1=12, var_34_arg_2=13, var_4=0, var_7=1] [L109] SORT_3 var_32 = var_32_arg_0 ? var_32_arg_1 : var_32_arg_2; [L110] SORT_1 var_34_arg_0 = var_33; [L111] SORT_3 var_34_arg_1 = state_8; [L112] SORT_3 var_34_arg_2 = var_32; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=29, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=13, state_5=0, state_8=13, var_10=0, var_10_arg_0=0, var_10_arg_1=13, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=13, var_20=15, var_21=1, var_21_arg_0=13, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=13, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=13, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=14, var_28_arg_0=13, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=13, var_30=1, var_30_arg_0=13, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=14, var_32_arg_0=1, var_32_arg_1=14, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=13, var_34=13, var_34_arg_0=0, var_34_arg_1=13, var_34_arg_2=14, var_4=0, var_7=1] [L113] EXPR var_34_arg_0 ? var_34_arg_1 : var_34_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=29, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=13, state_5=0, state_8=13, var_10=0, var_10_arg_0=0, var_10_arg_1=13, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=13, var_20=15, var_21=1, var_21_arg_0=13, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=13, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=13, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=14, var_28_arg_0=13, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=13, var_30=1, var_30_arg_0=13, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=14, var_32_arg_0=1, var_32_arg_1=14, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=13, var_34=13, var_34_arg_0=0, var_34_arg_0 ? var_34_arg_1 : var_34_arg_2=14, var_34_arg_1=13, var_34_arg_2=14, var_4=0, var_7=1] [L113] SORT_3 var_34 = var_34_arg_0 ? var_34_arg_1 : var_34_arg_2; [L114] var_34 = var_34 & mask_SORT_3 [L115] SORT_3 next_35_arg_1 = var_34; [L117] state_5 = next_27_arg_1 [L118] state_8 = next_35_arg_1 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=29, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=14, state_5=0, state_8=14, var_10=0, var_10_arg_0=0, var_10_arg_1=13, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=13, var_20=15, var_21=1, var_21_arg_0=13, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=13, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=13, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=14, var_28_arg_0=13, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=13, var_30=1, var_30_arg_0=13, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=14, var_32_arg_0=1, var_32_arg_1=14, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=13, var_34=14, var_34_arg_0=0, var_34_arg_1=13, var_34_arg_2=14, var_4=0, var_7=1] [L47] input_2 = __VERIFIER_nondet_uchar() [L50] SORT_3 var_10_arg_0 = state_5; [L51] SORT_3 var_10_arg_1 = state_8; [L52] SORT_1 var_10 = var_10_arg_0 > var_10_arg_1; [L53] SORT_1 var_11_arg_0 = var_10; [L54] SORT_1 var_11 = ~var_11_arg_0; [L55] SORT_1 var_15_arg_0 = var_11; [L56] SORT_1 var_15 = ~var_15_arg_0; [L57] SORT_1 var_16_arg_0 = var_14; [L58] SORT_1 var_16_arg_1 = var_15; [L59] SORT_1 var_16 = var_16_arg_0 & var_16_arg_1; [L60] var_16 = var_16 & mask_SORT_1 [L61] SORT_1 bad_17_arg_0 = var_16; [L62] CALL __VERIFIER_assert(!(bad_17_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L62] RET __VERIFIER_assert(!(bad_17_arg_0)) [L64] SORT_3 var_25_arg_0 = state_5; [L65] SORT_3 var_25_arg_1 = state_8; [L66] SORT_1 var_25 = var_25_arg_0 == var_25_arg_1; [L67] SORT_3 var_24_arg_0 = state_5; [L68] SORT_3 var_24_arg_1 = var_7; [L69] SORT_3 var_24 = var_24_arg_0 + var_24_arg_1; [L70] SORT_3 var_19_arg_0 = state_5; [L71] SORT_3 var_19_arg_1 = state_8; [L72] SORT_1 var_19 = var_19_arg_0 > var_19_arg_1; [L73] SORT_3 var_21_arg_0 = state_8; [L74] SORT_3 var_21_arg_1 = var_20; [L75] SORT_1 var_21 = var_21_arg_0 != var_21_arg_1; [L76] SORT_1 var_22_arg_0 = var_19; [L77] SORT_1 var_22_arg_1 = var_21; [L78] SORT_1 var_22 = var_22_arg_0 | var_22_arg_1; [L79] var_22 = var_22 & mask_SORT_1 [L80] SORT_1 var_23_arg_0 = var_22; [L81] SORT_3 var_23_arg_1 = state_5; [L82] SORT_3 var_23_arg_2 = state_8; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=30, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=14, state_5=0, state_8=14, var_10=0, var_10_arg_0=0, var_10_arg_1=14, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=14, var_20=15, var_21=1, var_21_arg_0=14, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=14, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=14, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=14, var_28_arg_0=13, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=13, var_30=1, var_30_arg_0=13, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=14, var_32_arg_0=1, var_32_arg_1=14, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=13, var_34=14, var_34_arg_0=0, var_34_arg_1=13, var_34_arg_2=14, var_4=0, var_7=1] [L83] EXPR var_23_arg_0 ? var_23_arg_1 : var_23_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=30, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=14, state_5=0, state_8=14, var_10=0, var_10_arg_0=0, var_10_arg_1=14, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=14, var_20=15, var_21=1, var_21_arg_0=14, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_0 ? var_23_arg_1 : var_23_arg_2=0, var_23_arg_1=0, var_23_arg_2=14, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=14, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=14, var_28_arg_0=13, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=13, var_30=1, var_30_arg_0=13, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=14, var_32_arg_0=1, var_32_arg_1=14, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=13, var_34=14, var_34_arg_0=0, var_34_arg_1=13, var_34_arg_2=14, var_4=0, var_7=1] [L83] SORT_3 var_23 = var_23_arg_0 ? var_23_arg_1 : var_23_arg_2; [L84] SORT_1 var_26_arg_0 = var_25; [L85] SORT_3 var_26_arg_1 = var_24; [L86] SORT_3 var_26_arg_2 = var_23; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=30, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=14, state_5=0, state_8=14, var_10=0, var_10_arg_0=0, var_10_arg_1=14, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=14, var_20=15, var_21=1, var_21_arg_0=14, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=14, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=14, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=14, var_28_arg_0=13, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=13, var_30=1, var_30_arg_0=13, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=14, var_32_arg_0=1, var_32_arg_1=14, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=13, var_34=14, var_34_arg_0=0, var_34_arg_1=13, var_34_arg_2=14, var_4=0, var_7=1] [L87] EXPR var_26_arg_0 ? var_26_arg_1 : var_26_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=30, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=14, state_5=0, state_8=14, var_10=0, var_10_arg_0=0, var_10_arg_1=14, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=14, var_20=15, var_21=1, var_21_arg_0=14, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=14, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=14, var_26=0, var_26_arg_0=0, var_26_arg_0 ? var_26_arg_1 : var_26_arg_2=0, var_26_arg_1=1, var_26_arg_2=0, var_28=14, var_28_arg_0=13, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=13, var_30=1, var_30_arg_0=13, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=14, var_32_arg_0=1, var_32_arg_1=14, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=13, var_34=14, var_34_arg_0=0, var_34_arg_1=13, var_34_arg_2=14, var_4=0, var_7=1] [L87] SORT_3 var_26 = var_26_arg_0 ? var_26_arg_1 : var_26_arg_2; [L88] var_26 = var_26 & mask_SORT_3 [L89] SORT_3 next_27_arg_1 = var_26; [L90] SORT_3 var_33_arg_0 = state_5; [L91] SORT_3 var_33_arg_1 = state_8; [L92] SORT_1 var_33 = var_33_arg_0 > var_33_arg_1; [L93] SORT_3 var_29_arg_0 = state_5; [L94] SORT_3 var_29_arg_1 = state_8; [L95] SORT_1 var_29 = var_29_arg_0 == var_29_arg_1; [L96] SORT_3 var_30_arg_0 = state_8; [L97] SORT_3 var_30_arg_1 = var_20; [L98] SORT_1 var_30 = var_30_arg_0 != var_30_arg_1; [L99] SORT_1 var_31_arg_0 = var_29; [L100] SORT_1 var_31_arg_1 = var_30; [L101] SORT_1 var_31 = var_31_arg_0 | var_31_arg_1; [L102] var_31 = var_31 & mask_SORT_1 [L103] SORT_3 var_28_arg_0 = state_8; [L104] SORT_3 var_28_arg_1 = var_7; [L105] SORT_3 var_28 = var_28_arg_0 + var_28_arg_1; [L106] SORT_1 var_32_arg_0 = var_31; [L107] SORT_3 var_32_arg_1 = var_28; [L108] SORT_3 var_32_arg_2 = state_5; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=30, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=14, state_5=0, state_8=14, var_10=0, var_10_arg_0=0, var_10_arg_1=14, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=14, var_20=15, var_21=1, var_21_arg_0=14, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=14, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=14, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=15, var_28_arg_0=14, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=14, var_30=1, var_30_arg_0=14, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=14, var_32_arg_0=1, var_32_arg_1=15, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=14, var_34=14, var_34_arg_0=0, var_34_arg_1=13, var_34_arg_2=14, var_4=0, var_7=1] [L109] EXPR var_32_arg_0 ? var_32_arg_1 : var_32_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=30, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=14, state_5=0, state_8=14, var_10=0, var_10_arg_0=0, var_10_arg_1=14, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=14, var_20=15, var_21=1, var_21_arg_0=14, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=14, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=14, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=15, var_28_arg_0=14, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=14, var_30=1, var_30_arg_0=14, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=14, var_32_arg_0=1, var_32_arg_0 ? var_32_arg_1 : var_32_arg_2=15, var_32_arg_1=15, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=14, var_34=14, var_34_arg_0=0, var_34_arg_1=13, var_34_arg_2=14, var_4=0, var_7=1] [L109] SORT_3 var_32 = var_32_arg_0 ? var_32_arg_1 : var_32_arg_2; [L110] SORT_1 var_34_arg_0 = var_33; [L111] SORT_3 var_34_arg_1 = state_8; [L112] SORT_3 var_34_arg_2 = var_32; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=30, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=14, state_5=0, state_8=14, var_10=0, var_10_arg_0=0, var_10_arg_1=14, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=14, var_20=15, var_21=1, var_21_arg_0=14, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=14, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=14, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=15, var_28_arg_0=14, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=14, var_30=1, var_30_arg_0=14, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=15, var_32_arg_0=1, var_32_arg_1=15, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=14, var_34=14, var_34_arg_0=0, var_34_arg_1=14, var_34_arg_2=15, var_4=0, var_7=1] [L113] EXPR var_34_arg_0 ? var_34_arg_1 : var_34_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=30, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=14, state_5=0, state_8=14, var_10=0, var_10_arg_0=0, var_10_arg_1=14, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=14, var_20=15, var_21=1, var_21_arg_0=14, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=14, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=14, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=15, var_28_arg_0=14, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=14, var_30=1, var_30_arg_0=14, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=15, var_32_arg_0=1, var_32_arg_1=15, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=14, var_34=14, var_34_arg_0=0, var_34_arg_0 ? var_34_arg_1 : var_34_arg_2=15, var_34_arg_1=14, var_34_arg_2=15, var_4=0, var_7=1] [L113] SORT_3 var_34 = var_34_arg_0 ? var_34_arg_1 : var_34_arg_2; [L114] var_34 = var_34 & mask_SORT_3 [L115] SORT_3 next_35_arg_1 = var_34; [L117] state_5 = next_27_arg_1 [L118] state_8 = next_35_arg_1 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=30, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=15, state_5=0, state_8=15, var_10=0, var_10_arg_0=0, var_10_arg_1=14, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=14, var_20=15, var_21=1, var_21_arg_0=14, var_21_arg_1=15, var_22=1, var_22_arg_0=0, var_22_arg_1=1, var_23=0, var_23_arg_0=1, var_23_arg_1=0, var_23_arg_2=14, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=14, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=15, var_28_arg_0=14, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=14, var_30=1, var_30_arg_0=14, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=15, var_32_arg_0=1, var_32_arg_1=15, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=14, var_34=15, var_34_arg_0=0, var_34_arg_1=14, var_34_arg_2=15, var_4=0, var_7=1] [L47] input_2 = __VERIFIER_nondet_uchar() [L50] SORT_3 var_10_arg_0 = state_5; [L51] SORT_3 var_10_arg_1 = state_8; [L52] SORT_1 var_10 = var_10_arg_0 > var_10_arg_1; [L53] SORT_1 var_11_arg_0 = var_10; [L54] SORT_1 var_11 = ~var_11_arg_0; [L55] SORT_1 var_15_arg_0 = var_11; [L56] SORT_1 var_15 = ~var_15_arg_0; [L57] SORT_1 var_16_arg_0 = var_14; [L58] SORT_1 var_16_arg_1 = var_15; [L59] SORT_1 var_16 = var_16_arg_0 & var_16_arg_1; [L60] var_16 = var_16 & mask_SORT_1 [L61] SORT_1 bad_17_arg_0 = var_16; [L62] CALL __VERIFIER_assert(!(bad_17_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L62] RET __VERIFIER_assert(!(bad_17_arg_0)) [L64] SORT_3 var_25_arg_0 = state_5; [L65] SORT_3 var_25_arg_1 = state_8; [L66] SORT_1 var_25 = var_25_arg_0 == var_25_arg_1; [L67] SORT_3 var_24_arg_0 = state_5; [L68] SORT_3 var_24_arg_1 = var_7; [L69] SORT_3 var_24 = var_24_arg_0 + var_24_arg_1; [L70] SORT_3 var_19_arg_0 = state_5; [L71] SORT_3 var_19_arg_1 = state_8; [L72] SORT_1 var_19 = var_19_arg_0 > var_19_arg_1; [L73] SORT_3 var_21_arg_0 = state_8; [L74] SORT_3 var_21_arg_1 = var_20; [L75] SORT_1 var_21 = var_21_arg_0 != var_21_arg_1; [L76] SORT_1 var_22_arg_0 = var_19; [L77] SORT_1 var_22_arg_1 = var_21; [L78] SORT_1 var_22 = var_22_arg_0 | var_22_arg_1; [L79] var_22 = var_22 & mask_SORT_1 [L80] SORT_1 var_23_arg_0 = var_22; [L81] SORT_3 var_23_arg_1 = state_5; [L82] SORT_3 var_23_arg_2 = state_8; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=31, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=15, state_5=0, state_8=15, var_10=0, var_10_arg_0=0, var_10_arg_1=15, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=15, var_20=15, var_21=0, var_21_arg_0=15, var_21_arg_1=15, var_22=0, var_22_arg_0=0, var_22_arg_1=0, var_23=0, var_23_arg_0=0, var_23_arg_1=0, var_23_arg_2=15, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=15, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=15, var_28_arg_0=14, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=14, var_30=1, var_30_arg_0=14, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=15, var_32_arg_0=1, var_32_arg_1=15, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=14, var_34=15, var_34_arg_0=0, var_34_arg_1=14, var_34_arg_2=15, var_4=0, var_7=1] [L83] EXPR var_23_arg_0 ? var_23_arg_1 : var_23_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=31, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=15, state_5=0, state_8=15, var_10=0, var_10_arg_0=0, var_10_arg_1=15, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=15, var_20=15, var_21=0, var_21_arg_0=15, var_21_arg_1=15, var_22=0, var_22_arg_0=0, var_22_arg_1=0, var_23=0, var_23_arg_0=0, var_23_arg_0 ? var_23_arg_1 : var_23_arg_2=15, var_23_arg_1=0, var_23_arg_2=15, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=15, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=0, var_28=15, var_28_arg_0=14, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=14, var_30=1, var_30_arg_0=14, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=15, var_32_arg_0=1, var_32_arg_1=15, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=14, var_34=15, var_34_arg_0=0, var_34_arg_1=14, var_34_arg_2=15, var_4=0, var_7=1] [L83] SORT_3 var_23 = var_23_arg_0 ? var_23_arg_1 : var_23_arg_2; [L84] SORT_1 var_26_arg_0 = var_25; [L85] SORT_3 var_26_arg_1 = var_24; [L86] SORT_3 var_26_arg_2 = var_23; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=31, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=15, state_5=0, state_8=15, var_10=0, var_10_arg_0=0, var_10_arg_1=15, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=15, var_20=15, var_21=0, var_21_arg_0=15, var_21_arg_1=15, var_22=0, var_22_arg_0=0, var_22_arg_1=0, var_23=15, var_23_arg_0=0, var_23_arg_1=0, var_23_arg_2=15, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=15, var_26=0, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=15, var_28=15, var_28_arg_0=14, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=14, var_30=1, var_30_arg_0=14, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=15, var_32_arg_0=1, var_32_arg_1=15, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=14, var_34=15, var_34_arg_0=0, var_34_arg_1=14, var_34_arg_2=15, var_4=0, var_7=1] [L87] EXPR var_26_arg_0 ? var_26_arg_1 : var_26_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=31, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=0, next_35_arg_1=15, state_5=0, state_8=15, var_10=0, var_10_arg_0=0, var_10_arg_1=15, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=15, var_20=15, var_21=0, var_21_arg_0=15, var_21_arg_1=15, var_22=0, var_22_arg_0=0, var_22_arg_1=0, var_23=15, var_23_arg_0=0, var_23_arg_1=0, var_23_arg_2=15, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=15, var_26=0, var_26_arg_0=0, var_26_arg_0 ? var_26_arg_1 : var_26_arg_2=15, var_26_arg_1=1, var_26_arg_2=15, var_28=15, var_28_arg_0=14, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=14, var_30=1, var_30_arg_0=14, var_30_arg_1=15, var_31=1, var_31_arg_0=0, var_31_arg_1=1, var_32=15, var_32_arg_0=1, var_32_arg_1=15, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=14, var_34=15, var_34_arg_0=0, var_34_arg_1=14, var_34_arg_2=15, var_4=0, var_7=1] [L87] SORT_3 var_26 = var_26_arg_0 ? var_26_arg_1 : var_26_arg_2; [L88] var_26 = var_26 & mask_SORT_3 [L89] SORT_3 next_27_arg_1 = var_26; [L90] SORT_3 var_33_arg_0 = state_5; [L91] SORT_3 var_33_arg_1 = state_8; [L92] SORT_1 var_33 = var_33_arg_0 > var_33_arg_1; [L93] SORT_3 var_29_arg_0 = state_5; [L94] SORT_3 var_29_arg_1 = state_8; [L95] SORT_1 var_29 = var_29_arg_0 == var_29_arg_1; [L96] SORT_3 var_30_arg_0 = state_8; [L97] SORT_3 var_30_arg_1 = var_20; [L98] SORT_1 var_30 = var_30_arg_0 != var_30_arg_1; [L99] SORT_1 var_31_arg_0 = var_29; [L100] SORT_1 var_31_arg_1 = var_30; [L101] SORT_1 var_31 = var_31_arg_0 | var_31_arg_1; [L102] var_31 = var_31 & mask_SORT_1 [L103] SORT_3 var_28_arg_0 = state_8; [L104] SORT_3 var_28_arg_1 = var_7; [L105] SORT_3 var_28 = var_28_arg_0 + var_28_arg_1; [L106] SORT_1 var_32_arg_0 = var_31; [L107] SORT_3 var_32_arg_1 = var_28; [L108] SORT_3 var_32_arg_2 = state_5; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=31, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=15, next_35_arg_1=15, state_5=0, state_8=15, var_10=0, var_10_arg_0=0, var_10_arg_1=15, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=15, var_20=15, var_21=0, var_21_arg_0=15, var_21_arg_1=15, var_22=0, var_22_arg_0=0, var_22_arg_1=0, var_23=15, var_23_arg_0=0, var_23_arg_1=0, var_23_arg_2=15, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=15, var_26=15, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=15, var_28=16, var_28_arg_0=15, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=15, var_30=0, var_30_arg_0=15, var_30_arg_1=15, var_31=0, var_31_arg_0=0, var_31_arg_1=0, var_32=15, var_32_arg_0=0, var_32_arg_1=16, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=15, var_34=15, var_34_arg_0=0, var_34_arg_1=14, var_34_arg_2=15, var_4=0, var_7=1] [L109] EXPR var_32_arg_0 ? var_32_arg_1 : var_32_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=31, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=15, next_35_arg_1=15, state_5=0, state_8=15, var_10=0, var_10_arg_0=0, var_10_arg_1=15, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=15, var_20=15, var_21=0, var_21_arg_0=15, var_21_arg_1=15, var_22=0, var_22_arg_0=0, var_22_arg_1=0, var_23=15, var_23_arg_0=0, var_23_arg_1=0, var_23_arg_2=15, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=15, var_26=15, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=15, var_28=16, var_28_arg_0=15, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=15, var_30=0, var_30_arg_0=15, var_30_arg_1=15, var_31=0, var_31_arg_0=0, var_31_arg_1=0, var_32=15, var_32_arg_0=0, var_32_arg_0 ? var_32_arg_1 : var_32_arg_2=0, var_32_arg_1=16, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=15, var_34=15, var_34_arg_0=0, var_34_arg_1=14, var_34_arg_2=15, var_4=0, var_7=1] [L109] SORT_3 var_32 = var_32_arg_0 ? var_32_arg_1 : var_32_arg_2; [L110] SORT_1 var_34_arg_0 = var_33; [L111] SORT_3 var_34_arg_1 = state_8; [L112] SORT_3 var_34_arg_2 = var_32; VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=31, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=15, next_35_arg_1=15, state_5=0, state_8=15, var_10=0, var_10_arg_0=0, var_10_arg_1=15, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=15, var_20=15, var_21=0, var_21_arg_0=15, var_21_arg_1=15, var_22=0, var_22_arg_0=0, var_22_arg_1=0, var_23=15, var_23_arg_0=0, var_23_arg_1=0, var_23_arg_2=15, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=15, var_26=15, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=15, var_28=16, var_28_arg_0=15, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=15, var_30=0, var_30_arg_0=15, var_30_arg_1=15, var_31=0, var_31_arg_0=0, var_31_arg_1=0, var_32=0, var_32_arg_0=0, var_32_arg_1=16, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=15, var_34=15, var_34_arg_0=0, var_34_arg_1=15, var_34_arg_2=0, var_4=0, var_7=1] [L113] EXPR var_34_arg_0 ? var_34_arg_1 : var_34_arg_2 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=31, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=15, next_35_arg_1=15, state_5=0, state_8=15, var_10=0, var_10_arg_0=0, var_10_arg_1=15, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=15, var_20=15, var_21=0, var_21_arg_0=15, var_21_arg_1=15, var_22=0, var_22_arg_0=0, var_22_arg_1=0, var_23=15, var_23_arg_0=0, var_23_arg_1=0, var_23_arg_2=15, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=15, var_26=15, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=15, var_28=16, var_28_arg_0=15, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=15, var_30=0, var_30_arg_0=15, var_30_arg_1=15, var_31=0, var_31_arg_0=0, var_31_arg_1=0, var_32=0, var_32_arg_0=0, var_32_arg_1=16, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=15, var_34=15, var_34_arg_0=0, var_34_arg_0 ? var_34_arg_1 : var_34_arg_2=0, var_34_arg_1=15, var_34_arg_2=0, var_4=0, var_7=1] [L113] SORT_3 var_34 = var_34_arg_0 ? var_34_arg_1 : var_34_arg_2; [L114] var_34 = var_34 & mask_SORT_3 [L115] SORT_3 next_35_arg_1 = var_34; [L117] state_5 = next_27_arg_1 [L118] state_8 = next_35_arg_1 VAL [bad_17_arg_0=0, init_6_arg_1=0, init_9_arg_1=1, input_2=31, mask_SORT_1=1, mask_SORT_3=15, msb_SORT_1=1, msb_SORT_3=8, next_27_arg_1=15, next_35_arg_1=0, state_5=15, state_8=0, var_10=0, var_10_arg_0=0, var_10_arg_1=15, var_11=255, var_11_arg_0=0, var_14=1, var_15=0, var_15_arg_0=255, var_16=0, var_16_arg_0=1, var_16_arg_1=0, var_19=0, var_19_arg_0=0, var_19_arg_1=15, var_20=15, var_21=0, var_21_arg_0=15, var_21_arg_1=15, var_22=0, var_22_arg_0=0, var_22_arg_1=0, var_23=15, var_23_arg_0=0, var_23_arg_1=0, var_23_arg_2=15, var_24=1, var_24_arg_0=0, var_24_arg_1=1, var_25=0, var_25_arg_0=0, var_25_arg_1=15, var_26=15, var_26_arg_0=0, var_26_arg_1=1, var_26_arg_2=15, var_28=16, var_28_arg_0=15, var_28_arg_1=1, var_29=0, var_29_arg_0=0, var_29_arg_1=15, var_30=0, var_30_arg_0=15, var_30_arg_1=15, var_31=0, var_31_arg_0=0, var_31_arg_1=0, var_32=0, var_32_arg_0=0, var_32_arg_1=16, var_32_arg_2=0, var_33=0, var_33_arg_0=0, var_33_arg_1=15, var_34=0, var_34_arg_0=0, var_34_arg_1=15, var_34_arg_2=0, var_4=0, var_7=1] [L47] input_2 = __VERIFIER_nondet_uchar() [L50] SORT_3 var_10_arg_0 = state_5; [L51] SORT_3 var_10_arg_1 = state_8; [L52] SORT_1 var_10 = var_10_arg_0 > var_10_arg_1; [L53] SORT_1 var_11_arg_0 = var_10; [L54] SORT_1 var_11 = ~var_11_arg_0; [L55] SORT_1 var_15_arg_0 = var_11; [L56] SORT_1 var_15 = ~var_15_arg_0; [L57] SORT_1 var_16_arg_0 = var_14; [L58] SORT_1 var_16_arg_1 = var_15; [L59] SORT_1 var_16 = var_16_arg_0 & var_16_arg_1; [L60] var_16 = var_16 & mask_SORT_1 [L61] SORT_1 bad_17_arg_0 = var_16; [L62] CALL __VERIFIER_assert(!(bad_17_arg_0)) [L20] COND TRUE !(cond) VAL [\old(cond)=0, cond=0] [L20] reach_error() VAL [\old(cond)=0, cond=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 19 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 817.9s, OverallIterations: 19, TraceHistogramMax: 16, PathProgramHistogramMax: 3, EmptinessCheckTime: 0.0s, AutomataDifference: 474.8s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 5664 SdHoareTripleChecker+Valid, 20.1s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 5664 mSDsluCounter, 15266 SdHoareTripleChecker+Invalid, 17.7s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 20894 IncrementalHoareTripleChecker+Unchecked, 14855 mSDsCounter, 1647 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 13500 IncrementalHoareTripleChecker+Invalid, 36041 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 1647 mSolverCounterUnsat, 411 mSDtfsCounter, 13500 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 4978 GetRequests, 3240 SyntacticMatches, 32 SemanticMatches, 1706 ConstructedPredicates, 0 IntricatePredicates, 1 DeprecatedPredicates, 112368 ImplicationChecksByTransitivity, 744.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=382occurred in iteration=18, InterpolantAutomatonStates: 811, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.3s AutomataMinimizationTime, 18 MinimizatonAttempts, 732 StatesRemovedByMinimization, 16 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 1.4s SsaConstructionTime, 3.6s SatisfiabilityAnalysisTime, 326.5s InterpolantComputationTime, 2311 NumberOfCodeBlocks, 2047 NumberOfCodeBlocksAsserted, 64 NumberOfCheckSat, 4125 ConstructedInterpolants, 1099 QuantifiedInterpolants, 162041 SizeOfPredicates, 1848 NumberOfNonLiveVariables, 12367 ConjunctsInSsa, 2162 ConjunctsInUnsatCore, 77 InterpolantComputations, 8 PerfectInterpolantSequences, 4587/12057 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [2022-11-03 02:56:49,937 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_dc44e55c-67d5-4478-9708-e77cc58b6a93/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE